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URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

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Rev 27 → Rev 28

/trunk/rtl/verilog/ud_cnt.v
1,18 → 1,15
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal Up/Down counter, library module ////
//// Generic Up/Down counter ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 34,10
 
// CVS Log
//
// $Id: ud_cnt.v,v 1.3 2001-11-14 11:45:25 rherveille Exp $
// $Id: ud_cnt.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.3 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 44,7
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
 
/////////////////////////////
55,9 → 53,11
 
`include "timescale.v"
 
module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, resd, rci, rco);
module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco);
// parameter declaration
parameter SIZE = 8;
parameter RESD = {SIZE{1'b0}}; // data after reset
 
// inputs & outputs
input clk; // master clock
input nReset; // asynchronous active low reset
67,7 → 67,6
input nld; // synchronous active low load
input [SIZE-1:0] d; // load counter value
output [SIZE-1:0] q; // current counter value
input [SIZE-1:0] resd; // initial data after/during reset
input rci; // carry input
output rco; // carry output
 
84,9 → 83,9
always@(posedge clk or negedge nReset)
begin
if (~nReset)
Qi <= #1 resd;
Qi <= #1 RESD;
else if (rst)
Qi <= #1 resd;
Qi <= #1 RESD;
else if (~nld)
Qi <= #1 d;
else if (cnt_en)
97,3 → 96,5
assign q = Qi;
assign rco = val[SIZE];
endmodule
 
 
/trunk/rtl/verilog/vga_vtim.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_vtim.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_vtim.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
94,16 → 94,56
end
 
// hookup sync counter
ro_cnt #(8) sync_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(go), .d(Tsync), .id(Tsync), .q(), .done(Dsync));
ro_cnt #(8, 1'b0, 8)
sync_cnt(
.clk(clk),
.rst(rst),
.nReset(1'b1),
.cnt_en(ena),
.go(go),
.d(Tsync),
.q(),
.done(Dsync)
);
 
// hookup gate delay counter
ro_cnt #(8) gdel_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(Dsync), .d(Tgdel), .id(Tgdel), .q(), .done(Dgdel));
ro_cnt #(8, 1'b0, 8)
gdel_cnt(
.clk(clk),
.rst(rst),
.nReset(1'b1),
.cnt_en(ena),
.go(Dsync),
.d(Tgdel),
.q(),
.done(Dgdel)
);
 
// hookup gate counter
ro_cnt #(16) gate_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(Dgdel), .d(Tgate), .id(Tgate), .q(), .done(Dgate));
ro_cnt #(16, 1'b0, 16)
gate_cnt(
.clk(clk),
.rst(rst),
.nReset(1'b1),
.cnt_en(ena),
.go(Dgdel),
.d(Tgate),
.q(),
.done(Dgate)
);
 
// hookup length counter
ro_cnt #(16) len_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(go), .d(Tlen), .id(Tlen), .q(), .done(Dlen));
ro_cnt #(16, 1'b0, 16)
len_cnt(
.clk(clk),
.rst(rst),
.nReset(1'b1),
.cnt_en(ena),
.go(go),
.d(Tlen),
.q(),
.done(Dlen)
);
 
// hold dgate signal
always@(posedge clk)
134,11 → 174,3
 
assign Done = Dlen;
endmodule
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/vga_fifo.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_fifo.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_fifo.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_wb_master.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_master.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_wb_master.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
274,8 → 274,8
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
2'b10: //24bpp
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
2'b11: //reserved
;
2'b11: //32bpp
hgate_cnt <= #1 Thgate; // 1 pixel per cycle
endcase
 
hgate_div_cnt <= 2'b10;
290,8 → 290,8
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
2'b10: //24bpp
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
2'b11: //reserved
;
2'b11: //32bpp
hgate_cnt <= #1 Thgate; // 1 pixel per cycle
endcase
hgate_div_cnt <= #1 2'b10;
end
439,3 → 439,4
endmodule
 
 
 
/trunk/rtl/verilog/ro_cnt.v
1,18 → 1,15
/////////////////////////////////////////////////////////////////////
//// ////
//// Run-Once Counter, library module ////
//// Run-Once counter ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 34,10
 
// CVS Log
//
// $Id: ro_cnt.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: ro_cnt.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 44,7
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
 
///////////////////////////
57,9 → 55,14
 
`include "timescale.v"
 
module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q, id);
module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q);
 
// parameter declaration
parameter SIZE = 8;
 
parameter UD = 1'b0; // default count down
parameter ID = {SIZE{1'b0}}; // initial data after reset
 
// inputs & outputs
input clk; // master clock
input nReset; // asynchronous active low reset
69,7 → 72,6
output done; // done counting
input [SIZE-1:0] d; // load counter value
output [SIZE-1:0] q; // current counter value
input [SIZE-1:0] id; // initial data after reset
 
// variable declarations
reg rci;
85,16 → 87,19
else if (rst)
rci <= #1 1'b0;
else //if (cnt_en)
rci <= #1 (go | rci) & !rco;
rci <= #1 go | (rci & !rco);
 
assign nld = !go;
 
// hookup counter
ud_cnt #(SIZE) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
.ud(1'b0), .nld(nld), .d(d), .q(q), .resd(id), .rci(rci), .rco(rco));
ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
.ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco));
 
 
// assign outputs
 
assign done = rco;
 
endmodule
 
 
/trunk/rtl/verilog/vga_fifo_dc.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_fifo_dc.v,v 1.3 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_fifo_dc.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.3 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_pgen.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_pgen.v,v 1.3 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_pgen.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.3 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_tgen.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_tgen.v,v 1.3 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_tgen.v,v 1.4 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.3 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_colproc.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_colproc.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_colproc.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
105,16 → 105,17
// generate statemachine
//
// extract color information from data buffer
parameter idle = 6'b00_0000,
fill_buf = 6'b00_0001,
bw_8bpp = 6'b00_0010,
col_8bpp = 6'b00_0100,
col_16bpp_a = 6'b00_1000,
col_16bpp_b = 6'b01_0000,
col_24bpp = 6'b10_0000;
parameter idle = 7'b000_0000,
fill_buf = 7'b000_0001,
bw_8bpp = 7'b000_0010,
col_8bpp = 7'b000_0100,
col_16bpp_a = 7'b000_1000,
col_16bpp_b = 7'b001_0000,
col_24bpp = 7'b010_0000,
col_32bpp = 7'b100_0000;
 
reg [5:0] c_state; // synopsis enum_state
reg [5:0] nxt_state; // synopsis enum_state
reg [6:0] c_state; // synopsys enum_state
reg [6:0] nxt_state; // synopsys enum_state
 
// next state decoder
always@(c_state or pixel_buffer_empty or ColorDepth or PseudoColor or RGB_fifo_full or colcnt or clut_ack)
140,9 → 141,12
2'b01:
nxt_state = col_16bpp_a;
 
default:
2'b10:
nxt_state = col_24bpp;
 
2'b11:
nxt_state = col_32bpp;
 
endcase
 
//
189,6 → 193,15
else
nxt_state = idle;
 
//
// 32 bits per pixel
//
col_32bpp:
if (!RGB_fifo_full)
if (!pixel_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
endcase
end // next state decoder
 
368,6 → 381,24
endcase
end
 
//
// 32 bits per pixel
//
col_32bpp:
begin
if (!RGB_fifo_full)
begin
RGBbuf_wreq = 1'b1;
 
if (!pixel_buffer_empty)
pixelbuf_rreq = 1'b1;
end
 
iR[7:0] = DataBuffer[23:16];
iG[7:0] = DataBuffer[15:8];
iB[7:0] = DataBuffer[7:0];
end
 
endcase
end // output decoder
 
418,3 → 449,5
else if (RGBbuf_wreq)
colcnt <= #1 colcnt -2'h1;
endmodule
 
 
/trunk/rtl/verilog/vga_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_top.v,v 1.5 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_top.v,v 1.6 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.5 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_wb_slave.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_slave.v,v 1.4 2001-11-14 11:45:24 rherveille Exp $
// $Id: vga_wb_slave.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:24 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_csm_pb.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_csm_pb.v,v 1.4 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_csm_pb.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.4 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
/trunk/rtl/verilog/vga_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_defines.v,v 1.2 2001-11-14 11:45:25 rherveille Exp $
// $Id: vga_defines.v,v 1.3 2002-01-28 03:47:16 rherveille Exp $
//
// $Date: 2001-11-14 11:45:25 $
// $Revision: 1.2 $
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $

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