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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 272 to Rev 273
    Reverse comparison

Rev 272 → Rev 273

/open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd
34,23 → 34,23
-- 0x1 AAAAAAAA B1 of Buffered Setpoint (W) or Current Setpoint(R)
-- 0x2 AAAAAAAA B2 of Buffered Setpoint (W) or Current Setpoint(R)
-- 0x3 AAAAAAAA B3 of Buffered Setpoint (W) or Current Setpoint(R)
-- 0x4 AAAAAAAA B0 of Current Epoch Time(RO)
-- 0x5 AAAAAAAA B1 of Current Epoch Time(RO)
-- 0x6 AAAAAAAA B2 of Current Epoch Time(RO)
-- 0x7 AAAAAAAA B3 of Current Epoch Time(RO)
-- 0x4 AAAAAAAA B0 of Buffered Current Epoch Time(RO)
-- 0x5 AAAAAAAA B1 of Buffered Current Epoch Time(RO)
-- 0x6 AAAAAAAA B2 of Buffered Current Epoch Time(RO)
-- 0x7 AAAAAAAA B3 of Buffered Current Epoch Time(RO)
-- Note that any write to 0x04,0x05, 0x06, or 0x07 will copy
-- the current epoch time to a readable output buffer
-- 0x8 xxxxxxxx (not used - returns 0x00)
-- 0x9 xxxxxxxx (not used - returns 0x00)
-- 0xA xxxxxxxx (not used - returns 0x00)
-- 0xB xxxxxxxx (not used - returns 0x00)
-- 0xC xxxxxxxx (not used - returns 0x00)
-- 0xD xxxxxxxx (not used - returns 0x00)
-- 0x8 -------- (not used - returns 0x00)
-- 0x9 -------- (not used - returns 0x00)
-- 0xA -------- (not used - returns 0x00)
-- 0xB -------- (not used - returns 0x00)
-- 0xC -------- (not used - returns 0x00)
-- 0xD -------- (not used - returns 0x00)
-- 0xE -------- Epoch Time Latch/Clear Control Register
-- Any write to 0xE will clear/reset the all timer regs
-- 0xF BA------ Status of buffer/alarm (1 = pending, 0 = current)
-- A = Pending status (R)
-- B = Alarm status (R)
-- B = Buffer status (R)
-- Note that any write will update the internal set point
-- and clear the alarm
--
61,6 → 61,7
-- change.
-- Seth Henry 04/16/20 Modifiefd to make use of Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
-- Seth Henry 11/01/20 Updated comments regarding buffered current time
 
library ieee;
use ieee.std_logic_1164.all;
/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
23,7 → 23,8
--
-- VHDL Units : o8_sdlc_if
-- Description: Provides a full memory-mapped SDLC stack with automatic CRC16
-- Checksum insertion and integrity checking.
-- Checksum insertion and integrity checking. Note that this
-- entity ONLY provides packet framing and checksum calculation.
--
-- Transmit Memory Map
-- "0_0000_0000" (0x000) TX Buffer START
65,6 → 66,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/18/20 Added write qualification input
-- Seth Henry 11/01/20 Updated comments regarding SDLC support
 
library ieee;
use ieee.std_logic_1164.all;
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
22,8 → 22,8
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_sys_timer
-- Description: Provides an 8-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU.
-- Description: Provides an 8-bit milli/microsecond resolution timer for
-- : generating periodic interrupts for the Open8 CPU.
--
--
-- Revision History
35,6 → 35,7
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
-- Seth Henry 11/01/20 Changed description to note different resolutions
 
library ieee;
use ieee.std_logic_1164.all;

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