URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 277 to Rev 278
- ↔ Reverse comparison
Rev 277 → Rev 278
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.50 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// Revision 1.49 2003/01/21 12:09:40 mohor |
// When receiving normal data frame and RxFlow control was switched on, RXB |
// interrupt was not set. |
486,9 → 489,6
wire [7:0] TempTxBDAddress; |
wire [7:0] TempRxBDAddress; |
|
wire SetGotData; |
wire GotDataEvaluate; |
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wire RxStatusWrite; |
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reg WB_ACK_O; |
935,7 → 935,7
if(Reset) |
ReadTxDataFromMemory <=#Tp 1'b0; |
else |
if(TxLengthEq0 | TxAbortPacket | TxRetryPacket) |
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) |
ReadTxDataFromMemory <=#Tp 1'b0; |
else |
if(SetReadTxDataFromMemory) |
944,9 → 944,8
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reg tx_burst_en; |
reg rx_burst_en; |
reg BlockingLastReadOn_Abort_Retry; |
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wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry; |
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory; |
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en; |
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wire [31:0] TxData_wb; |
957,7 → 956,7
if(Reset) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket))) |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))) |
BlockReadTxDataFromMemory <=#Tp 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) |
965,21 → 964,6
end |
|
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b0; |
else |
if(TxAbortPacket | TxRetryPacket) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b0; |
else |
if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b1; |
end |
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|
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
1271,7 → 1255,7
if(TxStartFrm_sync2) |
TxStartFrm <=#Tp 1'b1; |
else |
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort)) |
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) |
TxStartFrm <=#Tp 1'b0; |
end |
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk |
1425,8 → 1409,8
if(Reset) |
TxAbortPacket <=#Tp 1'b0; |
else |
if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked | |
TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked) |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket <=#Tp 1'b1; |
else |
TxAbortPacket <=#Tp 1'b0; |
1441,8 → 1425,8
if(TxEn & TxEn_q & TxAbortPacket_NotCleared) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished | |
TxAbort_wb & !MasterWbTX) |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket_NotCleared <=#Tp 1'b1; |
end |
|
1482,8 → 1466,8
if(StartTxBDRead) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished | |
TxRetry_wb & !MasterWbTX) |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket_NotCleared <=#Tp 1'b1; |
end |
|
1523,8 → 1507,8
if(TxEn & TxEn_q & TxDonePacket_NotCleared) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished | |
TxDone_wb & !MasterWbTX) |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) | |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked)) |
TxDonePacket_NotCleared <=#Tp 1'b1; |
end |
|
1542,15 → 1526,6
end |
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// Sinchronizing and evaluating tx data |
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I; |
assign SetGotData = (TxStartFrm_wb); |
|
// Evaluating data. If abort or retry occured meanwhile than data is ignored. |
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm)); |
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm)); |
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// Indication of the last word |
always @ (posedge MTxClk or posedge Reset) |
begin |