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Rev 277 → Rev 278

/trunk/syn/t8048/b5x300/compile_project.tcl
0,0 → 1,46
##############################################################################
#
# Generic project compile script
#
# $Id: compile_project.tcl,v 1.1 2008-04-12 21:27:07 arniml Exp $
#
# Execute from within xtclsh.
#
# Environment variables:
# $MODULE : Name of the toplevel project
# -> mandatory <-
# $BLD : Build directory where the project and all temporary files
# are stored
# -> optional, default is "bld" <-
#
##############################################################################
 
# mandatory environment variable for project name: $MODULE
if {[info exists env(MODULE)]} {
set PROJECT $env(MODULE)
puts "Info: Setting project name from \$MODULE: $PROJECT"
} else {
puts "Error: Environment variable MODULE not set."
exit 1
}
 
# optional environment variable for build directory: $BLD
# default is 'bld'
puts -nonewline "Info: "
if {[info exists env(BLD)]} {
set bld $env(BLD)
puts -nonewline "Setting build directory from \$BLD"
} else {
set bld bld
puts -nonewline "Setting build directory to default"
}
puts ": $bld"
 
cd $bld
 
project open $PROJECT.ise
 
puts "Starting design implementation..."
process run "Generate Programming File"
 
project close
/trunk/syn/t8048/b5x300/t48_rom.hex
0,0 → 1,2
:0700000023FF39D3010402C4
:00000001FF
/trunk/syn/t8048/b5x300/gen_ise_project.tcl
0,0 → 1,160
###############################################################################
#
# $Id: gen_ise_project.tcl,v 1.1 2008-04-12 21:27:07 arniml Exp $
#
# Based on
# Created by Phil Hays, Xilinx
# Setup Xilinx environment, then run from Unix with "xtclsh dice.tcl"
#
# This Tcl script will implement a design and load it in the S3E FPGA on
# the Spartan 3E Starter Kit Board
#
# There are two ucf files, one for pins and one for timing
#
###############################################################################
# Contact : e-mail hotline@xilinx.com
# phone + 1 800 255 7778
#
# Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
# provided to you "as is". Xilinx and its licensors make and you
# receive no warranties or conditions, express, implied,
# statutory or otherwise, and Xilinx specifically disclaims any
# implied warranties of merchantability, non-infringement, or
# fitness for a particular purpose. Xilinx does not warrant that
# the functions contained in these designs will meet your
# requirements, or that the operation of these designs will be
# uninterrupted or error free, or that defects in the Designs
# will be corrected. Furthermore, Xilinx does not warrant or
# make any representations regarding use or the results of the
# use of the designs in terms of correctness, accuracy,
# reliability, or otherwise.
#
# LIMITATION OF LIABILITY. In no event will Xilinx or its
# licensors be liable for any loss of data, lost profits, cost
# or procurement of substitute goods or services, or for any
# special, incidental, consequential, or indirect damages
# arising from the use or operation of the designs or
# accompanying documentation, however caused and on any theory
# of liability. This limitation will apply even if Xilinx
# has been advised of the possibility of such damage. This
# limitation shall apply not-withstanding the failure of the
# essential purpose of any limited remedies herein.
#
# Copyright (c) 2006 Xilinx, Inc.
# All rights reserved
#
###############################################################################
# Version 1.0 - 19-Oct-2006
# Initial version
###############################################################################
 
###############################################################################
# MAIN
###############################################################################
# Modify the project settings for the specific design
#
# Make sure there are no files in the build directory that you may want to
# keep, as this TCL script cleans that directory by default!
###############################################################################
 
# mandatory environment variable for project name: $MODULE
if {[info exists env(MODULE)]} {
set PROJECT $env(MODULE)
puts "Info: Setting project name from \$MODULE: $PROJECT"
} else {
puts "Error: Environment variable MODULE not set."
exit 1
}
 
# optional environment variable for build directory: $BLD
# default is 'bld'
puts -nonewline "Info: "
if {[info exists env(BLD)]} {
set bld $env(BLD)
puts -nonewline "Setting build directory from \$BLD"
} else {
set bld bld
puts -nonewline "Setting build directory to default"
}
puts ": $bld"
 
# optional environment variable for source file compile list: $COMPILE_LIST
# default is 'compile_list'
puts -nonewline "Info: "
if {[info exists env(COMPILE_LIST)]} {
set compile_list $env(COMPILE_LIST)
puts -nonewline "Setting source file compile list from \$COMPILE_LIST"
} else {
set compile_list compile_list
puts -nonewline "Setting source file compile list to default"
}
puts ": $compile_list"
 
if {[file exists $bld]} {
puts "Deleting all existing project files in '$bld'"
# Perhaps ask ok here??
# Or perhaps skip project creation if project exists??
file delete -force $bld
}
puts "Creating new project directory in '$bld'..."
file mkdir $bld
 
###############################################################################
# Put two ucf file into one.
# This could be made as complex as required, however for demonstration it is
# just a simple copy.
###############################################################################
 
puts "Creating new UCF file..."
 
set tempucf [file join $bld temp.ucf]
set outfile [open $tempucf "w"]
set infile [open "t8048.ucf" "r"]
while {![eof $infile]} {
puts $outfile [gets $infile]
}
close $infile
close $outfile
#
puts "Creating new ISE project..."
cd $bld
project new $PROJECT.ise
project set family spartan2e
project set device xc2s300e
project set package pq208
project set speed -6
 
 
###############################################################################
# Modify the xfile add argument for the source files in the design
###############################################################################
 
puts "Adding source files..."
set infile [open "../compile_list" "r"]
while {![eof $infile]} {
xfile add "../[gets $infile]"
}
xfile add temp.ucf
 
 
###############################################################################
# Set optional implementation options here. There is a problem with setting
# project properties that at least one source must be added to the project
# first. Therefore, the "project set" commands are after the "xfile add"
# commands.
###############################################################################
 
puts "Setting project properties..."
 
project set {Optimization Goal} Area -process {Synthesize - XST}
project set {Optimization Effort} Normal -process {Synthesize - XST}
#project set "Map Effort Level" High
#project set {Perform Timing-Driven Packing and Placement} 1
project set {Place & Route Effort Level (Overall)} Standard
#project set "Other Place & Route Command Line Options" "-intsyle xflow"
project set {Generate Post-Place & Route Static Timing Report} true
project set {Report Uncovered Paths} 10 -process {Generate Post-Place & Route Static Timing}
project set {Report Type} {Verbose Report} -process {Generate Post-Place & Route Static Timing}
project set {Create Binary Configuration File} 1 -process {Generate Programming File}
 
project close
/trunk/syn/t8048/b5x300/compile_list
0,0 → 1,32
../../../rtl/vhdl/t48_pack-p.vhd
../../../rtl/vhdl/psw.vhd
../../../rtl/vhdl/pmem_ctrl_pack-p.vhd
../../../rtl/vhdl/pmem_ctrl.vhd
../../../rtl/vhdl/p2.vhd
../../../rtl/vhdl/p1.vhd
../../../rtl/vhdl/timer.vhd
../../../rtl/vhdl/dmem_ctrl_pack-p.vhd
../../../rtl/vhdl/dmem_ctrl.vhd
../../../rtl/vhdl/decoder_pack-p.vhd
../../../rtl/vhdl/opc_table.vhd
../../../rtl/vhdl/cond_branch_pack-p.vhd
../../../rtl/vhdl/alu_pack-p.vhd
../../../rtl/vhdl/t48_comp_pack-p.vhd
../../../rtl/vhdl/opc_decoder.vhd
../../../rtl/vhdl/int.vhd
../../../rtl/vhdl/t48_tb_pack-p.vhd
../../../rtl/vhdl/decoder.vhd
../../../rtl/vhdl/db_bus.vhd
../../../rtl/vhdl/cond_branch.vhd
../../../rtl/vhdl/clock_ctrl.vhd
../../../rtl/vhdl/bus_mux.vhd
../../../rtl/vhdl/alu.vhd
../../../rtl/vhdl/t48_core.vhd
../../../rtl/vhdl/system/generic_ram_ena.vhd
t48_rom.vhd
../../../rtl/vhdl/system/t48_rom-e.vhd
../../../rtl/vhdl/system/t48_rom-struct-a.vhd
../../../rtl/vhdl/t48_core_comp_pack-p.vhd
../../../rtl/vhdl/system/t8048_notri.vhd
../../../rtl/vhdl/system/t48_system_comp_pack-p.vhd
../../../rtl/vhdl/system/t8048.vhd
/trunk/syn/t8048/b5x300/t8048.ucf
0,0 → 1,54
#NET "reset_n_i" LOC = "P187";
#NET "xtal_i" LOC = "P185";
NET "xtal_i" TNM_NET = "xtal_i";
TIMESPEC "TS_xtal_i" = PERIOD "xtal_i" 90 ns HIGH 50 %;
 
#PINLOCK_BEGIN
 
#Fri Apr 30 18:23:21 2004
 
#PINLOCK_END
#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "ale_o" LOC = "P205" ;
NET "db_b<0>" LOC = "P133" ;
NET "db_b<1>" LOC = "P134" ;
NET "db_b<2>" LOC = "P135" ;
NET "db_b<3>" LOC = "P136" ;
NET "db_b<4>" LOC = "P138" ;
NET "db_b<5>" LOC = "P139" ;
NET "db_b<6>" LOC = "P140" ;
NET "db_b<7>" LOC = "P141" ;
NET "ea_i" LOC = "P206" ;
NET "int_n_i" LOC = "P3" ;
NET "p1_b<0>" LOC = "P82" ;
NET "p1_b<1>" LOC = "P83" ;
NET "p1_b<2>" LOC = "P84" ;
NET "p1_b<3>" LOC = "P86" ;
NET "p1_b<4>" LOC = "P87" ;
NET "p1_b<5>" LOC = "P88" ;
NET "p1_b<6>" LOC = "P89" ;
NET "p1_b<7>" LOC = "P93" ;
NET "p2_b<0>" LOC = "P94" ;
NET "p2_b<1>" LOC = "P95" ;
NET "p2_b<2>" LOC = "P96" ;
NET "p2_b<3>" LOC = "P97" ;
NET "p2_b<4>" LOC = "P98" ;
NET "p2_b<5>" LOC = "P99" ;
NET "p2_b<6>" LOC = "P100" ;
NET "p2_b<7>" LOC = "P101" ;
NET "prog_n_o" LOC = "P202" ;
NET "psen_n_o" LOC = "P204" ;
NET "rd_n_o" LOC = "P203" ;
NET "reset_n_i" LOC = "P57" ;
NET "t0_b" LOC = "P181" ;
NET "t1_i" LOC = "P200" ;
NET "wr_n_o" LOC = "P201" ;
NET "xtal_i" LOC = "P77" ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
/trunk/syn/t8048/b5x300/t48_rom.vhd
0,0 → 1,37
-- This file was generated with hex2rom written by Daniel Wallner
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity rom_t48 is
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t48;
 
architecture rtl of rom_t48 is
signal A_r : std_logic_vector(9 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
A_r <= A;
end if;
end process;
process (A_r)
begin
case to_integer(unsigned(A_r)) is
when 000000 => D <= "00100011"; -- 0x0000
when 000001 => D <= "11111111"; -- 0x0001
when 000002 => D <= "00111001"; -- 0x0002
when 000003 => D <= "11010011"; -- 0x0003
when 000004 => D <= "00000001"; -- 0x0004
when 000005 => D <= "00000100"; -- 0x0005
when 000006 => D <= "00000010"; -- 0x0006
when others => D <= "--------";
end case;
end process;
end;
/trunk/syn/t8048/b5x300/Makefile
0,0 → 1,42
##############################################################################
#
# Generic Makefile for ISE projects
#
# $Id: Makefile,v 1.1 2008-04-12 21:27:07 arniml Exp $
#
# Execute with 'make <target>', where target is one of
# ise : build ISE project from
# - files in compile_list
# - project settings in timing.ucf and <board>.ucf
# - project settings applied in gen_ise_project.tcl
# compile : compile ISE project by means of tcl script
# compile_project.tcl
# <blank> | all : run through all targets above
#
##############################################################################
 
export MODULE := t8048
 
export COMPILE_LIST := compile_list
SOURCE_FILES := $(shell cat $(COMPILE_LIST))
export BLD := bld
 
.PHONY: all
all: $(BLD)/$(MODULE).bit
 
.PHONY: ise
ise: $(BLD)/$(MODULE).ise
 
.PHONY: compile
compile: $(BLD)/$(MODULE).bit
 
$(BLD)/$(MODULE).ise: $(COMPILE_LIST) *.ucf gen_ise_project.tcl
xtclsh gen_ise_project.tcl
 
$(BLD)/$(MODULE).bit: $(SOURCE_FILES) $(BLD)/$(MODULE).ise compile_project.tcl
xtclsh compile_project.tcl
touch $@
 
.PHONY: clean
clean:
rm -rf *~ bld
/trunk/syn/t8048/jopcyc/t48_rom.hex
0,0 → 1,2
:0700000023FF39D3010402C4
:00000001FF
/trunk/syn/t8048/jopcyc/t8048.qsf
0,0 → 1,73
set_global_assignment -name TOP_LEVEL_ENTITY t8048
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# t8048_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:20:14 MAY 08, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/pmem_ctrl_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/cond_branch_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/decoder_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/dmem_ctrl_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/alu_pack-p.vhd"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/alu.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/bus_mux.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/clock_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/cond_branch.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/db_bus.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/opc_table.vhd
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/opc_decoder.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/decoder.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/dmem_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/int.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/p1.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/p2.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/pmem_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/psw.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/timer.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t48_core.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/generic_ram_ena.vhd
set_global_assignment -name VHDL_FILE t48_rom.vhd
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_rom-e.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_rom-struct-a.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_core_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t8048_notri.vhd
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_system_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t8048.vhd
 
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name VHDL_INPUT_VERSION VHDL87
 
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name FMAX_REQUIREMENT "11 MHz" -section_id xtal
set_instance_assignment -name CLOCK_SETTINGS xtal -to xtal_i
/trunk/syn/t8048/jopcyc/t48_rom.vhd
0,0 → 1,37
-- This file was generated with hex2rom written by Daniel Wallner
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity rom_t48 is
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t48;
 
architecture rtl of rom_t48 is
signal A_r : std_logic_vector(9 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
A_r <= A;
end if;
end process;
process (A_r)
begin
case to_integer(unsigned(A_r)) is
when 000000 => D <= "00100011"; -- 0x0000
when 000001 => D <= "11111111"; -- 0x0001
when 000002 => D <= "00111001"; -- 0x0002
when 000003 => D <= "11010011"; -- 0x0003
when 000004 => D <= "00000001"; -- 0x0004
when 000005 => D <= "00000100"; -- 0x0005
when 000006 => D <= "00000010"; -- 0x0006
when others => D <= "--------";
end case;
end process;
end;
/trunk/syn/t8048/jopcyc/t8048.qpf
0,0 → 1,29
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
 
 
 
QUARTUS_VERSION = "4.1"
DATE = "22:42:11 December 02, 2004"
 
 
# Revisions
 
PROJECT_REVISION = "t8048"

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