URL
https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk
Subversion Repositories adv_debug_sys
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/adv_debug_sys/trunk/Software/adv_jtag_bridge/adv_dbg_commands.c
123,7 → 123,7
debug("selreg %ld\n", regidx); |
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// If this reg is already selected, don't do a JTAG transaction |
if(current_reg_idx[current_chain] == regidx) |
if((current_chain >= 0) && (current_reg_idx[current_chain] == regidx)) |
return APP_ERR_NONE; |
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switch(current_chain) { |
/adv_debug_sys/trunk/Software/adv_jtag_bridge/dbg_api.c
159,11 → 159,11
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int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
192,11 → 192,11
// Never actually called from the GDB interface |
int dbg_wb_read_block16(unsigned long adr, uint16_t *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
224,11 → 224,11
// Never actually called from the GDB interface |
int dbg_wb_read_block8(unsigned long adr, uint8_t *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
251,15 → 251,14
} |
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|
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// write a block to wishbone |
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
289,11 → 288,11
// Never actually called from the GDB interface |
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
321,11 → 320,11
// write a block to wishbone |
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(!len) |
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported |
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pthread_mutex_lock(&dbg_access_mutex); |
if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
if ((err = adbg_select_module(DC_WISHBONE))) |
379,10 → 378,10
/* read multiple registers from cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */ |
int dbg_cpu0_read_block(unsigned long adr, unsigned long *data, int count) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
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if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
pthread_mutex_lock(&dbg_access_mutex); |
if ((err = adbg_select_module(DC_CPU0))) |
{ |
cable_flush(); |
390,6 → 389,8
return err; |
} |
err = adbg_wb_burst_read(4, count, adr, (void *) data); // All CPU register reads / writes are bursts |
cable_flush(); |
pthread_mutex_unlock(&dbg_access_mutex); |
} |
else if(DEBUG_HARDWARE == DBG_HW_LEGACY) |
{ |
400,8 → 401,7
err |= dbg_cpu0_read(readaddr++, &data[i]); |
} |
} |
cable_flush(); |
pthread_mutex_unlock(&dbg_access_mutex); |
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debug("dbg_cpu_read_block(), addr 0x%X, count %i, data[0] = 0x%X\n", adr, count, data[0]); |
return err; |
} |
437,10 → 437,10
/* write multiple cpu registers to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */ |
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count) { |
int err; |
pthread_mutex_lock(&dbg_access_mutex); |
|
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if(DEBUG_HARDWARE == DBG_HW_ADVANCED) |
{ |
pthread_mutex_lock(&dbg_access_mutex); |
if ((err = adbg_select_module(DC_CPU0))) |
{ |
cable_flush(); |
448,6 → 448,8
return err; |
} |
err = adbg_wb_burst_write((void *)data, 4, count, adr); |
cable_flush(); |
pthread_mutex_unlock(&dbg_access_mutex); |
} |
else if(DEBUG_HARDWARE == DBG_HW_LEGACY) |
{ |
459,8 → 461,7
} |
} |
debug("cpu0_write_block, adr 0x%X, data[0] 0x%X, count %i, ret %i\n", adr, data[0], count, err); |
cable_flush(); |
pthread_mutex_unlock(&dbg_access_mutex); |
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return err; |
} |
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