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https://opencores.org/ocsvn/can/can/trunk
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Rev 28 → Rev 29
/trunk/bench/verilog/can_testbench.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.20 2003/02/09 02:24:11 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.19 2003/02/04 17:24:33 mohor |
// Backup. |
// |
279,9 → 283,9
|
task manual_frame; // Testbench sends a frame |
begin |
/* |
begin |
|
begin |
/* |
$display("\n\nTestbench sends a frame bit by bit"); |
send_bit(0); // SOF |
send_bit(1); // ID |
347,23 → 351,23
send_bit(1); // IDLE |
send_bit(1); // IDLE |
send_bit(1); // IDLE |
*/ |
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8 |
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7 |
write_register(8'd12, 8'h00); // data byte 1 |
write_register(8'd13, 8'h00); // data byte 2 |
write_register(8'd14, 8'h00); // data byte 3 |
write_register(8'd15, 8'h00); // data byte 4 |
write_register(8'd16, 8'h00); // data byte 5 |
write_register(8'd17, 8'h00); // data byte 6 |
write_register(8'd18, 8'h00); // data byte 7 |
write_register(8'd19, 8'h00); // data byte 8 |
end |
|
*/ |
// tx_bypassed=1; |
|
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8 |
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7 |
write_register(8'd12, 8'h00); // data byte 1 |
write_register(8'd13, 8'h00); // data byte 2 |
write_register(8'd14, 8'h00); // data byte 3 |
write_register(8'd15, 8'h00); // data byte 4 |
write_register(8'd16, 8'h00); // data byte 5 |
write_register(8'd17, 8'h00); // data byte 6 |
write_register(8'd18, 8'h00); // data byte 7 |
write_register(8'd19, 8'h00); // data byte 8 |
|
fork |
begin |
tx_request; |
416,13 → 420,44
send_bit(1); // EOF |
send_bit(1); // EOF |
// tx_bypassed=1; |
send_bit(0); // INTER |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER |
send_bit(1); // INTER |
send_bit(1); // INTER |
send_bit(0); // IDLE |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(1); // INTER overload |
send_bit(0); // INTER waiting for recessive |
send_bit(0); // INTER waiting for recessive |
send_bit(0); // INTER waiting for recessive |
send_bit(0); // INTER waiting for recessive |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // INTER overload delim |
send_bit(1); // IDLE |
send_bit(1); // IDLE |
send_bit(1); // IDLE |
send_bit(1); // IDLE |
|
end |
|
/trunk/rtl/verilog/can_btl.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.10 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.9 2003/01/31 01:13:38 mohor |
// backup. |
// |
114,7 → 118,8
|
/* Output from can_bsp module */ |
rx_idle, |
transmitting |
transmitting, |
last_bit_of_inter |
|
|
|
143,6 → 148,7
/* Output from can_bsp module */ |
input rx_idle; |
input transmitting; |
input last_bit_of_inter; |
|
/* Output signals from this module */ |
output clk_en; |
179,8 → 185,8
|
|
assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2 |
assign hard_sync = rx_idle & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization |
assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization |
assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization |
assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization |
|
|
/* Generating general enable signal that defines baud rate. */ |
/trunk/rtl/verilog/can_top.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.11 2003/02/04 14:34:52 mohor |
// *** empty log message *** |
// |
280,6 → 284,7
/* output from can_bsp module */ |
wire rx_idle; |
wire transmitting; |
wire last_bit_of_inter; |
|
|
|
314,7 → 319,8
|
/* output from can_bsp module */ |
.rx_idle(rx_idle), |
.transmitting(transmitting) |
.transmitting(transmitting), |
.last_bit_of_inter(last_bit_of_inter) |
|
|
|
351,6 → 357,7
/* output from can_bsp module */ |
.rx_idle(rx_idle), |
.transmitting(transmitting), |
.last_bit_of_inter(last_bit_of_inter), |
|
/* This section is for BASIC and EXTENDED mode */ |
/* Acceptance code register */ |
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.17 2003/02/04 17:24:41 mohor |
// Backup. |
// |
139,6 → 143,7
|
rx_idle, |
transmitting, |
last_bit_of_inter, |
|
/* This section is for BASIC and EXTENDED mode */ |
/* Acceptance code register */ |
205,7 → 210,9
|
output rx_idle; |
output transmitting; |
output last_bit_of_inter; |
|
|
/* This section is for BASIC and EXTENDED mode */ |
/* Acceptance code register */ |
input [7:0] acceptance_code_0; |
297,7 → 304,10
reg enable_error_cnt2; |
reg [2:0] error_cnt1; |
reg [2:0] error_cnt2; |
reg [2:0] error_delayed_dominant_cnt; |
reg [2:0] delayed_dominant_cnt; |
reg enable_overload_cnt2; |
reg [2:0] overload_cnt1; |
reg [2:0] overload_cnt2; |
reg tx; |
reg crc_err; |
|
382,13 → 392,13
wire bit_err; |
wire ack_err; |
wire stuff_err; |
// of intermission, it starts reading the identifier (and transmitting its own). |
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to |
// be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!! |
// of intermission, it starts reading the identifier (and transmitting its own). |
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to |
// be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!! |
|
wire id_ok; // If received ID matches ID set in registers |
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter. |
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter. |
wire id_ok; // If received ID matches ID set in registers |
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter. |
wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter. |
|
wire [2:0] header_len; |
wire storing_header; |
427,13 → 437,12
wire bit_err_exc2; |
wire bit_err_exc3; |
wire bit_err_exc4; |
//wire enable_cnt_active_station; |
//wire enable_cnt_passive_station; |
wire error_flag_over; |
wire overload_flag_over; |
|
|
assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); |
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2)); |
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter; |
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter); |
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10); |
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1; |
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit; |
448,15 → 457,15
assign go_rx_ack = sample_point & rx_crc_lim; |
assign go_rx_ack_lim = sample_point & rx_ack; |
assign go_rx_eof = sample_point & rx_ack_lim | (~reset_mode) & reset_mode_q; |
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended) & (~go_overload_frame) & (~overload_frame); |
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~go_overload_frame); |
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof)); |
assign error_frame_ended = (error_cnt2 == 7) & tx_point; |
assign overload_frame_ended = error_frame_ended & (~error_frame_q); |
assign overload_frame_ended = (overload_cnt2 == 7) & tx_point; |
|
assign go_overload_frame = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended) & overload_needed | |
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) | |
sample_point & (~sampled_bit) & (error_cnt2 == 7) |
assign go_overload_frame = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed | |
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) | |
sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7)) |
; |
|
|
474,10 → 483,11
assign bit_err_exc1 = tx_state & arbitration_field & tx; |
assign bit_err_exc2 = rx_ack & tx; |
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7); |
assign bit_err_exc4 = (error_frame | overload_frame) & (error_cnt1 == 7) & (~enable_error_cnt2); |
assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2)); |
|
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2; |
|
assign last_bit_of_inter = rx_inter & (bit_cnt == 2); |
|
|
// Rx idle state |
930,7 → 940,9
rule5 <= 1'b0; |
else if (reset_mode | error_flag_over) |
rule5 <=#Tp 1'b0; |
else if ((error_frame | overload_frame) & (~node_error_passive) & (error_cnt1 < 7) & bit_err & (~bit_err_latched)) |
else if ((~node_error_passive) & bit_err & (~bit_err_latched) & (error_frame & (error_cnt1 < 7) | |
overload_frame & (overload_cnt1 < 7) ) |
) |
rule5 <=#Tp 1'b1; |
end |
|
1049,7 → 1061,7
/* End: This section is for EXTENDED mode */ |
|
.go_rx_crc_lim(go_rx_crc_lim), |
.go_rx_idle(go_rx_idle), |
.go_rx_inter(go_rx_inter), |
|
.data0(tmp_fifo[0]), |
.data1(tmp_fifo[1]), |
1179,7 → 1191,7
); |
|
|
// Transmitting error frame. The same counters are used for sending overload frame, too. |
// Transmitting error frame. |
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
1204,25 → 1216,13
end |
|
|
// Transmitting error frame. The same counters are used for sending overload frame, too. |
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
overload_frame <= 1'b0; |
else if (reset_mode | overload_frame_ended) |
overload_frame <=#Tp 1'b0; |
else if (go_overload_frame) |
overload_frame <=#Tp 1'b1; |
end |
|
|
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
error_cnt1 <= 1'b0; |
else if (reset_mode | error_frame_ended | go_error_frame) |
error_cnt1 <=#Tp 1'b0; |
else if ((error_frame | overload_frame) & tx_point & (error_cnt1 < 7)) |
else if (error_frame & tx_point & (error_cnt1 < 7)) |
error_cnt1 <=#Tp error_cnt1 + 1'b1; |
end |
|
1249,7 → 1249,7
enable_error_cnt2 <= 1'b0; |
else if (reset_mode | error_frame_ended | go_error_frame) |
enable_error_cnt2 <=#Tp 1'b0; |
else if ((error_frame | overload_frame) & (error_flag_over & (~enable_error_cnt2) & sampled_bit)) |
else if (error_frame & (error_flag_over & (~enable_error_cnt2) & sampled_bit)) |
enable_error_cnt2 <=#Tp 1'b1; |
end |
|
1268,11 → 1268,11
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
error_delayed_dominant_cnt <= 0; |
else if (reset_mode | enable_error_cnt2 | go_error_frame) |
error_delayed_dominant_cnt <=#Tp 0; |
else if (sample_point & (~sampled_bit) & (error_cnt1 == 7)) |
error_delayed_dominant_cnt <=#Tp error_delayed_dominant_cnt + 1'b1; |
delayed_dominant_cnt <= 0; |
else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame) |
delayed_dominant_cnt <=#Tp 0; |
else if (sample_point & (~sampled_bit) & ((error_cnt1 == 7) | (overload_cnt1 == 7))) |
delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1; |
end |
|
|
1293,6 → 1293,55
end |
|
|
|
// Transmitting overload frame. |
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
overload_frame <= 1'b0; |
else if (reset_mode | overload_frame_ended | go_error_frame) |
overload_frame <=#Tp 1'b0; |
else if (go_overload_frame) |
overload_frame <=#Tp 1'b1; |
end |
|
|
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
overload_cnt1 <= 1'b0; |
else if (reset_mode | overload_frame_ended | go_error_frame) |
overload_cnt1 <=#Tp 1'b0; |
else if (overload_frame & tx_point & (overload_cnt1 < 7)) |
overload_cnt1 <=#Tp overload_cnt1 + 1'b1; |
end |
|
|
assign overload_flag_over = sample_point & (overload_cnt1 == 7); |
|
|
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
enable_overload_cnt2 <= 1'b0; |
else if (reset_mode | overload_frame_ended | go_error_frame) |
enable_overload_cnt2 <=#Tp 1'b0; |
else if (overload_frame & (overload_flag_over & (~enable_overload_cnt2) & sampled_bit)) |
enable_overload_cnt2 <=#Tp 1'b1; |
end |
|
|
always @ (posedge clk or posedge rst) |
begin |
if (rst) |
overload_cnt2 <= 0; |
else if (reset_mode | overload_frame_ended | go_error_frame) |
overload_cnt2 <=#Tp 0; |
else if (enable_overload_cnt2 & tx_point) |
overload_cnt2 <=#Tp overload_cnt2 + 1'b1; |
end |
|
|
assign send_ack = (~tx_state) & rx_ack & (~err); |
|
|
1300,7 → 1349,7
begin |
if (rst) |
tx <= 1'b1; |
else if (reset_mode | error_frame_ended) // Reset |
else if (reset_mode | error_frame_ended | overload_frame_ended) // Reset |
tx <=#Tp 1'b1; |
else if (tx_point) |
begin |
1308,18 → 1357,25
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q)); |
else if (send_ack) // Acknowledge |
tx <=#Tp 1'b0; |
else if (error_frame | overload_frame) // Transmitting error frame |
else if (error_frame) // Transmitting error frame |
begin |
if (error_cnt1 < 6) |
begin |
if (node_error_passive & (~overload_frame)) |
if (node_error_passive) |
tx <=#Tp 1'b1; |
else |
tx <=#Tp 1'b0; |
end |
else if (error_cnt2 < 7) |
else |
tx <=#Tp 1'b1; |
end |
else if (overload_frame) // Transmitting overload frame |
begin |
if (overload_cnt1 < 6) |
tx <=#Tp 1'b0; |
else |
tx <=#Tp 1'b1; |
end |
else |
tx <=#Tp 1'b1; |
end |
1436,7 → 1492,7
|
|
|
assign go_early_tx = need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2)); |
assign go_early_tx = need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter); |
assign go_tx = need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle); |
|
|
1496,7 → 1552,7
susp_cnt_en <= 0; |
else if (reset_mode | (sample_point & (susp_cnt == 7))) |
susp_cnt_en <=#Tp 0; |
else if (suspend & sample_point & rx_inter & (bit_cnt == 2)) |
else if (suspend & sample_point & last_bit_of_inter) |
susp_cnt_en <=#Tp 1'b1; |
end |
|
1551,7 → 1607,7
rx_err_cnt <=#Tp rx_err_cnt + 1'b1; |
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2 |
(go_error_frame_q & rule5 ) | // 5 |
(error_frame & sample_point & (~sampled_bit) & (error_delayed_dominant_cnt == 7) ) // 6 |
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6 |
) |
rx_err_cnt <=#Tp rx_err_cnt + 4'h8; |
end |
1576,7 → 1632,7
begin |
if ((tx_err_cnt < 1023) & transmitter) |
begin |
if ( (sample_point & (~sampled_bit) & (error_delayed_dominant_cnt == 7) ) | // 6 |
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6 |
(error_flag_over & (~error_flag_over_blocked) & rule5 ) | // 4 (rule 5 is the same as rule 4) |
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3 |
) |
/trunk/rtl/verilog/can_acf.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.3 2003/01/31 01:13:37 mohor |
// backup. |
// |
91,7 → 95,7
acceptance_mask_3, |
|
go_rx_crc_lim, |
go_rx_idle, |
go_rx_inter, |
|
data0, |
data1, |
125,7 → 129,7
input [7:0] acceptance_mask_2; |
input [7:0] acceptance_mask_3; |
input go_rx_crc_lim; |
input go_rx_idle; |
input go_rx_inter; |
input [7:0] data0; |
input [7:0] data1; |
input rtr1; |
328,9 → 332,9
begin |
if (acceptance_filter_mode) // dual filter |
begin |
if (ide) // extended frame message |
if (ide) // extended frame message |
id_ok <=#Tp match_df_ext; |
else // standard frame message |
else // standard frame message |
id_ok <=#Tp match_df_std; |
end |
else // single filter |
344,7 → 348,7
else |
id_ok <=#Tp match; |
end |
else if (reset_mode | go_rx_idle) // sample_point is already included in go_rx_idle |
else if (reset_mode | go_rx_inter) // sample_point is already included in go_rx_inter |
id_ok <=#Tp 0; |
end |
|
/trunk/sim/rtl_sim/run/wave.do
116,8 → 116,8
define variable nofullpathfilenames |
include bookmark with filenames |
include scope history without filenames |
define waveform window listpane 9.40 |
define waveform window namepane 13.34 |
define waveform window listpane 8.96 |
define waveform window namepane 14.36 |
define multivalueindication |
define pattern curpos dot |
define pattern cursor1 dot |
229,20 → 229,27
|
add group \ |
can_bsp \ |
can_testbench.i_can_top.i_can_bsp.ack_err_latched \ |
can_testbench.i_can_top.i_can_bsp.bit_err_latched \ |
can_testbench.i_can_top.i_can_bsp.form_err_latched \ |
can_testbench.i_can_top.i_can_bsp.stuff_err_latched \ |
can_testbench.i_can_top.i_can_bsp.crc_err \ |
can_testbench.i_can_top.i_can_bsp.ack_err \ |
can_testbench.i_can_top.i_can_bsp.bit_err \ |
can_testbench.i_can_top.i_can_bsp.crc_err \ |
can_testbench.i_can_top.i_can_bsp.form_err \ |
can_testbench.i_can_top.i_can_bsp.stuff_err \ |
can_testbench.i_can_top.i_can_bsp.err \ |
can_testbench.i_can_top.i_can_bsp.bit_err_exc1 \ |
can_testbench.i_can_top.i_can_bsp.bit_err_exc2 \ |
can_testbench.i_can_top.i_can_bsp.bit_err_exc3 \ |
can_testbench.i_can_top.i_can_bsp.set_form_error \ |
can_testbench.i_can_top.i_can_btl.hard_sync \ |
can_testbench.i_can_top.i_can_btl.resync \ |
can_testbench.i_can_top.sampled_bit \ |
can_testbench.i_can_top.sampled_bit_q \ |
can_testbench.i_can_top.i_can_bsp.transmitting \ |
can_testbench.rx \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.i_can_bsp.tx_q \ |
can_testbench.i_can_top.i_can_bsp.tx_bit \ |
can_testbench.i_can_top.tx \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
can_testbench.i_can_top.i_can_bsp.tx_point \ |
274,15 → 281,32
can_testbench.i_can_top.i_can_bsp.data_for_fifo[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.data_len[3:0]'h \ |
can_testbench.i_can_top.i_can_bsp.data_out[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.overload_frame_ended \ |
can_testbench.i_can_top.i_can_bsp.transmitter \ |
can_testbench.i_can_top.i_can_bsp.arbitration_field \ |
can_testbench.i_can_top.i_can_bsp.sampled_bit \ |
can_testbench.i_can_top.i_can_bsp.priority_lost \ |
can_testbench.i_can_top.i_can_bsp.error_flag_over \ |
can_testbench.i_can_top.i_can_bsp.rx_err_cnt_blocked \ |
can_testbench.i_can_top.i_can_bsp.rule5 \ |
can_testbench.i_can_top.i_can_bsp.rule3_exc1_1 \ |
can_testbench.i_can_top.i_can_bsp.rule3_exc1_2 \ |
can_testbench.i_can_top.i_can_bsp.rule3_exc2 \ |
can_testbench.i_can_top.i_can_bsp.go_error_frame \ |
can_testbench.i_can_top.i_can_bsp.error_frame \ |
can_testbench.i_can_top.i_can_bsp.overload_frame \ |
can_testbench.i_can_top.i_can_bsp.enable_error_cnt2 \ |
can_testbench.i_can_top.i_can_bsp.passive_cnt[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.eof_cnt[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.wr_fifo \ |
can_testbench.i_can_top.i_can_bsp.error_cnt1[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.error_cnt2[2:0]'h \ |
can_testbench.i_can_top.i_can_bsp.error_frame \ |
can_testbench.i_can_top.i_can_bsp.error_frame_ended \ |
can_testbench.i_can_top.i_can_bsp.rx_inter \ |
can_testbench.i_can_top.i_can_bsp.node_error_passive \ |
can_testbench.i_can_top.i_can_bsp.rx_err_cnt[9:0]'h \ |
can_testbench.i_can_top.i_can_bsp.tx_err_cnt[9:0]'h \ |
can_testbench.i_can_top.i_can_bsp.rtr1 \ |
can_testbench.i_can_top.i_can_bsp.rtr2 \ |
can_testbench.i_can_top.i_can_bsp.priority_lost \ |
298,8 → 322,6
can_testbench.i_can_top.tx \ |
can_testbench.rx \ |
can_testbench.i_can_top.rx \ |
can_testbench.i_can_top.i_can_bsp.tx_q \ |
can_testbench.i_can_top.i_can_bsp.tx_bit \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
can_testbench.i_can_top.i_can_bsp.tx_point \ |
can_testbench.i_can_top.i_can_bsp.rx_ack \ |
327,7 → 349,6
can_testbench.i_can_top.i_can_bsp.go_early_tx \ |
can_testbench.i_can_top.i_can_bsp.go_tx \ |
can_testbench.i_can_top.i_can_bsp.need_to_tx \ |
can_testbench.i_can_top.i_can_bsp.tx_succesful \ |
can_testbench.i_can_top.i_can_bsp.tx_request \ |
can_testbench.i_can_top.i_can_bsp.clk \ |
can_testbench.i_can_top.i_can_bsp.tx_state \ |
512,4 → 533,4
|
|
open window waveform 1 geometry 10 59 1592 1140 |
zoom at 0(0)ns 0.00003371 0.00000000 |
zoom at 0(0)ns 0.00003462 0.00000000 |