OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 28 to Rev 29
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  •

Rev 28 → Rev 29

/trunk/rx_engine/rxStateMachine.v
74,19 → 74,19
end
else begin
case (rxstate)
IDLE: begin
IDLE: begin //5'b00000;
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
rxReceiveDA: begin
rxReceiveDA: begin //5'b00001
rxstate_next <=#TP rxReceiveLT;
end
rxReceiveLT: begin
rxReceiveLT: begin //5'b00010
rxstate_next <=#TP rxReceiveData;
end
rxReceiveData: begin
rxReceiveData: begin //5'b00100
if (local_invalid |length_error| get_error_code)
rxstate_next <=#TP rxGetError;
else if (get_terminator)
94,10 → 94,16
else
rxstate_next <=#TP rxReceiveData;
end
rxGetError: begin
rxGetError: begin //5'b01000
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
rxIFGWait : begin
rxIFGWait : begin //5'b10000;
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
endcase
131,7 → 137,7
always@(posedge rxclk or posedge reset) begin
if (reset)
wait_crc_check <=#TP 0;
else if (rxstate[3])
else if (rxstate[4])
wait_crc_check <=#TP 1'b1;
else if (crc_check_valid || crc_check_invalid||length_error)
wait_crc_check <=#TP 1'b0;
145,7 → 151,7
good_frame_get <=#TP 0;
end
else begin
bad_frame_get <=#TP rxstate[3] || crc_check_invalid || length_error;
bad_frame_get <=#TP rxstate[3] || crc_check_invalid || length_error ;
good_frame_get <=#TP crc_check_valid;
end
end
/trunk/rx_engine/rxDAchecker.v
53,6 → 53,6
end
end
 
assign local_invalid = ~local_valid & ~multi_valid & ~broad_valid;
assign local_invalid = 1'b0;//~local_valid & ~multi_valid & ~broad_valid;
 
endmodule
/trunk/rx_engine/crc_fast.v
0,0 → 1,149
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:15:03 01/15/06
// Design Name:
// Module Name: crc_fast
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crc_fast(clk, reset, init, calc, d_valid, data, crc_reg, bits_more_reg,part_crc);
input clk;
input reset;
input init;
input calc;
input d_valid;
input[63:0] data;
input[2:0] bits_more_reg;
output[31:0] crc_reg;
output[31:0] part_crc;
 
 
 
reg[31:0] crc_reg;//,crc_reg_tmp;
 
always @ (posedge clk or posedge reset)
begin
if (reset) begin
crc_reg <= 32'hFFFFFFFF;
end
else if (init) begin
crc_reg <= 32'hFFFFFFFF;
end
 
else if (calc & d_valid) begin
crc_reg <=full_crc(crc_reg, data);
end
else if (~calc & d_valid) begin
crc_reg <= {crc_reg[23:0], 8'hFF};
end
end
 
reg [31:0] part_crc;
always @ (posedge clk or posedge reset)
begin
if (reset) begin
part_crc <= 32'hFFFFFFFF;
end
else if (init) begin
part_crc <= 32'hFFFFFFFF;
end
 
else if (calc & d_valid) begin
case (bits_more_reg)
3'b001: part_crc <= next_crc32_data64(32'h00000000,{24'h00, (crc_reg^{data[63: 56], 24'h00}),8'h00});
3'b010: part_crc <= next_crc32_data64(32'h00000000,{16'h00, (crc_reg^{data[63: 48], 16'h00}),16'h0000});
3'b011: part_crc <= next_crc32_data64(32'h00000000,{8'h00, (crc_reg^{data[63: 40], 8'h00}), 24'h000000});
3'b100: part_crc <= next_crc32_data64(32'h00000000,{crc_reg^data[63: 32],32'h00000000});
3'b101: part_crc <= five_crc(crc_reg, data);
3'b110: part_crc <= six_crc(crc_reg, data);
3'b111: part_crc <= seven_crc(crc_reg, data);
3'b000: part_crc <= 32'hffffffff;
endcase
end
 
end
 
 
//
function[31:0] full_crc;
input[31:0] crc;
input[63:0] data;
reg[31:0] crc_reg_tmp;
begin
crc_reg_tmp = 32'hffffffff;
crc_reg_tmp = next_crc32_data64(32'h00000000,{crc^data[63:32], 32'h00000000});
full_crc = next_crc32_data64(32'h00000000,{crc_reg_tmp^data[31:0], 32'h00000000});
end
endfunction
 
function[31:0] five_crc;
input[31:0] crc;
input[63:0] data;
reg[31:0] crc_reg_tmp;
begin
crc_reg_tmp = 32'hffffffff;
crc_reg_tmp = next_crc32_data64(32'h00000000,{crc^data[63:32], 32'h00000000});
five_crc = next_crc32_data64(32'h00000000,{24'h00, (crc_reg_tmp^{data[31: 24], 24'h00}),8'h00});
end
endfunction
 
function[31:0] six_crc;
input[31:0] crc;
input[63:0] data;
reg[31:0] crc_reg_tmp;
begin
crc_reg_tmp = 32'hffffffff;
crc_reg_tmp = next_crc32_data64(32'h00000000,{crc^data[63:32], 32'h00000000});
six_crc = next_crc32_data64(32'h00000000,{16'h00, (crc_reg_tmp^{data[31: 16], 16'h00}),16'h0000});
end
endfunction
 
function[31:0] seven_crc;
input[31:0] crc;
input[63:0] data;
reg[31:0] crc_reg_tmp;
begin
crc_reg_tmp = 32'hffffffff;
crc_reg_tmp = next_crc32_data64(32'h00000000,{crc^data[63:32], 32'h00000000});
seven_crc = next_crc32_data64(32'h00000000,{8'h00, (crc_reg_tmp^{data[31: 8], 8'h00}), 24'h000000});
end
endfunction
 
 
 
function [31:0] next_crc32_data64;
input [31:0] crc;
input [63:0] inp;
integer i;
begin
next_crc32_data64 = crc;
for(i=0; i<64; i=i+1)
next_crc32_data64 = next_div32_data1(next_crc32_data64, inp[63-i]);
end
endfunction
//
function [31:0] next_div32_data1; // remainder of M(x)/P(x)
input [31:0] crc; // previous CRC value
input B; // input data bit (MSB first)
begin
next_div32_data1 ={crc[30:0],B}^({32{crc[31]}} & 32'b00000100110000010001110110110111);
// ^26 ^23^22 ^16 ^12 ^11 ^10 ^8 ^7 ^5 ^4 ^2 ^1 ^0
end
endfunction
 
endmodule
/trunk/rx_engine/rxReceiveEngine.ucf
0,0 → 1,24
#AREA_GROUP "AG_counters" RANGE = SLICE_X34Y37:SLICE_X41Y32
#INST "counters" AREA_GROUP = "AG_counters"
#AREA_GROUP "AG_crcmodule" RANGE = SLICE_X32Y21:SLICE_X49Y4
#INST "crcmodule" AREA_GROUP = "AG_crcmodule"
#AREA_GROUP "AG_datapath_main" RANGE = SLICE_X14Y35:SLICE_X29Y20
#INST "datapath_main" AREA_GROUP = "AG_datapath_main"
#AREA_GROUP "AG_lenchecker" RANGE = SLICE_X44Y37:SLICE_X51Y30
#INST "lenchecker" AREA_GROUP = "AG_lenchecker"
#AREA_GROUP "AG_rx_rs" RANGE = SLICE_X0Y31:SLICE_X9Y20
#INST "rx_rs" AREA_GROUP = "AG_rx_rs"
#AREA_GROUP "AG_rx_stat" RANGE = SLICE_X46Y27:SLICE_X49Y24
#INST "rx_stat" AREA_GROUP = "AG_rx_stat"
#AREA_GROUP "AG_statemachine" RANGE = SLICE_X34Y27:SLICE_X41Y24
#INST "statemachine" AREA_GROUP = "AG_statemachine"
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
#PACE: Start of PACE Area Constraints
AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
NET "rxclk_in" TNM_NET = "rxclk_in";
TIMESPEC "TS_rxclk_in" = PERIOD "rxclk_in" 6.5 ns HIGH 50 %;
#OFFSET = IN 2 ns BEFORE "rxclk_in" HIGH ;
/trunk/rx_engine/rxDataPath.v
19,11 → 19,11
//
//////////////////////////////////////////////////////////////////////////////////
 
`define START 8'hdf
`define TERMINATE 8'hbf
`define SFD 8'b11010101
`define SEQUENCE 8'h59
`define ERROR 8'h7f
`define START 8'hfb
`define TERMINATE 8'hfd
`define SFD 8'hd5
`define SEQUENCE 8'h9a
`define ERROR 8'hfe
`define ALLONES 8'hff
`define ALLZEROS 8'h00
 
32,7 → 32,7
 
module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,
get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,
rx_data_valid, rx_data);
rx_data_valid, rx_data,get_terminator_d1);
input rxclk;
input reset;
input [63:0] rxd64;
42,6 → 42,7
input start_da;
input start_lt;
input wait_crc_check;
input get_terminator_d1;
output get_sfd;
output get_terminator; //get T indicator
output get_error_code; //get Error indicator
58,7 → 59,7
//////////////////////////////////////////////
// Pipe Line Stage
//////////////////////////////////////////////
reg [63:0] rxd64_d1,rxd64_d2,CRC_DATA;
reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
reg receiving_d1, receiving_d2;
reg wait_crc_check_d1;
66,6 → 67,7
if (reset) begin
rxd64_d1<=#TP 0;
rxd64_d2<=#TP 0;
rxd64_d3<=#TP 0;
CRC_DATA<=0;
end
72,9 → 74,16
else begin
rxd64_d1<=#TP rxd64;
rxd64_d2<=#TP rxd64_d1;
CRC_DATA <={rxd64_d2[7:0],rxd64_d2[15:8],rxd64_d2[23:16],rxd64_d2[31:24],
rxd64_d2[39:32],rxd64_d2[47:40],rxd64_d2[55:48],rxd64_d2[63:56]};
end
rxd64_d3<=#TP rxd64_d2;
CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],
rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],
rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],
rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],
rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],
rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],
rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],
rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};
end
end
always @(posedge rxclk or posedge reset)begin
112,57 → 121,67
end
 
//2. EFD
reg this_cycle;
always@(posedge rxclk or posedge reset) begin
if (reset) begin
get_terminator <=#TP 0;
terminator_location <=#TP 0;
rxc_end_data <=#TP 0;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 0;
end
else begin
if (rxc8[0] & (rxd64[7:0] ==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 0;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00001111;
end
else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 1;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00011111;
end
else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 2;
terminator_location <=#TP 2;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00111111;
end
else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 3;
terminator_location <=#TP 3;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b01111111;
end
else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 4;
rxc_end_data <=#TP 8'b00000000;
terminator_location <=#TP 4;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b11111111;
end
else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 5;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000001;
end
else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 6;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000011;
end
else if (rxc8[7] & (rxd64[63:56]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 7;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000111;
end
else begin
get_terminator <=#TP 1'b0;
terminator_location <=#TP terminator_location;
this_cycle <=#TP this_cycle;
rxc_end_data <=#TP rxc_end_data;
end
end
188,7 → 207,7
if (reset)
get_error_code <=#TP 0;
else
get_error_code <=#TP (| get_e_chk);
get_error_code <=#TP receiving & (| get_e_chk);
end
//////////////////////////////////////
246,10 → 265,14
always@(posedge rxclk or posedge reset) begin
if (reset)
rxc_final <=#TP 0;
else if (get_terminator)
else if (get_terminator & this_cycle)
rxc_final <=#TP rxc_end_data;
else
else if (get_terminator_d1 & ~this_cycle)
rxc_final <=#TP rxc_end_data;
else if (receiving)
rxc_final <=`ALLONES;
else
rxc_final <=0;
end
 
// assign rxc_final = get_terminator_d1? rxc_end_data: `ALLONES;
262,16 → 285,17
wire rxfifo_empty;
wire fifo_rd_en;
wire fifo_wr_en;
 
assign fifo_rd_en = ~(rxfifo_empty | wait_crc_check_d1);
assign fifo_wr_en = receiving_d1;
wire [63:0] rx_data_tmp;
wire [7:0] rx_data_valid_tmp;
assign fifo_rd_en = ~rxfifo_empty;// & (rx_data_valid_tmp ==8'hff);
assign fifo_wr_en = receiving_d2;
rxdatafifo rxdatain(.clk(rxclk),
.sinit(reset),
.din(rxd64_d2),
.din(rxd64_d3),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data),
.dout(rx_data_tmp),
.full(rxfifo_full),
.empty(rxfifo_empty));
 
280,8 → 304,28
.din(rxc_fifo),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data_valid),
.dout(rx_data_valid_tmp),
.full(),
.empty());
 
reg fifo_rd_en_d1;
always@(posedge rxclk) begin
fifo_rd_en_d1 <=#TP fifo_rd_en;
end
reg [63:0] rx_data;
always@(posedge rxclk or posedge reset) begin
if (reset)
rx_data <= 0;
else
rx_data <=#TP rx_data_tmp;
end
reg [7:0] rx_data_valid;
always@(posedge rxclk or posedge reset) begin
if (reset)
rx_data_valid <=#TP 0;
else if(fifo_rd_en)
rx_data_valid <=#TP rx_data_valid_tmp;
else
rx_data_valid <=#TP 0;
end
endmodule
/trunk/rx_engine/rxCRC.v
19,7 → 19,7
//
////////////////////////////////////////////////////////////////////////////////
`define ALLONES 64'hffffffffffffffff
module rxCRC(rxclk, reset, receiving, receiving_d1, receiving_d2, CRC_DATA, get_terminator, crc_check_invalid, crc_check_valid, terminator_location);
module rxCRC(rxclk, reset, receiving, receiving_d1, receiving_d2, CRC_DATA, get_terminator, get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location);
input rxclk;
input reset;
input get_terminator;
27,9 → 27,11
input receiving;
input receiving_d1,receiving_d2;
input [2:0] terminator_location;
input wait_crc_check;
 
output crc_check_invalid;
output crc_check_valid;
output get_terminator_d1;
 
parameter TP = 1;
 
105,6 → 107,16
start_tmp <=#TP 1'b0;
end
reg do_crc_check;
always@(posedge rxclk or posedge reset) begin
if (reset)
do_crc_check <=#TP 0;
else if(terminator_location == 0)
do_crc_check <=#TP get_terminator_d2;
else
do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);
end
wire[31:0] crc_tmp;
CRC32_D8 crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(start_tmp), .LOAD(~start_tmp), .CRC_IN(crc_gen), .CRC_OUT(crc_tmp));
113,7 → 125,7
////////////////////////////////////////////////////////////////////////////////////////////
wire crc_check_valid, crc_check_invalid;
 
assign crc_check_valid = (~bytes_cnt) & (crc_tmp==32'hc704dd7b);
assign crc_check_invalid =(~bytes_cnt) & (crc_tmp!=32'hc704dd7b);
assign crc_check_valid = wait_crc_check & do_crc_check & (crc_tmp==32'hc704dd7b);
assign crc_check_invalid = wait_crc_check & do_crc_check & (crc_tmp!=32'hc704dd7b);
 
endmodule
/trunk/rx_engine/rxReceiveEngine.v
27,7 → 27,7
input [3:0] rxc_in;
output reset_out;
output [17:0] rxStatRegPlus;
input [52:0] cfgRxRegData_in;
input [64:0] cfgRxRegData_in;
output [63:0] rx_data;
output [7:0] rx_data_valid;
output rx_good_frame;
38,6 → 38,7
parameter TP =1;
 
wire rxclk;
wire rxclk_180;
wire locked;
wire reset_dcm;
wire reset;
56,7 → 57,7
// wire [15:0] lt_data;
wire [11:0] frame_cnt;
wire [2:0] terminator_location;
wire get_sfd,get_error_code,get_terminator;
wire get_sfd,get_error_code,get_terminator, get_terminator_d1;
wire receiving;
wire receiving_d1,receiving_d2;
 
91,15 → 92,6
wire [63:0] rxd64;
wire [63:0] CRC_DATA;
wire [7:0] rxc8;
// reg [52:0]cfgRxRegData;
// always@(posedge rxclk or posedge reset) begin
// if (reset) begin
// cfgRxRegData <=#TP 0;
// end
// else begin
// cfgRxRegData <=#TP cfgRxRegData_in;
// end
// end
 
assign rxTxLinkFault = link_fault;
//////////////////////////////////////////
116,12 → 108,12
recv_rst <= 0;
end
else begin
MAC_Addr <= {cfgRxRegData_in[52:37], cfgRxRegData_in[31:0]};
vlan_enable <= cfgRxRegData_in[36];
recv_enable <= cfgRxRegData_in[35];
inband_fcs <= cfgRxRegData_in[34];
jumbo_enable <= cfgRxRegData_in[33];
recv_rst <= cfgRxRegData_in[32];
MAC_Addr <= cfgRxRegData_in[47:0];
vlan_enable <= cfgRxRegData_in[48];
recv_enable <= cfgRxRegData_in[49];
inband_fcs <= cfgRxRegData_in[50];
jumbo_enable <= cfgRxRegData_in[51];
recv_rst <= cfgRxRegData_in[52];
end
end
155,7 → 147,7
.start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),
.get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),
.da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),
.rx_data(rx_data));
.rx_data(rx_data), .get_terminator_d1(get_terminator_d1));
//////////////////////////////////////
// Destination Address Checker
200,7 → 192,7
/////////////////////////////////////
rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),
.crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
.receiving_d2(receiving_d2));
.receiving_d2(receiving_d2), .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check));
/////////////////////////////////////
// RS Layer
/////////////////////////////////////
/trunk/rx_engine/dcm0.v
4,14 → 4,14
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 8.1i
// \ \ \/ Version : 8.1.01i
// \ \ Application : xaw2verilog
// / / Filename : dcm0.v
// /___/ /\ Timestamp : 01/26/2006 15:09:20
// /___/ /\ Timestamp : 02/07/2006 20:12:33
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle F:/10G/ethmac10g_v2/dcm0.xaw -st dcm0.v
//Command: xaw2verilog -intstyle F:/10G/rx_engine_v2/dcm0.xaw -st dcm0.v
//Design Name: dcm0
//Device: xc2vp20-6fg676
//
/trunk/rx_engine/rxRSIO.v
65,39 → 65,39
// get_align_reg <=#TP get_align_reg;
// end
always@(posedge rxclk_180 or posedge reset) begin
if (reset)begin
rxd64_in_tmp[63:32] <=#TP 0;
rxc8_in_tmp[7:4] <=#TP 0;
end
else begin
always@(posedge rxclk_180) begin
// if (reset)begin
// rxd64_in_tmp[63:32] <=#TP 0;
// rxc8_in_tmp[7:4] <=#TP 0;
// end
// else begin
rxd64_in_tmp[63:32] <=#TP rxd_in;
rxc8_in_tmp[7:4] <=#TP rxc_in;
end
// end
end
always@(posedge rxclk or posedge reset) begin
if (reset)begin
rxd64_in_tmp[31:0] <=#TP 0;
rxc8_in_tmp[3:0] <=#TP 0;
end
else begin
always@(posedge rxclk) begin
// if (reset)begin
// rxd64_in_tmp[31:0] <=#TP 0;
// rxc8_in_tmp[3:0] <=#TP 0;
// end
// else begin
rxd64_in_tmp[31:0] <=#TP rxd_in;
rxc8_in_tmp[3:0] <=#TP rxc_in;
end
// end
end
 
reg[63:0] rxd64;
reg[7:0] rxc8;
always@(posedge rxclk or posedge reset) begin
if(reset) begin
rxc8<=#TP 0;
rxd64 <=#TP 0;
end
else begin
always@(posedge rxclk) begin
// if(reset) begin
// rxc8<=#TP 0;
// rxd64 <=#TP 0;
// end
// else begin
rxc8<=#TP rxc8_in_tmp;
rxd64 <=#TP rxd64_in_tmp;
end
// end
end
 
 
/trunk/rx_engine/rxtest.v
1,58 → 1,427
`timescale 1ns / 1ps
/*-------------------------------------------------------------------------------
-- $Revision: 1.8 $ $Date: 2006-02-08 04:07:42 $
-- Title : Demo testbench
-- Project : 10 Gigabit Ethernet MAC
-------------------------------------------------------------------------------
-- File : demo_tb.v
-------------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core to
-- demonstrate the functionality.
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Xilinx Inc.
-------------------------------------------------------------------------------
--
-- This testbench performs the following operations on the MAC core:
-- - The clock divide register is set for MIIM operation. */
/* - The clientXGMII port is wired as a loopback, so that transmitted frames
-- are then injected into the receiver.
-- - Four frames are pushed into the receiver. The first is a minimum
-- length frame, the second is slightly longer, the third has an error
-- asserted and the fourth is less than minimum length and is padded
-- up to the minimum.
-- - These frames are then looped back and sent out by the transmitter.
-- */
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:23:18 12/26/2005
// Design Name: rxReceiveEngine
// Module Name: rxtest.v
// Project Name: ethmac10g
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: rxReceiveEngine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
 
module rxtest_v;
 
// Inputs
reg rxclk_in;
reg reset_in;
reg [31:0] rxd_in;
reg [3:0] rxc_in;
reg [52:0] cfgRxRegData_in;
module frame_typ;
// This module abstracts the frame data for simpler manipulation
reg [31:0] data [0:31];
reg [ 3:0] ctrl [0:31];
reg [31:0] crc;
reg underrun;
 
wire rxclk_2x;
`define FRAME_TYP [32*32+32*4+32+1:1]
 
// Outputs
wire [17:0] rxStatRegPlus;
wire [63:0] rx_data;
wire [7:0] rx_data_valid;
wire rx_good_frame;
wire rx_bad_frame;
wire [2:0] rxCfgofRS;
wire [1:0] rxTxLinkFault;
wire reset_out;
reg `FRAME_TYP bits;
 
// Instantiate the Unit Under Test (UUT)
rxReceiveEngine uut (
.rxclk_in(rxclk_in),
.reset_in(reset_in),
.rxclk_2x(rxclk_2x),
.reset_out(reset_out),
.rxd_in(rxd_in),
.rxc_in(rxc_in),
function `FRAME_TYP tobits;
input dummy;
begin
bits = {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4],
data[ 5], data[ 6], data[ 7], data[ 8], data[ 9],
data[10], data[11], data[12], data[13], data[14],
data[15], data[16], data[17], data[18], data[19],
data[20], data[21], data[22], data[23], data[24],
data[25], data[26], data[27], data[28], data[29],
data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2],
ctrl[ 3], ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7],
ctrl[ 8], ctrl[ 9], ctrl[10], ctrl[11], ctrl[12],
ctrl[13], ctrl[14], ctrl[15], ctrl[16], ctrl[17],
ctrl[18], ctrl[19], ctrl[20], ctrl[21], ctrl[22],
ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun};
tobits = bits;
end
endfunction // tobits
 
task frombits;
input `FRAME_TYP frame;
begin
bits = frame;
{data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], data[ 5],
data[ 6], data[ 7], data[ 8], data[ 9], data[10], data[11],
data[12], data[13], data[14], data[15], data[16], data[17],
data[18], data[19], data[20], data[21], data[22], data[23],
data[24], data[25], data[26], data[27], data[28], data[29],
data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2], ctrl[ 3],
ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7], ctrl[ 8], ctrl[ 9],
ctrl[10], ctrl[11], ctrl[12], ctrl[13], ctrl[14], ctrl[15],
ctrl[16], ctrl[17], ctrl[18], ctrl[19], ctrl[20], ctrl[21],
ctrl[22], ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun} = bits;
end
endtask // frombits
endmodule // frame_typ
 
 
// Address of management configuration register
`define CONFIG_MANAGEMENT 9'b101000000
// Address of flow control configuration register
`define CONFIG_FLOW_CTRL 9'b011000000
// addresses of statistics registers
`define STATS_TX_OK 9'b000100000
`define STATS_TX_UNDERRUN 9'b000100011
`define STATS_RX_OK 9'b000000000
`define STATS_RX_FCS_ERR 9'b000000001
`define MIN_FRAME_DATA_BYTES 60
 
 
module testbench;
 
// Frame data....
frame_typ frame0();
frame_typ frame1();
frame_typ frame2();
frame_typ frame3();
 
frame_typ tx_stimulus_working_frame();
frame_typ tx_monitor_working_frame();
frame_typ rx_stimulus_working_frame();
frame_typ rx_monitor_working_frame();
 
// Store the frame data etc....
initial
begin
// Frame 0...
frame0.data[0] = 32'h04030201;
frame0.data[1] = 32'h02020605;
frame0.data[2] = 32'h06050403;
frame0.data[3] = 32'h55AA2E00;
frame0.data[4] = 32'hAA55AA55;
frame0.data[5] = 32'h55AA55AA;
frame0.data[6] = 32'hAA55AA55;
frame0.data[7] = 32'h55AA55AA;
frame0.data[8] = 32'hAA55AA55;
frame0.data[9] = 32'h55AA55AA;
frame0.data[10] = 32'hAA55AA55;
frame0.data[11] = 32'h55AA55AA;
frame0.data[12] = 32'hAA55AA55;
frame0.data[13] = 32'h55AA55AA;
frame0.data[14] = 32'hAA55AA55;
frame0.data[15] = 32'h00000000;
frame0.data[16] = 32'h00000000;
frame0.data[17] = 32'h00000000;
frame0.data[18] = 32'h00000000;
frame0.data[19] = 32'h00000000;
frame0.data[20] = 32'h00000000;
frame0.data[21] = 32'h00000000;
frame0.data[22] = 32'h00000000;
frame0.data[23] = 32'h00000000;
frame0.data[24] = 32'h00000000;
frame0.data[25] = 32'h00000000;
frame0.data[26] = 32'h00000000;
frame0.data[27] = 32'h00000000;
frame0.data[28] = 32'h00000000;
frame0.data[29] = 32'h00000000;
frame0.data[30] = 32'h00000000;
frame0.data[31] = 32'h00000000;
frame0.ctrl[0] = 4'b1111;
frame0.ctrl[1] = 4'b1111;
frame0.ctrl[2] = 4'b1111;
frame0.ctrl[3] = 4'b1111;
frame0.ctrl[4] = 4'b1111;
frame0.ctrl[5] = 4'b1111;
frame0.ctrl[6] = 4'b1111;
frame0.ctrl[7] = 4'b1111;
frame0.ctrl[8] = 4'b1111;
frame0.ctrl[9] = 4'b1111;
frame0.ctrl[10] = 4'b1111;
frame0.ctrl[11] = 4'b1111;
frame0.ctrl[12] = 4'b1111;
frame0.ctrl[13] = 4'b1111;
frame0.ctrl[14] = 4'b1111;
frame0.ctrl[15] = 4'b0000;
frame0.ctrl[16] = 4'b0000;
frame0.ctrl[17] = 4'b0000;
frame0.ctrl[18] = 4'b0000;
frame0.ctrl[19] = 4'b0000;
frame0.ctrl[20] = 4'b0000;
frame0.ctrl[21] = 4'b0000;
frame0.ctrl[22] = 4'b0000;
frame0.ctrl[23] = 4'b0000;
frame0.ctrl[24] = 4'b0000;
frame0.ctrl[25] = 4'b0000;
frame0.ctrl[26] = 4'b0000;
frame0.ctrl[27] = 4'b0000;
frame0.ctrl[28] = 4'b0000;
frame0.ctrl[29] = 4'b0000;
frame0.ctrl[30] = 4'b0000;
frame0.ctrl[31] = 4'b0000;
frame0.crc = 32'h0D4820F6;
frame0.underrun = 1'b0;
// Frame 1
frame1.data[0] = 32'h03040506;
frame1.data[1] = 32'h05060102;
frame1.data[2] = 32'h02020304;
frame1.data[3] = 32'hEE110080;
frame1.data[4] = 32'h11EE11EE;
frame1.data[5] = 32'hEE11EE11;
frame1.data[6] = 32'h11EE11EE;
frame1.data[7] = 32'hEE11EE11;
frame1.data[8] = 32'h11EE11EE;
frame1.data[9] = 32'hEE11EE11;
frame1.data[10] = 32'h11EE11EE;
frame1.data[11] = 32'hEE11EE11;
frame1.data[12] = 32'h11EE11EE;
frame1.data[13] = 32'hEE11EE11;
frame1.data[14] = 32'h11EE11EE;
frame1.data[15] = 32'hEE11EE11;
frame1.data[16] = 32'h11EE11EE;
frame1.data[17] = 32'hEE11EE11;
frame1.data[18] = 32'h11EE11EE;
frame1.data[19] = 32'hEE11EE11;
frame1.data[20] = 32'h11EE11EE;
frame1.data[21] = 32'h0000EE11;
frame1.data[22] = 32'h00000000;
frame1.data[23] = 32'h00000000;
frame1.data[24] = 32'h00000000;
frame1.data[25] = 32'h00000000;
frame1.data[26] = 32'h00000000;
frame1.data[27] = 32'h00000000;
frame1.data[28] = 32'h00000000;
frame1.data[29] = 32'h00000000;
frame1.data[30] = 32'h00000000;
frame1.data[31] = 32'h00000000;
 
frame1.ctrl[0] = 4'b1111;
frame1.ctrl[1] = 4'b1111;
frame1.ctrl[2] = 4'b1111;
frame1.ctrl[3] = 4'b1111;
frame1.ctrl[4] = 4'b1111;
frame1.ctrl[5] = 4'b1111;
frame1.ctrl[6] = 4'b1111;
frame1.ctrl[7] = 4'b1111;
frame1.ctrl[8] = 4'b1111;
frame1.ctrl[9] = 4'b1111;
frame1.ctrl[10] = 4'b1111;
frame1.ctrl[11] = 4'b1111;
frame1.ctrl[12] = 4'b1111;
frame1.ctrl[13] = 4'b1111;
frame1.ctrl[14] = 4'b1111;
frame1.ctrl[15] = 4'b1111;
frame1.ctrl[16] = 4'b1111;
frame1.ctrl[17] = 4'b1111;
frame1.ctrl[18] = 4'b1111;
frame1.ctrl[19] = 4'b1111;
frame1.ctrl[20] = 4'b1111;
frame1.ctrl[21] = 4'b0011;
frame1.ctrl[22] = 4'b0000;
frame1.ctrl[23] = 4'b0000;
frame1.ctrl[24] = 4'b0000;
frame1.ctrl[25] = 4'b0000;
frame1.ctrl[26] = 4'b0000;
frame1.ctrl[27] = 4'b0000;
frame1.ctrl[28] = 4'b0000;
frame1.ctrl[29] = 4'b0000;
frame1.ctrl[30] = 4'b0000;
frame1.ctrl[31] = 4'b0000;
frame1.crc = 32'hDE13388C;
frame1.underrun = 1'b0;
// Frame 2
frame2.data[0] = 32'h04030201;
frame2.data[1] = 32'h02020605;
frame2.data[2] = 32'h06050403;
frame2.data[3] = 32'h55AA2E80;
frame2.data[4] = 32'hAA55AA55;
frame2.data[5] = 32'h55AA55AA;
frame2.data[6] = 32'hAA55AA55;
frame2.data[7] = 32'h55AA55AA;
frame2.data[8] = 32'hAA55AA55;
frame2.data[9] = 32'h55AA55AA;
frame2.data[10] = 32'hAA55AA55;
frame2.data[11] = 32'h55AA55AA;
frame2.data[12] = 32'hAA55AA55;
frame2.data[13] = 32'h55AA55AA;
frame2.data[14] = 32'hAA55AA55;
frame2.data[15] = 32'h55AA55AA;
frame2.data[16] = 32'hAA55AA55;
frame2.data[17] = 32'h55AA55AA;
frame2.data[18] = 32'hAA55AA55;
frame2.data[19] = 32'h55AA55AA;
frame2.data[20] = 32'h00000000;
frame2.data[21] = 32'h00000000;
frame2.data[22] = 32'h00000000;
frame2.data[23] = 32'h00000000;
frame2.data[24] = 32'h00000000;
frame2.data[25] = 32'h00000000;
frame2.data[26] = 32'h00000000;
frame2.data[27] = 32'h00000000;
frame2.data[28] = 32'h00000000;
frame2.data[29] = 32'h00000000;
frame2.data[30] = 32'h00000000;
frame2.data[31] = 32'h00000000;
 
frame2.ctrl[0] = 4'b1111;
frame2.ctrl[1] = 4'b1111;
frame2.ctrl[2] = 4'b1111;
frame2.ctrl[3] = 4'b1111;
frame2.ctrl[4] = 4'b1111;
frame2.ctrl[5] = 4'b1111;
frame2.ctrl[6] = 4'b1111;
frame2.ctrl[7] = 4'b1111;
frame2.ctrl[8] = 4'b1111;
frame2.ctrl[9] = 4'b1111;
frame2.ctrl[10] = 4'b1111;
frame2.ctrl[11] = 4'b1111;
frame2.ctrl[12] = 4'b1111;
frame2.ctrl[13] = 4'b1111;
frame2.ctrl[14] = 4'b1111;
frame2.ctrl[15] = 4'b1111;
frame2.ctrl[16] = 4'b1111;
frame2.ctrl[17] = 4'b1111;
frame2.ctrl[18] = 4'b1111;
frame2.ctrl[19] = 4'b1111;
frame2.ctrl[20] = 4'b0000;
frame2.ctrl[21] = 4'b0000;
frame2.ctrl[22] = 4'b0000;
frame2.ctrl[23] = 4'b0000;
frame2.ctrl[24] = 4'b0000;
frame2.ctrl[25] = 4'b0000;
frame2.ctrl[26] = 4'b0000;
frame2.ctrl[27] = 4'b0000;
frame2.ctrl[28] = 4'b0000;
frame2.ctrl[29] = 4'b0000;
frame2.ctrl[30] = 4'b0000;
frame2.ctrl[31] = 4'b0000;
frame2.crc = 32'h20C6B69D;
frame2.underrun = 1'b1;
// Frame 3
frame3.data[0] = 32'h03040506;
frame3.data[1] = 32'h05060102;
frame3.data[2] = 32'h02020304;
frame3.data[3] = 32'hEE111500;
frame3.data[4] = 32'h11EE11EE;
frame3.data[5] = 32'hEE11EE11;
frame3.data[6] = 64'h11EE11EE;
frame3.data[7] = 32'hEE11EE11;
frame3.data[8] = 32'h00EE11EE;
frame3.data[9] = 32'h00000000;
frame3.data[10] = 32'h00000000;
frame3.data[11] = 32'h00000000;
frame3.data[12] = 32'h00000000;
frame3.data[13] = 32'h00000000;
frame3.data[14] = 32'h00000000;
frame3.data[15] = 32'h00000000;
frame3.data[16] = 32'h00000000;
frame3.data[17] = 32'h00000000;
frame3.data[18] = 32'h00000000;
frame3.data[19] = 32'h00000000;
frame3.data[20] = 32'h00000000;
frame3.data[21] = 32'h00000000;
frame3.data[22] = 32'h00000000;
frame3.data[23] = 32'h00000000;
frame3.data[24] = 32'h00000000;
frame3.data[25] = 32'h00000000;
frame3.data[26] = 32'h00000000;
frame3.data[27] = 32'h00000000;
frame3.data[28] = 32'h00000000;
frame3.data[29] = 32'h00000000;
frame3.data[30] = 32'h00000000;
frame3.data[31] = 32'h00000000;
 
frame3.ctrl[0] = 4'b1111;
frame3.ctrl[1] = 4'b1111;
frame3.ctrl[2] = 4'b1111;
frame3.ctrl[3] = 4'b1111;
frame3.ctrl[4] = 4'b1111;
frame3.ctrl[5] = 4'b1111;
frame3.ctrl[6] = 4'b1111;
frame3.ctrl[7] = 4'b1111;
frame3.ctrl[8] = 4'b0111;
frame3.ctrl[9] = 4'b0000;
frame3.ctrl[10] = 4'b0000;
frame3.ctrl[11] = 4'b0000;
frame3.ctrl[12] = 4'b0000;
frame3.ctrl[13] = 4'b0000;
frame3.ctrl[14] = 4'b0000;
frame3.ctrl[15] = 4'b0000;
frame3.ctrl[16] = 4'b0000;
frame3.ctrl[17] = 4'b0000;
frame3.ctrl[18] = 4'b0000;
frame3.ctrl[19] = 4'b0000;
frame3.ctrl[20] = 4'b0000;
frame3.ctrl[21] = 4'b0000;
frame3.ctrl[22] = 4'b0000;
frame3.ctrl[23] = 4'b0000;
frame3.ctrl[24] = 4'b0000;
frame3.ctrl[25] = 4'b0000;
frame3.ctrl[26] = 4'b0000;
frame3.ctrl[27] = 4'b0000;
frame3.ctrl[28] = 4'b0000;
frame3.ctrl[29] = 4'b0000;
frame3.ctrl[30] = 4'b0000;
frame3.ctrl[31] = 4'b0000;
frame3.crc = 32'h6B734A56;
frame3.underrun = 1'b0;
end // initial
 
// DUT signals
reg reset;
 
//Client transmitter signals
//client receiver signals
wire [63:0] rx_data;
wire [7:0] rx_data_valid;
wire rx_good_frame;
wire rx_bad_frame;
wire rx_clk;
wire [28:0] rx_statistics_vector;
wire rx_statistics_valid;
wire [64:0] configuration_vector;
reg xgmii_rx_clk;
reg [31:0] xgmii_rxd;
reg [3:0] xgmii_rxc;
 
reg rx_monitor_finished;
wire simulation_finished;
 
/*---------------------------------------------------------------------------
-- wire up Device Under Test
---------------------------------------------------------------------------*/
rxReceiveEngine uut (
.rxclk_in(xgmii_rx_clk),
.reset_in(reset),
.reset_out(),
.rxd_in(xgmii_rxd),
.rxc_in(xgmii_rxc),
.rxStatRegPlus(rxStatRegPlus),
.cfgRxRegData_in(cfgRxRegData_in),
.cfgRxRegData_in(configuration_vector),
.rx_data(rx_data),
.rx_data_valid(rx_data_valid),
.rx_good_frame(rx_good_frame),
61,277 → 430,286
.rxTxLinkFault(rxTxLinkFault)
);
 
initial begin
// Initialize Inputs
rxclk_in = 0;
rxd_in = 0;
rxc_in = 0;
cfgRxRegData_in = 0;
cfgRxRegData_in[35] = 1'b1;//recv_enable
cfgRxRegData_in[36] = 1'b1;//vlan enable
cfgRxRegData_in[34] = 1'b0;//inband fcs
cfgRxRegData_in[52:37] = 16'h4e94;
cfgRxRegData_in[31:0]=32'h47f90300;
assign configuration_vector = {1'b0, 64'h0583010203040506};
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
/*---------------------------------------------------------------------------
-- Clock drivers
---------------------------------------------------------------------------*/
initial
begin
xgmii_rx_clk <= 0;
#1000;
forever
begin
#3200;
xgmii_rx_clk <= 1;
#3200;
xgmii_rx_clk <= 0;
end
end // initial begin
 
end
 
wire [31:0] testvector[95:0];
wire [3:0] testvector1[95:0];
 
wire [31:0] trueframe1[21:0];
wire [3:0] trueframe2[21:0];
/* RX Stimulus process - insert frames into the PHY side of the
* receiver
*/
 
assign testvector[0]=32'h555555df;
assign testvector[1]=32'hd5555555;
assign testvector[2]=32'h47f90300;
assign testvector[3]=32'h0b004e94;
assign testvector[4]=32'hf7a0021f;
assign testvector[5]=32'h00a20010;
assign testvector[6]=32'h3d3c2680;
assign testvector[7]=32'h888c0000;
assign testvector[8]=32'ha1db65cc;
assign testvector[9]=32'h2850a414;
assign testvector[10]=32'h02f89650;
assign testvector[11]=32'h0a8005f0;
assign testvector[12]=32'h8040fe3f;
assign testvector[13]=32'h2ee40000;
assign testvector[14]=32'h6ceea484;
assign testvector[15]=32'h1c158c97;
assign testvector[16]=32'hb2caadb3;
assign testvector[17]=32'hc9498324;
assign testvector[18]=32'hafabaa1f;
assign testvector[19]=32'hd0b3567d;
assign testvector[20]=32'hc7ecf78f;
assign testvector[21]=32'hb84bde8b;
assign testvector[22]=32'h586af26c;
assign testvector[23]=32'haa3c3a94;
assign testvector[24]=32'hcc09ce77;
assign testvector[25]=32'ha5eed376;
assign testvector[26]=32'h03df2904;
assign testvector[27]=32'h265e28c9;
assign testvector[28]=32'h3770189f;
assign testvector[29]=32'h97eacc54;
assign testvector[30]=32'hc23fb610;
assign testvector[31]=32'hfe15e244;
assign testvector[32]=32'hc14de056;
assign testvector[33]=32'h02ee7034;
assign testvector[34]=32'h03659484;
assign testvector[35]=32'h4a9abae8;
assign testvector[36]=32'h918f6ed4;
assign testvector[37]=32'h3d34d604;
assign testvector[38]=32'h9a729914;
assign testvector[39]=32'haf0205c7;
assign testvector[40]=32'h4cc098d5;
assign testvector[41]=32'hc7e2acfc;
assign testvector[42]=32'h8a19bf8e;
assign testvector[43]=32'hd7639bda;
assign testvector[44]=32'hd1fb311e;
assign testvector[45]=32'ha238c4d9;
assign testvector[46]=32'hc9bdcd00;
assign testvector[47]=32'h21ada082;
assign testvector[48]=32'h3a66571f;
assign testvector[49]=32'h74ee977c;
assign testvector[50]=32'h7cb0e7f1;
assign testvector[51]=32'he63a2e50;
assign testvector[52]=32'hfb43b6ca;
assign testvector[53]=32'h0d63c968;
assign testvector[54]=32'h958185a0;
assign testvector[55]=32'hb7262b2a;
assign testvector[56]=32'ha0018bed;
assign testvector[57]=32'h91e62f95;
assign testvector[58]=32'h3ac7ac7e;
assign testvector[59]=32'hea2a392e;
assign testvector[60]=32'h4b6570d2;
assign testvector[61]=32'h2f8c5bdc;
assign testvector[62]=32'h24f3ea6c;
assign testvector[63]=32'h2f6555fb;
assign testvector[64]=32'hefdd06dd;
assign testvector[65]=32'haa043ab2;
assign testvector[66]=32'hede72cc6;
assign testvector[67]=32'h0515433a;
assign testvector[68]=32'h31a8eba8;
assign testvector[69]=32'h413537cb;
assign testvector[70]=32'h5fbe358c;
assign testvector[71]=32'hc3aab4e6;
assign testvector[72]=32'h4070e288;
assign testvector[73]=32'h87b6268a;
assign testvector[74]=32'h982b2629;
assign testvector[75]=32'h4b6296c9;
assign testvector[76]=32'h1986ac34;
assign testvector[77]=32'hb5a4b1ea;
assign testvector[78]=32'hfa3120b2;
assign testvector[79]=32'hd4487395;
assign testvector[80]=32'hfb9a1667;
assign testvector[81]=32'he4b132ec;
assign testvector[82]=32'hc46ea10d;
assign testvector[83]=32'hb70ea618;
assign testvector[84]=32'h79b254de;
assign testvector[85]=32'hfe9a53c0;
assign testvector[86]=32'hd9e83015;
assign testvector[87]=32'h0097f445;
assign testvector[88]=32'he209598f;
assign testvector[89]=32'h07aa176d;
assign testvector[90]=32'hafb00462;
assign testvector[91]=32'h2b2feabf;
assign testvector[92]=32'h9177bbd2;
assign testvector[93]=32'h949442cf;
assign testvector[94]=32'h9379c09a;
assign testvector[95]=32'h07bfe128;
task rx_stimulus_send_column;
input [31:0] d;
input [ 3:0] c;
begin
@(posedge xgmii_rx_clk or negedge xgmii_rx_clk);
#1600;
xgmii_rxd <= d;
xgmii_rxc <= c;
end
endtask // rx_stimulus_send_column
 
assign testvector1[0]=4'h1;
assign testvector1[1]=4'h0;
assign testvector1[2]=4'h0;
assign testvector1[3]=4'h0;
assign testvector1[4]=4'h0;
assign testvector1[5]=4'h0;
assign testvector1[6]=4'h0;
assign testvector1[7]=4'h0;
assign testvector1[8]=4'h0;
assign testvector1[9]=4'h0;
assign testvector1[10]=4'h0;
assign testvector1[11]=4'h0;
assign testvector1[12]=4'h0;
assign testvector1[13]=4'h0;
assign testvector1[14]=4'h0;
assign testvector1[15]=4'h0;
assign testvector1[16]=4'h0;
assign testvector1[17]=4'h0;
assign testvector1[18]=4'h0;
assign testvector1[19]=4'h0;
assign testvector1[20]=4'h0;
assign testvector1[21]=4'h0;
assign testvector1[22]=4'h0;
assign testvector1[23]=4'h0;
assign testvector1[24]=4'h0;
assign testvector1[25]=4'h0;
assign testvector1[26]=4'h0;
assign testvector1[27]=4'h0;
assign testvector1[28]=4'h0;
assign testvector1[29]=4'h0;
assign testvector1[30]=4'h0;
assign testvector1[31]=4'h0;
assign testvector1[32]=4'h0;
assign testvector1[33]=4'h0;
assign testvector1[34]=4'h0;
assign testvector1[35]=4'h0;
assign testvector1[36]=4'h0;
assign testvector1[37]=4'h0;
assign testvector1[38]=4'h0;
assign testvector1[39]=4'h0;
assign testvector1[40]=4'h0;
assign testvector1[41]=4'h0;
assign testvector1[42]=4'h0;
assign testvector1[43]=4'h0;
assign testvector1[44]=4'h0;
assign testvector1[45]=4'h0;
assign testvector1[46]=4'h0;
assign testvector1[47]=4'h0;
assign testvector1[48]=4'h0;
assign testvector1[49]=4'h0;
assign testvector1[50]=4'h0;
assign testvector1[51]=4'h0;
assign testvector1[52]=4'h0;
assign testvector1[53]=4'h0;
assign testvector1[54]=4'h0;
assign testvector1[55]=4'h0;
assign testvector1[56]=4'h0;
assign testvector1[57]=4'h0;
assign testvector1[58]=4'h0;
assign testvector1[59]=4'h0;
assign testvector1[60]=4'h0;
assign testvector1[61]=4'h0;
assign testvector1[62]=4'h0;
assign testvector1[63]=4'h0;
assign testvector1[64]=4'h0;
assign testvector1[65]=4'h0;
assign testvector1[66]=4'h0;
assign testvector1[67]=4'h0;
assign testvector1[68]=4'h0;
assign testvector1[69]=4'h0;
assign testvector1[70]=4'h0;
assign testvector1[71]=4'h0;
assign testvector1[72]=4'h0;
assign testvector1[73]=4'h0;
assign testvector1[74]=4'h0;
assign testvector1[75]=4'h0;
assign testvector1[76]=4'h0;
assign testvector1[77]=4'h0;
assign testvector1[78]=4'h0;
assign testvector1[79]=4'h0;
assign testvector1[80]=4'h0;
assign testvector1[81]=4'h0;
assign testvector1[82]=4'h0;
assign testvector1[83]=4'h0;
assign testvector1[84]=4'h0;
assign testvector1[85]=4'h0;
assign testvector1[86]=4'h0;
assign testvector1[87]=4'h0;
assign testvector1[88]=4'h0;
assign testvector1[89]=4'h0;
assign testvector1[90]=4'h0;
assign testvector1[91]=4'h0;
assign testvector1[92]=4'h0;
assign testvector1[93]=4'h0;
assign testvector1[94]=4'h0;
assign testvector1[95]=4'hc;
task rx_stimulus_send_idle;
begin
rx_stimulus_send_column(32'h07070707,4'b1111);
end
endtask // rx_stimulus_send_idle
task rx_stimulus_send_frame;
input `FRAME_TYP frame;
integer column_index, lane_index, byte_count, I, J;
reg [31:0] scratch_column_data, current_column_data;
reg [ 3:0] scratch_column_ctrl, current_column_ctrl;
reg [ 7:0] code_temp;
begin
rx_stimulus_working_frame.frombits(frame);
column_index = 0;
lane_index = 0;
byte_count = 0;
// send preamble
rx_stimulus_send_column(32'h555555FB, 4'b0001);
rx_stimulus_send_column(32'hD5555555, 4'b0000);
// send complete columns
while (rx_stimulus_working_frame.ctrl[column_index] === 4'b1111)
begin
rx_stimulus_send_column(rx_stimulus_working_frame.data[column_index],
4'b0000);
column_index = column_index + 1;
byte_count = byte_count + 4;
end
current_column_data = rx_stimulus_working_frame.data[column_index];//data which is not 64 bits
current_column_ctrl = rx_stimulus_working_frame.ctrl[column_index];
while (current_column_ctrl[lane_index]) //send out data which is not 64 bits
begin
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] =
current_column_data[lane_index*8+J];
scratch_column_ctrl[lane_index] = 0;
lane_index = lane_index + 1;
byte_count = byte_count + 1;
end
// send any padding required
while (byte_count < `MIN_FRAME_DATA_BYTES)
begin
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = 0;
scratch_column_ctrl[lane_index] = 0;
lane_index = lane_index + 1;
byte_count = byte_count + 1;
end // while (byte_count < `MIN_FRAME_DATA_BYTES)
// send the CRC
for (I = 3; I >= 0; I = I - 1)
begin
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] =
rx_stimulus_working_frame.crc[I*8+J];
scratch_column_ctrl = 0;
lane_index = lane_index + 1;
end // for (I = 3; I >= 0; I = I - 1)
// send the terminate/error column
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
// send an /E/ if underrun, /T/ if not
code_temp = rx_stimulus_working_frame.underrun ? 8'hFE : 8'hFD;
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = code_temp[J];
scratch_column_ctrl[lane_index] = 1;
 
assign trueframe2[0] = 4'hf;
assign trueframe2[1] = 4'hf;
assign trueframe2[2] = 4'h1;
assign trueframe2[3] = 4'h0;
assign trueframe2[4] = 4'h0;
assign trueframe2[5] = 4'h0;
assign trueframe2[6] = 4'h0;
assign trueframe2[7] = 4'h0;
assign trueframe2[8] = 4'h0;
assign trueframe2[9] = 4'h0;
assign trueframe2[10] = 4'h0;
assign trueframe2[11] = 4'h0;
assign trueframe2[12] = 4'h0;
assign trueframe2[13] = 4'h0;
assign trueframe2[14] = 4'h0;
assign trueframe2[15] = 4'h0;
assign trueframe2[16] = 4'h0;
assign trueframe2[17] = 4'h0;
assign trueframe2[18] = 4'h0;
assign trueframe2[19] = 4'h0;
assign trueframe2[20] = 4'hf;
assign trueframe2[21] = 4'hf;
lane_index = lane_index + 1;
while (lane_index < 4)
begin
code_temp = 8'h07;
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = code_temp[J];
scratch_column_ctrl[lane_index] = 1;
lane_index = lane_index + 1;
end
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
$display("Receiver: frame inserted into PHY interface");
end
endtask // rx_stimulus_send_frame
 
initial begin
reset_in = 1;
#100
reset_in = 0;
end
always rxclk_in =#10 ~rxclk_in;
initial
begin : p_rx_stimulus
integer I;
while (reset !== 0)
rx_stimulus_send_idle;
rx_stimulus_send_idle;
for (I = 0; I < 100; I = I + 1)
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame0.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame1.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame2.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame3.tobits(0));
while (1)
rx_stimulus_send_idle;
end // block: p_rx_stimulus
 
reg [7:0]i;
always@(posedge rxclk_2x or posedge reset_out) begin
if (reset_out) begin
i <= 0;
rxd_in <=0;
rxc_in <=0;
end
else begin
i <= i+1;
if(i==97)
i<=0;
// rxd64_in <=taggedvector1[i];
// rxc8_in <=taggedvector2[i];
// rxd64_in <=testvector1[i];
// rxc8_in <=testvector2[i];
rxd_in <=testvector[i];
rxc_in <=testvector1[i];
// rxd64_in <=smallvector1[i];
// rxc8_in <=smallvector2[i];
end
end
 
/* rx monitor - checks that the receiver extracts the information
* inserted into the PHY interface
*/
task wait_on_rx_clk;
begin
@(posedge rx_clk);
#6399;
end
endtask // wait_on_rx_clk
task rx_monitor_check_frame;
input `FRAME_TYP frame;
integer column_count, I, J;
reg [31:0] current_column_data;
reg good_frame_flagged;
reg bad_frame_flagged;
begin
rx_monitor_working_frame.frombits(frame);
column_count = 0;
// wait for the first real column of data
while (rx_data_valid === 8'b00000000)
wait_on_rx_clk;
// frame has started, get columns of frame
while (rx_data_valid !== 8'b00000000)
begin
// only check contents of good frames
if (!rx_monitor_working_frame.underrun)
begin
if (rx_data_valid !== { rx_monitor_working_frame.ctrl[column_count+1],
rx_monitor_working_frame.ctrl[column_count] })
$display("ERROR: Receiver fail: RX_DATA_VALID incorrect");
current_column_data = rx_monitor_working_frame.data[column_count];
for (I = 0; I < 4; I = I + 1)
if (rx_data_valid[I])
for (J = 0; J < 8; J = J + 1)
if (rx_data[I*8+J] !== current_column_data[I*8+J])
$display("ERROR: Receiver fail : RX_DATA incorrect");
current_column_data = rx_monitor_working_frame.data[column_count+1];
for (I = 4; I < 8; I = I + 1)
if (rx_data_valid[I])
for (J = 0; J < 8; J = J + 1)
if (rx_data[I*8+J] !== current_column_data[(I-4)*8+J])
$display("ERROR: Receiver fail : RX_DATA incorrect");
end // if (!rx_monitor_working_frame.underrun)
 
good_frame_flagged = rx_good_frame;
bad_frame_flagged = rx_bad_frame;
column_count = column_count + 2;
wait_on_rx_clk;
end // while (RX_DATA_VALID != 8'b00000000)
// check whether the frame has been flagged at the right time
while (!good_frame_flagged && !bad_frame_flagged)
begin
good_frame_flagged = rx_good_frame;
bad_frame_flagged = rx_bad_frame;
if (rx_data_valid !== 8'b00000000)
$display("ERROR: Receiver fail: New frame received before good/bad flag from previous frame");
wait_on_rx_clk;
end
if (rx_monitor_working_frame.underrun)
begin
if (good_frame_flagged)
$display("ERROR: Receive Fail: bad frame flagged as good");
end
else
begin
if (bad_frame_flagged)
$display("ERROR: Receive Fail: good frame flagged as bad");
end
$display("Receiver: Frame extracted from client interface");
end
endtask // rx_monitor_check_frame
 
/*---------------------------------------------------------------------------
-- RX Monitor process. This process checks the data coming out of the
receiver
-- to make sure that it matches that inserted into the transmitter.
---------------------------------------------------------------------------*/
initial
begin : p_rx_monitor
rx_monitor_finished = 0;
// first, get synced up with the RX clock
@(negedge reset)
wait_on_rx_clk;
 
rx_monitor_check_frame(frame0.tobits(0));
rx_monitor_check_frame(frame1.tobits(0));
rx_monitor_check_frame(frame2.tobits(0));
rx_monitor_check_frame(frame3.tobits(0));
rx_monitor_finished = 1;
end // block: p_rx_monitor
 
 
 
 
// reset process
initial
begin
$display("Resetting the core...");
reset <= 1;
#200000;
reset <= 0;
end
 
// Simulation control
assign simulation_finished =
rx_monitor_finished
;
 
initial
begin
fork: sim_in_progress
@(posedge simulation_finished) disable sim_in_progress;
#10000000 disable sim_in_progress;
join
if (simulation_finished)
$display("** failure: Simulation Stopped");
else
$display("** failure: Testbench timed out");
$stop;
end // initial begin
 
endmodule
 
/trunk/rx_engine/CRC32_D64.v
1,3 → 1,4
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////
// File: CRC32_D64.v
// Date: Sun Nov 27 19:32:12 2005
/trunk/rx_engine/CRC32_D8.v
1,3 → 1,4
`timescale 1ns / 1ps
module CRC32_D8(DATA_IN, CLK, RESET, START, LOAD, CRC_IN, CRC_OUT);
 
input [7:0] DATA_IN;

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