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/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/altsyncram.v
0,0 → 1,4662
// START_MODULE_NAME------------------------------------------------------------
//
// Module Name : ALTSYNCRAM
//
// Description : Synchronous ram model for Stratix series family
//
// Limitation :
//
// END_MODULE_NAME--------------------------------------------------------------
 
`timescale 1 ps / 1 ps
 
// BEGINNING OF MODULE
 
// MODULE DECLARATION
 
module altsyncram (
wren_a,
wren_b,
rden_a,
rden_b,
data_a,
data_b,
address_a,
address_b,
clock0,
clock1,
clocken0,
clocken1,
clocken2,
clocken3,
aclr0,
aclr1,
byteena_a,
byteena_b,
addressstall_a,
addressstall_b,
q_a,
q_b,
eccstatus
);
 
// GLOBAL PARAMETER DECLARATION
 
// PORT A PARAMETERS
parameter width_a = 1;
parameter widthad_a = 1;
parameter numwords_a = 0;
parameter outdata_reg_a = "UNREGISTERED";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter wrcontrol_aclr_a = "NONE";
parameter byteena_aclr_a = "NONE";
parameter width_byteena_a = 1;
 
// PORT B PARAMETERS
parameter width_b = 1;
parameter widthad_b = 1;
parameter numwords_b = 0;
parameter rdcontrol_reg_b = "CLOCK1";
parameter address_reg_b = "CLOCK1";
parameter outdata_reg_b = "UNREGISTERED";
parameter outdata_aclr_b = "NONE";
parameter rdcontrol_aclr_b = "NONE";
parameter indata_reg_b = "CLOCK1";
parameter wrcontrol_wraddress_reg_b = "CLOCK1";
parameter byteena_reg_b = "CLOCK1";
parameter indata_aclr_b = "NONE";
parameter wrcontrol_aclr_b = "NONE";
parameter address_aclr_b = "NONE";
parameter byteena_aclr_b = "NONE";
parameter width_byteena_b = 1;
 
// STRATIX II RELATED PARAMETERS
parameter clock_enable_input_a = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter clock_enable_input_b = "NORMAL";
parameter clock_enable_output_b = "NORMAL";
 
parameter clock_enable_core_a = "USE_INPUT_CLKEN";
parameter clock_enable_core_b = "USE_INPUT_CLKEN";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
 
// ECC STATUS RELATED PARAMETERS
parameter enable_ecc = "FALSE";
 
// GLOBAL PARAMETERS
parameter operation_mode = "BIDIR_DUAL_PORT";
parameter byte_size = 0;
parameter read_during_write_mode_mixed_ports = "DONT_CARE";
parameter ram_block_type = "AUTO";
parameter init_file = "UNUSED";
parameter init_file_layout = "UNUSED";
parameter maximum_depth = 0;
parameter intended_device_family = "Stratix";
 
parameter lpm_hint = "UNUSED";
parameter lpm_type = "altsyncram";
 
parameter implement_in_les = "OFF";
parameter power_up_uninitialized = "FALSE";
parameter sim_show_memory_data_in_port_b_layout = "OFF";
// Internal parameters
parameter is_lutram = ((ram_block_type == "LUTRAM") || (ram_block_type == "MLAB"))? 1 : 0;
parameter is_bidir_and_wrcontrol_addb_clk0 = (((operation_mode == "BIDIR_DUAL_PORT") && (address_reg_b == "CLOCK0"))?
1 : 0);
 
parameter is_bidir_and_wrcontrol_addb_clk1 = (((operation_mode == "BIDIR_DUAL_PORT") && (address_reg_b == "CLOCK1"))?
1 : 0);
 
parameter check_simultaneous_read_write = (((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT")) &&
((ram_block_type == "M-RAM") ||
(ram_block_type == "MEGARAM") ||
((ram_block_type == "AUTO") && (read_during_write_mode_mixed_ports == "DONT_CARE")) ||
((is_lutram == 1) && ((read_during_write_mode_mixed_ports != "OLD_DATA") || (outdata_reg_b == "UNREGISTERED")))))? 1 : 0;
 
parameter dual_port_addreg_b_clk0 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK0"))? 1: 0);
 
parameter dual_port_addreg_b_clk1 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK1"))? 1: 0);
 
parameter i_byte_size_tmp = (width_byteena_a > 1)? width_a / width_byteena_a : 8;
parameter i_lutram_read = (((is_lutram == 1) && (read_during_write_mode_port_a == "DONT_CARE")) ||
((is_lutram == 1) && (outdata_reg_a == "UNREGISTERED") && (operation_mode == "SINGLE_PORT")))? 1 : 0;
 
parameter enable_mem_data_b_reading = (sim_show_memory_data_in_port_b_layout == "ON") &&
((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT")) ? 1 : 0;
 
 
 
// INPUT PORT DECLARATION
 
input wren_a; // Port A write/read enable input
input wren_b; // Port B write enable input
input rden_a; // Port A read enable input
input rden_b; // Port B read enable input
input [width_a-1:0] data_a; // Port A data input
input [width_b-1:0] data_b; // Port B data input
input [widthad_a-1:0] address_a; // Port A address input
input [widthad_b-1:0] address_b; // Port B address input
 
// clock inputs on both ports and here are their usage
// Port A -- 1. all input registers must be clocked by clock0.
// 2. output register can be clocked by either clock0, clock1 or none.
// Port B -- 1. all input registered must be clocked by either clock0 or clock1.
// 2. output register can be clocked by either clock0, clock1 or none.
input clock0;
input clock1;
 
// clock enable inputs and here are their usage
// clocken0 -- can only be used for enabling clock0.
// clocken1 -- can only be used for enabling clock1.
// clocken2 -- as an alternative for enabling clock0.
// clocken3 -- as an alternative for enabling clock1.
input clocken0;
input clocken1;
input clocken2;
input clocken3;
 
// clear inputs on both ports and here are their usage
// Port A -- 1. all input registers can only be cleared by clear0 or none.
// 2. output register can be cleared by either clear0, clear1 or none.
// Port B -- 1. all input registers can be cleared by clear0, clear1 or none.
// 2. output register can be cleared by either clear0, clear1 or none.
input aclr0;
input aclr1;
 
input [width_byteena_a-1:0] byteena_a; // Port A byte enable input
input [width_byteena_b-1:0] byteena_b; // Port B byte enable input
 
// Stratix II related ports
input addressstall_a;
input addressstall_b;
 
 
 
// OUTPUT PORT DECLARATION
 
output [width_a-1:0] q_a; // Port A output
output [width_b-1:0] q_b; // Port B output
 
output [2:0] eccstatus; // ECC status flags
 
// INTERNAL REGISTERS DECLARATION
 
reg [width_a-1:0] mem_data [0:(1<<widthad_a)-1];
reg [width_b-1:0] mem_data_b [0:(1<<widthad_b)-1];
reg [width_a-1:0] i_data_reg_a;
reg [width_a-1:0] temp_wa;
reg [width_a-1:0] temp_wa2;
reg [width_a-1:0] temp_wa2b;
reg [width_a-1:0] init_temp;
reg [width_b-1:0] i_data_reg_b;
reg [width_b-1:0] temp_wb;
reg [width_b-1:0] temp_wb2;
reg temp;
reg [width_a-1:0] i_q_reg_a;
reg [width_a-1:0] i_q_tmp_a;
reg [width_a-1:0] i_q_tmp2_a;
reg [width_b-1:0] i_q_reg_b;
reg [width_b-1:0] i_q_tmp_b;
reg [width_b-1:0] i_q_tmp2_b;
reg [width_b-1:0] i_q_output_latch;
reg [width_a-1:0] i_byteena_mask_reg_a;
reg [width_b-1:0] i_byteena_mask_reg_b;
reg [widthad_a-1:0] i_address_reg_a;
reg [widthad_b-1:0] i_address_reg_b;
 
reg [widthad_a-1:0] i_original_address_a;
reg [width_a-1:0] i_byteena_mask_reg_a_tmp;
reg [width_b-1:0] i_byteena_mask_reg_b_tmp;
reg [width_a-1:0] i_byteena_mask_reg_a_out;
reg [width_b-1:0] i_byteena_mask_reg_b_out;
reg [width_a-1:0] i_byteena_mask_reg_a_x;
reg [width_b-1:0] i_byteena_mask_reg_b_x;
reg [width_a-1:0] i_byteena_mask_reg_a_out_b;
reg [width_b-1:0] i_byteena_mask_reg_b_out_a;
 
 
reg [8*256:1] ram_initf;
reg i_wren_reg_a;
reg i_wren_reg_b;
reg i_rden_reg_a;
reg i_rden_reg_b;
reg i_read_flag_a;
reg i_read_flag_b;
reg i_write_flag_a;
reg i_write_flag_b;
reg good_to_go_a;
reg good_to_go_b;
reg [31:0] file_desc;
reg init_file_b_port;
reg i_nmram_write_a;
reg i_nmram_write_b;
 
reg [width_a - 1: 0] wa_mult_x;
reg [width_a - 1: 0] wa_mult_x_ii;
reg [width_a - 1: 0] wa_mult_x_iii;
reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa;
reg [widthad_b + width_b -1:0] add_reg_b_mult_wb;
reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa_pl_wa;
reg [widthad_b + width_b -1:0] add_reg_b_mult_wb_pl_wb;
 
reg same_clock_pulse0;
reg same_clock_pulse1;
reg [width_b - 1 : 0] i_original_data_b;
reg [width_a - 1 : 0] i_original_data_a;
reg i_address_aclr_a_flag;
reg i_address_aclr_a_prev;
reg i_address_aclr_b_flag;
reg i_address_aclr_b_prev;
reg i_outdata_aclr_a_prev;
reg i_outdata_aclr_b_prev;
reg i_force_reread_a;
reg i_force_reread_a1;
reg i_force_reread_b;
reg i_force_reread_b1;
reg i_force_reread_a_signal;
reg i_force_reread_b_signal;
// INTERNAL PARAMETER
reg is_write_positive_edge_reg;
reg [9*8:0] cread_during_write_mode_mixed_ports;
reg i_lutram_single_port_fast_read;
reg i_lutram_dual_port_fast_read;
reg [7*8:0] i_ram_block_type;
integer i_byte_size;
wire i_good_to_write_a;
wire i_good_to_write_b;
reg i_good_to_write_a2;
reg i_good_to_write_b2;
 
reg i_core_clocken_a_reg;
reg i_core_clocken0_b_reg;
reg i_core_clocken1_b_reg;
 
wire s3_address_aclr_a;
wire s3_address_aclr_b;
 
// INTERNAL WIRE DECLARATIONS
 
wire i_indata_aclr_a;
wire i_address_aclr_a;
wire i_address_aclr_family_a;
wire i_wrcontrol_aclr_a;
wire i_indata_aclr_b;
wire i_address_aclr_b;
wire i_address_aclr_family_b;
wire i_wrcontrol_aclr_b;
wire i_outdata_aclr_a;
wire i_outdata_aclr_b;
wire i_rdcontrol_aclr_b;
wire i_byteena_aclr_a;
wire i_byteena_aclr_b;
wire i_outdata_clk_a;
wire i_outdata_clken_a;
wire i_outdata_clk_b;
wire i_outdata_clken_b;
wire i_clocken0;
wire i_clocken1_b;
wire i_clocken0_b;
wire i_core_clocken_a;
wire i_core_clocken_b;
wire i_core_clocken0_b;
wire i_core_clocken1_b;
 
// INTERNAL TRI DECLARATION
 
tri0 wren_a;
tri0 wren_b;
tri1 rden_a;
tri1 rden_b;
tri1 clock0;
tri1 clocken0;
tri1 clocken1;
tri1 clocken2;
tri1 clocken3;
tri0 aclr0;
tri0 aclr1;
tri0 addressstall_a;
tri0 addressstall_b;
tri1 [width_byteena_a-1:0] i_byteena_a;
tri1 [width_byteena_b-1:0] i_byteena_b;
 
 
// LOCAL INTEGER DECLARATION
 
integer i_numwords_a;
integer i_numwords_b;
integer i_aclr_flag_a;
integer i_aclr_flag_b;
integer i_q_tmp2_a_idx;
 
// for loop iterators
integer init_i;
integer i;
integer i2;
integer i3;
integer i4;
integer i5;
integer j;
integer j2;
integer j3;
integer k;
integer k2;
integer k3;
integer k4;
// For temporary calculation
integer i_div_wa;
integer i_div_wb;
integer j_plus_i2;
integer j2_plus_i5;
integer j3_plus_i5;
integer j_plus_i2_div_a;
integer j2_plus_i5_div_a;
integer j3_plus_i5_div_a;
integer j3_plus_i5_div_b;
integer i_byteena_count;
integer port_a_bit_count_low;
integer port_a_bit_count_high;
integer port_b_bit_count_low;
integer port_b_bit_count_high;
 
time i_data_write_time_a;
 
// ------------------------
// COMPONENT INSTANTIATIONS
// ------------------------
ALTERA_DEVICE_FAMILIES dev ();
ALTERA_MF_MEMORY_INITIALIZATION mem ();
 
// INITIAL CONSTRUCT BLOCK
 
initial
begin
 
i_numwords_a = (numwords_a != 0) ? numwords_a : (1 << widthad_a);
i_numwords_b = (numwords_b != 0) ? numwords_b : (1 << widthad_b);
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
begin
if ((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM"))
i_ram_block_type = "M144K";
else if ((((ram_block_type == "M144K") || (is_lutram == 1)) && (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)) ||
(ram_block_type == "M9K"))
i_ram_block_type = ram_block_type;
else
i_ram_block_type = "AUTO";
end
else
begin
if ((ram_block_type != "AUTO") &&
(ram_block_type != "M-RAM") && (ram_block_type != "MEGARAM") &&
(ram_block_type != "M512") &&
(ram_block_type != "M4K"))
i_ram_block_type = "AUTO";
else
i_ram_block_type = ram_block_type;
end
 
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) || (i_ram_block_type == "M9K") || (i_ram_block_type == "M144K") ||
((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (i_ram_block_type == "AUTO")))
is_write_positive_edge_reg = 1;
else
is_write_positive_edge_reg = 0;
if ((dev.FEATURE_FAMILY_CYCLONE(intended_device_family) == 1) || (dev.FEATURE_FAMILY_CYCLONEII(intended_device_family) == 1))
cread_during_write_mode_mixed_ports = "OLD_DATA";
else if (read_during_write_mode_mixed_ports == "UNUSED")
cread_during_write_mode_mixed_ports = "DONT_CARE";
else
cread_during_write_mode_mixed_ports = read_during_write_mode_mixed_ports;
if ((is_lutram == 1) &&
((read_during_write_mode_port_a == "DONT_CARE") || (outdata_reg_a == "UNREGISTERED")) &&
(operation_mode == "SINGLE_PORT"))
i_lutram_single_port_fast_read = 1;
else
i_lutram_single_port_fast_read = 0;
if ((is_lutram == 1) &&
((read_during_write_mode_mixed_ports == "NEW_DATA") ||
(read_during_write_mode_mixed_ports == "DONT_CARE") ||
((read_during_write_mode_mixed_ports == "OLD_DATA") && (outdata_reg_b == "UNREGISTERED"))))
i_lutram_dual_port_fast_read = 1;
else
i_lutram_dual_port_fast_read = 0;
i_byte_size = (byte_size > 0) ? byte_size
: ((((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) || dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9)) ||
(((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) && (i_byte_size_tmp != 1) && (i_byte_size_tmp != 2) && (i_byte_size_tmp != 4) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9)) ||
((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (i_byte_size_tmp != 5) && (i_byte_size_tmp !=10) && (i_byte_size_tmp != 8) && (i_byte_size_tmp != 9))) ?
8 : i_byte_size_tmp;
// Parameter Checking
if ((operation_mode != "BIDIR_DUAL_PORT") && (operation_mode != "SINGLE_PORT") &&
(operation_mode != "DUAL_PORT") && (operation_mode != "ROM"))
begin
$display("Error: Not a valid operation mode.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) &&
(ram_block_type != "M9K") && (ram_block_type != "M144K") && (is_lutram != 1) &&
(ram_block_type != "AUTO") && (((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM")) != 1))
begin
$display("Warning: RAM_BLOCK_TYPE HAS AN INVALID VALUE. IT CAN ONLY BE M9K, M144K, LUTRAM OR AUTO for %s device family. This parameter will take AUTO as it's value", intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
if (i_ram_block_type != ram_block_type)
begin
$display("Warning: RAM block type is assumed as %s", i_ram_block_type);
$display("Time: %0t Instance: %m", $time);
end
 
 
if ((cread_during_write_mode_mixed_ports != "DONT_CARE") &&
(cread_during_write_mode_mixed_ports != "OLD_DATA") &&
(cread_during_write_mode_mixed_ports != "NEW_DATA"))
begin
$display("Error: Invalid value for read_during_write_mode_mixed_ports parameter. It has to be OLD_DATA or DONT_CARE or NEW_DATA");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((cread_during_write_mode_mixed_ports != read_during_write_mode_mixed_ports) && ((operation_mode != "SINGLE_PORT") && (operation_mode != "ROM")))
begin
$display("Warning: read_during_write_mode_mixed_ports is assumed as %s", cread_during_write_mode_mixed_ports);
$display("Time: %0t Instance: %m", $time);
end
if ((is_lutram != 1) && (cread_during_write_mode_mixed_ports == "NEW_DATA"))
begin
$display("Warning: read_during_write_mode_mixed_ports cannot be set to NEW_DATA for non-LUTRAM ram block type. This will cause incorrect simulation result.");
$display("Time: %0t Instance: %m", $time);
end
 
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) && init_file != "UNUSED")
begin
$display("Error: M-RAM block type doesn't support the use of an initialization file");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((i_byte_size != 8) && (i_byte_size != 9) && (dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1))
begin
$display("Error: byte_size HAS TO BE EITHER 8 or 9");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((i_byte_size != 8) && (i_byte_size != 9) && (i_byte_size != 1) &&
(i_byte_size != 2) && (i_byte_size != 4) &&
((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)))
begin
$display("Error: byte_size has to be either 1, 2, 4, 8 or 9 for %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((i_byte_size != 5) && (i_byte_size != 8) && (i_byte_size != 9) && (i_byte_size != 10) &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))
begin
$display("Error: byte_size has to be either 5,8,9 or 10 for %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (width_a <= 0)
begin
$display("Error: Invalid value for WIDTH_A parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((width_b <= 0) &&
((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
begin
$display("Error: Invalid value for WIDTH_B parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (widthad_a <= 0)
begin
$display("Error: Invalid value for WIDTHAD_A parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((width_b <= 0) &&
((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
begin
$display("Error: Invalid value for WIDTHAD_B parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((operation_mode == "ROM") &&
((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")))
begin
$display("Error: ROM mode does not support RAM_BLOCK_TYPE = M-RAM");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (((wrcontrol_aclr_a != "NONE") && (wrcontrol_aclr_a != "UNUSED")) && (i_ram_block_type == "M512") && (operation_mode == "SINGLE_PORT"))
begin
$display("Error: Wren_a cannot have clear in single port mode for M512 block");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((operation_mode == "DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
begin
$display("Error: Total number of bits of port A and port B should be the same for dual port mode");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (((rdcontrol_aclr_b != "NONE") && (rdcontrol_aclr_b != "UNUSED")) && (i_ram_block_type == "M512") && (operation_mode == "DUAL_PORT"))
begin
$display("Error: rden_b cannot have clear in simple dual port mode for M512 block");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((operation_mode == "BIDIR_DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
begin
$display("Error: Total number of bits of port A and port B should be the same for bidir dual port mode");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((operation_mode == "BIDIR_DUAL_PORT") && (i_ram_block_type == "M512"))
begin
$display("Error: M512 block type doesn't support bidir dual mode");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")) &&
(cread_during_write_mode_mixed_ports == "OLD_DATA"))
begin
$display("Error: M-RAM doesn't support OLD_DATA value for READ_DURING_WRITE_MODE_MIXED_PORTS parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
(clock_enable_input_a == "BYPASS"))
begin
$display("Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
(clock_enable_output_a == "BYPASS"))
begin
$display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_A is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
(clock_enable_input_b == "BYPASS"))
begin
$display("Error: BYPASS value for CLOCK_ENABLE_INPUT_B is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family) == 1) &&
(clock_enable_output_b == "BYPASS"))
begin
$display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_B is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((implement_in_les != "OFF") && (implement_in_les != "ON"))
begin
$display("Error: Illegal value for implement_in_les parameter");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (((dev.FEATURE_FAMILY_HAS_M512(intended_device_family)) == 0) && (i_ram_block_type == "M512"))
begin
$display("Error: M512 value for RAM_BLOCK_TYPE parameter is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (((dev.FEATURE_FAMILY_HAS_MEGARAM(intended_device_family)) == 0) &&
((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM")))
begin
$display("Error: MEGARAM value for RAM_BLOCK_TYPE parameter is not supported in %s device family", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (((init_file == "UNUSED") || (init_file == "")) &&
(operation_mode == "ROM"))
begin
$display("Error! Altsyncram needs data file for memory initialization in ROM mode.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if (((dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1) || (dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) &&
(((indata_aclr_a != "UNUSED") && (indata_aclr_a != "NONE")) ||
((wrcontrol_aclr_a != "UNUSED") && (wrcontrol_aclr_a != "NONE")) ||
((byteena_aclr_a != "UNUSED") && (byteena_aclr_a != "NONE")) ||
((address_aclr_a != "UNUSED") && (address_aclr_a != "NONE") && (operation_mode != "ROM")) ||
((indata_aclr_b != "UNUSED") && (indata_aclr_b != "NONE")) ||
((rdcontrol_aclr_b != "UNUSED") && (rdcontrol_aclr_b != "NONE")) ||
((wrcontrol_aclr_b != "UNUSED") && (wrcontrol_aclr_b != "NONE")) ||
((byteena_aclr_b != "UNUSED") && (byteena_aclr_b != "NONE")) ||
((address_aclr_b != "UNUSED") && (address_aclr_b != "NONE") && (operation_mode != "DUAL_PORT"))))
begin
$display("Warning: %s device family does not support aclr signal on input ports. The aclr to input ports will be ignored.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) &&
(((indata_aclr_a != "UNUSED") && (indata_aclr_a != "NONE")) ||
((wrcontrol_aclr_a != "UNUSED") && (wrcontrol_aclr_a != "NONE")) ||
((byteena_aclr_a != "UNUSED") && (byteena_aclr_a != "NONE")) ||
((address_aclr_a != "UNUSED") && (address_aclr_a != "NONE") && (operation_mode != "ROM")) ||
((indata_aclr_b != "UNUSED") && (indata_aclr_b != "NONE")) ||
((rdcontrol_aclr_b != "UNUSED") && (rdcontrol_aclr_b != "NONE")) ||
((wrcontrol_aclr_b != "UNUSED") && (wrcontrol_aclr_b != "NONE")) ||
((byteena_aclr_b != "UNUSED") && (byteena_aclr_b != "NONE")) ||
((address_aclr_b != "UNUSED") && (address_aclr_b != "NONE") && (operation_mode != "DUAL_PORT"))))
begin
$display("Warning: %s device family does not support aclr signal on input ports. The aclr to input ports will be ignored.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
&& (read_during_write_mode_port_a != "NEW_DATA_NO_NBE_READ"))
begin
$display("Warning: %s value for read_during_write_mode_port_a is not supported in %s device family, it might cause incorrect behavioural simulation result", read_during_write_mode_port_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
&& (read_during_write_mode_port_b != "NEW_DATA_NO_NBE_READ"))
begin
$display("Warning: %s value for read_during_write_mode_port_b is not supported in %s device family, it might cause incorrect behavioural simulation result", read_during_write_mode_port_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
// SPR 249576: Enable don't care as RDW setting in MegaFunctions - eliminates checking for ram_block_type = "AUTO"
if (!((is_lutram == 1) || ((i_ram_block_type == "AUTO") && (dev.FEATURE_FAMILY_HAS_LUTRAM(intended_device_family) == 1)) ||
((i_ram_block_type != "AUTO") && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))) &&
(operation_mode != "SINGLE_PORT") && (read_during_write_mode_port_a == "DONT_CARE"))
begin
$display("Error: %s value for read_during_write_mode_port_a is not supported in %s device family for %s ram block type in %s operation_mode",
read_during_write_mode_port_a, intended_device_family, i_ram_block_type, operation_mode);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((is_lutram != 1) && (i_ram_block_type != "AUTO") &&
(read_during_write_mode_mixed_ports == "NEW_DATA"))
begin
$display("Error: %s value for read_during_write_mode_mixed_ports is not supported in %s RAM block type", read_during_write_mode_mixed_ports, i_ram_block_type);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((operation_mode == "DUAL_PORT") && (outdata_reg_b != "CLOCK0") && (is_lutram == 1) && (read_during_write_mode_mixed_ports == "OLD_DATA"))
begin
$display("Warning: Value for read_during_write_mode_mixed_ports of instance is not honoured in DUAL PORT operation mode when output registers are not clocked by clock0 for LUTRAM.");
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((indata_aclr_a != "NONE") && (indata_aclr_a != "UNUSED")))
begin
$display("Warning: %s value for indata_aclr_a is not supported in %s device family. The aclr to data_a registers will be ignored.", indata_aclr_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((wrcontrol_aclr_a != "NONE") && (wrcontrol_aclr_a != "UNUSED")))
begin
$display("Warning: %s value for wrcontrol_aclr_a is not supported in %s device family. The aclr to write control registers of port A will be ignored.", wrcontrol_aclr_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((byteena_aclr_a != "NONE") && (byteena_aclr_a != "UNUSED")))
begin
$display("Warning: %s value for byteena_aclr_a is not supported in %s device family. The aclr to byteena_a registers will be ignored.", byteena_aclr_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((address_aclr_a != "NONE") && (address_aclr_a != "UNUSED")) && (operation_mode != "ROM"))
begin
$display("Warning: %s value for address_aclr_a is not supported for write port in %s device family. The aclr to address_a registers will be ignored.", byteena_aclr_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((indata_aclr_b != "NONE") && (indata_aclr_b != "UNUSED")))
begin
$display("Warning: %s value for indata_aclr_b is not supported in %s device family. The aclr to data_b registers will be ignored.", indata_aclr_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((rdcontrol_aclr_b != "NONE") && (rdcontrol_aclr_b != "UNUSED")))
begin
$display("Warning: %s value for rdcontrol_aclr_b is not supported in %s device family. The aclr to read control registers will be ignored.", rdcontrol_aclr_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((wrcontrol_aclr_b != "NONE") && (wrcontrol_aclr_b != "UNUSED")))
begin
$display("Warning: %s value for wrcontrol_aclr_b is not supported in %s device family. The aclr to write control registers will be ignored.", wrcontrol_aclr_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((byteena_aclr_b != "NONE") && (byteena_aclr_b != "UNUSED")))
begin
$display("Warning: %s value for byteena_aclr_b is not supported in %s device family. The aclr to byteena_a register will be ignored.", byteena_aclr_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
&& ((address_aclr_b != "NONE") && (address_aclr_b != "UNUSED")) && (operation_mode == "BIDIR_DUAL_PORT"))
begin
$display("Warning: %s value for address_aclr_b is not supported for write port in %s device family. The aclr to address_b registers will be ignored.", address_aclr_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
if ((is_lutram == 1) && (read_during_write_mode_mixed_ports == "OLD_DATA")
&& ((address_aclr_b != "NONE") && (address_aclr_b != "UNUSED")) && (operation_mode == "DUAL_PORT"))
begin
$display("Warning : aclr signal for address_b is ignored for RAM block type %s when read_during_write_mode_mixed_ports is set to OLD_DATA", ram_block_type);
$display("Time: %0t Instance: %m", $time);
end
 
if (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1))
&& ((clock_enable_core_a != clock_enable_input_a) && (clock_enable_core_a != "USE_INPUT_CLKEN")))
begin
$display("Warning: clock_enable_core_a value must be USE_INPUT_CLKEN or same as clock_enable_input_a in %s device family. It will be set to clock_enable_input_a value.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1))
&& ((clock_enable_core_b != clock_enable_input_b) && (clock_enable_core_b != "USE_INPUT_CLKEN")))
begin
$display("Warning: clock_enable_core_b must be USE_INPUT_CLKEN or same as clock_enable_input_b in %s device family. It will be set to clock_enable_input_b value.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
&& (clock_enable_input_a == "ALTERNATE"))
begin
$display("Error: %s value for clock_enable_input_a is not supported in %s device family.", clock_enable_input_a, intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
&& (clock_enable_input_b == "ALTERNATE"))
begin
$display("Error: %s value for clock_enable_input_b is not supported in %s device family.", clock_enable_input_b, intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((i_ram_block_type != "M144K") && ((enable_ecc != "FALSE") && (enable_ecc != "NONE")) && (operation_mode != "DUAL_PORT"))
begin
$display("Warning: %s value for enable_ecc is not supported in %s ram block type for %s device family in %s operation mode", enable_ecc, i_ram_block_type, intended_device_family, operation_mode);
$display("Time: %0t Instance: %m", $time);
end
if ((i_ram_block_type == "M144K") && (enable_ecc == "TRUE") && (read_during_write_mode_mixed_ports == "OLD_DATA"))
begin
$display("Error : ECC is not supported for read-before-write mode.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (operation_mode != "DUAL_PORT")
begin
if ((outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1") && (outdata_reg_a != "UNUSED") && (outdata_reg_a != "UNREGISTERED"))
begin
$display("Error: %s value for outdata_reg_a is not supported.", outdata_reg_a);
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
 
if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "DUAL_PORT"))
begin
if ((address_reg_b != "CLOCK0") && (address_reg_b != "CLOCK1") && (address_reg_b != "UNUSED"))
begin
$display("Error: %s value for address_reg_b is not supported.", address_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1") && (outdata_reg_b != "UNUSED") && (outdata_reg_b != "UNREGISTERED"))
begin
$display("Error: %s value for outdata_reg_b is not supported.", outdata_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
 
if ((rdcontrol_reg_b != "CLOCK0") && (rdcontrol_reg_b != "CLOCK1") && (rdcontrol_reg_b != "UNUSED") && (operation_mode == "DUAL_PORT"))
begin
$display("Error: %s value for rdcontrol_reg_b is not supported.", rdcontrol_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((indata_reg_b != "CLOCK0") && (indata_reg_b != "CLOCK1") && (indata_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
begin
$display("Error: %s value for indata_reg_b is not supported.", indata_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((wrcontrol_wraddress_reg_b != "CLOCK0") && (wrcontrol_wraddress_reg_b != "CLOCK1") && (wrcontrol_wraddress_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
begin
$display("Error: %s value for wrcontrol_wraddress_reg_b is not supported.", wrcontrol_wraddress_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((byteena_reg_b != "CLOCK0") && (byteena_reg_b != "CLOCK1") && (byteena_reg_b != "UNUSED") && (operation_mode == "BIDIR_DUAL_PORT"))
begin
$display("Error: %s value for byteena_reg_b is not supported.", byteena_reg_b);
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
 
// *****************************************
// legal operations for all operation modes:
// | PORT A | PORT B |
// | RD WR | RD WR |
// BDP | x x | x x |
// DP | x | x |
// SP | x x | |
// ROM | x | |
// *****************************************
 
 
// Initialize mem_data
 
if ((init_file == "UNUSED") || (init_file == ""))
begin
if ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (power_up_uninitialized != "TRUE"))
begin
wa_mult_x = {width_a{1'b0}};
for (i = 0; i < (1 << widthad_a); i = i + 1)
mem_data[i] = wa_mult_x;
if (enable_mem_data_b_reading)
begin
for (i = 0; i < (1 << widthad_b); i = i + 1)
mem_data_b[i] = {width_b{1'b0}};
end
 
end
else if (((i_ram_block_type == "M-RAM") ||
(i_ram_block_type == "MEGARAM") ||
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE")) ||
(dev.FEATURE_FAMILY_STRATIX_HC(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_HARDCOPYII(intended_device_family) == 1) ||
(power_up_uninitialized == "TRUE") ) && (implement_in_les == "OFF"))
begin
wa_mult_x = {width_a{1'bx}};
for (i = 0; i < (1 << widthad_a); i = i + 1)
mem_data[i] = wa_mult_x;
 
if (enable_mem_data_b_reading)
begin
for (i = 0; i < (1 << widthad_b); i = i + 1)
mem_data_b[i] = {width_b{1'bx}};
end
end
else
begin
wa_mult_x = {width_a{1'b0}};
for (i = 0; i < (1 << widthad_a); i = i + 1)
mem_data[i] = wa_mult_x;
if (enable_mem_data_b_reading)
begin
for (i = 0; i < (1 << widthad_b); i = i + 1)
mem_data_b[i] = {width_b{1'b0}};
end
end
end
 
else // Memory initialization file is used
begin
 
wa_mult_x = {width_a{1'b0}};
for (i = 0; i < (1 << widthad_a); i = i + 1)
mem_data[i] = wa_mult_x;
for (i = 0; i < (1 << widthad_b); i = i + 1)
mem_data_b[i] = {width_b{1'b0}};
 
init_file_b_port = 0;
 
if ((init_file_layout != "PORT_A") &&
(init_file_layout != "PORT_B"))
begin
if (operation_mode == "DUAL_PORT")
init_file_b_port = 1;
else
init_file_b_port = 0;
end
else
begin
if (init_file_layout == "PORT_A")
init_file_b_port = 0;
else if (init_file_layout == "PORT_B")
init_file_b_port = 1;
end
 
if (init_file_b_port)
begin
`ifdef NO_PLI
$readmemh(init_file, mem_data_b);
`else
`ifdef USE_RIF
$readmemh(init_file, mem_data_b);
`else
mem.convert_to_ver_file(init_file, width_b, ram_initf);
$readmemh(ram_initf, mem_data_b);
`endif
`endif
 
for (i = 0; i < (i_numwords_b * width_b); i = i + 1)
begin
temp_wb = mem_data_b[i / width_b];
i_div_wa = i / width_a;
temp_wa = mem_data[i_div_wa];
temp_wa[i % width_a] = temp_wb[i % width_b];
mem_data[i_div_wa] = temp_wa;
end
end
else
begin
`ifdef NO_PLI
$readmemh(init_file, mem_data);
`else
`ifdef USE_RIF
$readmemh(init_file, mem_data);
`else
mem.convert_to_ver_file(init_file, width_a, ram_initf);
$readmemh(ram_initf, mem_data);
`endif
`endif
if (enable_mem_data_b_reading)
begin
for (i = 0; i < (i_numwords_a * width_a); i = i + 1)
begin
temp_wa = mem_data[i / width_a];
i_div_wb = i / width_b;
temp_wb = mem_data_b[i_div_wb];
temp_wb[i % width_b] = temp_wa[i % width_a];
mem_data_b[i_div_wb] = temp_wb;
end
end
end
end
i_nmram_write_a = 0;
i_nmram_write_b = 0;
 
i_aclr_flag_a = 0;
i_aclr_flag_b = 0;
 
i_outdata_aclr_a_prev = 0;
i_outdata_aclr_b_prev = 0;
i_address_aclr_a_prev = 0;
i_address_aclr_b_prev = 0;
i_force_reread_a = 0;
i_force_reread_a1 = 0;
i_force_reread_b = 0;
i_force_reread_b1 = 0;
i_force_reread_a_signal = 0;
i_force_reread_b_signal = 0;
// Initialize internal registers/signals
i_data_reg_a = 0;
i_data_reg_b = 0;
i_address_reg_a = 0;
i_address_reg_b = 0;
i_original_address_a = 0;
i_wren_reg_a = 0;
i_wren_reg_b = 0;
i_read_flag_a = 0;
i_read_flag_b = 0;
i_write_flag_a = 0;
i_write_flag_b = 0;
i_byteena_mask_reg_a = {width_a{1'b1}};
i_byteena_mask_reg_b = {width_b{1'b1}};
i_byteena_mask_reg_a_x = 0;
i_byteena_mask_reg_b_x = 0;
i_byteena_mask_reg_a_out = {width_a{1'b1}};
i_byteena_mask_reg_b_out = {width_b{1'b1}};
i_original_data_b = 0;
i_original_data_a = 0;
i_data_write_time_a = 0;
i_core_clocken_a_reg = 0;
i_core_clocken0_b_reg = 0;
i_core_clocken1_b_reg = 0;
 
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
begin
i_rden_reg_a = 0;
i_rden_reg_b = 0;
end
else
begin
i_rden_reg_a = 1;
i_rden_reg_b = 1;
end
 
 
if (((i_ram_block_type == "M-RAM") ||
(i_ram_block_type == "MEGARAM") ||
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE"))) &&
dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)
begin
i_q_tmp_a = {width_a{1'bx}};
i_q_tmp_b = {width_b{1'bx}};
i_q_tmp2_a = {width_a{1'bx}};
i_q_tmp2_b = {width_b{1'bx}};
i_q_reg_a = {width_a{1'bx}};
i_q_reg_b = {width_b{1'bx}};
end
else
begin
if (is_lutram == 1)
begin
i_q_tmp_a = mem_data[0];
i_q_tmp2_a = mem_data[0];
 
for (init_i = 0; init_i < width_b; init_i = init_i + 1)
begin
init_temp = mem_data[init_i / width_a];
i_q_tmp_b[init_i] = init_temp[init_i % width_a];
i_q_tmp2_b[init_i] = init_temp[init_i % width_a];
end
 
i_q_reg_a = 0;
i_q_reg_b = 0;
i_q_output_latch = 0;
end
else
begin
i_q_tmp_a = 0;
i_q_tmp_b = 0;
i_q_tmp2_a = 0;
i_q_tmp2_b = 0;
i_q_reg_a = 0;
i_q_reg_b = 0;
end
end
 
good_to_go_a = 0;
good_to_go_b = 0;
 
same_clock_pulse0 = 1'b0;
same_clock_pulse1 = 1'b0;
 
i_byteena_count = 0;
if (((dev.FEATURE_FAMILY_STRATIX_HC(intended_device_family) == 1) || (dev.FEATURE_FAMILY_HARDCOPYII(intended_device_family) == 1)) &&
(ram_block_type == "M4K") && (operation_mode != "SINGLE_PORT"))
begin
i_good_to_write_a2 = 0;
i_good_to_write_b2 = 0;
end
else
begin
i_good_to_write_a2 = 1;
i_good_to_write_b2 = 1;
end
 
end
 
 
// SIGNAL ASSIGNMENT
 
// Clock signal assignment
 
// port a clock assignments:
assign i_outdata_clk_a = (outdata_reg_a == "CLOCK1") ?
clock1 : ((outdata_reg_a == "CLOCK0") ?
clock0 : 1'b0);
// port b clock assignments:
assign i_outdata_clk_b = (outdata_reg_b == "CLOCK1") ?
clock1 : ((outdata_reg_b == "CLOCK0") ?
clock0 : 1'b0);
 
// Clock enable signal assignment
 
// port a clock enable assignments:
assign i_outdata_clken_a = (clock_enable_output_a == "BYPASS") ?
1'b1 : ((clock_enable_output_a == "ALTERNATE") && (outdata_reg_a == "CLOCK1")) ?
clocken3 : ((clock_enable_output_a == "ALTERNATE") && (outdata_reg_a == "CLOCK0")) ?
clocken2 : (outdata_reg_a == "CLOCK1") ?
clocken1 : (outdata_reg_a == "CLOCK0") ?
clocken0 : 1'b1;
// port b clock enable assignments:
assign i_outdata_clken_b = (clock_enable_output_b == "BYPASS") ?
1'b1 : ((clock_enable_output_b == "ALTERNATE") && (outdata_reg_b == "CLOCK1")) ?
clocken3 : ((clock_enable_output_b == "ALTERNATE") && (outdata_reg_b == "CLOCK0")) ?
clocken2 : (outdata_reg_b == "CLOCK1") ?
clocken1 : (outdata_reg_b == "CLOCK0") ?
clocken0 : 1'b1;
 
 
assign i_clocken0 = (clock_enable_input_a == "BYPASS") ?
1'b1 : (clock_enable_input_a == "NORMAL") ?
clocken0 : clocken2;
 
assign i_clocken0_b = (clock_enable_input_b == "BYPASS") ?
1'b1 : (clock_enable_input_b == "NORMAL") ?
clocken0 : clocken2;
 
assign i_clocken1_b = (clock_enable_input_b == "BYPASS") ?
1'b1 : (clock_enable_input_b == "NORMAL") ?
clocken1 : clocken3;
 
assign i_core_clocken_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
i_clocken0 : ((clock_enable_core_a == "BYPASS") ?
1'b1 : ((clock_enable_core_a == "USE_INPUT_CLKEN") ?
i_clocken0 : ((clock_enable_core_a == "NORMAL") ?
clocken0 : clocken2)));
assign i_core_clocken0_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
i_clocken0_b : ((clock_enable_core_b == "BYPASS") ?
1'b1 : ((clock_enable_core_b == "USE_INPUT_CLKEN") ?
i_clocken0_b : ((clock_enable_core_b == "NORMAL") ?
clocken0 : clocken2)));
 
assign i_core_clocken1_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) != 1)) ?
i_clocken1_b : ((clock_enable_core_b == "BYPASS") ?
1'b1 : ((clock_enable_core_b == "USE_INPUT_CLKEN") ?
i_clocken1_b : ((clock_enable_core_b == "NORMAL") ?
clocken1 : clocken3)));
 
assign i_core_clocken_b = (address_reg_b == "CLOCK0") ?
i_core_clocken0_b : i_core_clocken1_b;
 
// Async clear signal assignment
 
// port a clear assigments:
 
assign i_indata_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b0 : ((indata_aclr_a == "CLEAR0") ? aclr0 : 1'b0);
assign i_address_aclr_a = (address_aclr_a == "CLEAR0") ? aclr0 : 1'b0;
assign i_wrcontrol_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
1'b0 : ((wrcontrol_aclr_a == "CLEAR0") ? aclr0 : 1'b0);
assign i_byteena_aclr_a = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b0 : ((byteena_aclr_a == "CLEAR0") ?
aclr0 : ((byteena_aclr_a == "CLEAR1") ?
aclr1 : 1'b0));
assign i_outdata_aclr_a = (outdata_aclr_a == "CLEAR0") ?
aclr0 : ((outdata_aclr_a == "CLEAR1") ?
aclr1 : 1'b0);
// port b clear assignments:
assign i_indata_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
1'b0 : ((indata_aclr_b == "CLEAR0") ?
aclr0 : ((indata_aclr_b == "CLEAR1") ?
aclr1 : 1'b0));
assign i_address_aclr_b = (address_aclr_b == "CLEAR0") ?
aclr0 : ((address_aclr_b == "CLEAR1") ?
aclr1 : 1'b0);
assign i_wrcontrol_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1))?
1'b0 : ((wrcontrol_aclr_b == "CLEAR0") ?
aclr0 : ((wrcontrol_aclr_b == "CLEAR1") ?
aclr1 : 1'b0));
assign i_rdcontrol_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b0 : ((rdcontrol_aclr_b == "CLEAR0") ?
aclr0 : ((rdcontrol_aclr_b == "CLEAR1") ?
aclr1 : 1'b0));
assign i_byteena_aclr_b = ((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b0 : ((byteena_aclr_b == "CLEAR0") ?
aclr0 : ((byteena_aclr_b == "CLEAR1") ?
aclr1 : 1'b0));
assign i_outdata_aclr_b = (outdata_aclr_b == "CLEAR0") ?
aclr0 : ((outdata_aclr_b == "CLEAR1") ?
aclr1 : 1'b0);
 
assign i_byteena_a = byteena_a;
assign i_byteena_b = byteena_b;
// Ready to write setting
assign i_good_to_write_a = (((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)) && (i_core_clocken0_b) && (~clock0)) ?
1'b1 : (((is_bidir_and_wrcontrol_addb_clk1 == 1) || (dual_port_addreg_b_clk1 == 1)) && (i_core_clocken1_b) && (~clock1)) ?
1'b1 : i_good_to_write_a2;
assign i_good_to_write_b = ((i_core_clocken0_b) && (~clock0)) ? 1'b1 : i_good_to_write_b2;
assign s3_address_aclr_a = ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) && (is_lutram != 1) && (outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1")) ?
1'b1 : 1'b0;
 
assign s3_address_aclr_b = ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) && (is_lutram != 1) && (outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1")) ?
1'b1 : 1'b0;
 
assign i_address_aclr_family_a = (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (operation_mode != "ROM")) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b1 : 1'b0;
assign i_address_aclr_family_b = (((dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (operation_mode != "DUAL_PORT")) ||
((is_lutram == 1) && (operation_mode == "DUAL_PORT") && (read_during_write_mode_mixed_ports == "OLD_DATA")) ||
(dev.FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) == 1 || dev.FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) == 1)) ?
1'b1 : 1'b0;
 
always @(i_good_to_write_a)
begin
i_good_to_write_a2 = i_good_to_write_a;
end
always @(i_good_to_write_b)
begin
i_good_to_write_b2 = i_good_to_write_b;
end
// Port A inputs registered : indata, address, byeteena, wren
// Aclr status flags get updated here for M-RAM ram_block_type
 
always @(posedge clock0)
begin
if (i_force_reread_a)
begin
i_force_reread_a_signal <= ~ i_force_reread_a_signal;
i_force_reread_a <= 0;
end
if (i_force_reread_b && ((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)))
begin
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
i_force_reread_b <= 0;
end
 
if (clock1)
same_clock_pulse0 <= 1'b1;
else
same_clock_pulse0 <= 1'b0;
 
if (i_address_aclr_a && (~i_address_aclr_family_a))
i_address_reg_a <= 0;
 
i_core_clocken_a_reg <= i_core_clocken_a;
i_core_clocken0_b_reg <= i_core_clocken0_b;
 
if (i_core_clocken_a)
begin
 
if (i_force_reread_a1)
begin
i_force_reread_a_signal <= ~ i_force_reread_a_signal;
i_force_reread_a1 <= 0;
end
i_read_flag_a <= ~ i_read_flag_a;
if (i_force_reread_b1 && ((is_bidir_and_wrcontrol_addb_clk0 == 1) || (dual_port_addreg_b_clk0 == 1)))
begin
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
i_force_reread_b1 <= 0;
end
if (is_write_positive_edge_reg)
begin
if (i_wren_reg_a || wren_a)
begin
i_write_flag_a <= ~ i_write_flag_a;
end
if (operation_mode != "ROM")
i_nmram_write_a <= 1'b0;
end
else
begin
if (operation_mode != "ROM")
i_nmram_write_a <= 1'b1;
end
 
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && (is_lutram != 1))
begin
good_to_go_a <= 1;
i_rden_reg_a <= rden_a;
 
if (i_wrcontrol_aclr_a)
i_wren_reg_a <= 0;
else
begin
i_wren_reg_a <= wren_a;
end
end
end
else
i_nmram_write_a <= 1'b0;
 
if (i_core_clocken_b)
i_address_aclr_b_flag <= 0;
 
if (is_lutram)
begin
if (i_wrcontrol_aclr_a)
i_wren_reg_a <= 0;
else if (i_core_clocken_a)
begin
i_wren_reg_a <= wren_a;
end
end
 
if ((clock_enable_input_a == "BYPASS") ||
((clock_enable_input_a == "NORMAL") && clocken0) ||
((clock_enable_input_a == "ALTERNATE") && clocken2))
begin
 
// Port A inputs
if (i_indata_aclr_a)
i_data_reg_a <= 0;
else
i_data_reg_a <= data_a;
 
if (i_address_aclr_a && (~i_address_aclr_family_a))
i_address_reg_a <= 0;
else if (!addressstall_a)
i_address_reg_a <= address_a;
 
if (i_byteena_aclr_a)
begin
i_byteena_mask_reg_a <= {width_a{1'b1}};
i_byteena_mask_reg_a_out <= 0;
i_byteena_mask_reg_a_x <= 0;
i_byteena_mask_reg_a_out_b <= {width_a{1'bx}};
end
else
begin
if (width_byteena_a == 1)
begin
i_byteena_mask_reg_a <= {width_a{i_byteena_a[0]}};
i_byteena_mask_reg_a_out <= (i_byteena_a[0])? {width_a{1'b0}} : {width_a{1'bx}};
i_byteena_mask_reg_a_out_b <= (i_byteena_a[0])? {width_a{1'bx}} : {width_a{1'b0}};
i_byteena_mask_reg_a_x <= ((i_byteena_a[0]) || (i_byteena_a[0] == 1'b0))? {width_a{1'b0}} : {width_a{1'bx}};
end
else
for (k = 0; k < width_a; k = k+1)
begin
i_byteena_mask_reg_a[k] <= i_byteena_a[k/i_byte_size];
i_byteena_mask_reg_a_out_b[k] <= (i_byteena_a[k/i_byte_size])? 1'bx: 1'b0;
i_byteena_mask_reg_a_out[k] <= (i_byteena_a[k/i_byte_size])? 1'b0: 1'bx;
i_byteena_mask_reg_a_x[k] <= ((i_byteena_a[k/i_byte_size]) || (i_byteena_a[k/i_byte_size] == 1'b0))? 1'b0: 1'bx;
end
end
 
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) ||
(is_lutram == 1))
begin
good_to_go_a <= 1;
i_rden_reg_a <= rden_a;
if (i_wrcontrol_aclr_a)
i_wren_reg_a <= 0;
else
begin
i_wren_reg_a <= wren_a;
end
end
 
end
if (i_indata_aclr_a)
i_data_reg_a <= 0;
 
if (i_address_aclr_a && (~i_address_aclr_family_a))
i_address_reg_a <= 0;
 
if (i_byteena_aclr_a)
begin
i_byteena_mask_reg_a <= {width_a{1'b1}};
i_byteena_mask_reg_a_out <= 0;
i_byteena_mask_reg_a_x <= 0;
i_byteena_mask_reg_a_out_b <= {width_a{1'bx}};
end
// Port B
 
if (is_bidir_and_wrcontrol_addb_clk0)
begin
 
if (i_core_clocken0_b)
begin
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)
begin
good_to_go_b <= 1;
i_rden_reg_b <= rden_b;
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
else
begin
i_wren_reg_b <= wren_b;
end
end
i_read_flag_b <= ~i_read_flag_b;
if (is_write_positive_edge_reg)
begin
if (i_wren_reg_b || wren_b)
begin
i_write_flag_b <= ~ i_write_flag_b;
end
i_nmram_write_b <= 1'b0;
end
else
i_nmram_write_b <= 1'b1;
end
else
i_nmram_write_b <= 1'b0;
if ((clock_enable_input_b == "BYPASS") ||
((clock_enable_input_b == "NORMAL") && clocken0) ||
((clock_enable_input_b == "ALTERNATE") && clocken2))
begin
 
// Port B inputs
 
if (i_indata_aclr_b)
i_data_reg_b <= 0;
else
i_data_reg_b <= data_b;
 
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0)
begin
good_to_go_b <= 1;
i_rden_reg_b <= rden_b;
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
else
begin
i_wren_reg_b <= wren_b;
end
end
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
else if (!addressstall_b)
i_address_reg_b <= address_b;
 
if (i_byteena_aclr_b)
begin
i_byteena_mask_reg_b <= {width_b{1'b1}};
i_byteena_mask_reg_b_out <= 0;
i_byteena_mask_reg_b_x <= 0;
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
end
else
begin
if (width_byteena_b == 1)
begin
i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
i_byteena_mask_reg_b_out_a <= (i_byteena_b[0])? {width_b{1'bx}} : {width_b{1'b0}};
i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
end
else
for (k2 = 0; k2 < width_b; k2 = k2 + 1)
begin
i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/i_byte_size];
i_byteena_mask_reg_b_out_a[k2] <= (i_byteena_b[k2/i_byte_size])? 1'bx : 1'b0;
i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/i_byte_size])? 1'b0 : 1'bx;
i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/i_byte_size]) || (i_byteena_b[k2/i_byte_size] == 1'b0))? 1'b0 : 1'bx;
end
end
 
end
if (i_indata_aclr_b)
i_data_reg_b <= 0;
 
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
 
if (i_byteena_aclr_b)
begin
i_byteena_mask_reg_b <= {width_b{1'b1}};
i_byteena_mask_reg_b_out <= 0;
i_byteena_mask_reg_b_x <= 0;
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
end
end
if (dual_port_addreg_b_clk0)
begin
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
 
if (i_core_clocken0_b)
begin
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && !is_lutram)
begin
good_to_go_b <= 1;
if (i_rdcontrol_aclr_b)
i_rden_reg_b <= 1'b1;
else
i_rden_reg_b <= rden_b;
end
i_read_flag_b <= ~ i_read_flag_b;
end
if ((clock_enable_input_b == "BYPASS") ||
((clock_enable_input_b == "NORMAL") && clocken0) ||
((clock_enable_input_b == "ALTERNATE") && clocken2))
begin
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) || is_lutram)
begin
good_to_go_b <= 1;
if (i_rdcontrol_aclr_b)
i_rden_reg_b <= 1'b1;
else
i_rden_reg_b <= rden_b;
end
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
else if (!addressstall_b)
i_address_reg_b <= address_b;
 
end
if (i_rdcontrol_aclr_b)
i_rden_reg_b <= 1'b1;
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
 
end
 
end
 
 
always @(negedge clock0)
begin
if (clock1)
same_clock_pulse0 <= 1'b0;
 
if (!is_write_positive_edge_reg)
begin
if (i_nmram_write_a == 1'b1)
begin
i_write_flag_a <= ~ i_write_flag_a;
if (is_lutram)
i_read_flag_a <= ~i_read_flag_a;
end
 
if (is_bidir_and_wrcontrol_addb_clk0)
begin
if (i_nmram_write_b == 1'b1)
i_write_flag_b <= ~ i_write_flag_b;
end
end
 
if (i_core_clocken0_b && i_lutram_dual_port_fast_read && (dual_port_addreg_b_clk0 == 1))
begin
i_read_flag_b <= ~i_read_flag_b;
end
 
end
 
 
 
always @(posedge clock1)
begin
i_core_clocken1_b_reg <= i_core_clocken1_b;
 
if (i_force_reread_b && ((is_bidir_and_wrcontrol_addb_clk1 == 1) || (dual_port_addreg_b_clk1 == 1)))
begin
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
i_force_reread_b <= 0;
end
if (clock0)
same_clock_pulse1 <= 1'b1;
else
same_clock_pulse1 <= 1'b0;
 
if (i_core_clocken_b)
i_address_aclr_b_flag <= 0;
 
if (is_bidir_and_wrcontrol_addb_clk1)
begin
 
if (i_core_clocken1_b)
begin
i_read_flag_b <= ~i_read_flag_b;
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1)
begin
good_to_go_b <= 1;
i_rden_reg_b <= rden_b;
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
else
begin
i_wren_reg_b <= wren_b;
end
end
if (is_write_positive_edge_reg)
begin
if (i_wren_reg_b || wren_b)
begin
i_write_flag_b <= ~ i_write_flag_b;
end
i_nmram_write_b <= 1'b0;
end
else
i_nmram_write_b <= 1'b1;
end
else
i_nmram_write_b <= 1'b0;
if ((clock_enable_input_b == "BYPASS") ||
((clock_enable_input_b == "NORMAL") && clocken1) ||
((clock_enable_input_b == "ALTERNATE") && clocken3))
begin
// Port B inputs
if (address_reg_b == "CLOCK1")
begin
if (i_indata_aclr_b)
i_data_reg_b <= 0;
else
i_data_reg_b <= data_b;
end
 
if (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0)
begin
good_to_go_b <= 1;
i_rden_reg_b <= rden_b;
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
else
begin
i_wren_reg_b <= wren_b;
end
end
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
else if (!addressstall_b)
i_address_reg_b <= address_b;
 
if (i_byteena_aclr_b)
begin
i_byteena_mask_reg_b <= {width_b{1'b1}};
i_byteena_mask_reg_b_out <= 0;
i_byteena_mask_reg_b_x <= 0;
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
end
else
begin
if (width_byteena_b == 1)
begin
i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
i_byteena_mask_reg_b_out_a <= (i_byteena_b[0])? {width_b{1'bx}} : {width_b{1'b0}};
i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
end
else
for (k2 = 0; k2 < width_b; k2 = k2 + 1)
begin
i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/i_byte_size];
i_byteena_mask_reg_b_out_a[k2] <= (i_byteena_b[k2/i_byte_size])? 1'bx : 1'b0;
i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/i_byte_size])? 1'b0 : 1'bx;
i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/i_byte_size]) || (i_byteena_b[k2/i_byte_size] == 1'b0))? 1'b0 : 1'bx;
end
end
 
end
if (i_indata_aclr_b)
i_data_reg_b <= 0;
 
if (i_wrcontrol_aclr_b)
i_wren_reg_b <= 0;
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
 
if (i_byteena_aclr_b)
begin
i_byteena_mask_reg_b <= {width_b{1'b1}};
i_byteena_mask_reg_b_out <= 0;
i_byteena_mask_reg_b_x <= 0;
i_byteena_mask_reg_b_out_a <= {width_b{1'bx}};
end
end
 
if (dual_port_addreg_b_clk1)
begin
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
 
if (i_core_clocken1_b)
begin
if (i_force_reread_b1)
begin
i_force_reread_b_signal <= ~ i_force_reread_b_signal;
i_force_reread_b1 <= 0;
end
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 1) && !is_lutram)
begin
good_to_go_b <= 1;
if (i_rdcontrol_aclr_b)
begin
i_rden_reg_b <= 1'b1;
end
else
begin
i_rden_reg_b <= rden_b;
end
end
 
i_read_flag_b <= ~i_read_flag_b;
end
if ((clock_enable_input_b == "BYPASS") ||
((clock_enable_input_b == "NORMAL") && clocken1) ||
((clock_enable_input_b == "ALTERNATE") && clocken3))
begin
if ((dev.FEATURE_FAMILY_STRATIXIII(intended_device_family) == 0) || is_lutram)
begin
good_to_go_b <= 1;
if (i_rdcontrol_aclr_b)
begin
i_rden_reg_b <= 1'b1;
end
else
begin
i_rden_reg_b <= rden_b;
end
end
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
else if (!addressstall_b)
i_address_reg_b <= address_b;
 
end
if (i_rdcontrol_aclr_b)
i_rden_reg_b <= 1'b1;
 
if (i_address_aclr_b && (~i_address_aclr_family_b))
i_address_reg_b <= 0;
end
 
end
 
always @(negedge clock1)
begin
if (clock0)
same_clock_pulse1 <= 1'b0;
if (!is_write_positive_edge_reg)
begin
if (is_bidir_and_wrcontrol_addb_clk1)
begin
if (i_nmram_write_b == 1'b1)
i_write_flag_b <= ~ i_write_flag_b;
end
end
 
if (i_core_clocken1_b && i_lutram_dual_port_fast_read && (dual_port_addreg_b_clk1 ==1))
begin
i_read_flag_b <= ~i_read_flag_b;
end
 
end
always @(posedge i_address_aclr_b)
begin
if ((is_lutram == 1) && (operation_mode == "DUAL_PORT") && (~i_address_aclr_family_b))
i_read_flag_b <= ~i_read_flag_b;
end
 
always @(posedge i_address_aclr_a)
begin
if ((is_lutram == 1) && (operation_mode == "ROM") && (~i_address_aclr_family_a))
i_read_flag_a <= ~i_read_flag_a;
end
always @(posedge i_outdata_aclr_a)
begin
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
((outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1")))
i_read_flag_a <= ~i_read_flag_a;
end
 
always @(posedge i_outdata_aclr_b)
begin
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
((outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1")))
i_read_flag_b <= ~i_read_flag_b;
end
// Port A writting -------------------------------------------------------------
 
always @(posedge i_write_flag_a or negedge i_write_flag_a)
begin
if ((operation_mode == "BIDIR_DUAL_PORT") ||
(operation_mode == "DUAL_PORT") ||
(operation_mode == "SINGLE_PORT"))
begin
 
if ((i_wren_reg_a) && (i_good_to_write_a))
begin
i_aclr_flag_a = 0;
 
if (i_indata_aclr_a)
begin
if (i_data_reg_a != 0)
begin
mem_data[i_address_reg_a] = {width_a{1'bx}};
 
if (enable_mem_data_b_reading)
begin
j3 = i_address_reg_a * width_a;
for (i5 = 0; i5 < width_a; i5 = i5+1)
begin
j3_plus_i5 = j3 + i5;
temp_wb = mem_data_b[j3_plus_i5 / width_b];
temp_wb[j3_plus_i5 % width_b] = {1'bx};
mem_data_b[j3_plus_i5 / width_b] = temp_wb;
end
end
i_aclr_flag_a = 1;
end
end
else if (i_byteena_aclr_a)
begin
if (i_byteena_mask_reg_a != {width_a{1'b1}})
begin
mem_data[i_address_reg_a] = {width_a{1'bx}};
if (enable_mem_data_b_reading)
begin
j3 = i_address_reg_a * width_a;
for (i5 = 0; i5 < width_a; i5 = i5+1)
begin
j3_plus_i5 = j3 + i5;
temp_wb = mem_data_b[j3_plus_i5 / width_b];
temp_wb[j3_plus_i5 % width_b] = {1'bx};
mem_data_b[j3_plus_i5 / width_b] = temp_wb;
end
end
i_aclr_flag_a = 1;
end
end
else if (i_address_aclr_a && (~i_address_aclr_family_a))
begin
if (i_address_reg_a != 0)
begin
wa_mult_x_ii = {width_a{1'bx}};
for (i4 = 0; i4 < i_numwords_a; i4 = i4 + 1)
mem_data[i4] = wa_mult_x_ii;
if (enable_mem_data_b_reading)
begin
for (i4 = 0; i4 < i_numwords_b; i4 = i4 + 1)
mem_data_b[i4] = {width_b{1'bx}};
end
 
i_aclr_flag_a = 1;
end
end
 
if (i_aclr_flag_a == 0)
begin
i_original_data_a = mem_data[i_address_reg_a];
i_original_address_a = i_address_reg_a;
i_data_write_time_a = $time;
temp_wa = mem_data[i_address_reg_a];
port_a_bit_count_low = i_address_reg_a * width_a;
port_b_bit_count_low = i_address_reg_b * width_b;
port_b_bit_count_high = port_b_bit_count_low + width_b;
for (i5 = 0; i5 < width_a; i5 = i5 + 1)
begin
i_byteena_count = port_a_bit_count_low % width_b;
 
if ((port_a_bit_count_low >= port_b_bit_count_low) && (port_a_bit_count_low < port_b_bit_count_high) &&
((i_core_clocken0_b_reg && (is_bidir_and_wrcontrol_addb_clk0 == 1)) || (i_core_clocken1_b_reg && (is_bidir_and_wrcontrol_addb_clk1 == 1))) &&
(i_wren_reg_b) && ((same_clock_pulse0 && same_clock_pulse1) || (address_reg_b == "CLOCK0")) &&
(i_byteena_mask_reg_b[i_byteena_count]) && (i_byteena_mask_reg_a[i5]))
temp_wa[i5] = {1'bx};
else if (i_byteena_mask_reg_a[i5])
temp_wa[i5] = i_data_reg_a[i5];
 
if (enable_mem_data_b_reading)
begin
temp_wb = mem_data_b[port_a_bit_count_low / width_b];
temp_wb[port_a_bit_count_low % width_b] = temp_wa[i5];
mem_data_b[port_a_bit_count_low / width_b] = temp_wb;
end
 
port_a_bit_count_low = port_a_bit_count_low + 1;
end
 
mem_data[i_address_reg_a] = temp_wa;
 
if (((cread_during_write_mode_mixed_ports == "OLD_DATA") && (is_write_positive_edge_reg) && (address_reg_b == "CLOCK0")) ||
((i_lutram_dual_port_fast_read == 1) && (operation_mode == "DUAL_PORT")))
i_read_flag_b = ~i_read_flag_b;
if ((read_during_write_mode_port_a == "OLD_DATA") ||
((is_lutram == 1) && (read_during_write_mode_port_a == "DONT_CARE")))
i_read_flag_a = ~i_read_flag_a;
end
 
end
end
end // Port A writting ----------------------------------------------------
 
 
// Port B writting -----------------------------------------------------------
 
always @(posedge i_write_flag_b or negedge i_write_flag_b)
begin
if (operation_mode == "BIDIR_DUAL_PORT")
begin
 
if ((i_wren_reg_b) && (i_good_to_write_b))
begin
i_aclr_flag_b = 0;
 
// RAM content is following width_a
// if Port B is of different width, need to make some adjustments
 
if (i_indata_aclr_b)
begin
if (i_data_reg_b != 0)
begin
if (enable_mem_data_b_reading)
mem_data_b[i_address_reg_b] = {width_b{1'bx}};
if (width_a == width_b)
mem_data[i_address_reg_b] = {width_b{1'bx}};
else
begin
j = i_address_reg_b * width_b;
for (i2 = 0; i2 < width_b; i2 = i2+1)
begin
j_plus_i2 = j + i2;
temp_wa = mem_data[j_plus_i2 / width_a];
temp_wa[j_plus_i2 % width_a] = {1'bx};
mem_data[j_plus_i2 / width_a] = temp_wa;
end
end
i_aclr_flag_b = 1;
end
end
else if (i_byteena_aclr_b)
begin
if (i_byteena_mask_reg_b != {width_b{1'b1}})
begin
if (enable_mem_data_b_reading)
mem_data_b[i_address_reg_b] = {width_b{1'bx}};
if (width_a == width_b)
mem_data[i_address_reg_b] = {width_b{1'bx}};
else
begin
j = i_address_reg_b * width_b;
for (i2 = 0; i2 < width_b; i2 = i2+1)
begin
j_plus_i2 = j + i2;
j_plus_i2_div_a = j_plus_i2 / width_a;
temp_wa = mem_data[j_plus_i2_div_a];
temp_wa[j_plus_i2 % width_a] = {1'bx};
mem_data[j_plus_i2_div_a] = temp_wa;
end
end
i_aclr_flag_b = 1;
end
end
else if (i_address_aclr_b && (~i_address_aclr_family_b))
begin
if (i_address_reg_b != 0)
begin
if (enable_mem_data_b_reading)
begin
for (i2 = 0; i2 < i_numwords_b; i2 = i2 + 1)
begin
mem_data_b[i2] = {width_b{1'bx}};
end
end
wa_mult_x_iii = {width_a{1'bx}};
for (i2 = 0; i2 < i_numwords_a; i2 = i2 + 1)
begin
mem_data[i2] = wa_mult_x_iii;
end
i_aclr_flag_b = 1;
end
end
 
if (i_aclr_flag_b == 0)
begin
port_b_bit_count_low = i_address_reg_b * width_b;
port_a_bit_count_low = i_address_reg_a * width_a;
port_a_bit_count_high = port_a_bit_count_low + width_a;
for (i2 = 0; i2 < width_b; i2 = i2 + 1)
begin
port_b_bit_count_high = port_b_bit_count_low + i2;
temp_wa = mem_data[port_b_bit_count_high / width_a];
i_original_data_b[i2] = temp_wa[port_b_bit_count_high % width_a];
if ((port_b_bit_count_high >= port_a_bit_count_low) && (port_b_bit_count_high < port_a_bit_count_high) &&
((same_clock_pulse0 && same_clock_pulse1) || (address_reg_b == "CLOCK0")) &&
(i_core_clocken_a_reg) && (i_wren_reg_a) &&
(i_byteena_mask_reg_a[port_b_bit_count_high % width_a]) && (i_byteena_mask_reg_b[i2]))
temp_wa[port_b_bit_count_high % width_a] = {1'bx};
else if (i_byteena_mask_reg_b[i2])
temp_wa[port_b_bit_count_high % width_a] = i_data_reg_b[i2];
mem_data[port_b_bit_count_high / width_a] = temp_wa;
temp_wb[i2] = temp_wa[port_b_bit_count_high % width_a];
end
 
if (enable_mem_data_b_reading)
mem_data_b[i_address_reg_b] = temp_wb;
 
if ((read_during_write_mode_port_b == "OLD_DATA") && is_write_positive_edge_reg)
i_read_flag_b = ~i_read_flag_b;
if ((cread_during_write_mode_mixed_ports == "OLD_DATA")&& (address_reg_b == "CLOCK0") && is_write_positive_edge_reg)
i_read_flag_a = ~i_read_flag_a;
 
end
 
end
end
end
 
 
// Port A reading
 
always @(posedge i_read_flag_a or negedge i_read_flag_a)
begin
if ((operation_mode == "BIDIR_DUAL_PORT") ||
(operation_mode == "SINGLE_PORT") ||
(operation_mode == "ROM"))
begin
if (~good_to_go_a && (is_lutram == 0))
begin
 
if (((i_ram_block_type == "M-RAM") || (i_ram_block_type == "MEGARAM") ||
((i_ram_block_type == "AUTO") && (cread_during_write_mode_mixed_ports == "DONT_CARE"))) &&
(operation_mode != "ROM") &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
i_q_tmp2_a = {width_a{1'bx}};
else
i_q_tmp2_a = 0;
end
else
begin
if (i_rden_reg_a)
begin
// read from RAM content or flow through for write cycle
if (i_wren_reg_a)
begin
if (i_core_clocken_a)
begin
if (read_during_write_mode_port_a == "NEW_DATA_NO_NBE_READ")
if (is_lutram && clock0)
i_q_tmp2_a = mem_data[i_address_reg_a];
else
i_q_tmp2_a = ((i_data_reg_a & i_byteena_mask_reg_a) |
({width_a{1'bx}} & ~i_byteena_mask_reg_a));
else if (read_during_write_mode_port_a == "NEW_DATA_WITH_NBE_READ")
if (is_lutram && clock0)
i_q_tmp2_a = mem_data[i_address_reg_a];
else
i_q_tmp2_a = (i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
else if (read_during_write_mode_port_a == "OLD_DATA")
i_q_tmp2_a = i_original_data_a;
else
if (!i_lutram_single_port_fast_read && (i_ram_block_type != "AUTO"))
begin
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1)
i_q_tmp2_a = {width_a{1'bx}};
else
i_q_tmp2_a = i_original_data_a;
end
else
if (is_lutram)
i_q_tmp2_a = mem_data[i_address_reg_a];
else
i_q_tmp2_a = i_data_reg_a ^ i_byteena_mask_reg_a_out;
end
else
i_q_tmp2_a = mem_data[i_address_reg_a];
end
else
i_q_tmp2_a = mem_data[i_address_reg_a];
 
if (is_write_positive_edge_reg)
begin
 
if (is_bidir_and_wrcontrol_addb_clk0 || (same_clock_pulse0 && same_clock_pulse1))
begin
// B write, A read
if ((i_wren_reg_b & ~i_wren_reg_a) &
((((is_bidir_and_wrcontrol_addb_clk0 & i_clocken0_b) ||
(is_bidir_and_wrcontrol_addb_clk1 & i_clocken1_b)) && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
(((is_bidir_and_wrcontrol_addb_clk0 & i_core_clocken0_b) ||
(is_bidir_and_wrcontrol_addb_clk1 & i_core_clocken1_b)) && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
begin
add_reg_a_mult_wa = i_address_reg_a * width_a;
add_reg_b_mult_wb = i_address_reg_b * width_b;
add_reg_a_mult_wa_pl_wa = add_reg_a_mult_wa + width_a;
add_reg_b_mult_wb_pl_wb = add_reg_b_mult_wb + width_b;
 
if (
((add_reg_a_mult_wa >=
add_reg_b_mult_wb) &&
(add_reg_a_mult_wa <=
(add_reg_b_mult_wb_pl_wb - 1)))
 
||
 
(((add_reg_a_mult_wa_pl_wa - 1) >=
add_reg_b_mult_wb) &&
((add_reg_a_mult_wa_pl_wa - 1) <=
(add_reg_b_mult_wb_pl_wb - 1)))
)
for (i3 = add_reg_a_mult_wa;
i3 < add_reg_a_mult_wa_pl_wa;
i3 = i3 + 1)
begin
if ((i3 >= add_reg_b_mult_wb) &&
(i3 <= (add_reg_b_mult_wb_pl_wb - 1)))
begin
if (read_during_write_mode_mixed_ports == "OLD_DATA")
begin
i_byteena_count = i3 - add_reg_b_mult_wb;
i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa);
i_q_tmp2_a[i_q_tmp2_a_idx] = i_original_data_b[i_byteena_count];
end
else
begin
i_byteena_count = i3 - add_reg_b_mult_wb;
i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa);
i_q_tmp2_a[i_q_tmp2_a_idx] = i_q_tmp2_a[i_q_tmp2_a_idx] ^ i_byteena_mask_reg_b_out_a[i_byteena_count];
end
end
end
end
end
end
end
if ((is_lutram == 1) && i_address_aclr_a && (~i_address_aclr_family_a) && (operation_mode == "ROM"))
i_q_tmp2_a = mem_data[0];
if ((dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
(is_lutram != 1) &&
(i_outdata_aclr_a) &&
(outdata_reg_a != "CLOCK0") && (outdata_reg_a != "CLOCK1"))
i_q_tmp2_a = {width_a{1'b0}};
end // end good_to_go_a
end
end
 
 
// assigning the correct output values for i_q_tmp_a (non-registered output)
always @(i_q_tmp2_a or i_wren_reg_a or i_data_reg_a or i_address_aclr_a or
i_address_reg_a or i_byteena_mask_reg_a_out or i_numwords_a or i_outdata_aclr_a or i_force_reread_a_signal or i_original_data_a)
begin
if (i_address_reg_a >= i_numwords_a)
begin
if (i_wren_reg_a && i_core_clocken_a)
i_q_tmp_a <= i_q_tmp2_a;
else
i_q_tmp_a <= {width_a{1'bx}};
if (i_rden_reg_a == 1)
begin
$display("Warning : Address pointed at port A is out of bound!");
$display("Time: %0t Instance: %m", $time);
end
end
else
begin
if (i_outdata_aclr_a_prev && ~ i_outdata_aclr_a &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) &&
(is_lutram != 1))
begin
i_outdata_aclr_a_prev = i_outdata_aclr_a;
i_force_reread_a <= 1;
end
else if (~i_address_aclr_a_prev && i_address_aclr_a && (~i_address_aclr_family_a) && s3_address_aclr_a)
begin
if (i_rden_reg_a)
i_q_tmp_a <= {width_a{1'bx}};
i_force_reread_a1 <= 1;
end
else if ((i_force_reread_a1 == 0) && !(i_address_aclr_a_prev && ~i_address_aclr_a && (~i_address_aclr_family_a) && s3_address_aclr_a))
begin
i_q_tmp_a <= i_q_tmp2_a;
end
end
if ((i_outdata_aclr_a) && (s3_address_aclr_a))
begin
i_q_tmp_a <= {width_a{1'b0}};
i_outdata_aclr_a_prev <= i_outdata_aclr_a;
end
i_address_aclr_a_prev <= i_address_aclr_a;
end
 
 
// Port A outdata output registered
always @(posedge i_outdata_clk_a or posedge i_outdata_aclr_a)
begin
if (i_outdata_aclr_a)
i_q_reg_a <= 0;
else if (i_outdata_clken_a)
begin
if ((i_address_aclr_a_flag == 1) &&
(dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) &&
(outdata_reg_a == "CLOCK0") && (is_lutram != 1))
i_q_reg_a <= 'bx;
else
i_q_reg_a <= i_q_tmp_a;
if (i_core_clocken_a)
i_address_aclr_a_flag <= 0;
end
else if (i_core_clocken_a)
i_address_aclr_a_flag <= 0;
end
 
// Latch for address aclr till outclock enabled
always @(posedge i_address_aclr_a or posedge i_outdata_aclr_a)
if (i_outdata_aclr_a)
i_address_aclr_a_flag <= 0;
else
if (i_rden_reg_a && (~i_address_aclr_family_a))
i_address_aclr_a_flag <= 1;
 
// Port A : assigning the correct output values for q_a
assign q_a = (operation_mode == "DUAL_PORT") ?
{width_a{1'b0}} : (((outdata_reg_a == "CLOCK0") ||
(outdata_reg_a == "CLOCK1")) ?
i_q_reg_a : i_q_tmp_a);
 
 
// Port B reading
always @(posedge i_read_flag_b or negedge i_read_flag_b)
begin
if ((operation_mode == "BIDIR_DUAL_PORT") ||
(operation_mode == "DUAL_PORT"))
begin
if (~good_to_go_b && (is_lutram == 0))
begin
if ((check_simultaneous_read_write == 1) &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0) &&
(dev.FEATURE_FAMILY_CYCLONEII(intended_device_family) == 0))
i_q_tmp2_b = {width_b{1'bx}};
else
i_q_tmp2_b = 0;
end
else
begin
if (i_rden_reg_b)
begin
//If width_a is equal to b, no address calculation is needed
if (width_a == width_b)
begin
 
// read from memory or flow through for write cycle
if (i_wren_reg_b && (((is_bidir_and_wrcontrol_addb_clk0 == 1) && i_core_clocken0_b) ||
((is_bidir_and_wrcontrol_addb_clk1 == 1) && i_core_clocken1_b)))
begin
if (read_during_write_mode_port_b == "NEW_DATA_NO_NBE_READ")
temp_wb = ((i_data_reg_b & i_byteena_mask_reg_b) |
({width_b{1'bx}} & ~i_byteena_mask_reg_b));
else if (read_during_write_mode_port_b == "NEW_DATA_WITH_NBE_READ")
temp_wb = (i_data_reg_b & i_byteena_mask_reg_b) | (mem_data[i_address_reg_b] & ~i_byteena_mask_reg_b) ^ i_byteena_mask_reg_b_x;
else if (read_during_write_mode_port_b == "OLD_DATA")
temp_wb = i_original_data_b;
else
temp_wb = {width_b{1'bx}};
end
else if ((i_data_write_time_a == $time) && (operation_mode == "DUAL_PORT") &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
begin
// if A write to the same Ram address B is reading from
if ((i_address_reg_b == i_address_reg_a) && (i_original_address_a == i_address_reg_a))
begin
if (address_reg_b != "CLOCK0")
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
else if (cread_during_write_mode_mixed_ports == "OLD_DATA")
begin
if (mem_data[i_address_reg_b] == ((i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x))
temp_wb = i_original_data_a;
else
temp_wb = mem_data[i_address_reg_b];
end
else if (cread_during_write_mode_mixed_ports == "DONT_CARE")
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
else
temp_wb = mem_data[i_address_reg_b];
end
else
temp_wb = mem_data[i_address_reg_b];
end
else
temp_wb = mem_data[i_address_reg_b];
 
if (is_write_positive_edge_reg)
begin
if ((dual_port_addreg_b_clk0 == 1) ||
(is_bidir_and_wrcontrol_addb_clk0 == 1) || (same_clock_pulse0 && same_clock_pulse1))
begin
// A write, B read
if ((i_wren_reg_a & ~i_wren_reg_b) &&
((i_clocken0 && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
(i_core_clocken_a && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
begin
// if A write to the same Ram address B is reading from
if (i_address_reg_b == i_address_reg_a)
begin
if (i_lutram_dual_port_fast_read)
temp_wb = (i_data_reg_a & i_byteena_mask_reg_a) | (i_q_tmp2_a & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
else
if (cread_during_write_mode_mixed_ports == "OLD_DATA")
if ((mem_data[i_address_reg_b] == ((i_data_reg_a & i_byteena_mask_reg_a) | (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x))
&& (i_data_write_time_a == $time))
temp_wb = i_original_data_a;
else
temp_wb = mem_data[i_address_reg_b];
else
temp_wb = mem_data[i_address_reg_b] ^ i_byteena_mask_reg_a_out_b;
end
end
end
end
end
else
begin
j2 = i_address_reg_b * width_b;
 
for (i5=0; i5<width_b; i5=i5+1)
begin
j2_plus_i5 = j2 + i5;
temp_wa2b = mem_data[j2_plus_i5 / width_a];
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
end
if (i_wren_reg_b && ((is_bidir_and_wrcontrol_addb_clk0 && i_core_clocken0_b) ||
(is_bidir_and_wrcontrol_addb_clk1 && i_core_clocken1_b)))
begin
if (read_during_write_mode_port_b == "NEW_DATA_NO_NBE_READ")
temp_wb = i_data_reg_b ^ i_byteena_mask_reg_b_out;
else if (read_during_write_mode_port_b == "NEW_DATA_WITH_NBE_READ")
temp_wb = (i_data_reg_b & i_byteena_mask_reg_b) | (temp_wb & ~i_byteena_mask_reg_b) ^ i_byteena_mask_reg_b_x;
else if (read_during_write_mode_port_b == "OLD_DATA")
temp_wb = i_original_data_b;
else
temp_wb = {width_b{1'bx}};
end
else if ((i_data_write_time_a == $time) && (operation_mode == "DUAL_PORT") &&
(dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0))
begin
for (i5=0; i5<width_b; i5=i5+1)
begin
j2_plus_i5 = j2 + i5;
j2_plus_i5_div_a = j2_plus_i5 / width_a;
 
// if A write to the same Ram address B is reading from
if ((j2_plus_i5_div_a == i_address_reg_a) && (i_original_address_a == i_address_reg_a))
begin
if (address_reg_b != "CLOCK0")
begin
temp_wa2b = mem_data[j2_plus_i5_div_a];
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
end
else if (cread_during_write_mode_mixed_ports == "OLD_DATA")
temp_wa2b = i_original_data_a;
else if (cread_during_write_mode_mixed_ports == "DONT_CARE")
begin
temp_wa2b = mem_data[j2_plus_i5_div_a];
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
end
else
temp_wa2b = mem_data[j2_plus_i5_div_a];
end
else
temp_wa2b = mem_data[j2_plus_i5_div_a];
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
end
end
 
if (is_write_positive_edge_reg)
begin
if (((address_reg_b == "CLOCK0") & dual_port_addreg_b_clk0) ||
((wrcontrol_wraddress_reg_b == "CLOCK0") & is_bidir_and_wrcontrol_addb_clk0) || (same_clock_pulse0 && same_clock_pulse1))
begin
// A write, B read
if ((i_wren_reg_a & ~i_wren_reg_b) &&
((i_clocken0 && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 0)) ||
(i_core_clocken_a && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1))))
begin
for (i5=0; i5<width_b; i5=i5+1)
begin
j2_plus_i5 = j2 + i5;
j2_plus_i5_div_a = j2_plus_i5 / width_a;
// if A write to the same Ram address B is reading from
if (j2_plus_i5_div_a == i_address_reg_a)
begin
if (i_lutram_single_port_fast_read)
temp_wa2b = (i_data_reg_a & i_byteena_mask_reg_a) | (i_q_tmp2_a & ~i_byteena_mask_reg_a) ^ i_byteena_mask_reg_a_x;
else
begin
if ((cread_during_write_mode_mixed_ports == "OLD_DATA") && (i_data_write_time_a == $time))
temp_wa2b = i_original_data_a;
else
begin
temp_wa2b = mem_data[j2_plus_i5_div_a];
temp_wa2b = temp_wa2b ^ i_byteena_mask_reg_a_out_b;
end
end
temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
end
end
end
end
end
end
//end of width_a != width_b
i_q_tmp2_b = temp_wb;
 
end
if ((is_lutram == 1) && i_address_aclr_b && (~i_address_aclr_family_b) && (operation_mode == "DUAL_PORT"))
begin
for (init_i = 0; init_i < width_b; init_i = init_i + 1)
begin
init_temp = mem_data[init_i / width_a];
i_q_tmp_b[init_i] = init_temp[init_i % width_a];
i_q_tmp2_b[init_i] = init_temp[init_i % width_a];
end
end
else if ((is_lutram == 1) && (operation_mode == "DUAL_PORT"))
begin
j2 = i_address_reg_b * width_b;
 
for (i5=0; i5<width_b; i5=i5+1)
begin
j2_plus_i5 = j2 + i5;
temp_wa2b = mem_data[j2_plus_i5 / width_a];
i_q_tmp2_b[i5] = temp_wa2b[j2_plus_i5 % width_a];
end
end
if ((i_outdata_aclr_b) &&
(dev.FEATURE_FAMILY_CYCLONEIII(intended_device_family) == 1) &&
(is_lutram != 1) &&
(outdata_reg_b != "CLOCK0") && (outdata_reg_b != "CLOCK1"))
i_q_tmp2_b = {width_b{1'b0}};
end
end
end
 
 
// assigning the correct output values for i_q_tmp_b (non-registered output)
always @(i_q_tmp2_b or i_wren_reg_b or i_data_reg_b or i_address_aclr_b or
i_address_reg_b or i_byteena_mask_reg_b_out or i_rden_reg_b or
i_numwords_b or i_outdata_aclr_b or i_force_reread_b_signal)
begin
if (i_address_reg_b >= i_numwords_b)
begin
if (i_wren_reg_b && ((i_core_clocken0_b && (is_bidir_and_wrcontrol_addb_clk0 == 1)) || (i_core_clocken1_b && (is_bidir_and_wrcontrol_addb_clk1 == 1))))
i_q_tmp_b <= i_q_tmp2_b;
else
i_q_tmp_b <= {width_b{1'bx}};
if (i_rden_reg_b == 1)
begin
$display("Warning : Address pointed at port B is out of bound!");
$display("Time: %0t Instance: %m", $time);
end
end
else
if (operation_mode == "BIDIR_DUAL_PORT")
begin
if (i_outdata_aclr_b_prev && ~ i_outdata_aclr_b && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (is_lutram != 1))
begin
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
i_force_reread_b <= 1;
end
else
begin
i_q_tmp_b <= i_q_tmp2_b;
end
end
else if (operation_mode == "DUAL_PORT")
begin
if (i_outdata_aclr_b_prev && ~ i_outdata_aclr_b && (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family) == 1) && (is_lutram != 1))
begin
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
i_force_reread_b <= 1;
end
else if (~i_address_aclr_b_prev && i_address_aclr_b && (~i_address_aclr_family_b) && s3_address_aclr_b)
begin
if (i_rden_reg_b)
i_q_tmp_b <= {width_b{1'bx}};
i_force_reread_b1 <= 1;
end
else if ((i_force_reread_b1 == 0) && !(i_address_aclr_b_prev && ~i_address_aclr_b && (~i_address_aclr_family_b) && s3_address_aclr_b))
begin
if (i_rden_reg_b || (is_lutram == 1))
i_q_tmp_b <= i_q_tmp2_b;
end
end
if ((i_outdata_aclr_b) && (s3_address_aclr_b))
begin
i_q_tmp_b <= {width_b{1'b0}};
i_outdata_aclr_b_prev <= i_outdata_aclr_b;
end
i_address_aclr_b_prev <= i_address_aclr_b;
end
 
// output latch for lutram (only used when read_during_write_mode_mixed_ports == "OLD_DATA")
always @(negedge i_outdata_clk_b)
begin
if (i_core_clocken_a)
i_q_output_latch <= i_q_tmp2_b;
end
 
// Port B outdata output registered
always @(posedge i_outdata_clk_b or posedge i_outdata_aclr_b)
begin
if (i_outdata_aclr_b)
i_q_reg_b <= 0;
else if (i_outdata_clken_b)
begin
if ((is_lutram == 1) && (cread_during_write_mode_mixed_ports == "OLD_DATA") && (outdata_reg_b == "CLOCK0"))
i_q_reg_b <= i_q_output_latch;
else
begin
if ((i_address_aclr_b_flag == 1) && (dev.FEATURE_FAMILY_STRATIXIII(intended_device_family)) &&
(is_lutram != 1))
i_q_reg_b <= 'bx;
else
i_q_reg_b <= i_q_tmp_b;
end
end
end
 
// Latch for address aclr till outclock enabled
always @(posedge i_address_aclr_b or posedge i_outdata_aclr_b)
if (i_outdata_aclr_b)
i_address_aclr_b_flag <= 0;
else
begin
if (i_rden_reg_b)
i_address_aclr_b_flag <= 1;
end
 
// Port B : assigning the correct output values for q_b
assign q_b = ((operation_mode == "SINGLE_PORT") ||
(operation_mode == "ROM")) ?
{width_b{1'b0}} : (((outdata_reg_b == "CLOCK0") ||
(outdata_reg_b == "CLOCK1")) ?
i_q_reg_b : i_q_tmp_b);
 
 
// ECC status
assign eccstatus = {3'b000};
 
endmodule // ALTSYNCRAM
 
// END OF MODULE
 
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : ALTERA_DEVICE_FAMILIES
//
// Description : Common Altera device families comparison
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
 
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
 
// MODULE DECLARATION
module ALTERA_DEVICE_FAMILIES;
 
function IS_FAMILY_ACEX1K;
input[8*20:1] device;
reg is_acex1k;
begin
if ((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
is_acex1k = 1;
else
is_acex1k = 0;
 
IS_FAMILY_ACEX1K = is_acex1k;
end
endfunction //IS_FAMILY_ACEX1K
 
function IS_FAMILY_APEX20K;
input[8*20:1] device;
reg is_apex20k;
begin
if ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
is_apex20k = 1;
else
is_apex20k = 0;
 
IS_FAMILY_APEX20K = is_apex20k;
end
endfunction //IS_FAMILY_APEX20K
 
function IS_FAMILY_APEX20KC;
input[8*20:1] device;
reg is_apex20kc;
begin
if ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
is_apex20kc = 1;
else
is_apex20kc = 0;
 
IS_FAMILY_APEX20KC = is_apex20kc;
end
endfunction //IS_FAMILY_APEX20KC
 
function IS_FAMILY_APEX20KE;
input[8*20:1] device;
reg is_apex20ke;
begin
if ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
is_apex20ke = 1;
else
is_apex20ke = 0;
 
IS_FAMILY_APEX20KE = is_apex20ke;
end
endfunction //IS_FAMILY_APEX20KE
 
function IS_FAMILY_APEXII;
input[8*20:1] device;
reg is_apexii;
begin
if ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
is_apexii = 1;
else
is_apexii = 0;
 
IS_FAMILY_APEXII = is_apexii;
end
endfunction //IS_FAMILY_APEXII
 
function IS_FAMILY_EXCALIBUR_ARM;
input[8*20:1] device;
reg is_excalibur_arm;
begin
if ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
is_excalibur_arm = 1;
else
is_excalibur_arm = 0;
 
IS_FAMILY_EXCALIBUR_ARM = is_excalibur_arm;
end
endfunction //IS_FAMILY_EXCALIBUR_ARM
 
function IS_FAMILY_FLEX10KE;
input[8*20:1] device;
reg is_flex10ke;
begin
if ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
is_flex10ke = 1;
else
is_flex10ke = 0;
 
IS_FAMILY_FLEX10KE = is_flex10ke;
end
endfunction //IS_FAMILY_FLEX10KE
 
function IS_FAMILY_STRATIX;
input[8*20:1] device;
reg is_stratix;
begin
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
is_stratix = 1;
else
is_stratix = 0;
 
IS_FAMILY_STRATIX = is_stratix;
end
endfunction //IS_FAMILY_STRATIX
 
function IS_FAMILY_STRATIXGX;
input[8*20:1] device;
reg is_stratixgx;
begin
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
is_stratixgx = 1;
else
is_stratixgx = 0;
 
IS_FAMILY_STRATIXGX = is_stratixgx;
end
endfunction //IS_FAMILY_STRATIXGX
 
function IS_FAMILY_CYCLONE;
input[8*20:1] device;
reg is_cyclone;
begin
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
is_cyclone = 1;
else
is_cyclone = 0;
 
IS_FAMILY_CYCLONE = is_cyclone;
end
endfunction //IS_FAMILY_CYCLONE
 
function IS_FAMILY_MAXII;
input[8*20:1] device;
reg is_maxii;
begin
if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
is_maxii = 1;
else
is_maxii = 0;
 
IS_FAMILY_MAXII = is_maxii;
end
endfunction //IS_FAMILY_MAXII
 
function IS_FAMILY_HARDCOPYSTRATIX;
input[8*20:1] device;
reg is_hardcopystratix;
begin
if ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
is_hardcopystratix = 1;
else
is_hardcopystratix = 0;
 
IS_FAMILY_HARDCOPYSTRATIX = is_hardcopystratix;
end
endfunction //IS_FAMILY_HARDCOPYSTRATIX
 
function IS_FAMILY_STRATIXII;
input[8*20:1] device;
reg is_stratixii;
begin
if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
is_stratixii = 1;
else
is_stratixii = 0;
 
IS_FAMILY_STRATIXII = is_stratixii;
end
endfunction //IS_FAMILY_STRATIXII
 
function IS_FAMILY_STRATIXIIGX;
input[8*20:1] device;
reg is_stratixiigx;
begin
if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
is_stratixiigx = 1;
else
is_stratixiigx = 0;
 
IS_FAMILY_STRATIXIIGX = is_stratixiigx;
end
endfunction //IS_FAMILY_STRATIXIIGX
 
function IS_FAMILY_ARRIAGX;
input[8*20:1] device;
reg is_arriagx;
begin
if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
is_arriagx = 1;
else
is_arriagx = 0;
 
IS_FAMILY_ARRIAGX = is_arriagx;
end
endfunction //IS_FAMILY_ARRIAGX
 
function IS_FAMILY_CYCLONEII;
input[8*20:1] device;
reg is_cycloneii;
begin
if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
is_cycloneii = 1;
else
is_cycloneii = 0;
 
IS_FAMILY_CYCLONEII = is_cycloneii;
end
endfunction //IS_FAMILY_CYCLONEII
 
function IS_FAMILY_HARDCOPYII;
input[8*20:1] device;
reg is_hardcopyii;
begin
if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
is_hardcopyii = 1;
else
is_hardcopyii = 0;
 
IS_FAMILY_HARDCOPYII = is_hardcopyii;
end
endfunction //IS_FAMILY_HARDCOPYII
 
function IS_FAMILY_STRATIXIII;
input[8*20:1] device;
reg is_stratixiii;
begin
if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
is_stratixiii = 1;
else
is_stratixiii = 0;
 
IS_FAMILY_STRATIXIII = is_stratixiii;
end
endfunction //IS_FAMILY_STRATIXIII
 
function IS_FAMILY_CYCLONEIII;
input[8*20:1] device;
reg is_cycloneiii;
begin
if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
is_cycloneiii = 1;
else
is_cycloneiii = 0;
 
IS_FAMILY_CYCLONEIII = is_cycloneiii;
end
endfunction //IS_FAMILY_CYCLONEIII
 
function IS_FAMILY_STRATIXIV;
input[8*20:1] device;
reg is_stratixiv;
begin
if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
is_stratixiv = 1;
else
is_stratixiv = 0;
 
IS_FAMILY_STRATIXIV = is_stratixiv;
end
endfunction //IS_FAMILY_STRATIXIV
 
function IS_FAMILY_ARRIAIIGXGX;
input[8*20:1] device;
reg is_arriaiigx;
begin
if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
is_arriaiigx = 1;
else
is_arriaiigx = 0;
 
IS_FAMILY_ARRIAIIGXGX = is_arriaiigx;
end
endfunction //IS_FAMILY_ARRIAIIGXGX
 
function IS_FAMILY_HARDCOPYIII;
input[8*20:1] device;
reg is_hardcopyiii;
begin
if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
is_hardcopyiii = 1;
else
is_hardcopyiii = 0;
 
IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
end
endfunction //IS_FAMILY_HARDCOPYIII
 
function IS_FAMILY_HARDCOPYIV;
input[8*20:1] device;
reg is_hardcopyiv;
begin
if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)"))
is_hardcopyiv = 1;
else
is_hardcopyiv = 0;
 
IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
end
endfunction //IS_FAMILY_HARDCOPYIV
 
function IS_FAMILY_CYCLONEIIILS;
input[8*20:1] device;
reg is_cycloneiiils;
begin
if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
is_cycloneiiils = 1;
else
is_cycloneiiils = 0;
 
IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
end
endfunction //IS_FAMILY_CYCLONEIIILS
 
function FEATURE_FAMILY_FLEX10KE;
input[8*20:1] device;
reg var_family_flex10ke;
begin
if (IS_FAMILY_FLEX10KE(device) || IS_FAMILY_ACEX1K(device) )
var_family_flex10ke = 1;
else
var_family_flex10ke = 0;
 
FEATURE_FAMILY_FLEX10KE = var_family_flex10ke;
end
endfunction //FEATURE_FAMILY_FLEX10KE
 
function FEATURE_FAMILY_APEX20K;
input[8*20:1] device;
reg var_family_apex20k;
begin
if (IS_FAMILY_APEX20K(device) )
var_family_apex20k = 1;
else
var_family_apex20k = 0;
 
FEATURE_FAMILY_APEX20K = var_family_apex20k;
end
endfunction //FEATURE_FAMILY_APEX20K
 
function FEATURE_FAMILY_APEX20KE;
input[8*20:1] device;
reg var_family_apex20ke;
begin
if (IS_FAMILY_APEX20KE(device) || IS_FAMILY_EXCALIBUR_ARM(device) || IS_FAMILY_APEX20KC(device) )
var_family_apex20ke = 1;
else
var_family_apex20ke = 0;
 
FEATURE_FAMILY_APEX20KE = var_family_apex20ke;
end
endfunction //FEATURE_FAMILY_APEX20KE
 
function FEATURE_FAMILY_APEXII;
input[8*20:1] device;
reg var_family_apexii;
begin
if (IS_FAMILY_APEXII(device) || IS_FAMILY_APEXII(device) )
var_family_apexii = 1;
else
var_family_apexii = 0;
 
FEATURE_FAMILY_APEXII = var_family_apexii;
end
endfunction //FEATURE_FAMILY_APEXII
 
function FEATURE_FAMILY_STRATIXGX;
input[8*20:1] device;
reg var_family_stratixgx;
begin
if (IS_FAMILY_STRATIXGX(device) )
var_family_stratixgx = 1;
else
var_family_stratixgx = 0;
 
FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
end
endfunction //FEATURE_FAMILY_STRATIXGX
 
function FEATURE_FAMILY_CYCLONE;
input[8*20:1] device;
reg var_family_cyclone;
begin
if (IS_FAMILY_CYCLONE(device) )
var_family_cyclone = 1;
else
var_family_cyclone = 0;
 
FEATURE_FAMILY_CYCLONE = var_family_cyclone;
end
endfunction //FEATURE_FAMILY_CYCLONE
 
function FEATURE_FAMILY_STRATIXIIGX;
input[8*20:1] device;
reg var_family_stratixiigx;
begin
if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
var_family_stratixiigx = 1;
else
var_family_stratixiigx = 0;
 
FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
end
endfunction //FEATURE_FAMILY_STRATIXIIGX
 
function FEATURE_FAMILY_STRATIXIII;
input[8*20:1] device;
reg var_family_stratixiii;
begin
if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
var_family_stratixiii = 1;
else
var_family_stratixiii = 0;
 
FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
end
endfunction //FEATURE_FAMILY_STRATIXIII
 
function FEATURE_FAMILY_STRATIXII;
input[8*20:1] device;
reg var_family_stratixii;
begin
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
var_family_stratixii = 1;
else
var_family_stratixii = 0;
 
FEATURE_FAMILY_STRATIXII = var_family_stratixii;
end
endfunction //FEATURE_FAMILY_STRATIXII
 
function FEATURE_FAMILY_CYCLONEIII;
input[8*20:1] device;
reg var_family_cycloneiii;
begin
if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) )
var_family_cycloneiii = 1;
else
var_family_cycloneiii = 0;
 
FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
end
endfunction //FEATURE_FAMILY_CYCLONEIII
 
function FEATURE_FAMILY_STRATIX_HC;
input[8*20:1] device;
reg var_family_stratix_hc;
begin
if (IS_FAMILY_HARDCOPYSTRATIX(device) )
var_family_stratix_hc = 1;
else
var_family_stratix_hc = 0;
 
FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
end
endfunction //FEATURE_FAMILY_STRATIX_HC
 
function FEATURE_FAMILY_HARDCOPYII;
input[8*20:1] device;
reg var_family_hardcopyii;
begin
if (IS_FAMILY_HARDCOPYII(device) )
var_family_hardcopyii = 1;
else
var_family_hardcopyii = 0;
 
FEATURE_FAMILY_HARDCOPYII = var_family_hardcopyii;
end
endfunction //FEATURE_FAMILY_HARDCOPYII
 
function FEATURE_FAMILY_STRATIX;
input[8*20:1] device;
reg var_family_stratix;
begin
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
var_family_stratix = 1;
else
var_family_stratix = 0;
 
FEATURE_FAMILY_STRATIX = var_family_stratix;
end
endfunction //FEATURE_FAMILY_STRATIX
 
function FEATURE_FAMILY_MAXII;
input[8*20:1] device;
reg var_family_maxii;
begin
if (IS_FAMILY_MAXII(device) )
var_family_maxii = 1;
else
var_family_maxii = 0;
 
FEATURE_FAMILY_MAXII = var_family_maxii;
end
endfunction //FEATURE_FAMILY_MAXII
 
function FEATURE_FAMILY_CYCLONEII;
input[8*20:1] device;
reg var_family_cycloneii;
begin
if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
var_family_cycloneii = 1;
else
var_family_cycloneii = 0;
 
FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
end
endfunction //FEATURE_FAMILY_CYCLONEII
 
function FEATURE_FAMILY_STRATIXIV;
input[8*20:1] device;
reg var_family_stratixiv;
begin
if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGXGX(device) || IS_FAMILY_HARDCOPYIV(device) )
var_family_stratixiv = 1;
else
var_family_stratixiv = 0;
 
FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
end
endfunction //FEATURE_FAMILY_STRATIXIV
 
function FEATURE_FAMILY_ARRIAIIGX;
input[8*20:1] device;
reg var_family_arriaiigx;
begin
if (IS_FAMILY_ARRIAIIGXGX(device) )
var_family_arriaiigx = 1;
else
var_family_arriaiigx = 0;
 
FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
end
endfunction //FEATURE_FAMILY_ARRIAIIGX
 
function FEATURE_FAMILY_BASE_STRATIXII;
input[8*20:1] device;
reg var_family_base_stratixii;
begin
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
var_family_base_stratixii = 1;
else
var_family_base_stratixii = 0;
 
FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
end
endfunction //FEATURE_FAMILY_BASE_STRATIXII
 
function FEATURE_FAMILY_BASE_STRATIX;
input[8*20:1] device;
reg var_family_base_stratix;
begin
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_HARDCOPYSTRATIX(device) )
var_family_base_stratix = 1;
else
var_family_base_stratix = 0;
 
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
end
endfunction //FEATURE_FAMILY_BASE_STRATIX
 
function FEATURE_FAMILY_BASE_CYCLONEII;
input[8*20:1] device;
reg var_family_base_cycloneii;
begin
if (IS_FAMILY_CYCLONEII(device) )
var_family_base_cycloneii = 1;
else
var_family_base_cycloneii = 0;
 
FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
end
endfunction //FEATURE_FAMILY_BASE_CYCLONEII
 
function FEATURE_FAMILY_BASE_CYCLONE;
input[8*20:1] device;
reg var_family_base_cyclone;
begin
if (IS_FAMILY_CYCLONE(device) )
var_family_base_cyclone = 1;
else
var_family_base_cyclone = 0;
 
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
end
endfunction //FEATURE_FAMILY_BASE_CYCLONE
 
function FEATURE_FAMILY_HAS_MEGARAM;
input[8*20:1] device;
reg var_family_has_megaram;
begin
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_ARRIAIIGX(device) )
var_family_has_megaram = 1;
else
var_family_has_megaram = 0;
 
FEATURE_FAMILY_HAS_MEGARAM = var_family_has_megaram;
end
endfunction //FEATURE_FAMILY_HAS_MEGARAM
 
function FEATURE_FAMILY_HAS_M512;
input[8*20:1] device;
reg var_family_has_m512;
begin
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_STRATIXII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
var_family_has_m512 = 1;
else
var_family_has_m512 = 0;
 
FEATURE_FAMILY_HAS_M512 = var_family_has_m512;
end
endfunction //FEATURE_FAMILY_HAS_M512
 
function FEATURE_FAMILY_HAS_LUTRAM;
input[8*20:1] device;
reg var_family_has_lutram;
begin
if (FEATURE_FAMILY_STRATIXIII(device) )
var_family_has_lutram = 1;
else
var_family_has_lutram = 0;
 
FEATURE_FAMILY_HAS_LUTRAM = var_family_has_lutram;
end
endfunction //FEATURE_FAMILY_HAS_LUTRAM
 
function FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM;
input[8*20:1] device;
reg var_family_has_stratixi_style_ram;
begin
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) )
var_family_has_stratixi_style_ram = 1;
else
var_family_has_stratixi_style_ram = 0;
 
FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM = var_family_has_stratixi_style_ram;
end
endfunction //FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM
 
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
input[8*20:1] device;
reg var_family_has_stratixii_style_ram;
begin
if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
var_family_has_stratixii_style_ram = 1;
else
var_family_has_stratixii_style_ram = 0;
 
FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
end
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
 
function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
input[8*20:1] device;
reg var_family_has_stratixiii_style_ram;
begin
if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
var_family_has_stratixiii_style_ram = 1;
else
var_family_has_stratixiii_style_ram = 0;
 
FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
end
endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
 
function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
input[8*20:1] device;
reg var_family_has_stratix_style_pll;
begin
if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
var_family_has_stratix_style_pll = 1;
else
var_family_has_stratix_style_pll = 0;
 
FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
end
endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
 
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
input[8*20:1] device;
reg var_family_has_stratixii_style_pll;
begin
if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
var_family_has_stratixii_style_pll = 1;
else
var_family_has_stratixii_style_pll = 0;
 
FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
end
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
 
function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
input[8*20:1] device;
reg var_family_has_inverted_output_ddio;
begin
if (FEATURE_FAMILY_CYCLONEII(device) )
var_family_has_inverted_output_ddio = 1;
else
var_family_has_inverted_output_ddio = 0;
 
FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
end
endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
 
function IS_VALID_FAMILY;
input[8*20:1] device;
reg is_valid;
begin
if (((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
|| ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
|| ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
|| ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
|| ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
|| ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
|| ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
|| ((device == "FLEX10K") || (device == "flex10k") || (device == "FLEX 10K") || (device == "flex 10k"))
|| ((device == "FLEX10KA") || (device == "flex10ka") || (device == "FLEX 10KA") || (device == "flex 10ka"))
|| ((device == "FLEX6000") || (device == "flex6000") || (device == "FLEX 6000") || (device == "flex 6000") || (device == "FLEX6K") || (device == "flex6k"))
|| ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|| ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
|| ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali"))
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|| ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)"))
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")))
is_valid = 1;
else
is_valid = 0;
 
IS_VALID_FAMILY = is_valid;
end
endfunction // IS_VALID_FAMILY
 
 
endmodule // ALTERA_DEVICE_FAMILIES
 
 
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
 
`define TRUE 1
`define FALSE 0
`define NULL 0
`define EOF -1
`define MAX_BUFFER_SZ 2048
`define MAX_NAME_SZ 256
`define MAX_WIDTH 256
`define COLON ":"
`define DOT "."
`define NEWLINE "\n"
`define CARRIAGE_RETURN 8'h0D
`define SPACE " "
`define TAB "\t"
`define OPEN_BRACKET "["
`define CLOSE_BRACKET "]"
`define OFFSET 9
`define H10 8'h10
`define H10000 20'h10000
`define AWORD 8
`define MASK15 32'h000000FF
`define EXT_STR "ver"
`define PERCENT "%"
`define MINUS "-"
`define SEMICOLON ";"
`define EQUAL "="
 
// MODULE DECLARATION
module ALTERA_MF_MEMORY_INITIALIZATION;
 
/****************************************************************/
/* convert uppercase character values to lowercase. */
/****************************************************************/
function [8:1] tolower;
input [8:1] given_character;
reg [8:1] conv_char;
 
begin
if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
tolower = conv_char;
end
else
tolower = given_character;
end
endfunction
/****************************************************************/
/* Read in Altera-mif format data to verilog format data. */
/****************************************************************/
task convert_mif2ver;
input[`MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`MAX_NAME_SZ*8 : 1] out_file;
reg [`MAX_NAME_SZ*8 : 1] in_file;
reg [`MAX_NAME_SZ*8 : 1] out_file;
reg [`MAX_NAME_SZ*8 : 1] buffer;
reg [`MAX_WIDTH : 0] memory_data1, memory_data2;
reg [8 : 1] c;
reg [3 : 0] hex, tmp_char;
reg [24 : 1] address_radix, data_radix;
reg get_width;
reg get_depth;
reg get_data_radix;
reg get_address_radix;
reg width_found;
reg depth_found;
reg data_radix_found;
reg address_radix_found;
reg get_address_data_pairs;
reg get_address;
reg get_data;
reg display_address;
reg invalid_address;
reg get_start_address;
reg get_end_address;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
 
integer width;
integer memory_width, memory_depth;
integer value;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ;
integer start_address, end_address;
integer line_no;
integer character_count;
integer comment_with_percent_found;
integer comment_with_double_minus_found;
 
begin
`ifdef NO_PLI
`else
`ifdef USE_RIF
`else
done = `FALSE;
error_status = `FALSE;
first_rec = `FALSE;
last_rec = `FALSE;
comment_with_percent_found = `FALSE;
comment_with_double_minus_found = `FALSE;
 
off_addr= 0;
nn= 0;
address = 0;
start_address = 0;
end_address = 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
value = 0;
buffer = "";
character_count = 0;
memory_width = 0;
memory_depth = 0;
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
memory_data2 = {(`MAX_WIDTH+1) {1'b0}};
address_radix = "hex";
data_radix = "hex";
get_width = `FALSE;
get_depth = `FALSE;
get_data_radix = `FALSE;
get_address_radix = `FALSE;
width_found = `FALSE;
depth_found = `FALSE;
data_radix_found = `FALSE;
address_radix_found = `FALSE;
get_address_data_pairs = `FALSE;
display_address = `FALSE;
invalid_address = `FALSE;
get_start_address = `FALSE;
get_end_address = `FALSE;
 
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
 
if (ifp == `NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
done = `TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF"))
out_file[3*8 : 1] = `EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file);
done = `TRUE;
end
 
if (!done)
begin
ofp = $fopen(out_file, "w");
 
if (ofp == `NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
done = `TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
 
if (r == `EOF)
begin
// to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising
if(!first_rec)
begin
error_status = `TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
end
else if (!get_address_data_pairs)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
end
else if(!last_rec)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no);
end
done = `TRUE;
end
else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
begin
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
begin
get_address_data_pairs = `TRUE;
get_address = `TRUE;
buffer = "";
end
else if (buffer == "content")
begin
// continue to next character
end
else
if (buffer != "")
begin
// found invalid syntax in the particular line.
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
disable READER;
end
line_no = line_no +1;
end
else if ((r == `SPACE) || (r == `TAB))
begin
// continue to next character;
end
else if (r == `PERCENT)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
 
while ((r != `PERCENT) && (r != `NEWLINE) && (r != `CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
 
if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
begin
line_no = line_no +1;
 
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
begin
get_address_data_pairs = `TRUE;
get_address = `TRUE;
buffer = "";
end
end
end
else if (r == `MINUS)
begin
r = $fgetc(ifp);
if (r == `MINUS)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `NEWLINE) && (r != `CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
begin
line_no = line_no +1;
 
if ((buffer == "contentbegin") && (get_address_data_pairs == `FALSE))
begin
get_address_data_pairs = `TRUE;
get_address = `TRUE;
buffer = "";
end
end
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
else if (r == `EQUAL)
begin
if (buffer == "width")
begin
if (width_found == `FALSE)
begin
get_width = `TRUE;
buffer = "";
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no);
end
end
else if (buffer == "depth")
begin
get_depth = `TRUE;
buffer = "";
end
else if (buffer == "data_radix")
begin
get_data_radix = `TRUE;
buffer = "";
end
else if (buffer == "address_radix")
begin
get_address_radix = `TRUE;
buffer = "";
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer);
end
end
else if (r == `COLON)
begin
if (!get_address_data_pairs)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
end
else if (invalid_address == `TRUE)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
end
begin
get_address = `FALSE;
get_data = `TRUE;
display_address = `TRUE;
end
end
else if (r == `DOT)
begin
r = $fgetc(ifp);
if (r == `DOT)
begin
if (get_start_address == `TRUE)
begin
start_address = address;
address = 0;
get_start_address = `FALSE;
get_end_address = `TRUE;
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
else if (r == `OPEN_BRACKET)
begin
get_start_address = `TRUE;
end
else if (r == `CLOSE_BRACKET)
begin
if (get_end_address == `TRUE)
begin
end_address = address;
address = 0;
get_end_address = `FALSE;
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
else if (r == `SEMICOLON)
begin
if (get_width == `TRUE)
begin
width_found = `TRUE;
memory_width = value;
value = 0;
get_width = `FALSE;
end
else if (get_depth == `TRUE)
begin
depth_found = `TRUE;
memory_depth = value;
value = 0;
get_depth = `FALSE;
end
else if (get_data_radix == `TRUE)
begin
data_radix_found = `TRUE;
get_data_radix = `FALSE;
 
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
data_radix = buffer[24 : 1];
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer);
end
buffer = "";
end
else if (get_address_radix == `TRUE)
begin
address_radix_found = `TRUE;
get_address_radix = `FALSE;
 
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
address_radix = buffer[24 : 1];
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer);
end
buffer = "";
end
else if (buffer == "end")
begin
if (get_address_data_pairs == `TRUE)
begin
last_rec = `TRUE;
buffer = "";
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
end
end
else if (get_data == `TRUE)
begin
get_address = `TRUE;
get_data = `FALSE;
buffer = "";
character_count = 0;
if (start_address != end_address)
begin
for (address = start_address; address <= end_address; address = address+1)
begin
$fdisplay(ofp,"@%0h", address);
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
end
start_address = 0;
end_address = 0;
address = 0;
hex = 0;
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
end
else
begin
if (display_address == `TRUE)
begin
$fdisplay(ofp,"@%0h", address);
display_address = `FALSE;
end
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
address = 0;
hex = 0;
memory_data1 = {(`MAX_WIDTH+1) {1'b0}};
end
end
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no);
end
end
else if ((get_width == `TRUE) || (get_depth == `TRUE))
begin
if ((r >= "0") && (r <= "9"))
value = (value * 10) + (r - 'h30);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no);
end
end
else if (get_address == `TRUE)
begin
if (address_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
invalid_address = `TRUE;
end
address = (address * 16) + value;
end
else if ((address_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
invalid_address = `TRUE;
end
address = (address * 2) + value;
end
else if (address_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
invalid_address = `TRUE;
end
address = (address * 8) + value;
end
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
 
{tmp_char,buffer} = {buffer, c};
end
else if (get_data == `TRUE)
begin
character_count = character_count +1;
 
if (data_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
done = `TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 16) + value;
end
else if ((data_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
done = `TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
done = `TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
done = `TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 2) + value;
end
else if (data_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
done = `TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 8) + value;
end
end
else
begin
first_rec = `TRUE;
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
 
{tmp_char,buffer} = {buffer, c};
end
end
$fclose(ifp);
$fclose(ofp);
end
`endif
`endif
end
endtask // convert_mif2ver
 
/****************************************************************/
/* Read in Intel-hex format data to verilog format data. */
/* Intel-hex format :nnaaaaattddddcc */
/****************************************************************/
task convert_hex2ver;
input[`MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`MAX_NAME_SZ*8 : 1] out_file;
reg [`MAX_NAME_SZ*8 : 1] in_file;
reg [`MAX_NAME_SZ*8 : 1] out_file;
reg [8:1] c;
reg [3:0] hex, tmp_char;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
reg first_normal_record;
reg is_word_address_format;
 
integer width;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, aaaa, aaaa_pre, tt, cc, aah, aal, dd, sum ;
integer line_no;
integer divide_factor;
 
begin
`ifdef NO_PLI
`else
`ifdef USE_RIF
`else
done = `FALSE;
error_status = `FALSE;
first_rec = `FALSE;
last_rec = `FALSE;
first_normal_record = `TRUE;
is_word_address_format = `FALSE;
off_addr= 0;
nn= 0;
aaaa= 0;
aaaa_pre = 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
divide_factor = 1;
 
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
done = `TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
out_file[3*8 : 1] = `EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
done = `TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
done = `TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `EOF)
begin
if(!first_rec)
begin
error_status = `TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
end
else if(!last_rec)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
end
end
else if (r == `COLON)
begin
first_rec = `TRUE;
nn= 0;
aaaa_pre = aaaa;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
// get record length bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
nn = (nn * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
nn = (nn * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
nn = (nn * 16) + 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
// get address bytes
for (i = 0; i < 4; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
aaaa = (aaaa * 16) + hex;
if (i < 2)
aal = (aal * 16) + hex;
else
aah = (aah * 16) + hex;
end
// get record type bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
tt = (tt * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
tt = (tt * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
tt = (tt * 16) + 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
if((tt == 2) && (nn != 2) )
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
end
else
begin
// get the sum of all the bytes for record length, address and record types
sum = nn + aah + aal + tt ;
// check the record type
case(tt)
// normal_record
8'h00 :
begin
first_rec = `TRUE;
i = 0;
k = width / `AWORD;
if ((width % `AWORD) != 0)
k = k + 1;
if ((first_normal_record == `FALSE) &&(aaaa != k))
is_word_address_format = `TRUE;
first_normal_record = `FALSE;
 
if ((aaaa == k) && (is_word_address_format == `FALSE))
divide_factor = k;
 
// k = no. of bytes per entry.
while (i < nn)
begin
$fdisplay(ofp,"@%0h", (aaaa + off_addr)/divide_factor);
 
for (j = 1; j <= k; j = j +1)
begin
if ((k - j +1) > nn)
begin
for(m = 1; m <= 2; m= m+1)
begin
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "0");
end
end
else
begin
// get the data bytes
for(m = 1; m <= 2; m= m+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "%h", hex);
dd = (dd * 16) + hex;
if(m % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
end
end
$fwrite(ofp, "\n");
i = i + k;
aaaa = aaaa + 1;
end // end of while (i < nn)
end
// last record
8'h01:
begin
last_rec = `TRUE;
done = `TRUE;
end
// address base record
8'h02:
begin
off_addr= 0;
 
// get the extended segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
off_addr = (off_addr * `H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `H10;
end
// address base record
8'h03:
// get the start segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
 
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
// address base record
8'h04:
begin
off_addr= 0;
 
// get the extended linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
 
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
off_addr = (off_addr * `H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `H10000;
end
// address base record
8'h05:
// get the start linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
 
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
default:
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
end
endcase
// get the checksum bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
cc = (cc * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
cc = 10 + (cc * 16) + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
cc = 10 + (cc * 16) + (r - 'h61);
else
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
disable READER;
end
end
// Perform check sum.
if(((~sum+1)& `MASK15) != cc)
begin
error_status = `TRUE;
$display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
end
end
end
else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
begin
line_no = line_no +1;
end
else if (r == `SPACE)
begin
// continue to next character;
end
else
begin
error_status = `TRUE;
$display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
done = `TRUE;
end
end
$fclose(ifp);
$fclose(ofp);
end
`endif
`endif
end
endtask // convert_hex2ver
 
task convert_to_ver_file;
input[`MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`MAX_NAME_SZ*8 : 1] out_file;
reg [`MAX_NAME_SZ*8 : 1] in_file;
reg [`MAX_NAME_SZ*8 : 1] out_file;
integer width;
begin
if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") ||
(in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
convert_hex2ver(in_file, width, out_file);
else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF"))
convert_mif2ver(in_file, width, out_file);
else
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file);
end
endtask // convert_to_ver_file
 
endmodule // ALTERA_MF_MEMORY_INITIALIZATION
openmsp430/trunk/fpga/altera_de1_board/bench/verilog/altsyncram.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v (revision 29) @@ -0,0 +1,443 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: msp_debug.v +// +// *Module Description: +// MSP430 core debug utility signals +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module msp_debug ( + +// OUTPUTs + e_state, // Execution state + i_state, // Instruction fetch state + inst_cycle, // Cycle number within current instruction + inst_full, // Currently executed instruction (full version) + inst_number, // Instruction number since last system reset + inst_pc, // Instruction Program counter + inst_short, // Currently executed instruction (short version) + +// INPUTs + mclk, // Main system clock + puc // Main system reset +); + +// OUTPUTs +//============ +output [8*32-1:0] e_state; // Execution state +output [8*32-1:0] i_state; // Instruction fetch state +output [31:0] inst_cycle; // Cycle number within current instruction +output [8*32-1:0] inst_full; // Currently executed instruction (full version) +output [31:0] inst_number; // Instruction number since last system reset +output [15:0] inst_pc; // Instruction Program counter +output [8*32-1:0] inst_short; // Currently executed instruction (short version) + +// INPUTs +//============ +input mclk; // Main system clock +input puc; // Main system reset + + +//============================================================================= +// 1) ASCII FORMATING FUNCTIONS +//============================================================================= + +// This function simply concatenates two strings together, ignorning the NULL +// at the end of string2. +// The specified number of space will be inserted between string1 and string2 +function [64*8-1:0] myFormat; + + input [32*8-1:0] string1; + input [32*8-1:0] string2; + input [3:0] space; + + integer i,j; + begin + myFormat = 0; + j = 0; + for ( i=0; i < 32; i=i+1) // Copy string2 + begin + myFormat[8*i +: 8] = string2[8*i +: 8]; + if ((string2[8*i +: 8] == 0) && (j == 0)) j=i; + end + + for ( i=0; i < space; i=i+1) // Add spaces + myFormat[8*(j+i) +: 8] = " "; + j=j+space; + + for ( i=0; i < 32; i=i+1) // Copy string1 + myFormat[8*(j+i) +: 8] = string1[8*i +: 8]; + + end +endfunction + + +//============================================================================= +// 2) CONNECTIONS TO MSP430 CORE INTERNALS +//============================================================================= + +wire [2:0] i_state_bin = dut.openMSP430_0.frontend_0.i_state; +wire [3:0] e_state_bin = dut.openMSP430_0.frontend_0.e_state; + +wire decode = dut.openMSP430_0.frontend_0.decode; +wire [15:0] ir = dut.openMSP430_0.frontend_0.ir; +wire irq_detect = dut.openMSP430_0.frontend_0.irq_detect; +wire [3:0] irq_num = dut.openMSP430_0.frontend_0.irq_num; +wire [15:0] pc = dut.openMSP430_0.frontend_0.pc; + + +//============================================================================= +// 3) GENERATE DEBUG SIGNALS +//============================================================================= + +// Instruction fetch state +//========================= +reg [8*32-1:0] i_state; + +always @(i_state_bin) + case(i_state_bin) + 3'h0 : i_state = "IRQ_FETCH"; + 3'h1 : i_state = "IRQ_DONE"; + 3'h2 : i_state = "DEC"; + 3'h3 : i_state = "EXT1"; + 3'h4 : i_state = "EXT2"; + 3'h5 : i_state = "IDLE"; + default : i_state = "XXXXX"; + endcase + + +// Execution state +//========================= + +reg [8*32-1:0] e_state; + +always @(e_state_bin) + case(e_state_bin) + 4'h0 : e_state = "IRQ_0"; + 4'h1 : e_state = "IRQ_1"; + 4'h2 : e_state = "IRQ_2"; + 4'h3 : e_state = "IRQ_3"; + 4'h4 : e_state = "IRQ_4"; + 4'h5 : e_state = "SRC_AD"; + 4'h6 : e_state = "SRC_RD"; + 4'h7 : e_state = "SRC_WR"; + 4'h8 : e_state = "DST_AD"; + 4'h9 : e_state = "DST_RD"; + 4'hA : e_state = "DST_WR"; + 4'hB : e_state = "EXEC"; + 4'hC : e_state = "JUMP"; + 4'hD : e_state = "IDLE"; + default : e_state = "xxxx"; + endcase + + +// Count instruction number & cycles +//==================================== + +reg [31:0] inst_number; +always @(posedge mclk or posedge puc) + if (puc) inst_number <= 0; + else if (decode) inst_number <= inst_number+1; + +reg [31:0] inst_cycle; +always @(posedge mclk or posedge puc) + if (puc) inst_cycle <= 0; + else if (decode) inst_cycle <= 0; + else inst_cycle <= inst_cycle+1; + + +// Decode instruction +//==================================== + +// Buffer opcode +reg [15:0] opcode; +always @(posedge mclk or posedge puc) + if (puc) opcode <= 0; + else if (decode) opcode <= ir; + +// Interrupts +reg irq; +always @(posedge mclk or posedge puc) + if (puc) irq <= 1'b1; + else if (decode) irq <= irq_detect; + +// Instruction type +reg [8*32-1:0] inst_type; +always @(opcode or irq) + if (irq) + inst_type = "IRQ"; + else + case(opcode[15:13]) + 3'b000 : inst_type = "SIG-OP"; + 3'b001 : inst_type = "JUMP"; + default : inst_type = "TWO-OP"; + endcase + + +// Instructions name +reg [8*32-1:0] inst_name; +always @(opcode or inst_type or irq_num) + if (inst_type=="IRQ") + case(irq_num[3:0]) + 4'b0000 : inst_name = "IRQ 0"; + 4'b0001 : inst_name = "IRQ 1"; + 4'b0010 : inst_name = "IRQ 2"; + 4'b0011 : inst_name = "IRQ 3"; + 4'b0100 : inst_name = "IRQ 4"; + 4'b0101 : inst_name = "IRQ 5"; + 4'b0110 : inst_name = "IRQ 6"; + 4'b0111 : inst_name = "IRQ 7"; + 4'b1000 : inst_name = "IRQ 8"; + 4'b1001 : inst_name = "IRQ 9"; + 4'b1010 : inst_name = "IRQ 10"; + 4'b1011 : inst_name = "IRQ 11"; + 4'b1100 : inst_name = "IRQ 12"; + 4'b1101 : inst_name = "IRQ 13"; + 4'b1110 : inst_name = "NMI"; + default : inst_name = "RESET"; + endcase + else if (inst_type=="SIG-OP") + case(opcode[15:7]) + 9'b000100_000 : inst_name = "RRC"; + 9'b000100_001 : inst_name = "SWPB"; + 9'b000100_010 : inst_name = "RRA"; + 9'b000100_011 : inst_name = "SXT"; + 9'b000100_100 : inst_name = "PUSH"; + 9'b000100_101 : inst_name = "CALL"; + 9'b000100_110 : inst_name = "RETI"; + default : inst_name = "xxxx"; + endcase + else if (inst_type=="JUMP") + case(opcode[15:10]) + 6'b001_000 : inst_name = "JNE"; + 6'b001_001 : inst_name = "JEQ"; + 6'b001_010 : inst_name = "JNC"; + 6'b001_011 : inst_name = "JC"; + 6'b001_100 : inst_name = "JN"; + 6'b001_101 : inst_name = "JGE"; + 6'b001_110 : inst_name = "JL"; + 6'b001_111 : inst_name = "JMP"; + default : inst_name = "xxxx"; + endcase + else if (inst_type=="TWO-OP") + case(opcode[15:12]) + 4'b0100 : inst_name = "MOV"; + 4'b0101 : inst_name = "ADD"; + 4'b0110 : inst_name = "ADDC"; + 4'b0111 : inst_name = "SUBC"; + 4'b1000 : inst_name = "SUB"; + 4'b1001 : inst_name = "CMP"; + 4'b1010 : inst_name = "DADD"; + 4'b1011 : inst_name = "BIT"; + 4'b1100 : inst_name = "BIC"; + 4'b1101 : inst_name = "BIS"; + 4'b1110 : inst_name = "XOR"; + 4'b1111 : inst_name = "AND"; + default : inst_name = "xxxx"; + endcase + +// Instructions byte/word mode +reg [8*32-1:0] inst_bw; +always @(opcode or inst_type) + if (inst_type=="IRQ") + inst_bw = ""; + else if (inst_type=="SIG-OP") + inst_bw = opcode[6] ? ".B" : ""; + else if (inst_type=="JUMP") + inst_bw = ""; + else if (inst_type=="TWO-OP") + inst_bw = opcode[6] ? ".B" : ""; + +// Source register +reg [8*32-1:0] inst_src; +wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8]; + +always @(src_reg or inst_type) + if (inst_type=="IRQ") + inst_src = ""; + else if (inst_type=="JUMP") + inst_src = ""; + else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP")) + case(src_reg) + 4'b0000 : inst_src = "r0"; + 4'b0001 : inst_src = "r1"; + 4'b0010 : inst_src = "r2"; + 4'b0011 : inst_src = "r3"; + 4'b0100 : inst_src = "r4"; + 4'b0101 : inst_src = "r5"; + 4'b0110 : inst_src = "r6"; + 4'b0111 : inst_src = "r7"; + 4'b1000 : inst_src = "r8"; + 4'b1001 : inst_src = "r9"; + 4'b1010 : inst_src = "r10"; + 4'b1011 : inst_src = "r11"; + 4'b1100 : inst_src = "r12"; + 4'b1101 : inst_src = "r13"; + 4'b1110 : inst_src = "r14"; + default : inst_src = "r15"; + endcase + +// Destination register +reg [8*32-1:0] inst_dst; +always @(opcode or inst_type) + if (inst_type=="IRQ") + inst_dst = ""; + else if (inst_type=="SIG-OP") + inst_dst = ""; + else if (inst_type=="JUMP") + inst_dst = ""; + else if (inst_type=="TWO-OP") + case(opcode[3:0]) + 4'b0000 : inst_dst = "r0"; + 4'b0001 : inst_dst = "r1"; + 4'b0010 : inst_dst = "r2"; + 4'b0011 : inst_dst = "r3"; + 4'b0100 : inst_dst = "r4"; + 4'b0101 : inst_dst = "r5"; + 4'b0110 : inst_dst = "r6"; + 4'b0111 : inst_dst = "r7"; + 4'b1000 : inst_dst = "r8"; + 4'b1001 : inst_dst = "r9"; + 4'b1010 : inst_dst = "r10"; + 4'b1011 : inst_dst = "r11"; + 4'b1100 : inst_dst = "r12"; + 4'b1101 : inst_dst = "r13"; + 4'b1110 : inst_dst = "r14"; + default : inst_dst = "r15"; + endcase + +// Source Addressing mode +reg [8*32-1:0] inst_as; +always @(inst_type or src_reg or opcode or inst_src) + begin + if (inst_type=="IRQ") + inst_as = ""; + else if (inst_type=="JUMP") + inst_as = ""; + else if (src_reg==4'h3) // Addressing mode using R3 + case (opcode[5:4]) + 2'b11 : inst_as = "#-1"; + 2'b10 : inst_as = "#2"; + 2'b01 : inst_as = "#1"; + default: inst_as = "#0"; + endcase + else if (src_reg==4'h2) // Addressing mode using R2 + case (opcode[5:4]) + 2'b11 : inst_as = "#8"; + 2'b10 : inst_as = "#4"; + 2'b01 : inst_as = "&EDE"; + default: inst_as = inst_src; + endcase + else if (src_reg==4'h0) // Addressing mode using R0 + case (opcode[5:4]) + 2'b11 : inst_as = "#N"; + 2'b10 : inst_as = myFormat("@", inst_src, 0); + 2'b01 : inst_as = "EDE"; + default: inst_as = inst_src; + endcase + else // General Addressing mode + case (opcode[5:4]) + 2'b11 : begin + inst_as = myFormat("@", inst_src, 0); + inst_as = myFormat(inst_as, "+", 0); + end + 2'b10 : inst_as = myFormat("@", inst_src, 0); + 2'b01 : begin + inst_as = myFormat("x(", inst_src, 0); + inst_as = myFormat(inst_as, ")", 0); + end + default: inst_as = inst_src; + endcase + end + +// Destination Addressing mode +reg [8*32-1:0] inst_ad; +always @(opcode or inst_type or inst_dst) + begin + if (inst_type!="TWO-OP") + inst_ad = ""; + else if (opcode[3:0]==4'h2) // Addressing mode using R2 + case (opcode[7]) + 1'b1 : inst_ad = "&EDE"; + default: inst_ad = inst_dst; + endcase + else if (opcode[3:0]==4'h0) // Addressing mode using R0 + case (opcode[7]) + 2'b1 : inst_ad = "EDE"; + default: inst_ad = inst_dst; + endcase + else // General Addressing mode + case (opcode[7]) + 2'b1 : begin + inst_ad = myFormat("x(", inst_dst, 0); + inst_ad = myFormat(inst_ad, ")", 0); + end + default: inst_ad = inst_dst; + endcase + end + + +// Currently executed instruction +//================================ + +wire [32*8-1:0] inst_short = inst_name; + +reg [32*8-1:0] inst_full; +always @(inst_type or inst_name or inst_bw or inst_as or inst_ad) + begin + inst_full = myFormat(inst_name, inst_bw, 0); + inst_full = myFormat(inst_full, inst_as, 1); + if (inst_type=="TWO-OP") + inst_full = myFormat(inst_full, ",", 0); + inst_full = myFormat(inst_full, inst_ad, 1); + if (opcode==16'h4303) + inst_full = "NOP"; + if (opcode==`DBG_SWBRK_OP) + inst_full = "SBREAK"; + + end + + +// Instruction program counter +//================================ + +reg [15:0] inst_pc; +always @(posedge mclk or posedge puc) + if (puc) inst_pc <= 16'h0000; + else if (decode) inst_pc <= pc; + + +endmodule // msp_debug +
openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v (revision 29) @@ -0,0 +1,157 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: registers.v +// +// *Module Description: +// openMSP430 testbench +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 16 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $ +//---------------------------------------------------------------------------- + +// CPU registers +//====================== + +wire [15:0] r0 = dut.openMSP430_0.execution_unit_0.register_file_0.r0; +wire [15:0] r1 = dut.openMSP430_0.execution_unit_0.register_file_0.r1; +wire [15:0] r2 = dut.openMSP430_0.execution_unit_0.register_file_0.r2; +wire [15:0] r3 = dut.openMSP430_0.execution_unit_0.register_file_0.r3; +wire [15:0] r4 = dut.openMSP430_0.execution_unit_0.register_file_0.r4; +wire [15:0] r5 = dut.openMSP430_0.execution_unit_0.register_file_0.r5; +wire [15:0] r6 = dut.openMSP430_0.execution_unit_0.register_file_0.r6; +wire [15:0] r7 = dut.openMSP430_0.execution_unit_0.register_file_0.r7; +wire [15:0] r8 = dut.openMSP430_0.execution_unit_0.register_file_0.r8; +wire [15:0] r9 = dut.openMSP430_0.execution_unit_0.register_file_0.r9; +wire [15:0] r10 = dut.openMSP430_0.execution_unit_0.register_file_0.r10; +wire [15:0] r11 = dut.openMSP430_0.execution_unit_0.register_file_0.r11; +wire [15:0] r12 = dut.openMSP430_0.execution_unit_0.register_file_0.r12; +wire [15:0] r13 = dut.openMSP430_0.execution_unit_0.register_file_0.r13; +wire [15:0] r14 = dut.openMSP430_0.execution_unit_0.register_file_0.r14; +wire [15:0] r15 = dut.openMSP430_0.execution_unit_0.register_file_0.r15; + + +// RAM cells +//====================== + +//wire [15:0] mem200 = {dut.ram_8x512_hi_0.inst.mem[0], dut.ram_8x512_lo_0.inst.mem[0]}; +//wire [15:0] mem202 = {dut.ram_8x512_hi_0.inst.mem[1], dut.ram_8x512_lo_0.inst.mem[1]}; +//wire [15:0] mem204 = {dut.ram_8x512_hi_0.inst.mem[2], dut.ram_8x512_lo_0.inst.mem[2]}; +//wire [15:0] mem206 = {dut.ram_8x512_hi_0.inst.mem[3], dut.ram_8x512_lo_0.inst.mem[3]}; +//wire [15:0] mem208 = {dut.ram_8x512_hi_0.inst.mem[4], dut.ram_8x512_lo_0.inst.mem[4]}; +//wire [15:0] mem20A = {dut.ram_8x512_hi_0.inst.mem[5], dut.ram_8x512_lo_0.inst.mem[5]}; +//wire [15:0] mem20C = {dut.ram_8x512_hi_0.inst.mem[6], dut.ram_8x512_lo_0.inst.mem[6]}; +//wire [15:0] mem20E = {dut.ram_8x512_hi_0.inst.mem[7], dut.ram_8x512_lo_0.inst.mem[7]}; +//wire [15:0] mem210 = {dut.ram_8x512_hi_0.inst.mem[8], dut.ram_8x512_lo_0.inst.mem[8]}; +//wire [15:0] mem212 = {dut.ram_8x512_hi_0.inst.mem[9], dut.ram_8x512_lo_0.inst.mem[9]}; +//wire [15:0] mem214 = {dut.ram_8x512_hi_0.inst.mem[10], dut.ram_8x512_lo_0.inst.mem[10]}; +//wire [15:0] mem216 = {dut.ram_8x512_hi_0.inst.mem[11], dut.ram_8x512_lo_0.inst.mem[11]}; +//wire [15:0] mem218 = {dut.ram_8x512_hi_0.inst.mem[12], dut.ram_8x512_lo_0.inst.mem[12]}; +//wire [15:0] mem21A = {dut.ram_8x512_hi_0.inst.mem[13], dut.ram_8x512_lo_0.inst.mem[13]}; +//wire [15:0] mem21C = {dut.ram_8x512_hi_0.inst.mem[14], dut.ram_8x512_lo_0.inst.mem[14]}; +//wire [15:0] mem21E = {dut.ram_8x512_hi_0.inst.mem[15], dut.ram_8x512_lo_0.inst.mem[15]}; +//wire [15:0] mem220 = {dut.ram_8x512_hi_0.inst.mem[16], dut.ram_8x512_lo_0.inst.mem[16]}; +//wire [15:0] mem222 = {dut.ram_8x512_hi_0.inst.mem[17], dut.ram_8x512_lo_0.inst.mem[17]}; +//wire [15:0] mem224 = {dut.ram_8x512_hi_0.inst.mem[18], dut.ram_8x512_lo_0.inst.mem[18]}; +//wire [15:0] mem226 = {dut.ram_8x512_hi_0.inst.mem[19], dut.ram_8x512_lo_0.inst.mem[19]}; +//wire [15:0] mem228 = {dut.ram_8x512_hi_0.inst.mem[20], dut.ram_8x512_lo_0.inst.mem[20]}; +//wire [15:0] mem22A = {dut.ram_8x512_hi_0.inst.mem[21], dut.ram_8x512_lo_0.inst.mem[21]}; +//wire [15:0] mem22C = {dut.ram_8x512_hi_0.inst.mem[22], dut.ram_8x512_lo_0.inst.mem[22]}; +//wire [15:0] mem22E = {dut.ram_8x512_hi_0.inst.mem[23], dut.ram_8x512_lo_0.inst.mem[23]}; +//wire [15:0] mem230 = {dut.ram_8x512_hi_0.inst.mem[24], dut.ram_8x512_lo_0.inst.mem[24]}; +//wire [15:0] mem232 = {dut.ram_8x512_hi_0.inst.mem[25], dut.ram_8x512_lo_0.inst.mem[25]}; +//wire [15:0] mem234 = {dut.ram_8x512_hi_0.inst.mem[26], dut.ram_8x512_lo_0.inst.mem[26]}; +//wire [15:0] mem236 = {dut.ram_8x512_hi_0.inst.mem[27], dut.ram_8x512_lo_0.inst.mem[27]}; +//wire [15:0] mem238 = {dut.ram_8x512_hi_0.inst.mem[28], dut.ram_8x512_lo_0.inst.mem[28]}; +//wire [15:0] mem23A = {dut.ram_8x512_hi_0.inst.mem[29], dut.ram_8x512_lo_0.inst.mem[29]}; +//wire [15:0] mem23C = {dut.ram_8x512_hi_0.inst.mem[30], dut.ram_8x512_lo_0.inst.mem[30]}; +//wire [15:0] mem23E = {dut.ram_8x512_hi_0.inst.mem[31], dut.ram_8x512_lo_0.inst.mem[31]}; +//wire [15:0] mem240 = {dut.ram_8x512_hi_0.inst.mem[32], dut.ram_8x512_lo_0.inst.mem[32]}; +//wire [15:0] mem242 = {dut.ram_8x512_hi_0.inst.mem[33], dut.ram_8x512_lo_0.inst.mem[33]}; +//wire [15:0] mem244 = {dut.ram_8x512_hi_0.inst.mem[34], dut.ram_8x512_lo_0.inst.mem[34]}; +//wire [15:0] mem246 = {dut.ram_8x512_hi_0.inst.mem[35], dut.ram_8x512_lo_0.inst.mem[35]}; +//wire [15:0] mem248 = {dut.ram_8x512_hi_0.inst.mem[36], dut.ram_8x512_lo_0.inst.mem[36]}; +//wire [15:0] mem24A = {dut.ram_8x512_hi_0.inst.mem[37], dut.ram_8x512_lo_0.inst.mem[37]}; +//wire [15:0] mem24C = {dut.ram_8x512_hi_0.inst.mem[38], dut.ram_8x512_lo_0.inst.mem[38]}; +//wire [15:0] mem24E = {dut.ram_8x512_hi_0.inst.mem[39], dut.ram_8x512_lo_0.inst.mem[39]}; +//wire [15:0] mem250 = {dut.ram_8x512_hi_0.inst.mem[40], dut.ram_8x512_lo_0.inst.mem[40]}; +//wire [15:0] mem252 = {dut.ram_8x512_hi_0.inst.mem[41], dut.ram_8x512_lo_0.inst.mem[41]}; +//wire [15:0] mem254 = {dut.ram_8x512_hi_0.inst.mem[42], dut.ram_8x512_lo_0.inst.mem[42]}; +//wire [15:0] mem256 = {dut.ram_8x512_hi_0.inst.mem[43], dut.ram_8x512_lo_0.inst.mem[43]}; +//wire [15:0] mem258 = {dut.ram_8x512_hi_0.inst.mem[44], dut.ram_8x512_lo_0.inst.mem[44]}; +//wire [15:0] mem25A = {dut.ram_8x512_hi_0.inst.mem[45], dut.ram_8x512_lo_0.inst.mem[45]}; +//wire [15:0] mem25C = {dut.ram_8x512_hi_0.inst.mem[46], dut.ram_8x512_lo_0.inst.mem[46]}; +//wire [15:0] mem25E = {dut.ram_8x512_hi_0.inst.mem[47], dut.ram_8x512_lo_0.inst.mem[47]}; +//wire [15:0] mem260 = {dut.ram_8x512_hi_0.inst.mem[48], dut.ram_8x512_lo_0.inst.mem[48]}; +//wire [15:0] mem262 = {dut.ram_8x512_hi_0.inst.mem[49], dut.ram_8x512_lo_0.inst.mem[49]}; +//wire [15:0] mem264 = {dut.ram_8x512_hi_0.inst.mem[50], dut.ram_8x512_lo_0.inst.mem[50]}; +//wire [15:0] mem266 = {dut.ram_8x512_hi_0.inst.mem[51], dut.ram_8x512_lo_0.inst.mem[51]}; +//wire [15:0] mem268 = {dut.ram_8x512_hi_0.inst.mem[52], dut.ram_8x512_lo_0.inst.mem[52]}; +//wire [15:0] mem26A = {dut.ram_8x512_hi_0.inst.mem[53], dut.ram_8x512_lo_0.inst.mem[53]}; +//wire [15:0] mem26C = {dut.ram_8x512_hi_0.inst.mem[54], dut.ram_8x512_lo_0.inst.mem[54]}; +//wire [15:0] mem26E = {dut.ram_8x512_hi_0.inst.mem[55], dut.ram_8x512_lo_0.inst.mem[55]}; +//wire [15:0] mem270 = {dut.ram_8x512_hi_0.inst.mem[56], dut.ram_8x512_lo_0.inst.mem[56]}; +//wire [15:0] mem272 = {dut.ram_8x512_hi_0.inst.mem[57], dut.ram_8x512_lo_0.inst.mem[57]}; +//wire [15:0] mem274 = {dut.ram_8x512_hi_0.inst.mem[58], dut.ram_8x512_lo_0.inst.mem[58]}; +//wire [15:0] mem276 = {dut.ram_8x512_hi_0.inst.mem[59], dut.ram_8x512_lo_0.inst.mem[59]}; +//wire [15:0] mem278 = {dut.ram_8x512_hi_0.inst.mem[60], dut.ram_8x512_lo_0.inst.mem[60]}; +//wire [15:0] mem27A = {dut.ram_8x512_hi_0.inst.mem[61], dut.ram_8x512_lo_0.inst.mem[61]}; +//wire [15:0] mem27C = {dut.ram_8x512_hi_0.inst.mem[62], dut.ram_8x512_lo_0.inst.mem[62]}; +//wire [15:0] mem27E = {dut.ram_8x512_hi_0.inst.mem[63], dut.ram_8x512_lo_0.inst.mem[63]}; +//wire [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]}; + + +// ROM cells +//====================== +reg [15:0] rom_mem [2047:0]; + +// Interrupt vectors +wire [15:0] irq_vect_15 = rom_mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector +wire [15:0] irq_vect_14 = rom_mem[(1<<(`ROM_MSB+1))-2]; // NMI +wire [15:0] irq_vect_13 = rom_mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13 +wire [15:0] irq_vect_12 = rom_mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12 +wire [15:0] irq_vect_11 = rom_mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11 +wire [15:0] irq_vect_10 = rom_mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10 +wire [15:0] irq_vect_09 = rom_mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9 +wire [15:0] irq_vect_08 = rom_mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8 +wire [15:0] irq_vect_07 = rom_mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7 +wire [15:0] irq_vect_06 = rom_mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6 +wire [15:0] irq_vect_05 = rom_mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5 +wire [15:0] irq_vect_04 = rom_mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4 +wire [15:0] irq_vect_03 = rom_mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3 +wire [15:0] irq_vect_02 = rom_mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2 +wire [15:0] irq_vect_01 = rom_mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1 +wire [15:0] irq_vect_00 = rom_mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0 + + +// CPU internals +//====================== + +wire mclk = dut.openMSP430_0.mclk; +wire puc = dut.openMSP430_0.puc;
openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v (revision 29) @@ -0,0 +1,396 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: tb_openMSP430_fpga.v +// +// *Module Description: +// openMSP430 FPGA testbench +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module tb_openMSP430_fpga; + +// +// Wire & Register definition +//------------------------------ + +// Clock +reg [1:0] CLOCK_24; +reg [1:0] CLOCK_27; +reg CLOCK_50; +reg EXT_CLOCK; + +// Push Button +reg [3:0] KEY; + +// DPDT Switch +reg [9:0] SW; + +// 7-SEG Dispaly +wire [6:0] HEX0; +wire [6:0] HEX1; +wire [6:0] HEX2; +wire [6:0] HEX3; + +// LED +wire [7:0] LEDG; +wire [9:0] LEDR; + +// UART +wire UART_TXD; +reg UART_RXD; + +// SDRAM Interface +wire [15:0] DRAM_DQ; +wire [11:0] DRAM_ADDR; +wire DRAM_LDQM; +wire DRAM_UDQM; +wire DRAM_WE_N; +wire DRAM_CAS_N; +wire DRAM_RAS_N; +wire DRAM_CS_N; +wire DRAM_BA_0; +wire DRAM_BA_1; +wire DRAM_CLK; +wire DRAM_CKE; + +// Flash Interface +wire [7:0] FL_DQ; +wire [21:0] FL_ADDR; +wire FL_WE_N; +wire FL_RST_N; +wire FL_OE_N; +wire FL_CE_N; + +// SRAM Interface +wire [15:0] SRAM_DQ; +wire [17:0] SRAM_ADDR; +wire SRAM_UB_N; +wire SRAM_LB_N; +wire SRAM_WE_N; +wire SRAM_CE_N; +wire SRAM_OE_N; + +// SD Card Interface +wire SD_DAT; +wire SD_DAT3; +wire SD_CMD; +wire SD_CLK; + +// I2C +wire I2C_SDAT; +wire I2C_SCLK; + +// PS2 +reg PS2_DAT; +reg PS2_CLK; + +// USB JTAG link +reg TDI; +reg TCK; +reg TCS; +wire TDO; + +// VGA +wire VGA_HS; +wire VGA_VS; +wire [3:0] VGA_R; +wire [3:0] VGA_G; +wire [3:0] VGA_B; + +// Audio CODEC +wire AUD_ADCLRCK; +reg AUD_ADCDAT; +wire AUD_DACLRCK; +wire AUD_DACDAT; +wire AUD_BCLK; +wire AUD_XCK; + +// GPIO +wire [35:0] GPIO_0; +wire [35:0] GPIO_1; + + +// Core debug signals +wire [8*32-1:0] i_state; +wire [8*32-1:0] e_state; +wire [31:0] inst_cycle; +wire [8*32-1:0] inst_full; +wire [31:0] inst_number; +wire [15:0] inst_pc; +wire [8*32-1:0] inst_short; + +// Testbench variables +integer i; +integer error; +reg stimulus_done; + + +// +// Include files +//------------------------------ + +// CPU & Memory registers +`include "registers.v" + +// Verilog stimulus +`include "stimulus.v" + +// +// Initialize ROM +//------------------------------ + +initial + begin + // Read memory file + $readmemh("./rom.mem", rom_mem); + end + +// +// Generate Clock & Reset +//------------------------------ +initial + begin + CLOCK_24 = 2'b10; + forever #20.8 CLOCK_24 = ~CLOCK_24; // 24 MHz + end +initial + begin + CLOCK_27 = 2'b01; + forever #18.5 CLOCK_27 = ~CLOCK_27; // 27 MHz + end +initial + begin + CLOCK_50 = 1'b0; + forever #10.0 CLOCK_50 = ~CLOCK_50; // 50 MHz + end + +initial + begin + KEY[3] = 1'b1; + #100 KEY[3] = 1'b0; + #600 KEY[3] = 1'b1; + end + +// +// Global initialization +//------------------------------ +initial + begin + error = 0; + stimulus_done = 1; + EXT_CLOCK = 1'b0; + KEY[2:0] = 3'b111; + SW = 10'h000; + UART_RXD = 1'b0; + PS2_DAT = 1'b0; + PS2_CLK = 1'b0; + TDI = 1'b0; + TCK = 1'b0; + TCS = 1'b0; + AUD_ADCDAT = 1'b0; + end + +// +// openMSP430 FPGA Instance +//---------------------------------- + +main dut ( + + //////////////////////////////// Clock Input ///////////// + .CLOCK_24 (CLOCK_24), // 24 MHz + .CLOCK_27 (CLOCK_27), // 27 MHz + .CLOCK_50 (CLOCK_50), // 50 MHz + .EXT_CLOCK (EXT_CLOCK), // External Clock + //////////////////////////////// Push Button ///////////// + .KEY (KEY), // Pushbutton[3:0] + //////////////////////////////// DPDT Switch ///////////// + .SW (SW), // Toggle Switch[9:0] + //////////////////////////////// 7-SEG Dispaly ///////////// + .HEX0 (HEX0), // Seven Segment Digit 0 + .HEX1 (HEX1), // Seven Segment Digit 1 + .HEX2 (HEX2), // Seven Segment Digit 2 + .HEX3 (HEX3), // Seven Segment Digit 3 + //////////////////////////////// LED ///////////// + .LEDG (LEDG), // LED Green[7:0] + .LEDR (LEDR), // LED Red[9:0] + //////////////////////////////// UART ///////////// + .UART_TXD (UART_TXD), // UART Transmitter + .UART_RXD (UART_RXD), // UART Receiver + //////////////////////////////// SDRAM Interface ///////////// + .DRAM_DQ (DRAM_DQ), // SDRAM Data bus 16 Bits + .DRAM_ADDR (DRAM_ADDR), // SDRAM Address bus 12 Bits + .DRAM_LDQM (DRAM_LDQM), // SDRAM Low-byte Data Mask + .DRAM_UDQM (DRAM_UDQM), // SDRAM High-byte Data Mask + .DRAM_WE_N (DRAM_WE_N), // SDRAM Write Enable + .DRAM_CAS_N (DRAM_CAS_N), // SDRAM Column Address Strobe + .DRAM_RAS_N (DRAM_RAS_N), // SDRAM Row Address Strobe + .DRAM_CS_N (DRAM_CS_N), // SDRAM Chip Select + .DRAM_BA_0 (DRAM_BA_0), // SDRAM Bank Address 0 + .DRAM_BA_1 (DRAM_BA_1), // SDRAM Bank Address 0 + .DRAM_CLK (DRAM_CLK), // SDRAM Clock + .DRAM_CKE (DRAM_CKE), // SDRAM Clock Enable + //////////////////////////////// Flash Interface ///////////// + .FL_DQ (FL_DQ), // FLASH Data bus 8 Bits + .FL_ADDR (FL_ADDR), // FLASH Address bus 22 Bits + .FL_WE_N (FL_WE_N), // FLASH Write Enable + .FL_RST_N (FL_RST_N), // FLASH Reset + .FL_OE_N (FL_OE_N), // FLASH Output Enable + .FL_CE_N (FL_CE_N), // FLASH Chip Enable + //////////////////////////////// SRAM Interface ///////////// + .SRAM_DQ (SRAM_DQ), // SRAM Data bus 16 Bits + .SRAM_ADDR (SRAM_ADDR), // SRAM Address bus 18 Bits + .SRAM_UB_N (SRAM_UB_N), // SRAM High-byte Data Mask + .SRAM_LB_N (SRAM_LB_N), // SRAM Low-byte Data Mask + .SRAM_WE_N (SRAM_WE_N), // SRAM Write Enable + .SRAM_CE_N (SRAM_CE_N), // SRAM Chip Enable + .SRAM_OE_N (SRAM_OE_N), // SRAM Output Enable + //////////////////////////////// SD_Card Interface ///////////// + .SD_DAT (SD_DAT), // SD Card Data + .SD_DAT3 (SD_DAT3), // SD Card Data 3 + .SD_CMD (SD_CMD), // SD Card Command Signal + .SD_CLK (SD_CLK), // SD Card Clock + /////////////////////////////// USB JTAG link ///////////// + .TDI (TDI), // CPLD -> FPGA (data in) + .TCK (TCK), // CPLD -> FPGA (clk) + .TCS (TCS), // CPLD -> FPGA (CS) + .TDO (TDO), // FPGA -> CPLD (data out) + //////////////////////////////// I2C ///////////// + .I2C_SDAT (I2C_SDAT), // I2C Data + .I2C_SCLK (I2C_SCLK), // I2C Clock + //////////////////////////////// PS2 ///////////// + .PS2_DAT (PS2_DAT), // PS2 Data + .PS2_CLK (PS2_CLK), // PS2 Clock + //////////////////////////////// VGA ///////////// + .VGA_HS (VGA_HS), // VGA H_SYNC + .VGA_VS (VGA_VS), // VGA V_SYNC + .VGA_R (VGA_R), // VGA Red[3:0] + .VGA_G (VGA_G), // VGA Green[3:0] + .VGA_B (VGA_B), // VGA Blue[3:0] + //////////////////////////////// Audio CODEC ///////////// + .AUD_ADCLRCK (AUD_ADCLRCK), // Audio CODEC ADC LR Clock + .AUD_ADCDAT (AUD_ADCDAT), // Audio CODEC ADC Data + .AUD_DACLRCK (AUD_DACLRCK), // Audio CODEC DAC LR Clock + .AUD_DACDAT (AUD_DACDA), // Audio CODEC DAC Data + .AUD_BCLK (AUD_BCLK), // Audio CODEC Bit-Stream Clock + .AUD_XCK (AUD_XCK), // Audio CODEC Chip Clock + //////////////////////////////// GPIO ///////////// + .GPIO_0 (GPIO_0), // GPIO Connection 0 + .GPIO_1 (GPIO_1) // GPIO Connection 1 +); + + +// +// Debug utility signals +//---------------------------------------- +msp_debug msp_debug_0 ( + +// OUTPUTs + .e_state (e_state), // Execution state + .i_state (i_state), // Instruction fetch state + .inst_cycle (inst_cycle), // Cycle number within current instruction + .inst_full (inst_full), // Currently executed instruction (full version) + .inst_number (inst_number), // Instruction number since last system reset + .inst_pc (inst_pc), // Instruction Program counter + .inst_short (inst_short), // Currently executed instruction (short version) + +// INPUTs + .mclk (mclk), // Main system clock + .puc (puc) // Main system reset +); + +// +// Generate Waveform +//---------------------------------------- +initial + begin + `ifdef VPD_FILE + $vcdplusfile("tb_openMSP430_fpga.vpd"); + $vcdpluson(); + `else + $dumpfile("tb_openMSP430_fpga.vcd"); + $dumpvars(0, tb_openMSP430_fpga); + `endif + end + +// +// End of simulation +//---------------------------------------- + +initial // Timeout + begin + #500000; + $display(" ==============================================="); + $display("| SIMULATION FAILED |"); + $display("| (simulation Timeout) |"); + $display(" ==============================================="); + $finish; + end + +initial // Normal end of test + begin + @(inst_pc===16'hffff) + $display(" ==============================================="); + if (error!=0) + begin + $display("| SIMULATION FAILED |"); + $display("| (some verilog stimulus checks failed) |"); + end + else if (~stimulus_done) + begin + $display("| SIMULATION FAILED |"); + $display("| (the verilog stimulus didn't complete) |"); + end + else + begin + $display("| SIMULATION PASSED |"); + end + $display(" ==============================================="); + $finish; + end + + +// +// Tasks Definition +//------------------------------ + + task tb_error; + input [65*8:0] error_string; + begin + $display("ERROR: %s %t", error_string, $time); + error = error+1; + end + endtask + + +endmodule
openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ext_de1_sram.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ext_de1_sram.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ext_de1_sram.v (revision 29) @@ -0,0 +1,150 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: ext_de1_sram.v +// +// *Module Description: +// openMSP430 interface with altera DE1's external async SRAM (256kwords x 16bits) +// +// *Author(s): +// - Vadim Akimov, lvd.mhm@gmail.com + + +module ext_de1_sram( + + input clk, + + // ram interface with openmsp430 core + input [ADDR_WIDTH-1:0] ram_addr, + input ram_cen, + input [1:0] ram_wen, + input [15:0] ram_din, + output reg [15:0] ram_dout, + + // DE1's sram signals + inout [15:0] SRAM_DQ, + output reg [17:0] SRAM_ADDR, + output reg SRAM_UB_N, + output reg SRAM_LB_N, + output reg SRAM_WE_N, + output reg SRAM_CE_N, + output reg SRAM_OE_N +); + + + parameter ADDR_WIDTH = 9; // [8:0] - 512 words of 16 bits (1 kB) are only addressed by default + + + + // we assume SRAM is fast enough to accomodate 1-cycle access rate of openmsp430. Also it must be fast + // enough to provide read data half cycle after read access begins. It is highly recommended to + // set all SRAM_ signals as "Fast Output Register" in quartus. Also set Fast Enable Register for SRAM_DQ. + // SRAM used in DE1 has zero setup and hold times for address and data in write cycle, so we can write data + // in one clock cycle. + // + // we emulate ram_cen behavior by not changing read data when ram_cen=1 (last read data remain on ram_dout) + + + reg [15:0] sram_dout; + + reg rnw; // =1 - read, =0 - write (Read-Not_Write) + reg ena; // enable + + + + + // address is always loaded from core + always @(negedge clk) + begin + SRAM_ADDR <= { {18-ADDR_WIDTH{1'b0}}, ram_addr[ADDR_WIDTH-1:0] }; + end + + + // some control signals + always @(negedge clk) + begin + if( !ram_cen && !(&ram_wen) ) + rnw <= 1'b0; + else + rnw <= 1'b1; + + ena <= ~ram_cen; + end + + + // store data for write cycle + always @(negedge clk) + sram_dout <= ram_din; + + // bus control + assign SRAM_DQ = rnw ? {16{1'bZ}} : sram_dout; + + // read cycle - data latching + always @(posedge clk) + begin + if( ena && rnw ) + ram_dout <= SRAM_DQ; + end + + + // SRAM access signals + always @(negedge clk) + begin + if( !ram_cen ) + begin + if( &ram_wen[1:0] ) // read access + begin + SRAM_CE_N <= 1'b0; + SRAM_OE_N <= 1'b0; + SRAM_WE_N <= 1'b1; + SRAM_UB_N <= 1'b0; + SRAM_LB_N <= 1'b0; + end + else // !(&ram_wen[1:0]) - write access + begin + SRAM_CE_N <= 1'b0; + SRAM_OE_N <= 1'b1; + SRAM_WE_N <= 1'b0; + SRAM_UB_N <= ram_wen[1]; + SRAM_LB_N <= ram_wen[0]; + end + end + else // ram_cen - idle + begin + SRAM_CE_N <= 1'b1; + SRAM_OE_N <= 1'b1; + SRAM_WE_N <= 1'b1; + SRAM_UB_N <= 1'b1; + SRAM_LB_N <= 1'b1; + end + end + + + + + +endmodule + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ext_de1_sram.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/io_mux.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/io_mux.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/io_mux.v (revision 29) @@ -0,0 +1,112 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: io_mux.v +// +// *Module Description: +// I/O mux for port function selection. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- + + +module io_mux ( + +// Function A (typically GPIO) + a_din, + a_dout, + a_dout_en, + +// Function B (Timer A, ...) + b_din, + b_dout, + b_dout_en, + +// IO Cell + io_din, + io_dout, + io_dout_en, + +// Function selection (0=A, 1=B) + sel +); + +// PARAMETERs +//============ +parameter WIDTH = 8; + +// Function A (typically GPIO) +//=============================== +output [WIDTH-1:0] a_din; +input [WIDTH-1:0] a_dout; +input [WIDTH-1:0] a_dout_en; + +// Function B (Timer A, ...) +//=============================== +output [WIDTH-1:0] b_din; +input [WIDTH-1:0] b_dout; +input [WIDTH-1:0] b_dout_en; + +// IO Cell +//=============================== +input [WIDTH-1:0] io_din; +output [WIDTH-1:0] io_dout; +output [WIDTH-1:0] io_dout_en; + +// Function selection (0=A, 1=B) +//=============================== +input [WIDTH-1:0] sel; + + +//============================================================================= +// 1) I/O FUNCTION SELECTION MUX +//============================================================================= + +function [WIDTH-1:0] mux ( + input [WIDTH-1:0] A, + input [WIDTH-1:0] B, + input [WIDTH-1:0] SEL +); + integer i; + begin + mux = {WIDTH{1'b0}}; + for (i = 0; i < WIDTH; i = i + 1) + mux[i] = sel[i] ? B[i] : A[i]; + end +endfunction + + +assign a_din = mux( io_din, {WIDTH{1'b0}}, sel); +assign b_din = mux({WIDTH{1'b0}}, io_din, sel); +assign io_dout = mux( a_dout, b_dout, sel); +assign io_dout_en = mux( a_dout_en, b_dout_en, sel); + + +endmodule // io_mux
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/io_mux.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v (revision 29) @@ -0,0 +1,296 @@ +`ifdef OPENMSP430_DEFINES +`else +`define OPENMSP430_DEFINES +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_defines.v +// +// *Module Description: +// openMSP430 Configuration file +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// SYSTEM CONFIGURATION +//---------------------------------------------------------------------------- + +// ROM Size: +// 9 -> 1kB +// 10 -> 2kB +// 11 -> 4kB +// 12 -> 8kB +// 13 -> 16kB +`define ROM_AWIDTH 11 + +// RAM Size: +// 6 -> 128 B +// 7 -> 256 B +// 8 -> 512 B +// 9 -> 1 kB +// 10 -> 2 kB +`define RAM_AWIDTH 9 + +//---------------------------------------------------------------------------- +// REMOTE DEBUGGING INTERFACE CONFIGURATION +//---------------------------------------------------------------------------- + +// Include Debug interface +//`define DBG_EN + +// Debug interface selection +// `define DBG_UART -> Enable UART (8N1) debug interface +// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET +// +`define DBG_UART +//`define DBG_JTAG + +// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) +// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 +// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 +// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 +// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 +// +`define DBG_HWBRK_0 +`define DBG_HWBRK_1 +`define DBG_HWBRK_2 +`define DBG_HWBRK_3 + + +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// + +// ROM and RAM sizes +`define ROM_SIZE (2 << `ROM_AWIDTH) +`define RAM_SIZE (2 << `RAM_AWIDTH) + +// RAM Base Adresses +`define RAM_BASE 16'h0200 // RAM base address + +// ROM & RAM most significant address bit (for 16 bit words) +`define ROM_MSB `ROM_AWIDTH-1 +`define RAM_MSB `RAM_AWIDTH-1 + + +// Instructions type +`define INST_SO 0 +`define INST_JMP 1 +`define INST_TO 2 + +// Single-operand arithmetic +`define RRC 0 +`define SWPB 1 +`define RRA 2 +`define SXT 3 +`define PUSH 4 +`define CALL 5 +`define RETI 6 +`define IRQ 7 + +// Conditional jump +`define JNE 0 +`define JEQ 1 +`define JNC 2 +`define JC 3 +`define JN 4 +`define JGE 5 +`define JL 6 +`define JMP 7 + +// Two-operand arithmetic +`define MOV 0 +`define ADD 1 +`define ADDC 2 +`define SUBC 3 +`define SUB 4 +`define CMP 5 +`define DADD 6 +`define BIT 7 +`define BIC 8 +`define BIS 9 +`define XOR 10 +`define AND 11 + +// Addressing modes +`define DIR 0 +`define IDX 1 +`define INDIR 2 +`define INDIR_I 3 +`define SYMB 4 +`define IMM 5 +`define ABS 6 +`define CONST 7 + +// Execution state machine +`define E_IRQ_0 4'h0 +`define E_IRQ_1 4'h1 +`define E_IRQ_2 4'h2 +`define E_IRQ_3 4'h3 +`define E_IRQ_4 4'h4 +`define E_SRC_AD 4'h5 +`define E_SRC_RD 4'h6 +`define E_SRC_WR 4'h7 +`define E_DST_AD 4'h8 +`define E_DST_RD 4'h9 +`define E_DST_WR 4'hA +`define E_EXEC 4'hB +`define E_JUMP 4'hC +`define E_IDLE 4'hD + +// ALU control signals +`define ALU_SRC_INV 0 +`define ALU_INC 1 +`define ALU_INC_C 2 +`define ALU_ADD 3 +`define ALU_AND 4 +`define ALU_OR 5 +`define ALU_XOR 6 +`define ALU_DADD 7 +`define ALU_STAT_7 8 +`define ALU_STAT_F 9 +`define ALU_SHIFT 10 +`define EXEC_NO_WR 11 + +// Debug interface +`define DBG_UART_WR 18 +`define DBG_UART_BW 17 +`define DBG_UART_ADDR 16:11 + +// Debug interface CPU_CTL register +`define HALT 0 +`define RUN 1 +`define ISTEP 2 +`define SW_BRK_EN 3 +`define FRZ_BRK_EN 4 +`define RST_BRK_EN 5 +`define CPU_RST 6 + +// Debug interface CPU_STAT register +`define HALT_RUN 0 +`define PUC_PND 1 +`define SWBRK_PND 3 +`define HWBRK0_PND 4 +`define HWBRK1_PND 5 + +// Debug interface BRKx_CTL register +`define BRK_MODE_RD 0 +`define BRK_MODE_WR 1 +`define BRK_MODE 1:0 +`define BRK_EN 2 +`define BRK_I_EN 3 +`define BRK_RANGE 4 + +// Basic clock module: BCSCTL1 Control Register +`define DIVAx 5:4 + +// Basic clock module: BCSCTL2 Control Register +`define SELS 3 +`define DIVSx 2:1 + +// Timer A: TACTL Control Register +`define TASSELx 9:8 +`define TAIDx 7:6 +`define TAMCx 5:4 +`define TACLR 2 +`define TAIE 1 +`define TAIFG 0 + +// Timer A: TACCTLx Capture/Compare Control Register +`define TACMx 15:14 +`define TACCISx 13:12 +`define TASCS 11 +`define TASCCI 10 +`define TACAP 8 +`define TAOUTMODx 7:5 +`define TACCIE 4 +`define TACCI 3 +`define TAOUT 2 +`define TACOV 1 +`define TACCIFG 0 + +// +// DEBUG INTERFACE EXTRA CONFIGURATION +//====================================== + +// Debug interface: Software breakpoint opcode +`define DBG_SWBRK_OP 16'h4343 + +// Debug interface ID +`define DBG_ID 24'h4D5350 + +// Debug UART interface auto data synchronization +// If the following define is commented out, then +// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly +// defined. +`define DBG_UART_AUTO_SYNC + +// Debug UART interface data rate +// In order to properly setup the UART debug interface, you +// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and +// the chosen BAUD rate from the UART interface. +// +//`define DBG_UART_BAUD 9600 +//`define DBG_UART_BAUD 19200 +//`define DBG_UART_BAUD 38400 +//`define DBG_UART_BAUD 57600 +//`define DBG_UART_BAUD 115200 +//`define DBG_UART_BAUD 230400 +//`define DBG_UART_BAUD 460800 +//`define DBG_UART_BAUD 576000 +//`define DBG_UART_BAUD 921600 +`define DBG_UART_BAUD 2000000 +`define DBG_DCO_FREQ 20000000 +`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) + +// Check configuration +`ifdef DBG_EN + `ifdef DBG_UART + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED + `endif + `else + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET + `else +CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED + `endif + `endif +`endif + + +`endif \ No newline at end of file
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg.v (revision 29) @@ -0,0 +1,796 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: dbg.v +// +// *Module Description: +// Debug interface +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module dbg ( + +// OUTPUTs + dbg_freeze, // Freeze peripherals + dbg_halt_cmd, // Halt CPU command + dbg_mem_addr, // Debug address for rd/wr access + dbg_mem_dout, // Debug unit data output + dbg_mem_en, // Debug unit memory enable + dbg_mem_wr, // Debug unit memory write + dbg_reg_wr, // Debug unit CPU register write + dbg_reset, // Reset CPU from debug interface + dbg_uart_txd, // Debug interface: UART TXD + +// INPUTs + dbg_halt_st, // Halt/Run status from CPU + dbg_mem_din, // Debug unit Memory data input + dbg_reg_din, // Debug unit CPU register data input + dbg_uart_rxd, // Debug interface: UART RXD + decode, // Frontend decode instruction + eu_mab, // Execution-Unit Memory address bus + eu_mb_en, // Execution-Unit Memory bus enable + eu_mb_wr, // Execution-Unit Memory bus write transfer + eu_mdb_in, // Memory data bus input + eu_mdb_out, // Memory data bus output + exec_done, // Execution completed + fe_mb_en, // Frontend Memory bus enable + fe_mdb_in, // Frontend Memory data bus input + mclk, // Main system clock + pc, // Program counter + por, // Power on reset + puc // Main system reset +); + +// OUTPUTs +//========= +output dbg_freeze; // Freeze peripherals +output dbg_halt_cmd; // Halt CPU command +output [15:0] dbg_mem_addr; // Debug address for rd/wr access +output [15:0] dbg_mem_dout; // Debug unit data output +output dbg_mem_en; // Debug unit memory enable +output [1:0] dbg_mem_wr; // Debug unit memory write +output dbg_reg_wr; // Debug unit CPU register write +output dbg_reset; // Reset CPU from debug interface +output dbg_uart_txd; // Debug interface: UART TXD + +// INPUTs +//========= +input dbg_halt_st; // Halt/Run status from CPU +input [15:0] dbg_mem_din; // Debug unit Memory data input +input [15:0] dbg_reg_din; // Debug unit CPU register data input +input dbg_uart_rxd; // Debug interface: UART RXD +input decode; // Frontend decode instruction +input [15:0] eu_mab; // Execution-Unit Memory address bus +input eu_mb_en; // Execution-Unit Memory bus enable +input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer +input [15:0] eu_mdb_in; // Memory data bus input +input [15:0] eu_mdb_out; // Memory data bus output +input exec_done; // Execution completed +input fe_mb_en; // Frontend Memory bus enable +input [15:0] fe_mdb_in; // Frontend Memory data bus input +input mclk; // Main system clock +input [15:0] pc; // Program counter +input por; // Power on reset +input puc; // Main system reset + + +//============================================================================= +// 1) WIRE & PARAMETER DECLARATION +//============================================================================= + +// Diverse wires and registers +wire [5:0] dbg_addr; +wire [15:0] dbg_din; +wire dbg_wr; +reg mem_burst; +wire dbg_reg_rd; +wire dbg_mem_rd; +reg dbg_mem_rd_dly; +wire dbg_swbrk; +wire dbg_rd; +reg dbg_rd_rdy; +wire mem_burst_rd; +wire mem_burst_wr; +wire brk0_halt; +wire brk0_pnd; +wire [15:0] brk0_dout; +wire brk1_halt; +wire brk1_pnd; +wire [15:0] brk1_dout; +wire brk2_halt; +wire brk2_pnd; +wire [15:0] brk2_dout; +wire brk3_halt; +wire brk3_pnd; +wire [15:0] brk3_dout; + +// Register addresses +parameter CPU_ID_LO = 6'h00; +parameter CPU_ID_HI = 6'h01; +parameter CPU_CTL = 6'h02; +parameter CPU_STAT = 6'h03; +parameter MEM_CTL = 6'h04; +parameter MEM_ADDR = 6'h05; +parameter MEM_DATA = 6'h06; +parameter MEM_CNT = 6'h07; +`ifdef DBG_HWBRK_0 +parameter BRK0_CTL = 6'h08; +parameter BRK0_STAT = 6'h09; +parameter BRK0_ADDR0 = 6'h0A; +parameter BRK0_ADDR1 = 6'h0B; +`endif +`ifdef DBG_HWBRK_1 +parameter BRK1_CTL = 6'h0C; +parameter BRK1_STAT = 6'h0D; +parameter BRK1_ADDR0 = 6'h0E; +parameter BRK1_ADDR1 = 6'h0F; +`endif +`ifdef DBG_HWBRK_2 +parameter BRK2_CTL = 6'h10; +parameter BRK2_STAT = 6'h11; +parameter BRK2_ADDR0 = 6'h12; +parameter BRK2_ADDR1 = 6'h13; +`endif +`ifdef DBG_HWBRK_3 +parameter BRK3_CTL = 6'h14; +parameter BRK3_STAT = 6'h15; +parameter BRK3_ADDR0 = 6'h16; +parameter BRK3_ADDR1 = 6'h17; +`endif + +// Register one-hot decoder +parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO); +parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI); +parameter CPU_CTL_D = (64'h1 << CPU_CTL); +parameter CPU_STAT_D = (64'h1 << CPU_STAT); +parameter MEM_CTL_D = (64'h1 << MEM_CTL); +parameter MEM_ADDR_D = (64'h1 << MEM_ADDR); +parameter MEM_DATA_D = (64'h1 << MEM_DATA); +parameter MEM_CNT_D = (64'h1 << MEM_CNT); +`ifdef DBG_HWBRK_0 +parameter BRK0_CTL_D = (64'h1 << BRK0_CTL); +parameter BRK0_STAT_D = (64'h1 << BRK0_STAT); +parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0); +parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1); +`endif +`ifdef DBG_HWBRK_1 +parameter BRK1_CTL_D = (64'h1 << BRK1_CTL); +parameter BRK1_STAT_D = (64'h1 << BRK1_STAT); +parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0); +parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1); +`endif +`ifdef DBG_HWBRK_2 +parameter BRK2_CTL_D = (64'h1 << BRK2_CTL); +parameter BRK2_STAT_D = (64'h1 << BRK2_STAT); +parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0); +parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1); +`endif +`ifdef DBG_HWBRK_3 +parameter BRK3_CTL_D = (64'h1 << BRK3_CTL); +parameter BRK3_STAT_D = (64'h1 << BRK3_STAT); +parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0); +parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1); +`endif + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Select Data register during a burst +wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr; + +// Register address decode +reg [63:0] reg_dec; +always @(dbg_addr_in) + case (dbg_addr_in) + CPU_ID_LO : reg_dec = CPU_ID_LO_D; + CPU_ID_HI : reg_dec = CPU_ID_HI_D; + CPU_CTL : reg_dec = CPU_CTL_D; + CPU_STAT : reg_dec = CPU_STAT_D; + MEM_CTL : reg_dec = MEM_CTL_D; + MEM_ADDR : reg_dec = MEM_ADDR_D; + MEM_DATA : reg_dec = MEM_DATA_D; + MEM_CNT : reg_dec = MEM_CNT_D; +`ifdef DBG_HWBRK_0 + BRK0_CTL : reg_dec = BRK0_CTL_D; + BRK0_STAT : reg_dec = BRK0_STAT_D; + BRK0_ADDR0: reg_dec = BRK0_ADDR0_D; + BRK0_ADDR1: reg_dec = BRK0_ADDR1_D; +`endif +`ifdef DBG_HWBRK_1 + BRK1_CTL : reg_dec = BRK1_CTL_D; + BRK1_STAT : reg_dec = BRK1_STAT_D; + BRK1_ADDR0: reg_dec = BRK1_ADDR0_D; + BRK1_ADDR1: reg_dec = BRK1_ADDR1_D; +`endif +`ifdef DBG_HWBRK_2 + BRK2_CTL : reg_dec = BRK2_CTL_D; + BRK2_STAT : reg_dec = BRK2_STAT_D; + BRK2_ADDR0: reg_dec = BRK2_ADDR0_D; + BRK2_ADDR1: reg_dec = BRK2_ADDR1_D; +`endif +`ifdef DBG_HWBRK_3 + BRK3_CTL : reg_dec = BRK3_CTL_D; + BRK3_STAT : reg_dec = BRK3_STAT_D; + BRK3_ADDR0: reg_dec = BRK3_ADDR0_D; + BRK3_ADDR1: reg_dec = BRK3_ADDR1_D; +`endif + default: reg_dec = {64{1'b0}}; + endcase + +// Read/Write probes +wire reg_write = dbg_wr; +wire reg_read = 1'b1; + +// Read/Write vectors +wire [511:0] reg_wr = reg_dec & {64{reg_write}}; +wire [511:0] reg_rd = reg_dec & {64{reg_read}}; + + +//============================================================================= +// 3) REGISTER: CORE INTERFACE +//============================================================================= + +// CPU_ID Register +//----------------- + +wire [3:0] cpu_id_rom = `ROM_AWIDTH; +wire [3:0] cpu_id_ram = `RAM_AWIDTH; +wire [31:0] cpu_id = {`DBG_ID, cpu_id_rom, cpu_id_ram}; + + +// CPU_CTL Register +//----------------------------------------------------------------------------- +// 7 6 5 4 3 2 1 0 +// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT +//----------------------------------------------------------------------------- +reg [6:3] cpu_ctl; + +wire cpu_ctl_wr = reg_wr[CPU_CTL]; + +always @ (posedge mclk or posedge por) + if (por) cpu_ctl <= 4'h0; + else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3]; + +wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000}; + +wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st; +wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st; +wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st; + + +// CPU_STAT Register +//------------------------------------------------------------------------------------ +// 7 6 5 4 3 2 1 0 +// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN +//------------------------------------------------------------------------------------ +reg [3:2] cpu_stat; + +wire cpu_stat_wr = reg_wr[CPU_STAT]; +wire [3:2] cpu_stat_set = {dbg_swbrk, puc}; +wire [3:2] cpu_stat_clr = ~dbg_din[3:2]; + +always @ (posedge mclk or posedge por) + if (por) cpu_stat <= 2'b00; + else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set); + else cpu_stat <= (cpu_stat | cpu_stat_set); + +wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd, + cpu_stat, 1'b0, dbg_halt_st}; + + +//============================================================================= +// 4) REGISTER: MEMORY INTERFACE +//============================================================================= + +// MEM_CTL Register +//----------------------------------------------------------------------------- +// 7 6 5 4 3 2 1 0 +// Reserved B/W MEM/REG RD/WR START +// +// START : - 0 : Do nothing. +// - 1 : Initiate memory transfer. +// +// RD/WR : - 0 : Read access. +// - 1 : Write access. +// +// MEM/REG: - 0 : Memory access. +// - 1 : CPU Register access. +// +// B/W : - 0 : 16 bit access. +// - 1 : 8 bit access (not valid for CPU Registers). +// +//----------------------------------------------------------------------------- +reg [3:1] mem_ctl; + +wire mem_ctl_wr = reg_wr[MEM_CTL]; + +always @ (posedge mclk or posedge por) + if (por) mem_ctl <= 3'h0; + else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1]; + +wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0}; + +reg mem_start; +always @ (posedge mclk or posedge por) + if (por) mem_start <= 1'b0; + else mem_start <= mem_ctl_wr & dbg_din[0]; + +wire mem_bw = mem_ctl[3]; + +// MEM_DATA Register +//------------------ +reg [15:0] mem_data; +reg [15:0] mem_addr; +wire mem_access; + +wire mem_data_wr = reg_wr[MEM_DATA]; + +wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din : + mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} : + {8'h00, dbg_mem_din[7:0]}; + +always @ (posedge mclk or posedge por) + if (por) mem_data <= 16'h0000; + else if (mem_data_wr) mem_data <= dbg_din; + else if (dbg_reg_rd) mem_data <= dbg_reg_din; + else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw; + + +// MEM_ADDR Register +//------------------ +reg [15:0] mem_cnt; + +wire mem_addr_wr = reg_wr[MEM_ADDR]; +wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2])); +wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2])); + +wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 : + (dbg_mem_acc & ~mem_bw) ? 16'h0002 : + (dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000; + +always @ (posedge mclk or posedge por) + if (por) mem_addr <= 16'h0000; + else if (mem_addr_wr) mem_addr <= dbg_din; + else mem_addr <= mem_addr + mem_addr_inc; + +// MEM_CNT Register +//------------------ + +wire mem_cnt_wr = reg_wr[MEM_CNT]; + +wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 : + (dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000; + +always @ (posedge mclk or posedge por) + if (por) mem_cnt <= 16'h0000; + else if (mem_cnt_wr) mem_cnt <= dbg_din; + else mem_cnt <= mem_cnt + mem_cnt_dec; + + +//============================================================================= +// 5) BREAKPOINTS / WATCHPOINTS +//============================================================================= + +`ifdef DBG_HWBRK_0 +// Hardware Breakpoint/Watchpoint Register read select +wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1], + reg_rd[BRK0_ADDR0], + reg_rd[BRK0_STAT], + reg_rd[BRK0_CTL]}; + +// Hardware Breakpoint/Watchpoint Register write select +wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1], + reg_wr[BRK0_ADDR0], + reg_wr[BRK0_STAT], + reg_wr[BRK0_CTL]}; + +dbg_hwbrk dbg_hwbr_0 ( + +// OUTPUTs + .brk_halt (brk0_halt), // Hardware breakpoint command + .brk_pnd (brk0_pnd), // Hardware break/watch-point pending + .brk_dout (brk0_dout), // Hardware break/watch-point register data input + +// INPUTs + .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select + .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select + .dbg_din (dbg_din), // Debug register data input + .eu_mab (eu_mab), // Execution-Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer + .eu_mdb_in (eu_mdb_in), // Memory data bus input + .eu_mdb_out (eu_mdb_out), // Memory data bus output + .exec_done (exec_done), // Execution completed + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .por (por) // Power on reset +); + +`else +assign brk0_halt = 1'b0; +assign brk0_pnd = 1'b0; +assign brk0_dout = 16'h0000; +`endif + +`ifdef DBG_HWBRK_1 +// Hardware Breakpoint/Watchpoint Register read select +wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1], + reg_rd[BRK1_ADDR0], + reg_rd[BRK1_STAT], + reg_rd[BRK1_CTL]}; + +// Hardware Breakpoint/Watchpoint Register write select +wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1], + reg_wr[BRK1_ADDR0], + reg_wr[BRK1_STAT], + reg_wr[BRK1_CTL]}; + +dbg_hwbrk dbg_hwbr_1 ( + +// OUTPUTs + .brk_halt (brk1_halt), // Hardware breakpoint command + .brk_pnd (brk1_pnd), // Hardware break/watch-point pending + .brk_dout (brk1_dout), // Hardware break/watch-point register data input + +// INPUTs + .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select + .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select + .dbg_din (dbg_din), // Debug register data input + .eu_mab (eu_mab), // Execution-Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer + .eu_mdb_in (eu_mdb_in), // Memory data bus input + .eu_mdb_out (eu_mdb_out), // Memory data bus output + .exec_done (exec_done), // Execution completed + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .por (por) // Power on reset +); + +`else +assign brk1_halt = 1'b0; +assign brk1_pnd = 1'b0; +assign brk1_dout = 16'h0000; +`endif + + `ifdef DBG_HWBRK_2 +// Hardware Breakpoint/Watchpoint Register read select +wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1], + reg_rd[BRK2_ADDR0], + reg_rd[BRK2_STAT], + reg_rd[BRK2_CTL]}; + +// Hardware Breakpoint/Watchpoint Register write select +wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1], + reg_wr[BRK2_ADDR0], + reg_wr[BRK2_STAT], + reg_wr[BRK2_CTL]}; + +dbg_hwbrk dbg_hwbr_2 ( + +// OUTPUTs + .brk_halt (brk2_halt), // Hardware breakpoint command + .brk_pnd (brk2_pnd), // Hardware break/watch-point pending + .brk_dout (brk2_dout), // Hardware break/watch-point register data input + +// INPUTs + .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select + .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select + .dbg_din (dbg_din), // Debug register data input + .eu_mab (eu_mab), // Execution-Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer + .eu_mdb_in (eu_mdb_in), // Memory data bus input + .eu_mdb_out (eu_mdb_out), // Memory data bus output + .exec_done (exec_done), // Execution completed + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .por (por) // Power on reset +); + +`else +assign brk2_halt = 1'b0; +assign brk2_pnd = 1'b0; +assign brk2_dout = 16'h0000; +`endif + +`ifdef DBG_HWBRK_3 +// Hardware Breakpoint/Watchpoint Register read select +wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1], + reg_rd[BRK3_ADDR0], + reg_rd[BRK3_STAT], + reg_rd[BRK3_CTL]}; + +// Hardware Breakpoint/Watchpoint Register write select +wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1], + reg_wr[BRK3_ADDR0], + reg_wr[BRK3_STAT], + reg_wr[BRK3_CTL]}; + +dbg_hwbrk dbg_hwbr_3 ( + +// OUTPUTs + .brk_halt (brk3_halt), // Hardware breakpoint command + .brk_pnd (brk3_pnd), // Hardware break/watch-point pending + .brk_dout (brk3_dout), // Hardware break/watch-point register data input + +// INPUTs + .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select + .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select + .dbg_din (dbg_din), // Debug register data input + .eu_mab (eu_mab), // Execution-Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer + .eu_mdb_in (eu_mdb_in), // Memory data bus input + .eu_mdb_out (eu_mdb_out), // Memory data bus output + .exec_done (exec_done), // Execution completed + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .por (por) // Power on reset +); + +`else +assign brk3_halt = 1'b0; +assign brk3_pnd = 1'b0; +assign brk3_dout = 16'h0000; +`endif + + +//============================================================================ +// 6) DATA OUTPUT GENERATION +//============================================================================ + +wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}}; +wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}}; +wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}}; +wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}}; +wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}}; +wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}}; +wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}}; +wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}}; + +wire [15:0] dbg_dout = cpu_id_lo_rd | + cpu_id_hi_rd | + cpu_ctl_rd | + cpu_stat_rd | + mem_ctl_rd | + mem_data_rd | + mem_addr_rd | + mem_cnt_rd | + brk0_dout | + brk1_dout | + brk2_dout | + brk3_dout; + +// Tell UART/JTAG interface that the data is ready to be read +always @ (posedge mclk or posedge por) + if (por) dbg_rd_rdy <= 1'b0; + else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly); + else dbg_rd_rdy <= dbg_rd; + + +//============================================================================ +// 7) CPU CONTROL +//============================================================================ + +// Reset CPU +//-------------------------- +wire dbg_reset = cpu_ctl[`CPU_RST]; + + +// Break after reset +//-------------------------- +wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc; + + +// Freeze peripherals +//-------------------------- +wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN]; + + +// Software break +//-------------------------- +assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode & cpu_ctl[`SW_BRK_EN]; + + +// Single step +//-------------------------- +reg [1:0] inc_step; +always @(posedge mclk or posedge por) + if (por) inc_step <= 2'b00; + else if (istep) inc_step <= 2'b11; + else inc_step <= {inc_step[0], 1'b0}; + + +// Run / Halt +//-------------------------- +reg halt_flag; + +wire mem_halt_cpu; +wire mem_run_cpu; + +wire halt_flag_clr = run_cpu | mem_run_cpu; +wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu | + brk0_halt | brk1_halt | brk2_halt | brk3_halt; + +always @(posedge mclk or posedge por) + if (por) halt_flag <= 1'b0; + else if (halt_flag_clr) halt_flag <= 1'b0; + else if (halt_flag_set) halt_flag <= 1'b1; + +wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1]; + + +//============================================================================ +// 8) MEMORY CONTROL +//============================================================================ + +// Control Memory bursts +//------------------------------ + +wire mem_burst_start = (mem_start & |mem_cnt); +wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt); + +// Detect when burst is on going +always @(posedge mclk or posedge por) + if (por) mem_burst <= 1'b0; + else if (mem_burst_start) mem_burst <= 1'b1; + else if (mem_burst_end) mem_burst <= 1'b0; + +// Control signals for UART/JTAG interface +assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]); +assign mem_burst_wr = (mem_burst_start & mem_ctl[1]); + +// Trigger CPU Register or memory access during a burst +reg mem_startb; +always @(posedge mclk or posedge por) + if (por) mem_startb <= 1'b0; + else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd; + +// Combine single and burst memory start of sequence +wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb); + + +// Memory access state machine +//------------------------------ +reg [1:0] mem_state; +reg [1:0] mem_state_nxt; + +// State machine definition +parameter M_IDLE = 2'h0; +parameter M_SET_BRK = 2'h1; +parameter M_ACCESS_BRK = 2'h2; +parameter M_ACCESS = 2'h3; + +// State transition +always @(mem_state or mem_seq_start or dbg_halt_st) + case (mem_state) + M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE : + dbg_halt_st ? M_ACCESS : M_SET_BRK; + M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK; + M_ACCESS_BRK : mem_state_nxt = M_IDLE; + M_ACCESS : mem_state_nxt = M_IDLE; + default : mem_state_nxt = M_IDLE; + endcase + +// State machine +always @(posedge mclk or posedge por) + if (por) mem_state <= M_IDLE; + else mem_state <= mem_state_nxt; + +// Utility signals +assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK); +assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE); +assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK); + + +// Interface to CPU Registers and Memory bacbkone +//------------------------------------------------ +assign dbg_mem_addr = mem_addr; +assign dbg_mem_dout = ~mem_bw ? mem_data : + mem_addr[0] ? {mem_data[7:0], 8'h00} : + {8'h00, mem_data[7:0]}; + +assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2]; +assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2]; + +assign dbg_mem_en = mem_access & ~mem_ctl[2]; +assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1]; + +wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 : + mem_addr[0] ? 2'b10 : 2'b01; +assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk; + + +// It takes one additional cycle to read from Memory as from registers +always @(posedge mclk or posedge por) + if (por) dbg_mem_rd_dly <= 1'b0; + else dbg_mem_rd_dly <= dbg_mem_rd; + + +//============================================================================= +// 9) UART COMMUNICATION +//============================================================================= +`ifdef DBG_UART +dbg_uart dbg_uart_0 ( + +// OUTPUTs + .dbg_addr (dbg_addr), // Debug register address + .dbg_din (dbg_din), // Debug register data input + .dbg_rd (dbg_rd), // Debug register data read + .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD + .dbg_wr (dbg_wr), // Debug register data write + +// INPUTs + .dbg_dout (dbg_dout), // Debug register data output + .dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read + .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD + .mclk (mclk), // Main system clock + .mem_burst (mem_burst), // Burst on going + .mem_burst_end(mem_burst_end), // End TX/RX burst + .mem_burst_rd (mem_burst_rd), // Start TX burst + .mem_burst_wr (mem_burst_wr), // Start RX burst + .mem_bw (mem_bw), // Burst byte width + .por (por) // Power on reset +); + +`else +assign dbg_addr = 6'h00; +assign dbg_din = 16'h0000; +assign dbg_rd = 1'b0; +assign dbg_uart_txd = 1'b0; +assign dbg_wr = 1'b0; +`endif + + +//============================================================================= +// 10) JTAG COMMUNICATION +//============================================================================= +`ifdef DBG_JTAG +JTAG INTERFACE IS NOT SUPPORTED YET +`else +`endif + +endmodule // dbg + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/frontend.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/frontend.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/frontend.v (revision 29) @@ -0,0 +1,756 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: frontend.v +// +// *Module Description: +// openMSP430 Instruction fetch and decode unit +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module frontend ( + +// OUTPUTs + dbg_halt_st, // Halt/Run status from CPU + decode, // Frontend decode instruction + e_state, // Execution state + exec_done, // Execution completed + inst_ad, // Decoded Inst: destination addressing mode + inst_as, // Decoded Inst: source addressing mode + inst_alu, // ALU control signals + inst_bw, // Decoded Inst: byte width + inst_dest, // Decoded Inst: destination (one hot) + inst_dext, // Decoded Inst: destination extended instruction word + inst_irq_rst, // Decoded Inst: Reset interrupt + inst_jmp, // Decoded Inst: Conditional jump + inst_sext, // Decoded Inst: source extended instruction word + inst_so, // Decoded Inst: Single-operand arithmetic + inst_src, // Decoded Inst: source (one hot) + inst_type, // Decoded Instruction type + irq_acc, // Interrupt request accepted (one-hot signal) + mab, // Frontend Memory address bus + mb_en, // Frontend Memory bus enable + nmi_acc, // Non-Maskable interrupt request accepted + pc, // Program counter + pc_nxt, // Next PC value (for CALL & IRQ) + +// INPUTs + cpuoff, // Turns off the CPU + dbg_halt_cmd, // Halt CPU command + dbg_reg_sel, // Debug selected register for rd/wr access + fe_rom_wait, // Frontend wait for ROM + gie, // General interrupt enable + irq, // Maskable interrupts + mclk, // Main system clock + mdb_in, // Frontend Memory data bus input + nmi_evt, // Non-maskable interrupt event + pc_sw, // Program counter software value + pc_sw_wr, // Program counter software write + puc, // Main system reset + wdt_irq // Watchdog-timer interrupt +); + +// OUTPUTs +//========= +output dbg_halt_st; // Halt/Run status from CPU +output decode; // Frontend decode instruction +output [3:0] e_state; // Execution state +output exec_done; // Execution completed +output [7:0] inst_ad; // Decoded Inst: destination addressing mode +output [7:0] inst_as; // Decoded Inst: source addressing mode +output [11:0] inst_alu; // ALU control signals +output inst_bw; // Decoded Inst: byte width +output [15:0] inst_dest; // Decoded Inst: destination (one hot) +output [15:0] inst_dext; // Decoded Inst: destination extended instruction word +output inst_irq_rst; // Decoded Inst: Reset interrupt +output [7:0] inst_jmp; // Decoded Inst: Conditional jump +output [15:0] inst_sext; // Decoded Inst: source extended instruction word +output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic +output [15:0] inst_src; // Decoded Inst: source (one hot) +output [2:0] inst_type; // Decoded Instruction type +output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) +output [15:0] mab; // Frontend Memory address bus +output mb_en; // Frontend Memory bus enable +output nmi_acc; // Non-Maskable interrupt request accepted +output [15:0] pc; // Program counter +output [15:0] pc_nxt; // Next PC value (for CALL & IRQ) + +// INPUTs +//========= +input cpuoff; // Turns off the CPU +input dbg_halt_cmd; // Halt CPU command +input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access +input fe_rom_wait; // Frontend wait for ROM +input gie; // General interrupt enable +input [13:0] irq; // Maskable interrupts +input mclk; // Main system clock +input [15:0] mdb_in; // Frontend Memory data bus input +input nmi_evt; // Non-maskable interrupt event +input [15:0] pc_sw; // Program counter software value +input pc_sw_wr; // Program counter software write +input puc; // Main system reset +input wdt_irq; // Watchdog-timer interrupt + + +//============================================================================= +// 1) FRONTEND STATE MACHINE +//============================================================================= + +// The wire "conv" is used as state bits to calculate the next response +reg [2:0] i_state; +reg [2:0] i_state_nxt; + +reg [1:0] inst_sz; +wire [1:0] inst_sz_nxt; +wire irq_detect; +wire [2:0] inst_type_nxt; +wire is_const; +reg [15:0] sconst_nxt; +reg [3:0] e_state_nxt; + +// State machine definitons +parameter I_IRQ_FETCH = 3'h0; +parameter I_IRQ_DONE = 3'h1; +parameter I_DEC = 3'h2; // New instruction ready for decode +parameter I_EXT1 = 3'h3; // 1st Extension word +parameter I_EXT2 = 3'h4; // 2nd Extension word +parameter I_IDLE = 3'h5; // CPU is in IDLE mode + +// States Transitions +always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or + exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state) + case(i_state) + I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH : + (~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE; + I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE; + I_IRQ_DONE : i_state_nxt = I_DEC; + I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH : + (cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE : + dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE : + pc_sw_wr ? I_DEC : + ~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state + (inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed + I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH : + pc_sw_wr ? I_DEC : + (inst_sz!=2'b01) ? I_EXT2 : I_DEC; + I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC; + default : i_state_nxt = I_IRQ_FETCH; + endcase + +// State machine +always @(posedge mclk or posedge puc) + if (puc) i_state <= I_IRQ_FETCH; + else i_state <= i_state_nxt; + +// Utility signals +wire decode = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))) | irq_detect; +wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE); + +// Debug interface cpu status +reg dbg_halt_st; +always @(posedge mclk or posedge puc) + if (puc) dbg_halt_st <= 1'b0; + else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE); + + +//============================================================================= +// 2) INTERRUPT HANDLING +//============================================================================= + +// Detect nmi interrupt +reg inst_nmi; +always @(posedge mclk or posedge puc) + if (puc) inst_nmi <= 1'b0; + else if (nmi_evt) inst_nmi <= 1'b1; + else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0; + + +// Detect reset interrupt +reg inst_irq_rst; +always @(posedge mclk or posedge puc) + if (puc) inst_irq_rst <= 1'b1; + else if (exec_done) inst_irq_rst <= 1'b0; + +// Detect other interrupts +assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE)); + +// Select interrupt vector +reg [3:0] irq_num; +always @(posedge mclk or posedge puc) + if (puc) irq_num <= 4'hf; + else if (irq_detect) irq_num <= inst_nmi ? 4'he : + irq[13] ? 4'hd : + irq[12] ? 4'hc : + irq[11] ? 4'hb : + (irq[10] | wdt_irq) ? 4'ha : + irq[9] ? 4'h9 : + irq[8] ? 4'h8 : + irq[7] ? 4'h7 : + irq[6] ? 4'h6 : + irq[5] ? 4'h5 : + irq[4] ? 4'h4 : + irq[3] ? 4'h3 : + irq[2] ? 4'h2 : + irq[1] ? 4'h1 : + irq[0] ? 4'h0 : 4'hf; + +wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0}; + +// Interrupt request accepted +wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}}; +wire [13:0] irq_acc = irq_acc_all[13:0]; +wire nmi_acc = irq_acc_all[14]; + + +//============================================================================= +// 3) FETCH INSTRUCTION +//============================================================================= + +// +// 3.1) PROGRAM COUNTER & MEMORY INTERFACE +//----------------------------------------- + +// Program counter +reg [15:0] pc; + +// Detect if PC needs to be incremented +wire pc_inc = (~pc_sw_wr & fetch) & ~(i_state==I_IRQ_FETCH) & ~(i_state==I_IRQ_DONE); + +// Mux between software update and old PC +wire [15:0] pc_sel = pc_sw_wr ? pc_sw : + (i_state==I_IRQ_FETCH) ? irq_addr : + (i_state==I_IRQ_DONE) ? mdb_in : pc; + +// Compute next PC value +wire [15:0] pc_nxt = pc_sel + {14'h0000, pc_inc, 1'b0}; + +always @(posedge mclk or posedge puc) + if (puc) pc <= 16'h0000; + else pc <= pc_nxt; + +// Check if ROM has been busy in order to retry ROM access +reg rom_busy; +always @(posedge mclk or posedge puc) + if (puc) rom_busy <= 16'h0000; + else rom_busy <= fe_rom_wait; + +// Memory interface +wire [15:0] mab = pc_nxt; +wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | rom_busy | (dbg_halt_st & ~dbg_halt_cmd); + + +// +// 3.2) INSTRUCTION REGISTER +//-------------------------------- + +// Instruction register +wire [15:0] ir = mdb_in; + +// Detect if source extension word is required +wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]); + +// Detect if destination extension word is required +wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]); + +// For the Symbolic addressing mode, add -2 to the extension word in order +// to make up for the PC address +wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) | + ((i_state==I_EXT2) & inst_ad[`SYMB]) | + ((i_state==I_EXT1) & ~inst_as[`SYMB] & + ~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000; + +wire [15:0] ext_nxt = ir + ext_incr; + +// Store source extension word +reg [15:0] inst_sext; +always @(posedge mclk or posedge puc) + if (puc) inst_sext <= 16'h0000; + else if (decode & is_const) inst_sext <= sconst_nxt; + else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0}; + else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt; + +// Source extension word is ready +wire inst_sext_rdy = (i_state==I_EXT1) & is_sext; + + +// Store destination extension word +reg [15:0] inst_dext; +always @(posedge mclk or posedge puc) + if (puc) inst_dext <= 16'h0000; + else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt; + else if (i_state==I_EXT2) inst_dext <= ext_nxt; + +// Destination extension word is ready +wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2)); + + +//============================================================================= +// 4) DECODE INSTRUCTION +//============================================================================= + +// +// 4.1) OPCODE: INSTRUCTION TYPE +//---------------------------------------- +// Instructions type is encoded in a one hot fashion as following: +// +// 3'b001: Single-operand arithmetic +// 3'b010: Conditional jump +// 3'b100: Two-operand arithmetic + +reg [2:0] inst_type; +assign inst_type_nxt = {(ir[15:14]!=2'b00), + (ir[15:13]==3'b001), + (ir[15:13]==3'b000)} & {3{~irq_detect}}; + +always @(posedge mclk or posedge puc) + if (puc) inst_type <= 3'b000; + else if (decode) inst_type <= inst_type_nxt; + +// +// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC +//---------------------------------------- +// Instructions are encoded in a one hot fashion as following: +// +// 8'b00000001: RRC +// 8'b00000010: SWPB +// 8'b00000100: RRA +// 8'b00001000: SXT +// 8'b00010000: PUSH +// 8'b00100000: CALL +// 8'b01000000: RETI +// 8'b10000000: IRQ + +reg [7:0] inst_so; +wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/frontend.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/clock_module.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/clock_module.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/clock_module.v (revision 29) @@ -0,0 +1,246 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: clock_module.v +// +// *Module Description: +// Basic clock module implementation. +// Since the openMSP430 mainly targets FPGA and hobby +// designers. The clock structure has been greatly +// symplified in order to ease integration. +// See online wiki for more info. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module clock_module ( + +// OUTPUTs + aclk_en, // ACLK enable + mclk, // Main system clock + per_dout, // Peripheral data output + por, // Power-on reset + puc, // Main system reset + smclk_en, // SMCLK enable + +// INPUTs + dbg_reset, // Reset CPU from debug interface + dco_clk, // Fast oscillator (fast clock) + lfxt_clk, // Low frequency oscillator (typ 32kHz) + oscoff, // Turns off LFXT1 clock input + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + reset_n, // Reset Pin (low active) + scg1, // System clock generator 1. Turns off the SMCLK + wdt_reset // Watchdog-timer reset +); + +// OUTPUTs +//========= +output aclk_en; // ACLK enable +output mclk; // Main system clock +output [15:0] per_dout; // Peripheral data output +output por; // Power-on reset +output puc; // Main system reset +output smclk_en; // SMCLK enable + +// INPUTs +//========= +input dbg_reset; // Reset CPU from debug interface +input dco_clk; // Fast oscillator (fast clock) +input lfxt_clk; // Low frequency oscillator (typ 32kHz) +input oscoff; // Turns off LFXT1 clock input +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input reset_n; // Reset Pin (low active) +input scg1; // System clock generator 1. Turns off the SMCLK +input wdt_reset; // Watchdog-timer reset + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter BCSCTL1 = 9'h057; +parameter BCSCTL2 = 9'h058; + +// Register one-hot decoder +parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2)); +parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2)); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [255:0] reg_dec; +always @(per_addr) + case (per_addr) + (BCSCTL1 /2): reg_dec = BCSCTL1_D; + (BCSCTL2 /2): reg_dec = BCSCTL2_D; + default : reg_dec = {256{1'b0}}; + endcase + +// Read/Write probes +wire reg_lo_write = per_wen[0] & per_en; +wire reg_hi_write = per_wen[1] & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; +wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; +wire [255:0] reg_rd = reg_dec & {256{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// BCSCTL1 Register +//-------------- +reg [7:0] bcsctl1; +wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2]; +wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) bcsctl1 <= 8'h00; + else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits + + +// BCSCTL2 Register +//-------------- +reg [7:0] bcsctl2; +wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2]; +wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) bcsctl2 <= 8'h00; + else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}}); +wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}}); + +wire [15:0] per_dout = bcsctl1_rd | + bcsctl2_rd; + + +//============================================================================= +// 5) CLOCK GENERATION +//============================================================================= + +// Synchronize LFXT_CLK & edge detection +//--------------------------------------- +reg [2:0] lfxt_clk_s; + +always @ (posedge mclk or posedge puc) + if (puc) lfxt_clk_s <= 3'b000; + else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk}; + +wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]); + + +// Generate main system clock +//---------------------------- + +wire mclk = dco_clk; +wire mclk_n = !dco_clk; + + +// Generate ACLK +//---------------------------- + +reg [2:0] aclk_div; + +wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 : + (bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] : + (bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] : + &aclk_div[2:0]); + +always @ (posedge mclk or posedge puc) + if (puc) aclk_div <= 3'h0; + else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1; + + +// Generate SMCLK +//---------------------------- + +reg [2:0] smclk_div; + +wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1); + +wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 : + (bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] : + (bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] : + &smclk_div[2:0]); + +always @ (posedge mclk or posedge puc) + if (puc) smclk_div <= 3'h0; + else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1; + + +//============================================================================= +// 6) RESET GENERATION +//============================================================================= + +// Generate synchronized POR +wire por_reset = !reset_n; + +reg [1:0] por_s; +always @(posedge mclk_n or posedge por_reset) + if (por_reset) por_s <= 2'b11; + else por_s <= {por_s[0], 1'b0}; +wire por = por_s[1]; + +// Generate main system reset +wire puc_reset = por_reset | wdt_reset | dbg_reset; + +reg [1:0] puc_s; +always @(posedge mclk_n or posedge puc_reset) + if (puc_reset) puc_s <= 2'b11; + else puc_s <= {puc_s[0], 1'b0}; +wire puc = puc_s[1]; + + +endmodule // clock_module +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/clock_module.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/watchdog.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/watchdog.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/watchdog.v (revision 29) @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: watchdog.v +// +// *Module Description: +// Watchdog Timer +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module watchdog ( + +// OUTPUTs + nmi_evt, // NMI Event + per_dout, // Peripheral data output + wdtifg_set, // Set Watchdog-timer interrupt flag + wdtpw_error, // Watchdog-timer password error + wdttmsel, // Watchdog-timer mode select + +// INPUTs + aclk_en, // ACLK enable + dbg_freeze, // Freeze Watchdog counter + mclk, // Main system clock + nmi, // Non-maskable interrupt (asynchronous) + nmie, // Non-maskable interrupt enable + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc, // Main system reset + smclk_en, // SMCLK enable + wdtie // Watchdog timer interrupt enable +); + +// OUTPUTs +//========= +output nmi_evt; // NMI Event +output [15:0] per_dout; // Peripheral data output +output wdtifg_set; // Set Watchdog-timer interrupt flag +output wdtpw_error; // Watchdog-timer password error +output wdttmsel; // Watchdog-timer mode select + +// INPUTs +//========= +input aclk_en; // ACLK enable +input dbg_freeze; // Freeze Watchdog counter +input mclk; // Main system clock +input nmi; // Non-maskable interrupt (asynchronous) +input nmie; // Non-maskable interrupt enable +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset +input smclk_en; // SMCLK enable +input wdtie; // Watchdog timer interrupt enable + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter WDTCTL = 9'h120; + + +// Register one-hot decoder +parameter WDTCTL_D = (512'h1 << WDTCTL); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [511:0] reg_dec; +always @(per_addr) + case ({per_addr,1'b0}) + WDTCTL : reg_dec = WDTCTL_D; + default: reg_dec = {512{1'b0}}; + endcase + +// Read/Write probes +wire reg_write = |per_wen & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [511:0] reg_wr = reg_dec & {512{reg_write}}; +wire [511:0] reg_rd = reg_dec & {512{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// WDTCTL Register +//----------------- +// WDTNMI & WDTSSEL are not implemented and therefore masked + +reg [7:0] wdtctl; + +wire wdtctl_wr = reg_wr[WDTCTL]; + +always @ (posedge mclk or posedge puc) + if (puc) wdtctl <= 8'h00; + else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7; + +wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a); +wire wdttmsel = wdtctl[4]; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// Data output mux +wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}}; + +wire [15:0] per_dout = wdtctl_rd; + + +//============================================================================= +// 4) NMI GENERATION +//============================================================================= + +// Synchronization state +reg [2:0] nmi_sync; +always @ (posedge mclk or posedge puc) + if (puc) nmi_sync <= 3'h0; + else nmi_sync <= {nmi_sync[1:0], nmi}; + +// Edge detection +wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie; +wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie; + +// NMI event +wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re; + + +//============================================================================= +// 5) WATCHDOG TIMER +//============================================================================= + +// Watchdog clock source selection +//--------------------------------- +wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en; + + +// Watchdog 16 bit counter +//-------------------------- +reg [15:0] wdtcnt; + +wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set; + +always @ (posedge mclk or posedge puc) + if (puc) wdtcnt <= 16'h0000; + else if (wdtcnt_clr) wdtcnt <= 16'h0000; + else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001; + + +// Interval selection mux +//-------------------------- +reg wdtqn; + +always @(wdtctl or wdtcnt) + case(wdtctl[1:0]) + 2'b00 : wdtqn = wdtcnt[15]; + 2'b01 : wdtqn = wdtcnt[13]; + 2'b10 : wdtqn = wdtcnt[9]; + default: wdtqn = wdtcnt[6]; + endcase + + +// Watchdog event detection +//----------------------------- +reg wdtqn_dly; + +always @ (posedge mclk or posedge puc) + if (puc) wdtqn_dly <= 1'b0; + else wdtqn_dly <= wdtqn; + +wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error; + + +endmodule // watchdog + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/watchdog.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/alu.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/alu.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/alu.v (revision 29) @@ -0,0 +1,248 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: alu.v +// +// *Module Description: +// openMSP430 ALU +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module alu ( + +// OUTPUTs + alu_out, // ALU output value + alu_out_add, // ALU adder output value + alu_stat, // ALU Status {V,N,Z,C} + alu_stat_wr, // ALU Status write {V,N,Z,C} + +// INPUTs + dbg_halt_st, // Halt/Run status from CPU + exec_cycle, // Instruction execution cycle + inst_alu, // ALU control signals + inst_bw, // Decoded Inst: byte width + inst_jmp, // Decoded Inst: Conditional jump + inst_so, // Single-operand arithmetic + op_dst, // Destination operand + op_src, // Source operand + status // R2 Status {V,N,Z,C} +); + +// OUTPUTs +//========= +output [15:0] alu_out; // ALU output value +output [15:0] alu_out_add; // ALU adder output value +output [3:0] alu_stat; // ALU Status {V,N,Z,C} +output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} + +// INPUTs +//========= +input dbg_halt_st; // Halt/Run status from CPU +input exec_cycle; // Instruction execution cycle +input [11:0] inst_alu; // ALU control signals +input inst_bw; // Decoded Inst: byte width +input [7:0] inst_jmp; // Decoded Inst: Conditional jump +input [7:0] inst_so; // Single-operand arithmetic +input [15:0] op_dst; // Destination operand +input [15:0] op_src; // Source operand +input [3:0] status; // R2 Status {V,N,Z,C} + + +//============================================================================= +// 1) FUNCTIONS +//============================================================================= + +function [4:0] bcd_add; + + input [3:0] X; + input [3:0] Y; + input C; + + reg [4:0] Z; + begin + Z = {1'b0,X}+{1'b0,Y}+C; + if (Z<10) bcd_add = Z; + else bcd_add = Z+6; + end + +endfunction + + +//============================================================================= +// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE +//============================================================================= +// SINGLE-OPERAND ARITHMETIC: +//----------------------------------------------------------------------------- +// Mnemonic S-Reg, Operation Status bits +// D-Reg, V N Z C +// +// RRC dst C->MSB->...LSB->C * * * * +// RRA dst MSB->MSB->...LSB->C 0 * * * +// SWPB dst Swap bytes - - - - +// SXT dst Bit7->Bit8...Bit15 0 * * * +// PUSH src SP-2->SP, src->@SP - - - - +// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - - +// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * * +// +//----------------------------------------------------------------------------- +// TWO-OPERAND ARITHMETIC: +//----------------------------------------------------------------------------- +// Mnemonic S-Reg, Operation Status bits +// D-Reg, V N Z C +// +// MOV src,dst src -> dst - - - - +// ADD src,dst src + dst -> dst * * * * +// ADDC src,dst src + dst + C -> dst * * * * +// SUB src,dst dst + ~src + 1 -> dst * * * * +// SUBC src,dst dst + ~src + C -> dst * * * * +// CMP src,dst dst + ~src + 1 * * * * +// DADD src,dst src + dst + C -> dst (decimaly) * * * * +// BIT src,dst src & dst 0 * * * +// BIC src,dst ~src & dst -> dst - - - - +// BIS src,dst src | dst -> dst - - - - +// XOR src,dst src ^ dst -> dst * * * * +// AND src,dst src & dst -> dst 0 * * * +// +//----------------------------------------------------------------------------- +// * the status bit is affected +// - the status bit is not affected +// 0 the status bit is cleared +// 1 the status bit is set +//----------------------------------------------------------------------------- + +// Invert source for substract and compare instructions. +wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]); +wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src; + + +// Mask the bit 8 for the Byte instructions for correct flags generation +wire op_bit8_msk = ~exec_cycle | ~inst_bw; +wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]}; +wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]}; + +// Clear the source operand (= jump offset) for conditional jumps +wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) | + (inst_jmp[`JGE] & (status[3]^status[2])) | + (inst_jmp[`JN] & ~status[2]) | + (inst_jmp[`JC] & ~status[0]) | + (inst_jmp[`JNC] & status[0]) | + (inst_jmp[`JEQ] & ~status[1]) | + (inst_jmp[`JNE] & status[1]); +wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}}; + +// Adder / AND / OR / XOR +wire [16:0] alu_add = op_src_in_jmp + op_dst_in; +wire [16:0] alu_and = op_src_in & op_dst_in; +wire [16:0] alu_or = op_src_in | op_dst_in; +wire [16:0] alu_xor = op_src_in ^ op_dst_in; + + +// Incrementer +wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) | + inst_alu[`ALU_INC]); +wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc}; + + + +// Decimal adder (DADD) +wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]); +wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]); +wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]); +wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]); +wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]}; + + +// Shifter for rotate instructions (RRC & RRA) +wire alu_shift_msb = inst_so[`RRC] ? status[0] : + inst_bw ? op_src[7] : op_src[15]; +wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8]; +wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]}; + + +// Swap bytes / Extend Sign +wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]}; +wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]}; + + +// Combine short paths toghether to simplify final ALU mux +wire alu_short_thro = ~(inst_alu[`ALU_AND] | + inst_alu[`ALU_OR] | + inst_alu[`ALU_XOR] | + inst_alu[`ALU_SHIFT] | + inst_so[`SWPB] | + inst_so[`SXT]); + +wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) | + ({16{inst_alu[`ALU_OR]}} & alu_or) | + ({16{inst_alu[`ALU_XOR]}} & alu_xor) | + ({16{inst_alu[`ALU_SHIFT]}} & alu_shift) | + ({16{inst_so[`SWPB]}} & alu_swpb) | + ({16{inst_so[`SXT]}} & alu_sxt) | + ({16{alu_short_thro}} & op_src_in); + + +// ALU output mux +wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st | + inst_alu[`ALU_ADD]) ? alu_add_inc : + inst_alu[`ALU_DADD] ? alu_dadd : alu_short; + +assign alu_out = alu_out_nxt[15:0]; +assign alu_out_add = alu_add[15:0]; + + +//----------------------------------------------------------------------------- +// STATUS FLAG GENERATION +//----------------------------------------------------------------------------- + +wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) : + (op_src_in[15] & op_dst_in[15]); + +wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) | + ( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) : + ((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) | + ( op_src_in[15] & op_dst_in[15] & ~alu_out[15])); + +wire N = inst_bw ? alu_out[7] : alu_out[15]; +wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0); +wire C = inst_bw ? alu_out[8] : alu_out_nxt[16]; + +assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} : + inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} : + inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C}; + +assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000; + + +endmodule // alu + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/alu.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/execution_unit.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/execution_unit.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/execution_unit.v (revision 29) @@ -0,0 +1,366 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: execution_unit.v +// +// *Module Description: +// openMSP430 Execution unit +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module execution_unit ( + +// OUTPUTs + cpuoff, // Turns off the CPU + dbg_reg_din, // Debug unit CPU register data input + gie, // General interrupt enable + mab, // Memory address bus + mb_en, // Memory bus enable + mb_wr, // Memory bus write transfer + mdb_out, // Memory data bus output + oscoff, // Turns off LFXT1 clock input + pc_sw, // Program counter software value + pc_sw_wr, // Program counter software write + scg1, // System clock generator 1. Turns off the SMCLK + +// INPUTs + dbg_halt_st, // Halt/Run status from CPU + dbg_mem_dout, // Debug unit data output + dbg_reg_wr, // Debug unit CPU register write + e_state, // Execution state + exec_done, // Execution completed + inst_ad, // Decoded Inst: destination addressing mode + inst_as, // Decoded Inst: source addressing mode + inst_alu, // ALU control signals + inst_bw, // Decoded Inst: byte width + inst_dest, // Decoded Inst: destination (one hot) + inst_dext, // Decoded Inst: destination extended instruction word + inst_irq_rst, // Decoded Inst: reset interrupt + inst_jmp, // Decoded Inst: Conditional jump + inst_sext, // Decoded Inst: source extended instruction word + inst_so, // Decoded Inst: Single-operand arithmetic + inst_src, // Decoded Inst: source (one hot) + inst_type, // Decoded Instruction type + mclk, // Main system clock + mdb_in, // Memory data bus input + pc, // Program counter + pc_nxt, // Next PC value (for CALL & IRQ) + puc // Main system reset +); + +// OUTPUTs +//========= +output cpuoff; // Turns off the CPU +output [15:0] dbg_reg_din; // Debug unit CPU register data input +output gie; // General interrupt enable +output [15:0] mab; // Memory address bus +output mb_en; // Memory bus enable +output [1:0] mb_wr; // Memory bus write transfer +output [15:0] mdb_out; // Memory data bus output +output oscoff; // Turns off LFXT1 clock input +output [15:0] pc_sw; // Program counter software value +output pc_sw_wr; // Program counter software write +output scg1; // System clock generator 1. Turns off the SMCLK + +// INPUTs +//========= +input dbg_halt_st; // Halt/Run status from CPU +input [15:0] dbg_mem_dout; // Debug unit data output +input dbg_reg_wr; // Debug unit CPU register write +input [3:0] e_state; // Execution state +input exec_done; // Execution completed +input [7:0] inst_ad; // Decoded Inst: destination addressing mode +input [7:0] inst_as; // Decoded Inst: source addressing mode +input [11:0] inst_alu; // ALU control signals +input inst_bw; // Decoded Inst: byte width +input [15:0] inst_dest; // Decoded Inst: destination (one hot) +input [15:0] inst_dext; // Decoded Inst: destination extended instruction word +input inst_irq_rst; // Decoded Inst: reset interrupt +input [7:0] inst_jmp; // Decoded Inst: Conditional jump +input [15:0] inst_sext; // Decoded Inst: source extended instruction word +input [7:0] inst_so; // Decoded Inst: Single-operand arithmetic +input [15:0] inst_src; // Decoded Inst: source (one hot) +input [2:0] inst_type; // Decoded Instruction type +input mclk; // Main system clock +input [15:0] mdb_in; // Memory data bus input +input [15:0] pc; // Program counter +input [15:0] pc_nxt; // Next PC value (for CALL & IRQ) +input puc; // Main system reset + + +//============================================================================= +// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION +//============================================================================= + +wire [15:0] alu_out; +wire [15:0] alu_out_add; +wire [3:0] alu_stat; +wire [3:0] alu_stat_wr; +wire [15:0] op_dst; +wire [15:0] op_src; +wire [15:0] reg_dest; +wire [15:0] reg_src; +wire [15:0] mdb_in_bw; +wire [15:0] mdb_in_val; +wire [3:0] status; + + +//============================================================================= +// 2) REGISTER FILE +//============================================================================= + +wire reg_dest_wr = ((e_state==`E_EXEC) & ( + (inst_type[`INST_TO] & inst_ad[`DIR] & ~inst_alu[`EXEC_NO_WR]) | + (inst_type[`INST_SO] & inst_as[`DIR] & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI])) | + inst_type[`INST_JMP])) | dbg_reg_wr; + +wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) | + ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])); + +wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI]; + +wire reg_sr_clr = (e_state==`E_IRQ_2); + +wire reg_pc_call = ((e_state==`E_EXEC) & inst_so[`CALL]) | + ((e_state==`E_DST_WR) & inst_so[`RETI]); + +wire reg_incr = (exec_done & inst_as[`INDIR_I]) | + ((e_state==`E_SRC_RD) & inst_so[`RETI]) | + ((e_state==`E_EXEC) & inst_so[`RETI]); + +assign dbg_reg_din = reg_dest; + + +register_file register_file_0 ( + +// OUTPUTs + .cpuoff (cpuoff), // Turns off the CPU + .gie (gie), // General interrupt enable + .oscoff (oscoff), // Turns off LFXT1 clock input + .pc_sw (pc_sw), // Program counter software value + .pc_sw_wr (pc_sw_wr), // Program counter software write + .reg_dest (reg_dest), // Selected register destination content + .reg_src (reg_src), // Selected register source content + .scg1 (scg1), // System clock generator 1. Turns off the SMCLK + .status (status), // R2 Status {V,N,Z,C} + +// INPUTs + .alu_stat (alu_stat), // ALU Status {V,N,Z,C} + .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} + .inst_bw (inst_bw), // Decoded Inst: byte width + .inst_dest (inst_dest), // Register destination selection + .inst_src (inst_src), // Register source selection + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .puc (puc), // Main system reset + .reg_dest_val (alu_out), // Selected register destination value + .reg_dest_wr (reg_dest_wr), // Write selected register destination + .reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction + .reg_sp_val (alu_out_add), // Stack Pointer next value + .reg_sp_wr (reg_sp_wr), // Stack Pointer write + .reg_sr_clr (reg_sr_clr), // Status register clear for interrupts + .reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction + .reg_incr (reg_incr) // Increment source register +); + + +//============================================================================= +// 3) SOURCE OPERAND MUXING +//============================================================================= +// inst_as[`DIR] : Register direct. -> Source is in register +// inst_as[`IDX] : Register indexed. -> Source is in memory, address is register+offset +// inst_as[`INDIR] : Register indirect. +// inst_as[`INDIR_I]: Register indirect autoincrement. +// inst_as[`SYMB] : Symbolic (operand is in memory at address PC+x). +// inst_as[`IMM] : Immediate (operand is next word in the instruction stream). +// inst_as[`ABS] : Absolute (operand is in memory at address x). +// inst_as[`CONST] : Constant. + +wire src_reg_src_sel = (e_state==`E_IRQ_0) | + (e_state==`E_IRQ_2) | + ((e_state==`E_SRC_RD) & ~inst_as[`ABS]) | + ((e_state==`E_SRC_WR) & ~inst_as[`ABS]) | + ((e_state==`E_EXEC) & inst_as[`DIR] & ~inst_type[`INST_JMP]); + +wire src_reg_dest_sel = (e_state==`E_IRQ_1) | + (e_state==`E_IRQ_3) | + ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])); + +wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) | + ((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] | + inst_as[`IDX] | inst_as[`SYMB] | + inst_as[`ABS])); + +wire src_inst_dext_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL])) | + ((e_state==`E_DST_WR) & ~(inst_so[`PUSH] | inst_so[`CALL] | + inst_so[`RETI])); + +wire src_inst_sext_sel = ((e_state==`E_EXEC) & (inst_type[`INST_JMP] | inst_as[`IMM] | + inst_as[`CONST] | inst_so[`RETI])); + + +assign op_src = src_reg_src_sel ? reg_src : + src_reg_dest_sel ? reg_dest : + src_mdb_in_val_sel ? mdb_in_val : + src_inst_dext_sel ? inst_dext : + src_inst_sext_sel ? inst_sext : 16'h0000; + + +//============================================================================= +// 4) DESTINATION OPERAND MUXING +//============================================================================= +// inst_ad[`DIR] : Register direct. +// inst_ad[`IDX] : Register indexed. +// inst_ad[`SYMB] : Symbolic (operand is in memory at address PC+x). +// inst_ad[`ABS] : Absolute (operand is in memory at address x). + + +wire dst_inst_sext_sel = ((e_state==`E_SRC_RD) & (inst_as[`IDX] | inst_as[`SYMB] | + inst_as[`ABS])) | + ((e_state==`E_SRC_WR) & (inst_as[`IDX] | inst_as[`SYMB] | + inst_as[`ABS])); + +wire dst_mdb_in_bw_sel = ((e_state==`E_DST_WR) & inst_so[`RETI]) | + ((e_state==`E_EXEC) & ~(inst_ad[`DIR] | inst_type[`INST_JMP] | + inst_type[`INST_SO]) & ~inst_so[`RETI]); + +wire dst_fffe_sel = (e_state==`E_IRQ_0) | + (e_state==`E_IRQ_1) | + (e_state==`E_IRQ_3) | + ((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]); + +wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) | + ((e_state==`E_DST_WR) & ~inst_ad[`ABS]) | + ((e_state==`E_EXEC) & (inst_ad[`DIR] | inst_type[`INST_JMP] | + inst_type[`INST_SO]) & ~inst_so[`RETI]); + + +assign op_dst = dbg_halt_st ? dbg_mem_dout : + dst_inst_sext_sel ? inst_sext : + dst_mdb_in_bw_sel ? mdb_in_bw : + dst_reg_dest_sel ? reg_dest : + dst_fffe_sel ? 16'hfffe : 16'h0000; + + +//============================================================================= +// 5) ALU +//============================================================================= + +wire exec_cycle = (e_state==`E_EXEC); + +alu alu_0 ( + +// OUTPUTs + .alu_out (alu_out), // ALU output value + .alu_out_add (alu_out_add), // ALU adder output value + .alu_stat (alu_stat), // ALU Status {V,N,Z,C} + .alu_stat_wr (alu_stat_wr), // ALU Status write {V,N,Z,C} + +// INPUTs + .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU + .exec_cycle (exec_cycle), // Instruction execution cycle + .inst_alu (inst_alu), // ALU control signals + .inst_bw (inst_bw), // Decoded Inst: byte width + .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump + .inst_so (inst_so), // Single-operand arithmetic + .op_dst (op_dst), // Destination operand + .op_src (op_src), // Source operand + .status (status) // R2 Status {V,N,Z,C} +); + + +//============================================================================= +// 6) MEMORY INTERFACE +//============================================================================= + +// Detect memory read/write access +assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | + ((e_state==`E_IRQ_3) & ~inst_irq_rst) | + ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | + (e_state==`E_SRC_WR) | + ((e_state==`E_EXEC) & inst_so[`RETI]) | + (e_state==`E_DST_RD) | + (e_state==`E_DST_WR); + +wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 : + ~inst_bw ? 2'b11 : + alu_out_add[0] ? 2'b10 : 2'b01; +assign mb_wr = ({2{(e_state==`E_IRQ_1)}} | + {2{(e_state==`E_IRQ_3)}} | + {2{(e_state==`E_DST_WR)}} | + {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk; + +// Memory address bus +assign mab = alu_out_add[15:0]; + +// Memory data bus output +reg [15:0] mdb_out_nxt; +always @(posedge mclk or posedge puc) + if (puc) mdb_out_nxt <= 16'h0000; + else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt; + else if ((e_state==`E_EXEC & ~inst_so[`CALL]) | + (e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out; + +assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt; + +// Format memory data bus input depending on BW +reg mab_lsb; +always @(posedge mclk or posedge puc) + if (puc) mab_lsb <= 1'b0; + else if (mb_en) mab_lsb <= alu_out_add[0]; + +assign mdb_in_bw = ~inst_bw ? mdb_in : + mab_lsb ? {2{mdb_in[15:8]}} : mdb_in; + +// Memory data bus input buffer (buffer after a source read) +reg mdb_in_buf_en; +always @(posedge mclk or posedge puc) + if (puc) mdb_in_buf_en <= 1'b0; + else mdb_in_buf_en <= (e_state==`E_SRC_RD); + +reg mdb_in_buf_valid; +always @(posedge mclk or posedge puc) + if (puc) mdb_in_buf_valid <= 1'b0; + else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0; + else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1; + +reg [15:0] mdb_in_buf; +always @(posedge mclk or posedge puc) + if (puc) mdb_in_buf <= 16'h0000; + else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw; + +assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw; + + +endmodule // execution_unit +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/execution_unit.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/mem_backbone.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/mem_backbone.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/mem_backbone.v (revision 29) @@ -0,0 +1,246 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: mem_backbone.v +// +// *Module Description: +// Memory interface backbone (decoder + arbiter) +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module mem_backbone ( + +// OUTPUTs + dbg_mem_din, // Debug unit Memory data input + eu_mdb_in, // Execution Unit Memory data bus input + fe_mdb_in, // Frontend Memory data bus input + fe_rom_wait, // Frontend wait for ROM + per_addr, // Peripheral address + per_din, // Peripheral data input + per_wen, // Peripheral write enable (high active) + per_en, // Peripheral enable (high active) + ram_addr, // RAM address + ram_cen, // RAM chip enable (low active) + ram_din, // RAM data input + ram_wen, // RAM write enable (low active) + rom_addr, // ROM address + rom_cen, // ROM chip enable (low active) + rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE-- + rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF-- + +// INPUTs + dbg_halt_st, // Halt/Run status from CPU + dbg_mem_addr, // Debug address for rd/wr access + dbg_mem_dout, // Debug unit data output + dbg_mem_en, // Debug unit memory enable + dbg_mem_wr, // Debug unit memory write + eu_mab, // Execution Unit Memory address bus + eu_mb_en, // Execution Unit Memory bus enable + eu_mb_wr, // Execution Unit Memory bus write transfer + eu_mdb_out, // Execution Unit Memory data bus output + fe_mab, // Frontend Memory address bus + fe_mb_en, // Frontend Memory bus enable + mclk, // Main system clock + per_dout, // Peripheral data output + puc, // Main system reset + ram_dout, // RAM data output + rom_dout // ROM data output +); + +// OUTPUTs +//========= +output [15:0] dbg_mem_din; // Debug unit Memory data input +output [15:0] eu_mdb_in; // Execution Unit Memory data bus input +output [15:0] fe_mdb_in; // Frontend Memory data bus input +output fe_rom_wait; // Frontend wait for ROM +output [7:0] per_addr; // Peripheral address +output [15:0] per_din; // Peripheral data input +output [1:0] per_wen; // Peripheral write enable (high active) +output per_en; // Peripheral enable (high active) +output [`RAM_MSB:0] ram_addr; // RAM address +output ram_cen; // RAM chip enable (low active) +output [15:0] ram_din; // RAM data input +output [1:0] ram_wen; // RAM write enable (low active) +output [`ROM_MSB:0] rom_addr; // ROM address +output rom_cen; // ROM chip enable (low active) +output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE-- +output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF-- + +// INPUTs +//========= +input dbg_halt_st; // Halt/Run status from CPU +input [15:0] dbg_mem_addr; // Debug address for rd/wr access +input [15:0] dbg_mem_dout; // Debug unit data output +input dbg_mem_en; // Debug unit memory enable +input [1:0] dbg_mem_wr; // Debug unit memory write +input [14:0] eu_mab; // Execution Unit Memory address bus +input eu_mb_en; // Execution Unit Memory bus enable +input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer +input [15:0] eu_mdb_out; // Execution Unit Memory data bus output +input [14:0] fe_mab; // Frontend Memory address bus +input fe_mb_en; // Frontend Memory bus enable +input mclk; // Main system clock +input [15:0] per_dout; // Peripheral data output +input puc; // Main system reset +input [15:0] ram_dout; // RAM data output +input [15:0] rom_dout; // ROM data output + + +//============================================================================= +// 1) DECODER +//============================================================================= + +// RAM Interface +//------------------ + +// Execution unit access +wire eu_ram_cen = ~(eu_mb_en & (eu_mab>=(`RAM_BASE>>1)) & + (eu_mab<((`RAM_BASE+`RAM_SIZE)>>1))); +wire [15:0] eu_ram_addr = eu_mab-(`RAM_BASE>>1); + +// Debug interface access +wire dbg_ram_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`RAM_BASE>>1)) & + (dbg_mem_addr[15:1]<((`RAM_BASE+`RAM_SIZE)>>1))); +wire [15:0] dbg_ram_addr = dbg_mem_addr[15:1]-(`RAM_BASE>>1); + + +// RAM Interface +wire [`RAM_MSB:0] ram_addr = ~dbg_ram_cen ? dbg_ram_addr[`RAM_MSB:0] : eu_ram_addr[`RAM_MSB:0]; +wire ram_cen = dbg_ram_cen & eu_ram_cen; +wire [1:0] ram_wen = ~(dbg_mem_wr | eu_mb_wr); +wire [15:0] ram_din = ~dbg_ram_cen ? dbg_mem_dout : eu_mdb_out; + + +// ROM Interface +//------------------ +parameter ROM_OFFSET = (16'hFFFF-`ROM_SIZE+1); + +// Execution unit access (only read access are accepted) +wire eu_rom_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(ROM_OFFSET>>1))); +wire [15:0] eu_rom_addr = eu_mab-(ROM_OFFSET>>1); + +// Front-end access +wire fe_rom_cen = ~(fe_mb_en & (fe_mab>=(ROM_OFFSET>>1))); +wire [15:0] fe_rom_addr = fe_mab-(ROM_OFFSET>>1); + +// Debug interface access +wire dbg_rom_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(ROM_OFFSET>>1))); +wire [15:0] dbg_rom_addr = dbg_mem_addr[15:1]-(ROM_OFFSET>>1); + + +// ROM Interface (Execution unit has priority) +wire [`ROM_MSB:0] rom_addr = ~dbg_rom_cen ? dbg_rom_addr[`ROM_MSB:0] : + ~eu_rom_cen ? eu_rom_addr[`ROM_MSB:0] : fe_rom_addr[`ROM_MSB:0]; +wire rom_cen = fe_rom_cen & eu_rom_cen & dbg_rom_cen; +wire [1:0] rom_wen_dbg = ~dbg_mem_wr; +wire [15:0] rom_din_dbg = dbg_mem_dout; + +wire fe_rom_wait = (~fe_rom_cen & ~eu_rom_cen); + + +// Peripherals +//-------------------- +wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00); +wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00); + +wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0]; +wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out; +wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr; +wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en; + +reg [15:0] per_dout_val; +always @ (posedge mclk or posedge puc) + if (puc) per_dout_val <= 16'h0000; + else per_dout_val <= per_dout; + + +// Frontend data Mux +//--------------------------------- +// Whenever the frontend doesn't access the ROM, backup the data + +// Detect whenever the data should be backuped and restored +reg fe_rom_cen_dly; +always @(posedge mclk or posedge puc) + if (puc) fe_rom_cen_dly <= 1'b0; + else fe_rom_cen_dly <= fe_rom_cen; + +wire fe_rom_save = ( fe_rom_cen & ~fe_rom_cen_dly) & ~dbg_halt_st; +wire fe_rom_restore = (~fe_rom_cen & fe_rom_cen_dly) | dbg_halt_st; + +reg [15:0] rom_dout_bckup; +always @(posedge mclk or posedge puc) + if (puc) rom_dout_bckup <= 16'h0000; + else if (fe_rom_save) rom_dout_bckup <= rom_dout; + +// Mux between the ROM data and the backup +reg rom_dout_bckup_sel; +always @(posedge mclk or posedge puc) + if (puc) rom_dout_bckup_sel <= 1'b0; + else if (fe_rom_save) rom_dout_bckup_sel <= 1'b1; + else if (fe_rom_restore) rom_dout_bckup_sel <= 1'b0; + +assign fe_mdb_in = rom_dout_bckup_sel ? rom_dout_bckup : rom_dout; + + +// Execution-Unit data Mux +//--------------------------------- + +// Select between peripherals, RAM and ROM +reg [1:0] eu_mdb_in_sel; +always @(posedge mclk or posedge puc) + if (puc) eu_mdb_in_sel <= 2'b00; + else eu_mdb_in_sel <= {~eu_rom_cen, per_en}; + +// Mux +assign eu_mdb_in = eu_mdb_in_sel[1] ? rom_dout : + eu_mdb_in_sel[0] ? per_dout_val : ram_dout; + +// Debug interface data Mux +//--------------------------------- + +// Select between peripherals, RAM and ROM +reg [1:0] dbg_mem_din_sel; +always @(posedge mclk or posedge puc) + if (puc) dbg_mem_din_sel <= 2'b00; + else dbg_mem_din_sel <= {~dbg_rom_cen, dbg_per_en}; + +// Mux +assign dbg_mem_din = dbg_mem_din_sel[1] ? rom_dout : + dbg_mem_din_sel[0] ? per_dout_val : ram_dout; + + +endmodule // mem_backbone + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/mem_backbone.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v (revision 29) @@ -0,0 +1,189 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: template_periph_8b.v +// +// *Module Description: +// 8 bit peripheral template. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module template_periph_8b ( + +// OUTPUTs + per_dout, // Peripheral data output + +// INPUTs + mclk, // Main system clock + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc // Main system reset +); + +// OUTPUTs +//========= +output [15:0] per_dout; // Peripheral data output + +// INPUTs +//========= +input mclk; // Main system clock +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter CNTRL1 = 9'h090; +parameter CNTRL2 = 9'h091; +parameter CNTRL3 = 9'h092; +parameter CNTRL4 = 9'h093; + + +// Register one-hot decoder +parameter CNTRL1_D = (256'h1 << (CNTRL1 /2)); +parameter CNTRL2_D = (256'h1 << (CNTRL2 /2)); +parameter CNTRL3_D = (256'h1 << (CNTRL3 /2)); +parameter CNTRL4_D = (256'h1 << (CNTRL4 /2)); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [255:0] reg_dec; +always @(per_addr) + case (per_addr) + (CNTRL1 /2): reg_dec = CNTRL1_D; + (CNTRL2 /2): reg_dec = CNTRL2_D; + (CNTRL3 /2): reg_dec = CNTRL3_D; + (CNTRL4 /2): reg_dec = CNTRL4_D; + default : reg_dec = {256{1'b0}}; + endcase + +// Read/Write probes +wire reg_lo_write = per_wen[0] & per_en; +wire reg_hi_write = per_wen[1] & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; +wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; +wire [255:0] reg_rd = reg_dec & {256{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// CNTRL1 Register +//----------------- +reg [7:0] cntrl1; + +wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1/2] : reg_lo_wr[CNTRL1/2]; +wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl1 <= 8'h00; + else if (cntrl1_wr) cntrl1 <= cntrl1_nxt; + + +// CNTRL2 Register +//----------------- +reg [7:0] cntrl2; + +wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2/2] : reg_lo_wr[CNTRL2/2]; +wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl2 <= 8'h00; + else if (cntrl2_wr) cntrl2 <= cntrl2_nxt; + + +// CNTRL3 Register +//----------------- +reg [7:0] cntrl3; + +wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3/2] : reg_lo_wr[CNTRL3/2]; +wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl3 <= 8'h00; + else if (cntrl3_wr) cntrl3 <= cntrl3_nxt; + + +// CNTRL4 Register +//----------------- +reg [7:0] cntrl4; + +wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4/2] : reg_lo_wr[CNTRL4/2]; +wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl4 <= 8'h00; + else if (cntrl4_wr) cntrl4 <= cntrl4_nxt; + + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] cntrl1_rd = (cntrl1 & {8{reg_rd[CNTRL1/2]}}) << (8 & {4{CNTRL1[0]}}); +wire [15:0] cntrl2_rd = (cntrl2 & {8{reg_rd[CNTRL2/2]}}) << (8 & {4{CNTRL2[0]}}); +wire [15:0] cntrl3_rd = (cntrl3 & {8{reg_rd[CNTRL3/2]}}) << (8 & {4{CNTRL3[0]}}); +wire [15:0] cntrl4_rd = (cntrl4 & {8{reg_rd[CNTRL4/2]}}) << (8 & {4{CNTRL4[0]}}); + +wire [15:0] per_dout = cntrl1_rd | + cntrl2_rd | + cntrl3_rd | + cntrl4_rd; + + +endmodule // template_periph_8b + + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/gpio.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/gpio.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/gpio.v (revision 29) @@ -0,0 +1,778 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: gpio.v +// +// *Module Description: +// Digital I/O interface +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module gpio ( + +// OUTPUTs + irq_port1, // Port 1 interrupt + irq_port2, // Port 2 interrupt + p1_dout, // Port 1 data output + p1_dout_en, // Port 1 data output enable + p1_sel, // Port 1 function select + p2_dout, // Port 2 data output + p2_dout_en, // Port 2 data output enable + p2_sel, // Port 2 function select + p3_dout, // Port 3 data output + p3_dout_en, // Port 3 data output enable + p3_sel, // Port 3 function select + p4_dout, // Port 4 data output + p4_dout_en, // Port 4 data output enable + p4_sel, // Port 4 function select + p5_dout, // Port 5 data output + p5_dout_en, // Port 5 data output enable + p5_sel, // Port 5 function select + p6_dout, // Port 6 data output + p6_dout_en, // Port 6 data output enable + p6_sel, // Port 6 function select + per_dout, // Peripheral data output + +// INPUTs + mclk, // Main system clock + p1_din, // Port 1 data input + p2_din, // Port 2 data input + p3_din, // Port 3 data input + p4_din, // Port 4 data input + p5_din, // Port 5 data input + p6_din, // Port 6 data input + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc // Main system reset +); + +// PARAMETERs +//============ +parameter P1_EN = 1'b1; // Enable Port 1 +parameter P2_EN = 1'b1; // Enable Port 2 +parameter P3_EN = 1'b0; // Enable Port 3 +parameter P4_EN = 1'b0; // Enable Port 4 +parameter P5_EN = 1'b0; // Enable Port 5 +parameter P6_EN = 1'b0; // Enable Port 6 + + +// OUTPUTs +//========= +output irq_port1; // Port 1 interrupt +output irq_port2; // Port 2 interrupt +output [7:0] p1_dout; // Port 1 data output +output [7:0] p1_dout_en; // Port 1 data output enable +output [7:0] p1_sel; // Port 1 function select +output [7:0] p2_dout; // Port 2 data output +output [7:0] p2_dout_en; // Port 2 data output enable +output [7:0] p2_sel; // Port 2 function select +output [7:0] p3_dout; // Port 3 data output +output [7:0] p3_dout_en; // Port 3 data output enable +output [7:0] p3_sel; // Port 3 function select +output [7:0] p4_dout; // Port 4 data output +output [7:0] p4_dout_en; // Port 4 data output enable +output [7:0] p4_sel; // Port 4 function select +output [7:0] p5_dout; // Port 5 data output +output [7:0] p5_dout_en; // Port 5 data output enable +output [7:0] p5_sel; // Port 5 function select +output [7:0] p6_dout; // Port 6 data output +output [7:0] p6_dout_en; // Port 6 data output enable +output [7:0] p6_sel; // Port 6 function select +output [15:0] per_dout; // Peripheral data output + +// INPUTs +//========= +input mclk; // Main system clock +input [7:0] p1_din; // Port 1 data input +input [7:0] p2_din; // Port 2 data input +input [7:0] p3_din; // Port 3 data input +input [7:0] p4_din; // Port 4 data input +input [7:0] p5_din; // Port 5 data input +input [7:0] p6_din; // Port 6 data input +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Masks +parameter P1_EN_MSK = {8{P1_EN[0]}}; +parameter P2_EN_MSK = {8{P2_EN[0]}}; +parameter P3_EN_MSK = {8{P3_EN[0]}}; +parameter P4_EN_MSK = {8{P4_EN[0]}}; +parameter P5_EN_MSK = {8{P5_EN[0]}}; +parameter P6_EN_MSK = {8{P6_EN[0]}}; + +// Register addresses +parameter P1IN = 9'h020; // Port 1 +parameter P1OUT = 9'h021; +parameter P1DIR = 9'h022; +parameter P1IFG = 9'h023; +parameter P1IES = 9'h024; +parameter P1IE = 9'h025; +parameter P1SEL = 9'h026; +parameter P2IN = 9'h028; // Port 2 +parameter P2OUT = 9'h029; +parameter P2DIR = 9'h02A; +parameter P2IFG = 9'h02B; +parameter P2IES = 9'h02C; +parameter P2IE = 9'h02D; +parameter P2SEL = 9'h02E; +parameter P3IN = 9'h018; // Port 3 +parameter P3OUT = 9'h019; +parameter P3DIR = 9'h01A; +parameter P3SEL = 9'h01B; +parameter P4IN = 9'h01C; // Port 4 +parameter P4OUT = 9'h01D; +parameter P4DIR = 9'h01E; +parameter P4SEL = 9'h01F; +parameter P5IN = 9'h030; // Port 5 +parameter P5OUT = 9'h031; +parameter P5DIR = 9'h032; +parameter P5SEL = 9'h033; +parameter P6IN = 9'h034; // Port 6 +parameter P6OUT = 9'h035; +parameter P6DIR = 9'h036; +parameter P6SEL = 9'h037; + + +// Register one-hot decoder +parameter P1IN_D = (256'h1 << (P1IN /2)); // Port 1 +parameter P1OUT_D = (256'h1 << (P1OUT /2)); +parameter P1DIR_D = (256'h1 << (P1DIR /2)); +parameter P1IFG_D = (256'h1 << (P1IFG /2)); +parameter P1IES_D = (256'h1 << (P1IES /2)); +parameter P1IE_D = (256'h1 << (P1IE /2)); +parameter P1SEL_D = (256'h1 << (P1SEL /2)); +parameter P2IN_D = (256'h1 << (P2IN /2)); // Port 2 +parameter P2OUT_D = (256'h1 << (P2OUT /2)); +parameter P2DIR_D = (256'h1 << (P2DIR /2)); +parameter P2IFG_D = (256'h1 << (P2IFG /2)); +parameter P2IES_D = (256'h1 << (P2IES /2)); +parameter P2IE_D = (256'h1 << (P2IE /2)); +parameter P2SEL_D = (256'h1 << (P2SEL /2)); +parameter P3IN_D = (256'h1 << (P3IN /2)); // Port 3 +parameter P3OUT_D = (256'h1 << (P3OUT /2)); +parameter P3DIR_D = (256'h1 << (P3DIR /2)); +parameter P3SEL_D = (256'h1 << (P3SEL /2)); +parameter P4IN_D = (256'h1 << (P4IN /2)); // Port 4 +parameter P4OUT_D = (256'h1 << (P4OUT /2)); +parameter P4DIR_D = (256'h1 << (P4DIR /2)); +parameter P4SEL_D = (256'h1 << (P4SEL /2)); +parameter P5IN_D = (256'h1 << (P5IN /2)); // Port 5 +parameter P5OUT_D = (256'h1 << (P5OUT /2)); +parameter P5DIR_D = (256'h1 << (P5DIR /2)); +parameter P5SEL_D = (256'h1 << (P5SEL /2)); +parameter P6IN_D = (256'h1 << (P6IN /2)); // Port 6 +parameter P6OUT_D = (256'h1 << (P6OUT /2)); +parameter P6DIR_D = (256'h1 << (P6DIR /2)); +parameter P6SEL_D = (256'h1 << (P6SEL /2)); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [255:0] reg_dec; +always @(per_addr) + case (per_addr) + (P1IN /2): reg_dec = P1IN_D & {256{P1_EN[0]}}; + (P1OUT /2): reg_dec = P1OUT_D & {256{P1_EN[0]}}; + (P1DIR /2): reg_dec = P1DIR_D & {256{P1_EN[0]}}; + (P1IFG /2): reg_dec = P1IFG_D & {256{P1_EN[0]}}; + (P1IES /2): reg_dec = P1IES_D & {256{P1_EN[0]}}; + (P1IE /2): reg_dec = P1IE_D & {256{P1_EN[0]}}; + (P1SEL /2): reg_dec = P1SEL_D & {256{P1_EN[0]}}; + (P2IN /2): reg_dec = P2IN_D & {256{P2_EN[0]}}; + (P2OUT /2): reg_dec = P2OUT_D & {256{P2_EN[0]}}; + (P2DIR /2): reg_dec = P2DIR_D & {256{P2_EN[0]}}; + (P2IFG /2): reg_dec = P2IFG_D & {256{P2_EN[0]}}; + (P2IES /2): reg_dec = P2IES_D & {256{P2_EN[0]}}; + (P2IE /2): reg_dec = P2IE_D & {256{P2_EN[0]}}; + (P2SEL /2): reg_dec = P2SEL_D & {256{P2_EN[0]}}; + (P3IN /2): reg_dec = P3IN_D & {256{P3_EN[0]}}; + (P3OUT /2): reg_dec = P3OUT_D & {256{P3_EN[0]}}; + (P3DIR /2): reg_dec = P3DIR_D & {256{P3_EN[0]}}; + (P3SEL /2): reg_dec = P3SEL_D & {256{P3_EN[0]}}; + (P4IN /2): reg_dec = P4IN_D & {256{P4_EN[0]}}; + (P4OUT /2): reg_dec = P4OUT_D & {256{P4_EN[0]}}; + (P4DIR /2): reg_dec = P4DIR_D & {256{P4_EN[0]}}; + (P4SEL /2): reg_dec = P4SEL_D & {256{P4_EN[0]}}; + (P5IN /2): reg_dec = P5IN_D & {256{P5_EN[0]}}; + (P5OUT /2): reg_dec = P5OUT_D & {256{P5_EN[0]}}; + (P5DIR /2): reg_dec = P5DIR_D & {256{P5_EN[0]}}; + (P5SEL /2): reg_dec = P5SEL_D & {256{P5_EN[0]}}; + (P6IN /2): reg_dec = P6IN_D & {256{P6_EN[0]}}; + (P6OUT /2): reg_dec = P6OUT_D & {256{P6_EN[0]}}; + (P6DIR /2): reg_dec = P6DIR_D & {256{P6_EN[0]}}; + (P6SEL /2): reg_dec = P6SEL_D & {256{P6_EN[0]}}; + default : reg_dec = {256{1'b0}}; + endcase + +// Read/Write probes +wire reg_lo_write = per_wen[0] & per_en; +wire reg_hi_write = per_wen[1] & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; +wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; +wire [255:0] reg_rd = reg_dec & {256{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// P1IN Register +//--------------- +reg [7:0] p1in; + +always @ (posedge mclk or posedge puc) + if (puc) p1in <= 8'h00; + else p1in <= p1_din & P1_EN_MSK; + + +// P1OUT Register +//---------------- +reg [7:0] p1out; + +wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT/2] : reg_lo_wr[P1OUT/2]; +wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p1out <= 8'h00; + else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK; + +assign p1_dout = p1out; + + +// P1DIR Register +//---------------- +reg [7:0] p1dir; + +wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR/2] : reg_lo_wr[P1DIR/2]; +wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p1dir <= 8'h00; + else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK; + +assign p1_dout_en = p1dir; + + +// P1IFG Register +//---------------- +reg [7:0] p1ifg; + +wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG/2] : reg_lo_wr[P1IFG/2]; +wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0]; +wire [7:0] p1ifg_set; + +always @ (posedge mclk or posedge puc) + if (puc) p1ifg <= 8'h00; + else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK; + else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK; + +// P1IES Register +//---------------- +reg [7:0] p1ies; + +wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES/2] : reg_lo_wr[P1IES/2]; +wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p1ies <= 8'h00; + else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK; + + +// P1IE Register +//---------------- +reg [7:0] p1ie; + +wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE/2] : reg_lo_wr[P1IE/2]; +wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p1ie <= 8'h00; + else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK; + + +// P1SEL Register +//---------------- +reg [7:0] p1sel; + +wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL/2] : reg_lo_wr[P1SEL/2]; +wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p1sel <= 8'h00; + else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK; + +assign p1_sel = p1sel; + + +// P2IN Register +//--------------- +reg [7:0] p2in; + +always @ (posedge mclk or posedge puc) + if (puc) p2in <= 8'h00; + else p2in <= p2_din & P2_EN_MSK; + + +// P2OUT Register +//---------------- +reg [7:0] p2out; + +wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT/2] : reg_lo_wr[P2OUT/2]; +wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p2out <= 8'h00; + else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK; + +assign p2_dout = p2out; + + +// P2DIR Register +//---------------- +reg [7:0] p2dir; + +wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR/2] : reg_lo_wr[P2DIR/2]; +wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p2dir <= 8'h00; + else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK; + +assign p2_dout_en = p2dir; + + +// P2IFG Register +//---------------- +reg [7:0] p2ifg; + +wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG/2] : reg_lo_wr[P2IFG/2]; +wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0]; +wire [7:0] p2ifg_set; + +always @ (posedge mclk or posedge puc) + if (puc) p2ifg <= 8'h00; + else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK; + else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK; + + +// P2IES Register +//---------------- +reg [7:0] p2ies; + +wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES/2] : reg_lo_wr[P2IES/2]; +wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p2ies <= 8'h00; + else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK; + + +// P2IE Register +//---------------- +reg [7:0] p2ie; + +wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE/2] : reg_lo_wr[P2IE/2]; +wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p2ie <= 8'h00; + else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK; + + +// P2SEL Register +//---------------- +reg [7:0] p2sel; + +wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL/2] : reg_lo_wr[P2SEL/2]; +wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p2sel <= 8'h00; + else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK; + +assign p2_sel = p2sel; + + +// P3IN Register +//--------------- +reg [7:0] p3in; + +always @ (posedge mclk or posedge puc) + if (puc) p3in <= 8'h00; + else p3in <= p3_din & P3_EN_MSK; + + +// P3OUT Register +//---------------- +reg [7:0] p3out; + +wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT/2] : reg_lo_wr[P3OUT/2]; +wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p3out <= 8'h00; + else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK; + +assign p3_dout = p3out; + + +// P3DIR Register +//---------------- +reg [7:0] p3dir; + +wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR/2] : reg_lo_wr[P3DIR/2]; +wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p3dir <= 8'h00; + else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK; + +assign p3_dout_en = p3dir; + + +// P3SEL Register +//---------------- +reg [7:0] p3sel; + +wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL/2] : reg_lo_wr[P3SEL/2]; +wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p3sel <= 8'h00; + else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK; + +assign p3_sel = p3sel; + + +// P4IN Register +//--------------- +reg [7:0] p4in; + +always @ (posedge mclk or posedge puc) + if (puc) p4in <= 8'h00; + else p4in <= p4_din & P4_EN_MSK; + + +// P4OUT Register +//---------------- +reg [7:0] p4out; + +wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT/2] : reg_lo_wr[P4OUT/2]; +wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p4out <= 8'h00; + else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK; + +assign p4_dout = p4out; + + +// P4DIR Register +//---------------- +reg [7:0] p4dir; + +wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR/2] : reg_lo_wr[P4DIR/2]; +wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p4dir <= 8'h00; + else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK; + +assign p4_dout_en = p4dir; + + +// P4SEL Register +//---------------- +reg [7:0] p4sel; + +wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL/2] : reg_lo_wr[P4SEL/2]; +wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p4sel <= 8'h00; + else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK; + +assign p4_sel = p4sel; + + +// P5IN Register +//--------------- +reg [7:0] p5in; + +always @ (posedge mclk or posedge puc) + if (puc) p5in <= 8'h00; + else p5in <= p5_din & P5_EN_MSK; + + +// P5OUT Register +//---------------- +reg [7:0] p5out; + +wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT/2] : reg_lo_wr[P5OUT/2]; +wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p5out <= 8'h00; + else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK; + +assign p5_dout = p5out; + + +// P5DIR Register +//---------------- +reg [7:0] p5dir; + +wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR/2] : reg_lo_wr[P5DIR/2]; +wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p5dir <= 8'h00; + else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK; + +assign p5_dout_en = p5dir; + + +// P5SEL Register +//---------------- +reg [7:0] p5sel; + +wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL/2] : reg_lo_wr[P5SEL/2]; +wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p5sel <= 8'h00; + else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK; + +assign p5_sel = p5sel; + + +// P6IN Register +//--------------- +reg [7:0] p6in; + +always @ (posedge mclk or posedge puc) + if (puc) p6in <= 8'h00; + else p6in <= p6_din & P6_EN_MSK; + + +// P6OUT Register +//---------------- +reg [7:0] p6out; + +wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT/2] : reg_lo_wr[P6OUT/2]; +wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p6out <= 8'h00; + else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK; + +assign p6_dout = p6out; + + +// P6DIR Register +//---------------- +reg [7:0] p6dir; + +wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR/2] : reg_lo_wr[P6DIR/2]; +wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p6dir <= 8'h00; + else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK; + +assign p6_dout_en = p6dir; + + +// P6SEL Register +//---------------- +reg [7:0] p6sel; + +wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL/2] : reg_lo_wr[P6SEL/2]; +wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) p6sel <= 8'h00; + else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK; + +assign p6_sel = p6sel; + + + +//============================================================================ +// 4) INTERRUPT GENERATION +//============================================================================ + +// Port 1 interrupt +//------------------ + +// Delay input +reg [7:0] p1in_dly; +always @ (posedge mclk or posedge puc) + if (puc) p1in_dly <= 8'h00; + else p1in_dly <= p1in & P1_EN_MSK; + +// Edge detection +wire [7:0] p1in_re = p1in & ~p1in_dly; +wire [7:0] p1in_fe = ~p1in & p1in_dly; + +// Set interrupt flag +assign p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7], + p1ies[6] ? p1in_fe[6] : p1in_re[6], + p1ies[5] ? p1in_fe[5] : p1in_re[5], + p1ies[4] ? p1in_fe[4] : p1in_re[4], + p1ies[3] ? p1in_fe[3] : p1in_re[3], + p1ies[2] ? p1in_fe[2] : p1in_re[2], + p1ies[1] ? p1in_fe[1] : p1in_re[1], + p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK; + +// Generate CPU interrupt +assign irq_port1 = |(p1ie & p1ifg) & P1_EN[0]; + + +// Port 1 interrupt +//------------------ + +// Delay input +reg [7:0] p2in_dly; +always @ (posedge mclk or posedge puc) + if (puc) p2in_dly <= 8'h00; + else p2in_dly <= p2in & P2_EN_MSK; + +// Edge detection +wire [7:0] p2in_re = p2in & ~p2in_dly; +wire [7:0] p2in_fe = ~p2in & p2in_dly; + +// Set interrupt flag +assign p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7], + p2ies[6] ? p2in_fe[6] : p2in_re[6], + p2ies[5] ? p2in_fe[5] : p2in_re[5], + p2ies[4] ? p2in_fe[4] : p2in_re[4], + p2ies[3] ? p2in_fe[3] : p2in_re[3], + p2ies[2] ? p2in_fe[2] : p2in_re[2], + p2ies[1] ? p2in_fe[1] : p2in_re[1], + p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK; + +// Generate CPU interrupt +assign irq_port2 = |(p2ie & p2ifg) & P2_EN[0]; + + +//============================================================================ +// 5) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] p1in_rd = (p1in & {8{reg_rd[P1IN/2]}}) << (8 & {4{P1IN[0]}}); +wire [15:0] p1out_rd = (p1out & {8{reg_rd[P1OUT/2]}}) << (8 & {4{P1OUT[0]}}); +wire [15:0] p1dir_rd = (p1dir & {8{reg_rd[P1DIR/2]}}) << (8 & {4{P1DIR[0]}}); +wire [15:0] p1ifg_rd = (p1ifg & {8{reg_rd[P1IFG/2]}}) << (8 & {4{P1IFG[0]}}); +wire [15:0] p1ies_rd = (p1ies & {8{reg_rd[P1IES/2]}}) << (8 & {4{P1IES[0]}}); +wire [15:0] p1ie_rd = (p1ie & {8{reg_rd[P1IE/2]}}) << (8 & {4{P1IE[0]}}); +wire [15:0] p1sel_rd = (p1sel & {8{reg_rd[P1SEL/2]}}) << (8 & {4{P1SEL[0]}}); +wire [15:0] p2in_rd = (p2in & {8{reg_rd[P2IN/2]}}) << (8 & {4{P2IN[0]}}); +wire [15:0] p2out_rd = (p2out & {8{reg_rd[P2OUT/2]}}) << (8 & {4{P2OUT[0]}}); +wire [15:0] p2dir_rd = (p2dir & {8{reg_rd[P2DIR/2]}}) << (8 & {4{P2DIR[0]}}); +wire [15:0] p2ifg_rd = (p2ifg & {8{reg_rd[P2IFG/2]}}) << (8 & {4{P2IFG[0]}}); +wire [15:0] p2ies_rd = (p2ies & {8{reg_rd[P2IES/2]}}) << (8 & {4{P2IES[0]}}); +wire [15:0] p2ie_rd = (p2ie & {8{reg_rd[P2IE/2]}}) << (8 & {4{P2IE[0]}}); +wire [15:0] p2sel_rd = (p2sel & {8{reg_rd[P2SEL/2]}}) << (8 & {4{P2SEL[0]}}); +wire [15:0] p3in_rd = (p3in & {8{reg_rd[P3IN/2]}}) << (8 & {4{P3IN[0]}}); +wire [15:0] p3out_rd = (p3out & {8{reg_rd[P3OUT/2]}}) << (8 & {4{P3OUT[0]}}); +wire [15:0] p3dir_rd = (p3dir & {8{reg_rd[P3DIR/2]}}) << (8 & {4{P3DIR[0]}}); +wire [15:0] p3sel_rd = (p3sel & {8{reg_rd[P3SEL/2]}}) << (8 & {4{P3SEL[0]}}); +wire [15:0] p4in_rd = (p4in & {8{reg_rd[P4IN/2]}}) << (8 & {4{P4IN[0]}}); +wire [15:0] p4out_rd = (p4out & {8{reg_rd[P4OUT/2]}}) << (8 & {4{P4OUT[0]}}); +wire [15:0] p4dir_rd = (p4dir & {8{reg_rd[P4DIR/2]}}) << (8 & {4{P4DIR[0]}}); +wire [15:0] p4sel_rd = (p4sel & {8{reg_rd[P4SEL/2]}}) << (8 & {4{P4SEL[0]}}); +wire [15:0] p5in_rd = (p5in & {8{reg_rd[P5IN/2]}}) << (8 & {4{P5IN[0]}}); +wire [15:0] p5out_rd = (p5out & {8{reg_rd[P5OUT/2]}}) << (8 & {4{P5OUT[0]}}); +wire [15:0] p5dir_rd = (p5dir & {8{reg_rd[P5DIR/2]}}) << (8 & {4{P5DIR[0]}}); +wire [15:0] p5sel_rd = (p5sel & {8{reg_rd[P5SEL/2]}}) << (8 & {4{P5SEL[0]}}); +wire [15:0] p6in_rd = (p6in & {8{reg_rd[P6IN/2]}}) << (8 & {4{P6IN[0]}}); +wire [15:0] p6out_rd = (p6out & {8{reg_rd[P6OUT/2]}}) << (8 & {4{P6OUT[0]}}); +wire [15:0] p6dir_rd = (p6dir & {8{reg_rd[P6DIR/2]}}) << (8 & {4{P6DIR[0]}}); +wire [15:0] p6sel_rd = (p6sel & {8{reg_rd[P6SEL/2]}}) << (8 & {4{P6SEL[0]}}); + +wire [15:0] per_dout = p1in_rd | + p1out_rd | + p1dir_rd | + p1ifg_rd | + p1ies_rd | + p1ie_rd | + p1sel_rd | + p2in_rd | + p2out_rd | + p2dir_rd | + p2ifg_rd | + p2ies_rd | + p2ie_rd | + p2sel_rd | + p3in_rd | + p3out_rd | + p3dir_rd | + p3sel_rd | + p4in_rd | + p4out_rd | + p4dir_rd | + p4sel_rd | + p5in_rd | + p5out_rd | + p5dir_rd | + p5sel_rd | + p6in_rd | + p6out_rd | + p6dir_rd | + p6sel_rd; + +endmodule // gpio + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/gpio.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/timerA.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/timerA.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/timerA.v (revision 29) @@ -0,0 +1,694 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: timerA.v +// +// *Module Description: +// Timer A top-level +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module timerA ( + +// OUTPUTs + irq_ta0, // Timer A interrupt: TACCR0 + irq_ta1, // Timer A interrupt: TAIV, TACCR1, TACCR2 + per_dout, // Peripheral data output + ta_out0, // Timer A output 0 + ta_out0_en, // Timer A output 0 enable + ta_out1, // Timer A output 1 + ta_out1_en, // Timer A output 1 enable + ta_out2, // Timer A output 2 + ta_out2_en, // Timer A output 2 enable + +// INPUTs + aclk_en, // ACLK enable (from CPU) + dbg_freeze, // Freeze Timer A counter + inclk, // INCLK external timer clock (SLOW) + irq_ta0_acc, // Interrupt request TACCR0 accepted + mclk, // Main system clock + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc, // Main system reset + smclk_en, // SMCLK enable (from CPU) + ta_cci0a, // Timer A capture 0 input A + ta_cci0b, // Timer A capture 0 input B + ta_cci1a, // Timer A capture 1 input A + ta_cci1b, // Timer A capture 1 input B + ta_cci2a, // Timer A capture 2 input A + ta_cci2b, // Timer A capture 2 input B + taclk // TACLK external timer clock (SLOW) +); + +// OUTPUTs +//========= +output irq_ta0; // Timer A interrupt: TACCR0 +output irq_ta1; // Timer A interrupt: TAIV, TACCR1, TACCR2 +output [15:0] per_dout; // Peripheral data output +output ta_out0; // Timer A output 0 +output ta_out0_en; // Timer A output 0 enable +output ta_out1; // Timer A output 1 +output ta_out1_en; // Timer A output 1 enable +output ta_out2; // Timer A output 2 +output ta_out2_en; // Timer A output 2 enable + +// INPUTs +//========= +input aclk_en; // ACLK enable (from CPU) +input dbg_freeze; // Freeze Timer A counter +input inclk; // INCLK external timer clock (SLOW) +input irq_ta0_acc; // Interrupt request TACCR0 accepted +input mclk; // Main system clock +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset +input smclk_en; // SMCLK enable (from CPU) +input ta_cci0a; // Timer A capture 0 input A +input ta_cci0b; // Timer A capture 0 input B +input ta_cci1a; // Timer A capture 1 input A +input ta_cci1b; // Timer A capture 1 input B +input ta_cci2a; // Timer A capture 2 input A +input ta_cci2b; // Timer A capture 2 input B +input taclk; // TACLK external timer clock (SLOW) + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter TACTL = 9'h160; +parameter TAR = 9'h170; +parameter TACCTL0 = 9'h162; +parameter TACCR0 = 9'h172; +parameter TACCTL1 = 9'h164; +parameter TACCR1 = 9'h174; +parameter TACCTL2 = 9'h166; +parameter TACCR2 = 9'h176; +parameter TAIV = 9'h12E; + + +// Register one-hot decoder +parameter TACTL_D = (512'h1 << TACTL); +parameter TAR_D = (512'h1 << TAR); +parameter TACCTL0_D = (512'h1 << TACCTL0); +parameter TACCR0_D = (512'h1 << TACCR0); +parameter TACCTL1_D = (512'h1 << TACCTL1); +parameter TACCR1_D = (512'h1 << TACCR1); +parameter TACCTL2_D = (512'h1 << TACCTL2); +parameter TACCR2_D = (512'h1 << TACCR2); +parameter TAIV_D = (512'h1 << TAIV); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [511:0] reg_dec; +always @(per_addr) + case ({per_addr,1'b0}) + TACTL : reg_dec = TACTL_D; + TAR : reg_dec = TAR_D; + TACCTL0: reg_dec = TACCTL0_D; + TACCR0 : reg_dec = TACCR0_D; + TACCTL1: reg_dec = TACCTL1_D; + TACCR1 : reg_dec = TACCR1_D; + TACCTL2: reg_dec = TACCTL2_D; + TACCR2 : reg_dec = TACCR2_D; + TAIV : reg_dec = TAIV_D; + default: reg_dec = {512{1'b0}}; + endcase + +// Read/Write probes +wire reg_write = |per_wen & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [511:0] reg_wr = reg_dec & {512{reg_write}}; +wire [511:0] reg_rd = reg_dec & {512{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// TACTL Register +//----------------- +reg [9:0] tactl; + +wire tactl_wr = reg_wr[TACTL]; +wire taclr = tactl_wr & per_din[`TACLR]; +wire taifg_set; +wire taifg_clr; + +always @ (posedge mclk or posedge puc) + if (puc) tactl <= 10'h000; + else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; + else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr}; + + +// TAR Register +//----------------- +reg [15:0] tar; + +wire tar_wr = reg_wr[TAR]; + +wire tar_clk; +wire tar_clr; +wire tar_inc; +wire tar_dec; +wire [15:0] tar_add = tar_inc ? 16'h0001 : + tar_dec ? 16'hffff : 16'h0000; +wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add); + +always @ (posedge mclk or posedge puc) + if (puc) tar <= 16'h0000; + else if (tar_wr) tar <= per_din; + else if (taclr) tar <= 16'h0000; + else if (tar_clk & ~dbg_freeze) tar <= tar_nxt; + + +// TACCTL0 Register +//------------------ +reg [15:0] tacctl0; + +wire tacctl0_wr = reg_wr[TACCTL0]; +wire ccifg0_set; +wire cov0_set; + +always @ (posedge mclk or posedge puc) + if (puc) tacctl0 <= 16'h0000; + else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; + else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc}; + +wire cci0; +reg scci0; +wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0}; + + +// TACCR0 Register +//------------------ +reg [15:0] taccr0; + +wire taccr0_wr = reg_wr[TACCR0]; +wire cci0_cap; + +always @ (posedge mclk or posedge puc) + if (puc) taccr0 <= 16'h0000; + else if (taccr0_wr) taccr0 <= per_din; + else if (cci0_cap) taccr0 <= tar; + + +// TACCTL1 Register +//------------------ +reg [15:0] tacctl1; + +wire tacctl1_wr = reg_wr[TACCTL1]; +wire ccifg1_set; +wire ccifg1_clr; +wire cov1_set; + +always @ (posedge mclk or posedge puc) + if (puc) tacctl1 <= 16'h0000; + else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; + else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr}; + +wire cci1; +reg scci1; +wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0}; + + +// TACCR1 Register +//------------------ +reg [15:0] taccr1; + +wire taccr1_wr = reg_wr[TACCR1]; +wire cci1_cap; + +always @ (posedge mclk or posedge puc) + if (puc) taccr1 <= 16'h0000; + else if (taccr1_wr) taccr1 <= per_din; + else if (cci1_cap) taccr1 <= tar; + + +// TACCTL2 Register +//------------------ +reg [15:0] tacctl2; + +wire tacctl2_wr = reg_wr[TACCTL2]; +wire ccifg2_set; +wire ccifg2_clr; +wire cov2_set; + +always @ (posedge mclk or posedge puc) + if (puc) tacctl2 <= 16'h0000; + else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; + else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr}; + +wire cci2; +reg scci2; +wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0}; + + +// TACCR2 Register +//------------------ +reg [15:0] taccr2; + +wire taccr2_wr = reg_wr[TACCR2]; +wire cci2_cap; + +always @ (posedge mclk or posedge puc) + if (puc) taccr2 <= 16'h0000; + else if (taccr2_wr) taccr2 <= per_din; + else if (cci2_cap) taccr2 <= tar; + + +// TAIV Register +//------------------ + +wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 : + (tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 : + (tactl[`TAIFG] & tactl[`TAIE]) ? 4'hA : + 4'h0; + +assign ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2); +assign ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4); +assign taifg_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA); + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] tactl_rd = {6'h00, tactl} & {16{reg_rd[TACTL]}}; +wire [15:0] tar_rd = tar & {16{reg_rd[TAR]}}; +wire [15:0] tacctl0_rd = tacctl0_full & {16{reg_rd[TACCTL0]}}; +wire [15:0] taccr0_rd = taccr0 & {16{reg_rd[TACCR0]}}; +wire [15:0] tacctl1_rd = tacctl1_full & {16{reg_rd[TACCTL1]}}; +wire [15:0] taccr1_rd = taccr1 & {16{reg_rd[TACCR1]}}; +wire [15:0] tacctl2_rd = tacctl2_full & {16{reg_rd[TACCTL2]}}; +wire [15:0] taccr2_rd = taccr2 & {16{reg_rd[TACCR2]}}; +wire [15:0] taiv_rd = {12'h000, taiv} & {16{reg_rd[TAIV]}}; + +wire [15:0] per_dout = tactl_rd | + tar_rd | + tacctl0_rd | + taccr0_rd | + tacctl1_rd | + taccr1_rd | + tacctl2_rd | + taccr2_rd | + taiv_rd; + + +//============================================================================ +// 5) Timer A counter control +//============================================================================ + +// Clock input synchronization (TACLK & INCLK) +//----------------------------------------------------------- +reg [2:0] taclk_s; + +always @ (posedge mclk or posedge puc) + if (puc) taclk_s <= 3'b000; + else taclk_s <= {taclk_s[1:0], taclk}; + +wire taclk_en = taclk_s[1] & ~taclk_s[2]; + + +reg [2:0] inclk_s; + +always @ (posedge mclk or posedge puc) + if (puc) inclk_s <= 3'b000; + else inclk_s <= {inclk_s[1:0], inclk}; + +wire inclk_en = inclk_s[1] & ~inclk_s[2]; + + +// Timer clock input mux +//----------------------------------------------------------- + +wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en : + (tactl[`TASSELx]==2'b01) ? aclk_en : + (tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en; + + +// Generate update pluse for the counter (<=> divided clock) +//----------------------------------------------------------- +reg [2:0] clk_div; + +assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 : + (tactl[`TAIDx]==2'b01) ? clk_div[0] : + (tactl[`TAIDx]==2'b10) ? &clk_div[1:0] : + &clk_div[2:0]); + +always @ (posedge mclk or posedge puc) + if (puc) clk_div <= 3'h0; + else if (tar_clk | taclr) clk_div <= 3'h0; + else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1; + + +// Time counter control signals +//----------------------------------------------------------- + +assign tar_clr = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0)) | + ((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000)); + +assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) | + ((tactl[`TAMCx]==2'b11) & ~tar_dec); + +reg tar_dir; +always @ (posedge mclk or posedge puc) + if (puc) tar_dir <= 1'b0; + else if (taclr) tar_dir <= 1'b0; + else if (tactl[`TAMCx]==2'b11) + begin + if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0; + else if (tar>=taccr0) tar_dir <= 1'b1; + end + else tar_dir <= 1'b0; + +assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0)); + + +//============================================================================ +// 6) Timer A comparator +//============================================================================ + +wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0); +wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1); +wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2); + + +//============================================================================ +// 7) Timer A capture logic +//============================================================================ + +// Input selection +//------------------ +assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a : + (tacctl0[`TACCISx]==2'b01) ? ta_cci0b : + (tacctl0[`TACCISx]==2'b10) ? 1'b0 : 1'b1; + +assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a : + (tacctl1[`TACCISx]==2'b01) ? ta_cci1b : + (tacctl1[`TACCISx]==2'b10) ? 1'b0 : 1'b1; + +assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a : + (tacctl2[`TACCISx]==2'b01) ? ta_cci2b : + (tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1; + +// Register CCIx for synchronization and edge detection +reg [2:0] cci_s; +always @ (posedge mclk or posedge puc) + if (puc) cci_s <= 3'h0; + else cci_s <= {cci2, cci1, cci0}; +reg [2:0] cci_ss; +always @ (posedge mclk or posedge puc) + if (puc) cci_ss <= 3'h0; + else cci_ss <= cci_s; +reg [2:0] cci_sss; +always @ (posedge mclk or posedge puc) + if (puc) cci_sss <= 3'h0; + else cci_sss <= cci_ss; + + +// Generate SCCIx +//------------------ + +always @ (posedge mclk or posedge puc) + if (puc) scci0 <= 1'b0; + else if (tar_clk & equ0) scci0 <= cci_ss[0]; + +always @ (posedge mclk or posedge puc) + if (puc) scci1 <= 1'b0; + else if (tar_clk & equ1) scci1 <= cci_ss[1]; + +always @ (posedge mclk or posedge puc) + if (puc) scci2 <= 1'b0; + else if (tar_clk & equ2) scci2 <= cci_ss[2]; + + +// Capture mode +//------------------ +wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 : + (tacctl0[`TACMx]==2'b01) ? ( cci_ss[0] & ~cci_sss[0]) : // Rising edge + (tacctl0[`TACMx]==2'b10) ? (~cci_ss[0] & cci_sss[0]) : // Falling edge + ( cci_ss[0] ^ cci_sss[0]); // Both edges + +wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 : + (tacctl1[`TACMx]==2'b01) ? ( cci_ss[1] & ~cci_sss[1]) : // Rising edge + (tacctl1[`TACMx]==2'b10) ? (~cci_ss[1] & cci_sss[1]) : // Falling edge + ( cci_ss[1] ^ cci_sss[1]); // Both edges + +wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 : + (tacctl2[`TACMx]==2'b01) ? ( cci_ss[2] & ~cci_sss[2]) : // Rising edge + (tacctl2[`TACMx]==2'b10) ? (~cci_ss[2] & cci_sss[2]) : // Falling edge + ( cci_ss[2] ^ cci_sss[2]); // Both edges + +// Event Synchronization +//----------------------- + +reg cci0_evt_s; +always @ (posedge mclk or posedge puc) + if (puc) cci0_evt_s <= 1'b0; + else if (tar_clk) cci0_evt_s <= 1'b0; + else if (cci0_evt) cci0_evt_s <= 1'b1; + +reg cci1_evt_s; +always @ (posedge mclk or posedge puc) + if (puc) cci1_evt_s <= 1'b0; + else if (tar_clk) cci1_evt_s <= 1'b0; + else if (cci1_evt) cci1_evt_s <= 1'b1; + +reg cci2_evt_s; +always @ (posedge mclk or posedge puc) + if (puc) cci2_evt_s <= 1'b0; + else if (tar_clk) cci2_evt_s <= 1'b0; + else if (cci2_evt) cci2_evt_s <= 1'b1; + +reg cci0_sync; +always @ (posedge mclk or posedge puc) + if (puc) cci0_sync <= 1'b0; + else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s); + +reg cci1_sync; +always @ (posedge mclk or posedge puc) + if (puc) cci1_sync <= 1'b0; + else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s); + +reg cci2_sync; +always @ (posedge mclk or posedge puc) + if (puc) cci2_sync <= 1'b0; + else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s); + + +// Generate final capture command +//----------------------------------- + +assign cci0_cap = tacctl0[`TASCS] ? cci0_sync : cci0_evt; +assign cci1_cap = tacctl1[`TASCS] ? cci1_sync : cci1_evt; +assign cci2_cap = tacctl2[`TASCS] ? cci2_sync : cci2_evt; + + +// Generate capture overflow flag +//----------------------------------- + +reg cap0_taken; +wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]); +always @ (posedge mclk or posedge puc) + if (puc) cap0_taken <= 1'b0; + else if (cci0_cap) cap0_taken <= 1'b1; + else if (cap0_taken_clr) cap0_taken <= 1'b0; + +reg cap1_taken; +wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]); +always @ (posedge mclk or posedge puc) + if (puc) cap1_taken <= 1'b0; + else if (cci1_cap) cap1_taken <= 1'b1; + else if (cap1_taken_clr) cap1_taken <= 1'b0; + +reg cap2_taken; +wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]); +always @ (posedge mclk or posedge puc) + if (puc) cap2_taken <= 1'b0; + else if (cci2_cap) cap2_taken <= 1'b1; + else if (cap2_taken_clr) cap2_taken <= 1'b0; + + +assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0]; +assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1]; +assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2]; + + +//============================================================================ +// 8) Timer A output unit +//============================================================================ + +// Output unit 0 +//------------------- +reg ta_out0; + +wire ta_out0_mode0 = tacctl0[`TAOUT]; // Output +wire ta_out0_mode1 = equ0 ? 1'b1 : ta_out0; // Set +wire ta_out0_mode2 = equ0 ? ~ta_out0 : // Toggle/Reset + equ0 ? 1'b0 : ta_out0; +wire ta_out0_mode3 = equ0 ? 1'b1 : // Set/Reset + equ0 ? 1'b0 : ta_out0; +wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0; // Toggle +wire ta_out0_mode5 = equ0 ? 1'b0 : ta_out0; // Reset +wire ta_out0_mode6 = equ0 ? ~ta_out0 : // Toggle/Set + equ0 ? 1'b1 : ta_out0; +wire ta_out0_mode7 = equ0 ? 1'b0 : // Reset/Set + equ0 ? 1'b1 : ta_out0; + +wire ta_out0_nxt = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 : + (tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 : + (tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 : + (tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 : + (tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 : + (tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 : + (tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 : + ta_out0_mode7; + +always @ (posedge mclk or posedge puc) + if (puc) ta_out0 <= 1'b0; + else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0; + else if (tar_clk) ta_out0 <= ta_out0_nxt; + +assign ta_out0_en = ~tacctl0[`TACAP]; + + +// Output unit 1 +//------------------- +reg ta_out1; + +wire ta_out1_mode0 = tacctl1[`TAOUT]; // Output +wire ta_out1_mode1 = equ1 ? 1'b1 : ta_out1; // Set +wire ta_out1_mode2 = equ1 ? ~ta_out1 : // Toggle/Reset + equ0 ? 1'b0 : ta_out1; +wire ta_out1_mode3 = equ1 ? 1'b1 : // Set/Reset + equ0 ? 1'b0 : ta_out1; +wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1; // Toggle +wire ta_out1_mode5 = equ1 ? 1'b0 : ta_out1; // Reset +wire ta_out1_mode6 = equ1 ? ~ta_out1 : // Toggle/Set + equ0 ? 1'b1 : ta_out1; +wire ta_out1_mode7 = equ1 ? 1'b0 : // Reset/Set + equ0 ? 1'b1 : ta_out1; + +wire ta_out1_nxt = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 : + (tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 : + (tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 : + (tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 : + (tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 : + (tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 : + (tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 : + ta_out1_mode7; + +always @ (posedge mclk or posedge puc) + if (puc) ta_out1 <= 1'b0; + else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0; + else if (tar_clk) ta_out1 <= ta_out1_nxt; + +assign ta_out1_en = ~tacctl1[`TACAP]; + + +// Output unit 2 +//------------------- +reg ta_out2; + +wire ta_out2_mode0 = tacctl2[`TAOUT]; // Output +wire ta_out2_mode1 = equ2 ? 1'b1 : ta_out2; // Set +wire ta_out2_mode2 = equ2 ? ~ta_out2 : // Toggle/Reset + equ0 ? 1'b0 : ta_out2; +wire ta_out2_mode3 = equ2 ? 1'b1 : // Set/Reset + equ0 ? 1'b0 : ta_out2; +wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2; // Toggle +wire ta_out2_mode5 = equ2 ? 1'b0 : ta_out2; // Reset +wire ta_out2_mode6 = equ2 ? ~ta_out2 : // Toggle/Set + equ0 ? 1'b1 : ta_out2; +wire ta_out2_mode7 = equ2 ? 1'b0 : // Reset/Set + equ0 ? 1'b1 : ta_out2; + +wire ta_out2_nxt = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 : + (tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 : + (tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 : + (tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 : + (tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 : + (tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 : + (tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 : + ta_out2_mode7; + +always @ (posedge mclk or posedge puc) + if (puc) ta_out2 <= 1'b0; + else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0; + else if (tar_clk) ta_out2 <= ta_out2_nxt; + +assign ta_out2_en = ~tacctl2[`TACAP]; + + +//============================================================================ +// 9) Timer A interrupt generation +//============================================================================ + + +assign taifg_set = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0)) | + ((tactl[`TAMCx]==2'b10) & (tar==16'hffff)) | + ((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec)); + +assign ccifg0_set = tacctl0[`TACAP] ? cci0_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ0)); +assign ccifg1_set = tacctl1[`TACAP] ? cci1_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ1)); +assign ccifg2_set = tacctl2[`TACAP] ? cci2_cap : (tar_clk & ((tactl[`TAMCx]!=2'b00) & equ2)); + + +wire irq_ta0 = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]); + +wire irq_ta1 = (tactl[`TAIFG] & tactl[`TAIE]) | + (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) | + (tacctl2[`TACCIFG] & tacctl2[`TACCIE]); + + +endmodule // timerA + + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/timerA.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v (revision 29) @@ -0,0 +1,181 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: template_periph_16b.v +// +// *Module Description: +// 16 bit peripheral template. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module template_periph_16b ( + +// OUTPUTs + per_dout, // Peripheral data output + +// INPUTs + mclk, // Main system clock + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc // Main system reset +); + +// OUTPUTs +//========= +output [15:0] per_dout; // Peripheral data output + +// INPUTs +//========= +input mclk; // Main system clock +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter CNTRL1 = 9'h190; +parameter CNTRL2 = 9'h192; +parameter CNTRL3 = 9'h194; +parameter CNTRL4 = 9'h196; + + +// Register one-hot decoder +parameter CNTRL1_D = (512'h1 << CNTRL1); +parameter CNTRL2_D = (512'h1 << CNTRL2); +parameter CNTRL3_D = (512'h1 << CNTRL3); +parameter CNTRL4_D = (512'h1 << CNTRL4); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [511:0] reg_dec; +always @(per_addr) + case ({per_addr,1'b0}) + CNTRL1 : reg_dec = CNTRL1_D; + CNTRL2 : reg_dec = CNTRL2_D; + CNTRL3 : reg_dec = CNTRL3_D; + CNTRL4 : reg_dec = CNTRL4_D; + default: reg_dec = {512{1'b0}}; + endcase + +// Read/Write probes +wire reg_write = |per_wen & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [511:0] reg_wr = reg_dec & {512{reg_write}}; +wire [511:0] reg_rd = reg_dec & {512{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// CNTRL1 Register +//----------------- +reg [15:0] cntrl1; + +wire cntrl1_wr = reg_wr[CNTRL1]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl1 <= 16'h0000; + else if (cntrl1_wr) cntrl1 <= per_din; + + +// CNTRL2 Register +//----------------- +reg [15:0] cntrl2; + +wire cntrl2_wr = reg_wr[CNTRL2]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl2 <= 16'h0000; + else if (cntrl2_wr) cntrl2 <= per_din; + + +// CNTRL3 Register +//----------------- +reg [15:0] cntrl3; + +wire cntrl3_wr = reg_wr[CNTRL3]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl3 <= 16'h0000; + else if (cntrl3_wr) cntrl3 <= per_din; + + +// CNTRL4 Register +//----------------- +reg [15:0] cntrl4; + +wire cntrl4_wr = reg_wr[CNTRL4]; + +always @ (posedge mclk or posedge puc) + if (puc) cntrl4 <= 16'h0000; + else if (cntrl4_wr) cntrl4 <= per_din; + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}}; +wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}}; +wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}}; +wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}}; + +wire [15:0] per_dout = cntrl1_rd | + cntrl2_rd | + cntrl3_rd | + cntrl4_rd; + + +endmodule // template_periph_16b + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/register_file.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/register_file.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/register_file.v (revision 29) @@ -0,0 +1,347 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: register_file.v +// +// *Module Description: +// openMSP430 Register files +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module register_file ( + +// OUTPUTs + cpuoff, // Turns off the CPU + gie, // General interrupt enable + oscoff, // Turns off LFXT1 clock input + pc_sw, // Program counter software value + pc_sw_wr, // Program counter software write + reg_dest, // Selected register destination content + reg_src, // Selected register source content + scg1, // System clock generator 1. Turns off the SMCLK + status, // R2 Status {V,N,Z,C} + +// INPUTs + alu_stat, // ALU Status {V,N,Z,C} + alu_stat_wr, // ALU Status write {V,N,Z,C} + inst_bw, // Decoded Inst: byte width + inst_dest, // Register destination selection + inst_src, // Register source selection + mclk, // Main system clock + pc, // Program counter + puc, // Main system reset + reg_dest_val, // Selected register destination value + reg_dest_wr, // Write selected register destination + reg_pc_call, // Trigger PC update for a CALL instruction + reg_sp_val, // Stack Pointer next value + reg_sp_wr, // Stack Pointer write + reg_sr_wr, // Status register update for RETI instruction + reg_sr_clr, // Status register clear for interrupts + reg_incr // Increment source register +); + +// OUTPUTs +//========= +output cpuoff; // Turns off the CPU +output gie; // General interrupt enable +output oscoff; // Turns off LFXT1 clock input +output [15:0] pc_sw; // Program counter software value +output pc_sw_wr; // Program counter software write +output [15:0] reg_dest; // Selected register destination content +output [15:0] reg_src; // Selected register source content +output scg1; // System clock generator 1. Turns off the SMCLK +output [3:0] status; // R2 Status {V,N,Z,C} + +// INPUTs +//========= +input [3:0] alu_stat; // ALU Status {V,N,Z,C} +input [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C} +input inst_bw; // Decoded Inst: byte width +input [15:0] inst_dest; // Register destination selection +input [15:0] inst_src; // Register source selection +input mclk; // Main system clock +input [15:0] pc; // Program counter +input puc; // Main system reset +input [15:0] reg_dest_val; // Selected register destination value +input reg_dest_wr; // Write selected register destination +input reg_pc_call; // Trigger PC update for a CALL instruction +input [15:0] reg_sp_val; // Stack Pointer next value +input reg_sp_wr; // Stack Pointer write +input reg_sr_wr; // Status register update for RETI instruction +input reg_sr_clr; // Status register clear for interrupts +input reg_incr; // Increment source register + + +//============================================================================= +// 1) AUTOINCREMENT UNIT +//============================================================================= + +wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002; +wire [15:0] reg_incr_val = reg_src+incr_op; + +wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val; + + +//============================================================================= +// 2) SPECIAL REGISTERS (R1/R2/R3) +//============================================================================= + +// Source input selection mask (for interrupt support) +//----------------------------------------------------- + +wire [15:0] inst_src_in = reg_sr_clr ? 16'h0004 : inst_src; + + +// R0: Program counter +//--------------------- + +wire [15:0] r0 = pc; + +wire [15:0] pc_sw = reg_dest_val_in; +wire pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call; + + +// R1: Stack pointer +//------------------- +reg [15:0] r1; +wire r1_wr = inst_dest[1] & reg_dest_wr; +wire r1_inc = inst_src_in[1] & reg_incr; + +always @(posedge mclk or posedge puc) + if (puc) r1 <= 16'h0000; + else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe; + else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe; + else if (r1_inc) r1 <= reg_incr_val & 16'hfffe; + + +// R2: Status register +//--------------------- +reg [15:0] r2; +wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr; + +wire r2_c = alu_stat_wr[0] ? alu_stat[0] : + r2_wr ? reg_dest_val_in[0] : r2[0]; // C + +wire r2_z = alu_stat_wr[1] ? alu_stat[1] : + r2_wr ? reg_dest_val_in[1] : r2[1]; // Z + +wire r2_n = alu_stat_wr[2] ? alu_stat[2] : + r2_wr ? reg_dest_val_in[2] : r2[2]; // N + +wire [7:3] r2_nxt = r2_wr ? reg_dest_val_in[7:3] : r2[7:3]; + +wire r2_v = alu_stat_wr[3] ? alu_stat[3] : + r2_wr ? reg_dest_val_in[8] : r2[8]; // V + + +always @(posedge mclk or posedge puc) + if (puc) r2 <= 16'h0000; + else if (reg_sr_clr) r2 <= 16'h0000; + else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c}; + +assign status = {r2[8], r2[2:0]}; +assign gie = r2[3]; +assign cpuoff = r2[4] | (r2_nxt[4] & r2_wr); +assign oscoff = r2[5]; +assign scg1 = r2[7]; + + +// R3: Constant generator +//------------------------ +reg [15:0] r3; +wire r3_wr = inst_dest[3] & reg_dest_wr; +wire r3_inc = inst_src_in[3] & reg_incr; + +always @(posedge mclk or posedge puc) + if (puc) r3 <= 16'h0000; + else if (r3_wr) r3 <= reg_dest_val_in; + else if (r3_inc) r3 <= reg_incr_val; + + +//============================================================================= +// 4) GENERAL PURPOSE REGISTERS (R4...R15) +//============================================================================= + +// R4 +reg [15:0] r4; +wire r4_wr = inst_dest[4] & reg_dest_wr; +wire r4_inc = inst_src_in[4] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r4 <= 16'h0000; + else if (r4_wr) r4 <= reg_dest_val_in; + else if (r4_inc) r4 <= reg_incr_val; + +// R5 +reg [15:0] r5; +wire r5_wr = inst_dest[5] & reg_dest_wr; +wire r5_inc = inst_src_in[5] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r5 <= 16'h0000; + else if (r5_wr) r5 <= reg_dest_val_in; + else if (r5_inc) r5 <= reg_incr_val; + +// R6 +reg [15:0] r6; +wire r6_wr = inst_dest[6] & reg_dest_wr; +wire r6_inc = inst_src_in[6] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r6 <= 16'h0000; + else if (r6_wr) r6 <= reg_dest_val_in; + else if (r6_inc) r6 <= reg_incr_val; + +// R7 +reg [15:0] r7; +wire r7_wr = inst_dest[7] & reg_dest_wr; +wire r7_inc = inst_src_in[7] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r7 <= 16'h0000; + else if (r7_wr) r7 <= reg_dest_val_in; + else if (r7_inc) r7 <= reg_incr_val; + +// R8 +reg [15:0] r8; +wire r8_wr = inst_dest[8] & reg_dest_wr; +wire r8_inc = inst_src_in[8] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r8 <= 16'h0000; + else if (r8_wr) r8 <= reg_dest_val_in; + else if (r8_inc) r8 <= reg_incr_val; + +// R9 +reg [15:0] r9; +wire r9_wr = inst_dest[9] & reg_dest_wr; +wire r9_inc = inst_src_in[9] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r9 <= 16'h0000; + else if (r9_wr) r9 <= reg_dest_val_in; + else if (r9_inc) r9 <= reg_incr_val; + +// R10 +reg [15:0] r10; +wire r10_wr = inst_dest[10] & reg_dest_wr; +wire r10_inc = inst_src_in[10] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r10 <= 16'h0000; + else if (r10_wr) r10 <= reg_dest_val_in; + else if (r10_inc) r10 <= reg_incr_val; + +// R11 +reg [15:0] r11; +wire r11_wr = inst_dest[11] & reg_dest_wr; +wire r11_inc = inst_src_in[11] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r11 <= 16'h0000; + else if (r11_wr) r11 <= reg_dest_val_in; + else if (r11_inc) r11 <= reg_incr_val; + +// R12 +reg [15:0] r12; +wire r12_wr = inst_dest[12] & reg_dest_wr; +wire r12_inc = inst_src_in[12] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r12 <= 16'h0000; + else if (r12_wr) r12 <= reg_dest_val_in; + else if (r12_inc) r12 <= reg_incr_val; + +// R13 +reg [15:0] r13; +wire r13_wr = inst_dest[13] & reg_dest_wr; +wire r13_inc = inst_src_in[13] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r13 <= 16'h0000; + else if (r13_wr) r13 <= reg_dest_val_in; + else if (r13_inc) r13 <= reg_incr_val; + +// R14 +reg [15:0] r14; +wire r14_wr = inst_dest[14] & reg_dest_wr; +wire r14_inc = inst_src_in[14] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r14 <= 16'h0000; + else if (r14_wr) r14 <= reg_dest_val_in; + else if (r14_inc) r14 <= reg_incr_val; + +// R15 +reg [15:0] r15; +wire r15_wr = inst_dest[15] & reg_dest_wr; +wire r15_inc = inst_src_in[15] & reg_incr; +always @(posedge mclk or posedge puc) + if (puc) r15 <= 16'h0000; + else if (r15_wr) r15 <= reg_dest_val_in; + else if (r15_inc) r15 <= reg_incr_val; + + +//============================================================================= +// 5) READ MUX +//============================================================================= + +assign reg_src = (r0 & {16{inst_src_in[0]}}) | + (r1 & {16{inst_src_in[1]}}) | + (r2 & {16{inst_src_in[2]}}) | + (r3 & {16{inst_src_in[3]}}) | + (r4 & {16{inst_src_in[4]}}) | + (r5 & {16{inst_src_in[5]}}) | + (r6 & {16{inst_src_in[6]}}) | + (r7 & {16{inst_src_in[7]}}) | + (r8 & {16{inst_src_in[8]}}) | + (r9 & {16{inst_src_in[9]}}) | + (r10 & {16{inst_src_in[10]}}) | + (r11 & {16{inst_src_in[11]}}) | + (r12 & {16{inst_src_in[12]}}) | + (r13 & {16{inst_src_in[13]}}) | + (r14 & {16{inst_src_in[14]}}) | + (r15 & {16{inst_src_in[15]}}); + +assign reg_dest = (r0 & {16{inst_dest[0]}}) | + (r1 & {16{inst_dest[1]}}) | + (r2 & {16{inst_dest[2]}}) | + (r3 & {16{inst_dest[3]}}) | + (r4 & {16{inst_dest[4]}}) | + (r5 & {16{inst_dest[5]}}) | + (r6 & {16{inst_dest[6]}}) | + (r7 & {16{inst_dest[7]}}) | + (r8 & {16{inst_dest[8]}}) | + (r9 & {16{inst_dest[9]}}) | + (r10 & {16{inst_dest[10]}}) | + (r11 & {16{inst_dest[11]}}) | + (r12 & {16{inst_dest[12]}}) | + (r13 & {16{inst_dest[13]}}) | + (r14 & {16{inst_dest[14]}}) | + (r15 & {16{inst_dest[15]}}); + + +endmodule // register_file + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/register_file.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/timescale.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/timescale.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/timescale.v (revision 29) @@ -0,0 +1 @@ +`timescale 1ns / 100ps
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/timescale.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_uart.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_uart.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_uart.v (revision 29) @@ -0,0 +1,273 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: dbg_uart.v +// +// *Module Description: +// Debug UART communication interface (8N1, Half-duplex) +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module dbg_uart ( + +// OUTPUTs + dbg_addr, // Debug register address + dbg_din, // Debug register data input + dbg_rd, // Debug register data read + dbg_uart_txd, // Debug interface: UART TXD + dbg_wr, // Debug register data write + +// INPUTs + dbg_dout, // Debug register data output + dbg_rd_rdy, // Debug register data is ready for read + dbg_uart_rxd, // Debug interface: UART RXD + mclk, // Main system clock + mem_burst, // Burst on going + mem_burst_end, // End TX/RX burst + mem_burst_rd, // Start TX burst + mem_burst_wr, // Start RX burst + mem_bw, // Burst byte width + por // Power on reset +); + +// OUTPUTs +//========= +output [5:0] dbg_addr; // Debug register address +output [15:0] dbg_din; // Debug register data input +output dbg_rd; // Debug register data read +output dbg_uart_txd; // Debug interface: UART TXD +output dbg_wr; // Debug register data write + +// INPUTs +//========= +input [15:0] dbg_dout; // Debug register data output +input dbg_rd_rdy; // Debug register data is ready for read +input dbg_uart_rxd; // Debug interface: UART RXD +input mclk; // Main system clock +input mem_burst; // Burst on going +input mem_burst_end; // End TX/RX burst +input mem_burst_rd; // Start TX burst +input mem_burst_wr; // Start RX burst +input mem_bw; // Burst byte width +input por; // Power on reset + + +//============================================================================= +// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING +//============================================================================= + +// Synchronize RXD input & buffer +//-------------------------------- +reg [3:0] rxd_sync; +always @ (posedge mclk or posedge por) + if (por) rxd_sync <= 4'h0; + else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd}; + +// Majority decision +//------------------------ +reg rxd_maj; + +wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} + + {1'b0, rxd_sync[2]} + + {1'b0, rxd_sync[3]}; +wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10); + +always @ (posedge mclk or posedge por) + if (por) rxd_maj <= 1'b0; + else rxd_maj <= rxd_maj_nxt; + +wire rxd_s = rxd_maj; +wire rxd_fe = rxd_maj & ~rxd_maj_nxt; +wire rxd_re = ~rxd_maj & rxd_maj_nxt; + + +//============================================================================= +// 2) UART STATE MACHINE +//============================================================================= + +// Receive state +//------------------------ +reg [2:0] uart_state; +reg [2:0] uart_state_nxt; + +wire sync_done; +wire xfer_done; +reg [19:0] xfer_buf; + +// State machine definition +parameter RX_SYNC = 3'h0; +parameter RX_CMD = 3'h1; +parameter RX_DATA1 = 3'h2; +parameter RX_DATA2 = 3'h3; +parameter TX_DATA1 = 3'h4; +parameter TX_DATA2 = 3'h5; + +// State transition +always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw) + case (uart_state) + RX_SYNC : uart_state_nxt = RX_CMD; + RX_CMD : uart_state_nxt = mem_burst_wr ? + (mem_bw ? RX_DATA2 : RX_DATA1) : + mem_burst_rd ? + (mem_bw ? TX_DATA2 : TX_DATA1) : + (xfer_buf[`DBG_UART_WR] ? + (xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) : + (xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1)); + RX_DATA1 : uart_state_nxt = RX_DATA2; + RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? + (mem_bw ? RX_DATA2 : RX_DATA1) : + RX_CMD; + TX_DATA1 : uart_state_nxt = TX_DATA2; + TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ? + (mem_bw ? TX_DATA2 : TX_DATA1) : + RX_CMD; + default : uart_state_nxt = RX_CMD; + endcase + +// State machine +always @(posedge mclk or posedge por) + if (por) uart_state <= RX_SYNC; + else if (xfer_done | sync_done | + mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt; + +// Utility signals +wire cmd_valid = (uart_state==RX_CMD) & xfer_done; +wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2); + + +//============================================================================= +// 3) UART SYNCHRONIZATION +//============================================================================= +// After POR, the host needs to fist send a synchronization character (0x80) +// If this feature doesn't work properly, it is possible to disable it by +// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file. + +reg sync_busy; +always @ (posedge mclk or posedge por) + if (por) sync_busy <= 1'b0; + else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1; + else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0; + +assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy; + +`ifdef DBG_UART_AUTO_SYNC + +reg [14:0] sync_cnt; +always @ (posedge mclk or posedge por) + if (por) sync_cnt <= 15'h7ff8; + else if (sync_busy) sync_cnt <= sync_cnt+15'h0001; + +wire [11:0] bit_cnt_max = sync_cnt[14:3]; +`else +wire [11:0] bit_cnt_max = `DBG_UART_CNT; +`endif + + +//============================================================================= +// 4) UART RECEIVE / TRANSMIT +//============================================================================= + +// Transfer counter +//------------------------ +reg [3:0] xfer_bit; +reg [11:0] xfer_cnt; + +wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1)); +wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC)); +wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000); +assign xfer_done = (xfer_bit==4'hb); + +always @ (posedge mclk or posedge por) + if (por) xfer_bit <= 4'h0; + else if (txd_start | rxd_start) xfer_bit <= 4'h1; + else if (xfer_done) xfer_bit <= 4'h0; + else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1; + +always @ (posedge mclk or posedge por) + if (por) xfer_cnt <= 12'h000; + else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]}; + else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max; + else xfer_cnt <= xfer_cnt+12'hfff; + + +// Receive/Transmit buffer +//------------------------- +wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]}; + +always @ (posedge mclk or posedge por) + if (por) xfer_buf <= 18'h00000; + else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0}; + else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt; + + +// Generate TXD output +//------------------------ +reg dbg_uart_txd; + +always @ (posedge mclk or posedge por) + if (por) dbg_uart_txd <= 1'b1; + else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0]; + + +//============================================================================= +// 5) INTERFACE TO DEBUG REGISTERS +//============================================================================= + +reg [5:0] dbg_addr; + always @ (posedge mclk or posedge por) + if (por) dbg_addr <= 6'h00; + else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR]; + +reg dbg_bw; +always @ (posedge mclk or posedge por) + if (por) dbg_bw <= 1'b0; + else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW]; + +wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw; + +wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} : + {xfer_buf[18:11], xfer_buf[8:1]}; +wire dbg_wr = (xfer_done & (uart_state==RX_DATA2)); +wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) : + (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd; + + + +endmodule // dbg_uart + + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_uart.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v (revision 29) @@ -0,0 +1,439 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430.v +// +// *Module Description: +// openMSP430 Top level file +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module openMSP430 ( + +// OUTPUTs + aclk_en, // ACLK enable + dbg_freeze, // Freeze peripherals + dbg_uart_txd, // Debug interface: UART TXD + irq_acc, // Interrupt request accepted (one-hot signal) + mclk, // Main system clock + per_addr, // Peripheral address + per_din, // Peripheral data input + per_wen, // Peripheral write enable (high active) + per_en, // Peripheral enable (high active) + puc, // Main system reset + ram_addr, // RAM address + ram_cen, // RAM chip enable (low active) + ram_din, // RAM data input + ram_wen, // RAM write enable (low active) + rom_addr, // ROM address + rom_cen, // ROM chip enable (low active) + rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE-- + rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF-- + smclk_en, // SMCLK enable + +// INPUTs + dbg_uart_rxd, // Debug interface: UART RXD + dco_clk, // Fast oscillator (fast clock) + irq, // Maskable interrupts + lfxt_clk, // Low frequency oscillator (typ 32kHz) + nmi, // Non-maskable interrupt (asynchronous) + per_dout, // Peripheral data output + ram_dout, // RAM data output + reset_n, // Reset Pin (low active) + rom_dout // ROM data output +); + +// OUTPUTs +//========= +output aclk_en; // ACLK enable +output dbg_freeze; // Freeze peripherals +output dbg_uart_txd; // Debug interface: UART TXD +output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) +output mclk; // Main system clock +output [7:0] per_addr; // Peripheral address +output [15:0] per_din; // Peripheral data input +output [1:0] per_wen; // Peripheral write enable (high active) +output per_en; // Peripheral enable (high active) +output puc; // Main system reset +output [`RAM_MSB:0] ram_addr; // RAM address +output ram_cen; // RAM chip enable (low active) +output [15:0] ram_din; // RAM data input +output [1:0] ram_wen; // RAM write enable (low active) +output [`ROM_MSB:0] rom_addr; // ROM address +output rom_cen; // ROM chip enable (low active) +output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE-- +output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF-- +output smclk_en; // SMCLK enable + + +// INPUTs +//========= +input dbg_uart_rxd; // Debug interface: UART RXD +input dco_clk; // Fast oscillator (fast clock) +input [13:0] irq; // Maskable interrupts +input lfxt_clk; // Low frequency oscillator (typ 32kHz) +input nmi; // Non-maskable interrupt (asynchronous) +input [15:0] per_dout; // Peripheral data output +input [15:0] ram_dout; // RAM data output +input reset_n; // Reset Pin (active low) +input [15:0] rom_dout; // ROM data output + + + +//============================================================================= +// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION +//============================================================================= + +wire [7:0] inst_ad; +wire [7:0] inst_as; +wire [11:0] inst_alu; +wire inst_bw; +wire [15:0] inst_dest; +wire [15:0] inst_dext; +wire [15:0] inst_sext; +wire [7:0] inst_so; +wire [15:0] inst_src; +wire [2:0] inst_type; +wire [3:0] e_state; +wire exec_done; + +wire [15:0] eu_mab; +wire [15:0] eu_mdb_in; +wire [15:0] eu_mdb_out; +wire [1:0] eu_mb_wr; +wire [15:0] fe_mab; +wire [15:0] fe_mdb_in; + +wire [15:0] pc_sw; +wire [7:0] inst_jmp; +wire [15:0] pc; +wire [15:0] pc_nxt; + +wire [15:0] dbg_mem_addr; +wire [15:0] dbg_mem_dout; +wire [15:0] dbg_mem_din; +wire [15:0] dbg_reg_din; +wire [1:0] dbg_mem_wr; + +wire [15:0] per_dout_or; +wire [15:0] per_dout_sfr; +wire [15:0] per_dout_wdog; +wire [15:0] per_dout_clk; + + +//============================================================================= +// 2) GLOBAL CLOCK & RESET MANAGEMENT +//============================================================================= + +clock_module clock_module_0 ( + +// OUTPUTs + .aclk_en (aclk_en), // ACLK enablex + .mclk (mclk), // Main system clock + .per_dout (per_dout_clk), // Peripheral data output + .por (por), // Power-on reset + .puc (puc), // Main system reset + .smclk_en (smclk_en), // SMCLK enable + +// INPUTs + .dbg_reset (dbg_reset), // Reset CPU from debug interface + .dco_clk (dco_clk), // Fast oscillator (fast clock) + .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz) + .oscoff (oscoff), // Turns off LFXT1 clock input + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .reset_n (reset_n), // Reset Pin (low active) + .scg1 (scg1), // System clock generator 1. Turns off the SMCLK + .wdt_reset (wdt_reset) // Watchdog-timer reset +); + + +//============================================================================= +// 3) FRONTEND (<=> FETCH & DECODE) +//============================================================================= + +frontend frontend_0 ( + +// OUTPUTs + .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU + .decode (decode), // Frontend decode instruction + .e_state (e_state), // Execution state + .exec_done (exec_done), // Execution completed + .inst_ad (inst_ad), // Decoded Inst: destination addressing mode + .inst_as (inst_as), // Decoded Inst: source addressing mode + .inst_alu (inst_alu), // ALU control signals + .inst_bw (inst_bw), // Decoded Inst: byte width + .inst_dest (inst_dest), // Decoded Inst: destination (one hot) + .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word + .inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt + .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump + .inst_sext (inst_sext), // Decoded Inst: source extended instruction word + .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic + .inst_src (inst_src), // Decoded Inst: source (one hot) + .inst_type (inst_type), // Decoded Instruction type + .irq_acc (irq_acc), // Interrupt request accepted + .mab (fe_mab), // Frontend Memory address bus + .mb_en (fe_mb_en), // Frontend Memory bus enable + .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted + .pc (pc), // Program counter + .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) + +// INPUTs + .cpuoff (cpuoff), // Turns off the CPU + .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command + .dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access + .fe_rom_wait (fe_rom_wait), // Frontend wait for ROM + .gie (gie), // General interrupt enable + .irq (irq), // Maskable interrupts + .mclk (mclk), // Main system clock + .mdb_in (fe_mdb_in), // Frontend Memory data bus input + .nmi_evt (nmi_evt), // Non-maskable interrupt event + .pc_sw (pc_sw), // Program counter software value + .pc_sw_wr (pc_sw_wr), // Program counter software write + .puc (puc), // Main system reset + .wdt_irq (wdt_irq) // Watchdog-timer interrupt +); + + +//============================================================================= +// 4) EXECUTION UNIT +//============================================================================= + +execution_unit execution_unit_0 ( + +// OUTPUTs + .cpuoff (cpuoff), // Turns off the CPU + .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input + .mab (eu_mab), // Memory address bus + .mb_en (eu_mb_en), // Memory bus enable + .mb_wr (eu_mb_wr), // Memory bus write transfer + .mdb_out (eu_mdb_out), // Memory data bus output + .oscoff (oscoff), // Turns off LFXT1 clock input + .pc_sw (pc_sw), // Program counter software value + .pc_sw_wr (pc_sw_wr), // Program counter software write + .scg1 (scg1), // System clock generator 1. Turns off the SMCLK + +// INPUTs + .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU + .dbg_mem_dout (dbg_mem_dout), // Debug unit data output + .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write + .e_state (e_state), // Execution state + .exec_done (exec_done), // Execution completed + .gie (gie), // General interrupt enable + .inst_ad (inst_ad), // Decoded Inst: destination addressing mode + .inst_as (inst_as), // Decoded Inst: source addressing mode + .inst_alu (inst_alu), // ALU control signals + .inst_bw (inst_bw), // Decoded Inst: byte width + .inst_dest (inst_dest), // Decoded Inst: destination (one hot) + .inst_dext (inst_dext), // Decoded Inst: destination extended instruction word + .inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt + .inst_jmp (inst_jmp), // Decoded Inst: Conditional jump + .inst_sext (inst_sext), // Decoded Inst: source extended instruction word + .inst_so (inst_so), // Decoded Inst: Single-operand arithmetic + .inst_src (inst_src), // Decoded Inst: source (one hot) + .inst_type (inst_type), // Decoded Instruction type + .mclk (mclk), // Main system clock + .mdb_in (eu_mdb_in), // Memory data bus input + .pc (pc), // Program counter + .pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ) + .puc (puc) // Main system reset +); + + +//============================================================================= +// 5) MEMORY BACKBONE +//============================================================================= + +mem_backbone mem_backbone_0 ( + +// OUTPUTs + .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input + .eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input + .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input + .fe_rom_wait (fe_rom_wait), // Frontend wait for ROM + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_wen (per_wen), // Peripheral write enable (high active) + .per_en (per_en), // Peripheral enable (high active) + .ram_addr (ram_addr), // RAM address + .ram_cen (ram_cen), // RAM chip enable (low active) + .ram_din (ram_din), // RAM data input + .ram_wen (ram_wen), // RAM write enable (low active) + .rom_addr (rom_addr), // ROM address + .rom_cen (rom_cen), // ROM chip enable (low active) + .rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE-- + .rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF-- + +// INPUTs + .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU + .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access + .dbg_mem_dout (dbg_mem_dout), // Debug unit data output + .dbg_mem_en (dbg_mem_en), // Debug unit memory enable + .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write + .eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer + .eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output + .fe_mab (fe_mab[15:1]), // Frontend Memory address bus + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .mclk (mclk), // Main system clock + .per_dout (per_dout_or), // Peripheral data output + .puc (puc), // Main system reset + .ram_dout (ram_dout), // RAM data output + .rom_dout (rom_dout) // ROM data output +); + + +//============================================================================= +// 6) SPECIAL FUNCTION REGISTERS +//============================================================================= + +sfr sfr_0 ( + +// OUTPUTs + .nmie (nmie), // Non-maskable interrupt enable + .per_dout (per_dout_sfr), // Peripheral data output + .wdt_irq (wdt_irq), // Watchdog-timer interrupt + .wdt_reset (wdt_reset), // Watchdog-timer reset + .wdtie (wdtie), // Watchdog-timer interrupt enable + +// INPUTs + .mclk (mclk), // Main system clock + .nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .por (por), // Power-on reset + .puc (puc), // Main system reset + .wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag + .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag + .wdtpw_error (wdtpw_error), // Watchdog-timer password error + .wdttmsel (wdttmsel) // Watchdog-timer mode select +); + + +//============================================================================= +// 7) WATCHDOG TIMER +//============================================================================= + +watchdog watchdog_0 ( + +// OUTPUTs + .nmi_evt (nmi_evt), // NMI Event + .per_dout (per_dout_wdog), // Peripheral data output + .wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag + .wdtpw_error (wdtpw_error), // Watchdog-timer password error + .wdttmsel (wdttmsel), // Watchdog-timer mode select + +// INPUTs + .aclk_en (aclk_en), // ACLK enable + .dbg_freeze (dbg_freeze), // Freeze Watchdog counter + .mclk (mclk), // Main system clock + .nmi (nmi), // Non-maskable interrupt (asynchronous) + .nmie (nmie), // Non-maskable interrupt enable + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .puc (puc), // Main system reset + .smclk_en (smclk_en), // SMCLK enable + .wdtie (wdtie) // Watchdog-timer interrupt enable +); + + +//============================================================================= +// 8) PERIPHERALS' OUTPUT BUS +//============================================================================= + +assign per_dout_or = per_dout | + per_dout_clk | + per_dout_sfr | + per_dout_wdog; + + +//============================================================================= +// 9) DEBUG INTERFACE +//============================================================================= + +`ifdef DBG_EN +dbg dbg_0 ( + +// OUTPUTs + .dbg_freeze (dbg_freeze), // Freeze peripherals + .dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command + .dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access + .dbg_mem_dout (dbg_mem_dout), // Debug unit data output + .dbg_mem_en (dbg_mem_en), // Debug unit memory enable + .dbg_mem_wr (dbg_mem_wr), // Debug unit memory write + .dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write + .dbg_reset (dbg_reset), // Reset CPU from debug interface + .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD + +// INPUTs + .dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU + .dbg_mem_din (dbg_mem_din), // Debug unit Memory data input + .dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input + .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD + .decode (decode), // Frontend decode instruction + .eu_mab (eu_mab), // Execution-Unit Memory address bus + .eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable + .eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer + .eu_mdb_in (eu_mdb_in), // Memory data bus input + .eu_mdb_out (eu_mdb_out), // Memory data bus output + .exec_done (exec_done), // Execution completed + .fe_mb_en (fe_mb_en), // Frontend Memory bus enable + .fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input + .mclk (mclk), // Main system clock + .pc (pc), // Program counter + .por (por), // Power on reset + .puc (puc) // Main system reset +); + +`else +assign dbg_freeze = 1'b0; +assign dbg_halt_cmd = 1'b0; +assign dbg_mem_addr = 16'h0000; +assign dbg_mem_dout = 16'h0000; +assign dbg_mem_en = 1'b0; +assign dbg_mem_wr = 2'b00; +assign dbg_reg_wr = 1'b0; +assign dbg_reset = 1'b0; +assign dbg_uart_txd = 1'b0; +`endif + + +endmodule // openMSP430 +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_hwbrk.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_hwbrk.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_hwbrk.v (revision 29) @@ -0,0 +1,275 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: dbg_hwbrk.v +// +// *Module Description: +// Hardware Breakpoint / Watchpoint module +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module dbg_hwbrk ( + +// OUTPUTs + brk_halt, // Hardware breakpoint command + brk_pnd, // Hardware break/watch-point pending + brk_dout, // Hardware break/watch-point register data input + +// INPUTs + brk_reg_rd, // Hardware break/watch-point register read select + brk_reg_wr, // Hardware break/watch-point register write select + dbg_din, // Debug register data input + eu_mab, // Execution-Unit Memory address bus + eu_mb_en, // Execution-Unit Memory bus enable + eu_mb_wr, // Execution-Unit Memory bus write transfer + eu_mdb_in, // Memory data bus input + eu_mdb_out, // Memory data bus output + exec_done, // Execution completed + fe_mb_en, // Frontend Memory bus enable + mclk, // Main system clock + pc, // Program counter + por // Power on reset +); + +// OUTPUTs +//========= +output brk_halt; // Hardware breakpoint command +output brk_pnd; // Hardware break/watch-point pending +output [15:0] brk_dout; // Hardware break/watch-point register data input + +// INPUTs +//========= +input [3:0] brk_reg_rd; // Hardware break/watch-point register read select +input [3:0] brk_reg_wr; // Hardware break/watch-point register write select +input [15:0] dbg_din; // Debug register data input +input [15:0] eu_mab; // Execution-Unit Memory address bus +input eu_mb_en; // Execution-Unit Memory bus enable +input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer +input [15:0] eu_mdb_in; // Memory data bus input +input [15:0] eu_mdb_out; // Memory data bus output +input exec_done; // Execution completed +input fe_mb_en; // Frontend Memory bus enable +input mclk; // Main system clock +input [15:0] pc; // Program counter +input por; // Power on reset + + +//============================================================================= +// 1) WIRE & PARAMETER DECLARATION +//============================================================================= + +wire range_wr_set; +wire range_rd_set; +wire addr1_wr_set; +wire addr1_rd_set; +wire addr0_wr_set; +wire addr0_rd_set; + + +parameter BRK_CTL = 0, + BRK_STAT = 1, + BRK_ADDR0 = 2, + BRK_ADDR1 = 3; + + +//============================================================================= +// 2) CONFIGURATION REGISTERS +//============================================================================= + +// BRK_CTL Register +//----------------------------------------------------------------------------- +// 7 6 5 4 3 2 1 0 +// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE +// +// ACCESS_MODE: - 00 : Disabled +// - 01 : Detect read access +// - 10 : Detect write access +// - 11 : Detect read/write access +// NOTE: '10' & '11' modes are not supported on the instruction flow +// +// BREAK_EN: - 0 : Watchmode enable +// - 1 : Break enable +// +// INST_EN: - 0 : Checks are done on the execution unit (data flow) +// - 1 : Checks are done on the frontend (instruction flow) +// +// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1 +// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range +// +//----------------------------------------------------------------------------- +reg [4:0] brk_ctl; + +wire brk_ctl_wr = brk_reg_wr[BRK_CTL]; + +always @ (posedge mclk or posedge por) + if (por) brk_ctl <= 5'h00; + else if (brk_ctl_wr) brk_ctl <= dbg_din[4:0]; + +wire [7:0] brk_ctl_full = {3'b000, brk_ctl}; + + +// BRK_STAT Register +//----------------------------------------------------------------------------- +// 7 6 5 4 3 2 1 0 +// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD +//----------------------------------------------------------------------------- +reg [5:0] brk_stat; + +wire brk_stat_wr = brk_reg_wr[BRK_STAT]; +wire [5:0] brk_stat_set = {range_wr_set, range_rd_set, + addr1_wr_set, addr1_rd_set, + addr0_wr_set, addr0_rd_set}; +wire [5:0] brk_stat_clr = ~dbg_din[5:0]; + +always @ (posedge mclk or posedge por) + if (por) brk_stat <= 6'h00; + else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set); + else brk_stat <= (brk_stat | brk_stat_set); + +wire [7:0] brk_stat_full = {2'b00, brk_stat}; +wire brk_pnd = |brk_stat; + + +// BRK_ADDR0 Register +//----------------------------------------------------------------------------- +reg [15:0] brk_addr0; + +wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0]; + +always @ (posedge mclk or posedge por) + if (por) brk_addr0 <= 16'h0000; + else if (brk_addr0_wr) brk_addr0 <= dbg_din; + + +// BRK_ADDR1/DATA0 Register +//----------------------------------------------------------------------------- +reg [15:0] brk_addr1; + +wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1]; + +always @ (posedge mclk or posedge por) + if (por) brk_addr1 <= 16'h0000; + else if (brk_addr1_wr) brk_addr1 <= dbg_din; + + +//============================================================================ +// 3) DATA OUTPUT GENERATION +//============================================================================ + +wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}}; +wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}}; +wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}}; +wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}}; + +wire [15:0] brk_dout = brk_ctl_rd | + brk_stat_rd | + brk_addr0_rd | + brk_addr1_rd; + + +//============================================================================ +// 4) BREAKPOINT / WATCHPOINT GENERATION +//============================================================================ + +// Comparators +//--------------------------- +// Note: here the comparison logic is instanciated several times in order +// to improve the timings, at the cost of a bit more area. + +wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE]; +wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE]; +wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & brk_ctl[`BRK_RANGE]; + +reg fe_mb_en_buf; +always @ (posedge mclk or posedge por) + if (por) fe_mb_en_buf <= 1'b0; + else fe_mb_en_buf <= fe_mb_en; + +wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; +wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; +wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & brk_ctl[`BRK_RANGE]; + + +// Detect accesses +//--------------------------- + +// Detect Instruction read access +wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN]; +wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN]; +wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN]; + +// Detect Execution-Unit write access +wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; +wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; +wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr; + +// Detect DATA read access +// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read +// before being written back. In that case, the read flag should not be set. +// In general, We should here make sure no write access occures during the +// same instruction cycle before setting the read flag. +reg [2:0] d_rd_trig; +always @ (posedge mclk or posedge por) + if (por) d_rd_trig <= 3'h0; + else if (exec_done) d_rd_trig <= 3'h0; + else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, + equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr, + equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr}; + +wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr; +wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr; +wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr; + + +// Set flags +assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd); +assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr; +assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd); +assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr; +assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd); +assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr; + + +// Break CPU +assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set; + + +endmodule // dbg_hwbrk + + + + + + + +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/dbg_hwbrk.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/sfr.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/sfr.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/sfr.v (revision 29) @@ -0,0 +1,202 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: sfr.v +// +// *Module Description: +// Processor Special function register +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev$ +// $LastChangedBy$ +// $LastChangedDate$ +//---------------------------------------------------------------------------- +`include "timescale.v" +`include "openMSP430_defines.v" + +module sfr ( + +// OUTPUTs + nmie, // Non-maskable interrupt enable + per_dout, // Peripheral data output + wdt_irq, // Watchdog-timer interrupt + wdt_reset, // Watchdog-timer reset + wdtie, // Watchdog-timer interrupt enable + +// INPUTs + mclk, // Main system clock + nmi_acc, // Non-Maskable interrupt request accepted + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + por, // Power-on reset + puc, // Main system reset + wdtifg_clr, // Clear Watchdog-timer interrupt flag + wdtifg_set, // Set Watchdog-timer interrupt flag + wdtpw_error, // Watchdog-timer password error + wdttmsel // Watchdog-timer mode select +); + +// OUTPUTs +//========= +output nmie; // Non-maskable interrupt enable +output [15:0] per_dout; // Peripheral data output +output wdt_irq; // Watchdog-timer interrupt +output wdt_reset; // Watchdog-timer reset +output wdtie; // Watchdog-timer interrupt enable + +// INPUTs +//========= +input mclk; // Main system clock +input nmi_acc; // Non-Maskable interrupt request accepted +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input por; // Power-on reset +input puc; // Main system reset +input wdtifg_clr; // Clear Watchdog-timer interrupt flag +input wdtifg_set; // Set Watchdog-timer interrupt flag +input wdtpw_error; // Watchdog-timer password error +input wdttmsel; // Watchdog-timer mode select + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter IE1 = 9'h000; +parameter IFG1 = 9'h002; + +// Register one-hot decoder +parameter IE1_D = (256'h1 << (IE1 /2)); +parameter IFG1_D = (256'h1 << (IFG1 /2)); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [255:0] reg_dec; +always @(per_addr) + case (per_addr) + (IE1 /2): reg_dec = IE1_D; + (IFG1 /2): reg_dec = IFG1_D; + default : reg_dec = {256{1'b0}}; + endcase + +// Read/Write probes +wire reg_lo_write = per_wen[0] & per_en; +wire reg_hi_write = per_wen[1] & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; +wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; +wire [255:0] reg_rd = reg_dec & {256{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// IE1 Register +//-------------- +wire [7:0] ie1; +wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2]; +wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0]; + +reg nmie; +always @ (posedge mclk or posedge puc) + if (puc) nmie <= 1'b0; + else if (nmi_acc) nmie <= 1'b0; + else if (ie1_wr) nmie <= ie1_nxt[4]; + +reg wdtie; +always @ (posedge mclk or posedge puc) + if (puc) wdtie <= 1'b0; + else if (ie1_wr) wdtie <= ie1_nxt[0]; + +assign ie1 = {3'b000, nmie, 3'b000, wdtie}; + + +// IFG1 Register +//--------------- +wire [7:0] ifg1; +wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2]; +wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0]; + +reg nmiifg; +always @ (posedge mclk or posedge puc) + if (puc) nmiifg <= 1'b0; + else if (nmi_acc) nmiifg <= 1'b1; + else if (ifg1_wr) nmiifg <= ifg1_nxt[4]; + +reg wdtifg; +always @ (posedge mclk or posedge por) + if (por) wdtifg <= 1'b0; + else if (wdtifg_set) wdtifg <= 1'b1; + else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0; + else if (ifg1_wr) wdtifg <= ifg1_nxt[0]; + +assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg}; + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}}); +wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}}); + +wire [15:0] per_dout = ie1_rd | + ifg1_rd; + + +//============================================================================= +// 5) WATCHDOG INTERRUPT & RESET +//============================================================================= + +// Watchdog interrupt generation +//--------------------------------- +wire wdt_irq = wdttmsel & wdtifg & wdtie; + + +// Watchdog reset generation +//----------------------------- +reg wdt_reset; + +always @ (posedge mclk or posedge por) + if (por) wdt_reset <= 1'b0; + else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel); + + +endmodule // sfr
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/sfr.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Date Revision Author \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v (revision 29) @@ -0,0 +1,220 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: driver_7segment.v +// +// *Module Description: +// Driver for the four-digit, seven-segment LED display. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- + + +module driver_7segment ( + +// OUTPUTs + per_dout, // Peripheral data output + + hex0, // outputs to the segments + hex1, + hex2, + hex3, + +// INPUTs + mclk, // Main system clock + per_addr, // Peripheral address + per_din, // Peripheral data input + per_en, // Peripheral enable (high active) + per_wen, // Peripheral write enable (high active) + puc // Main system reset +); + +// OUTPUTs +//========= +output [15:0] per_dout; // Peripheral data output + +output [7:0] hex0,hex1,hex2,hex3; + + +// INPUTs +//========= +input mclk; // Main system clock +input [7:0] per_addr; // Peripheral address +input [15:0] per_din; // Peripheral data input +input per_en; // Peripheral enable (high active) +input [1:0] per_wen; // Peripheral write enable (high active) +input puc; // Main system reset + + +//============================================================================= +// 1) PARAMETER DECLARATION +//============================================================================= + +// Register addresses +parameter DIGIT0 = 9'h090; +parameter DIGIT1 = 9'h091; +parameter DIGIT2 = 9'h092; +parameter DIGIT3 = 9'h093; + + +// Register one-hot decoder +parameter DIGIT0_D = (256'h1 << (DIGIT0 /2)); +parameter DIGIT1_D = (256'h1 << (DIGIT1 /2)); +parameter DIGIT2_D = (256'h1 << (DIGIT2 /2)); +parameter DIGIT3_D = (256'h1 << (DIGIT3 /2)); + + +//============================================================================ +// 2) REGISTER DECODER +//============================================================================ + +// Register address decode +reg [255:0] reg_dec; +always @(per_addr) + case (per_addr) + (DIGIT0 /2): reg_dec = DIGIT0_D; + (DIGIT1 /2): reg_dec = DIGIT1_D; + (DIGIT2 /2): reg_dec = DIGIT2_D; + (DIGIT3 /2): reg_dec = DIGIT3_D; + default : reg_dec = {256{1'b0}}; + endcase + +// Read/Write probes +wire reg_lo_write = per_wen[0] & per_en; +wire reg_hi_write = per_wen[1] & per_en; +wire reg_read = ~|per_wen & per_en; + +// Read/Write vectors +wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}}; +wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}}; +wire [255:0] reg_rd = reg_dec & {256{reg_read}}; + + +//============================================================================ +// 3) REGISTERS +//============================================================================ + +// DIGIT0 Register +//----------------- +reg [7:0] digit0; + +wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0/2] : reg_lo_wr[DIGIT0/2]; +wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) digit0 <= 8'h00; + else if (digit0_wr) digit0 <= digit0_nxt; + + +// DIGIT1 Register +//----------------- +reg [7:0] digit1; + +wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1/2] : reg_lo_wr[DIGIT1/2]; +wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) digit1 <= 8'h00; + else if (digit1_wr) digit1 <= digit1_nxt; + + +// DIGIT2 Register +//----------------- +reg [7:0] digit2; + +wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2/2] : reg_lo_wr[DIGIT2/2]; +wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) digit2 <= 8'h00; + else if (digit2_wr) digit2 <= digit2_nxt; + + +// DIGIT3 Register +//----------------- +reg [7:0] digit3; + +wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3/2] : reg_lo_wr[DIGIT3/2]; +wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0]; + +always @ (posedge mclk or posedge puc) + if (puc) digit3 <= 8'h00; + else if (digit3_wr) digit3 <= digit3_nxt; + + +//============================================================================ +// 4) DATA OUTPUT GENERATION +//============================================================================ + +// Data output mux +wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0/2]}}) << (8 & {4{DIGIT0[0]}}); +wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1/2]}}) << (8 & {4{DIGIT1[0]}}); +wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2/2]}}) << (8 & {4{DIGIT2[0]}}); +wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3/2]}}) << (8 & {4{DIGIT3[0]}}); + +wire [15:0] per_dout = digit0_rd | + digit1_rd | + digit2_rd | + digit3_rd; + + +//============================================================================ +// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER +//============================================================================ + + +// Segment selection +//---------------------------- + +////// +////// +////// changed by Vadim Akimov, lvd.mhm@gmail.com +////// because altera DE1 has non-multiplexed 7seg display + + +bit_reverse revhex0 ( .in(~digit0), .out(hex0) ); +bit_reverse revhex1 ( .in(~digit1), .out(hex1) ); +bit_reverse revhex2 ( .in(~digit2), .out(hex2) ); +bit_reverse revhex3 ( .in(~digit3), .out(hex3) ); + + +endmodule // driver_7segment + + + +module bit_reverse( + input [7:0] in, + output [7:0] out +); + + assign out[7:0] = { in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7] }; + +endmodule +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v (revision 29) @@ -0,0 +1,680 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_fpga.v +// +// *Module Description: +// openMSP430 FPGA Top-level for the Altera DE1 board +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// - Vadim Akimov, lvd.mhm@gmail.com + + +`include "openMSP430_defines.v" + + +module main + ( + //////////////////// Clock Input //////////////// + CLOCK_24, // 24 MHz + CLOCK_27, // 27 MHz + CLOCK_50, // 50 MHz + EXT_CLOCK, // External Clock + //////////////////// Push Button //////////////// + KEY, // Pushbutton[3:0] + //////////////////// DPDT Switch //////////////// + SW, // Toggle Switch[9:0] + //////////////////// 7-SEG Dispaly //////////////// + HEX0, // Seven Segment Digit 0 + HEX1, // Seven Segment Digit 1 + HEX2, // Seven Segment Digit 2 + HEX3, // Seven Segment Digit 3 + //////////////////// LED //////////////// + LEDG, // LED Green[7:0] + LEDR, // LED Red[9:0] + //////////////////// UART //////////////// + UART_TXD, // UART Transmitter + UART_RXD, // UART Receiver + //////////////////// SDRAM Interface //////////////// + DRAM_DQ, // SDRAM Data bus 16 Bits + DRAM_ADDR, // SDRAM Address bus 12 Bits + DRAM_LDQM, // SDRAM Low-byte Data Mask + DRAM_UDQM, // SDRAM High-byte Data Mask + DRAM_WE_N, // SDRAM Write Enable + DRAM_CAS_N, // SDRAM Column Address Strobe + DRAM_RAS_N, // SDRAM Row Address Strobe + DRAM_CS_N, // SDRAM Chip Select + DRAM_BA_0, // SDRAM Bank Address 0 + DRAM_BA_1, // SDRAM Bank Address 0 + DRAM_CLK, // SDRAM Clock + DRAM_CKE, // SDRAM Clock Enable + //////////////////// Flash Interface //////////////// + FL_DQ, // FLASH Data bus 8 Bits + FL_ADDR, // FLASH Address bus 22 Bits + FL_WE_N, // FLASH Write Enable + FL_RST_N, // FLASH Reset + FL_OE_N, // FLASH Output Enable + FL_CE_N, // FLASH Chip Enable + //////////////////// SRAM Interface //////////////// + SRAM_DQ, // SRAM Data bus 16 Bits + SRAM_ADDR, // SRAM Address bus 18 Bits + SRAM_UB_N, // SRAM High-byte Data Mask + SRAM_LB_N, // SRAM Low-byte Data Mask + SRAM_WE_N, // SRAM Write Enable + SRAM_CE_N, // SRAM Chip Enable + SRAM_OE_N, // SRAM Output Enable + //////////////////// SD_Card Interface //////////////// + SD_DAT, // SD Card Data + SD_DAT3, // SD Card Data 3 + SD_CMD, // SD Card Command Signal + SD_CLK, // SD Card Clock + //////////////////// USB JTAG link //////////////// + TDI, // CPLD -> FPGA (data in) + TCK, // CPLD -> FPGA (clk) + TCS, // CPLD -> FPGA (CS) + TDO, // FPGA -> CPLD (data out) + //////////////////// I2C //////////////// + I2C_SDAT, // I2C Data + I2C_SCLK, // I2C Clock + //////////////////// PS2 //////////////// + PS2_DAT, // PS2 Data + PS2_CLK, // PS2 Clock + //////////////////// VGA //////////////// + VGA_HS, // VGA H_SYNC + VGA_VS, // VGA V_SYNC + VGA_R, // VGA Red[3:0] + VGA_G, // VGA Green[3:0] + VGA_B, // VGA Blue[3:0] + //////////////////// Audio CODEC //////////////// + AUD_ADCLRCK, // Audio CODEC ADC LR Clock + AUD_ADCDAT, // Audio CODEC ADC Data + AUD_DACLRCK, // Audio CODEC DAC LR Clock + AUD_DACDAT, // Audio CODEC DAC Data + AUD_BCLK, // Audio CODEC Bit-Stream Clock + AUD_XCK, // Audio CODEC Chip Clock + //////////////////// GPIO //////////////// + GPIO_0, // GPIO Connection 0 + GPIO_1 // GPIO Connection 1 + ); + +//////////////////////// Clock Input ///////////// +input [1:0] CLOCK_24; // 24 MHz +input [1:0] CLOCK_27; // 27 MHz +input CLOCK_50; // 50 MHz +input EXT_CLOCK; // External Clock +//////////////////////// Push Button ///////////// +input [3:0] KEY; // Pushbutton[3:0] +//////////////////////// DPDT Switch ///////////// +input [9:0] SW; // Toggle Switch[9:0] +//////////////////////// 7-SEG Dispaly ///////////// +output [6:0] HEX0; // Seven Segment Digit 0 +output [6:0] HEX1; // Seven Segment Digit 1 +output [6:0] HEX2; // Seven Segment Digit 2 +output [6:0] HEX3; // Seven Segment Digit 3 +//////////////////////// LED ///////////// +output [7:0] LEDG; // LED Green[7:0] +output [9:0] LEDR; // LED Red[9:0] +//////////////////////// UART ///////////// +output UART_TXD; // UART Transmitter +input UART_RXD; // UART Receiver +//////////////////////// SDRAM Interface ///////////// +inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits +output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits +output DRAM_LDQM; // SDRAM Low-byte Data Mask +output DRAM_UDQM; // SDRAM High-byte Data Mask +output DRAM_WE_N; // SDRAM Write Enable +output DRAM_CAS_N; // SDRAM Column Address Strobe +output DRAM_RAS_N; // SDRAM Row Address Strobe +output DRAM_CS_N; // SDRAM Chip Select +output DRAM_BA_0; // SDRAM Bank Address 0 +output DRAM_BA_1; // SDRAM Bank Address 0 +output DRAM_CLK; // SDRAM Clock +output DRAM_CKE; // SDRAM Clock Enable +//////////////////////// Flash Interface ///////////// +inout [7:0] FL_DQ; // FLASH Data bus 8 Bits +output [21:0] FL_ADDR; // FLASH Address bus 22 Bits +output FL_WE_N; // FLASH Write Enable +output FL_RST_N; // FLASH Reset +output FL_OE_N; // FLASH Output Enable +output FL_CE_N; // FLASH Chip Enable +//////////////////////// SRAM Interface ///////////// +inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits +output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits +output SRAM_UB_N; // SRAM High-byte Data Mask +output SRAM_LB_N; // SRAM Low-byte Data Mask +output SRAM_WE_N; // SRAM Write Enable +output SRAM_CE_N; // SRAM Chip Enable +output SRAM_OE_N; // SRAM Output Enable +//////////////////////// SD Card Interface ///////////// +inout SD_DAT; // SD Card Data +inout SD_DAT3; // SD Card Data 3 +inout SD_CMD; // SD Card Command Signal +output SD_CLK; // SD Card Clock +//////////////////////// I2C ///////////// +inout I2C_SDAT; // I2C Data +output I2C_SCLK; // I2C Clock +//////////////////////// PS2 ///////////// +input PS2_DAT; // PS2 Data +input PS2_CLK; // PS2 Clock +//////////////////////// USB JTAG link ///////////// +input TDI; // CPLD -> FPGA (data in) +input TCK; // CPLD -> FPGA (clk) +input TCS; // CPLD -> FPGA (CS) +output TDO; // FPGA -> CPLD (data out) +//////////////////////// VGA ///////////// +output VGA_HS; // VGA H_SYNC +output VGA_VS; // VGA V_SYNC +output [3:0] VGA_R; // VGA Red[3:0] +output [3:0] VGA_G; // VGA Green[3:0] +output [3:0] VGA_B; // VGA Blue[3:0] +//////////////////////// Audio CODEC ///////////// +output AUD_ADCLRCK; // Audio CODEC ADC LR Clock +input AUD_ADCDAT; // Audio CODEC ADC Data +output AUD_DACLRCK; // Audio CODEC DAC LR Clock +output AUD_DACDAT; // Audio CODEC DAC Data +inout AUD_BCLK; // Audio CODEC Bit-Stream Clock +output AUD_XCK; // Audio CODEC Chip Clock +//////////////////////// GPIO ///////////// +inout [35:0] GPIO_0; // GPIO Connection 0 +inout [35:0] GPIO_1; // GPIO Connection 1 +//////////////////////////////////////////////////////////////// + +// All inout port turn to tri-state +assign DRAM_DQ = 16'hzzzz; +assign FL_DQ = 8'hzz; +assign SD_DAT = 1'bz; +assign I2C_SDAT = 1'bz; +assign GPIO_0 = 36'hzzzzzzzzz; +assign GPIO_1 = 36'hzzzzzzzzz; + +// SDRAM blocking +assign DRAM_CS_N = 1'b1; +assign DRAM_CKE = 1'b0; +// FLASH blocking +assign FL_RST_N = 1'b1; +assign FL_CE_N = 1'b1; +assign FL_OE_N = 1'b1; +assign FL_WE_N = 1'b1; + + + + + +// overall clock +wire clk_sys; + + + + +//============================================================================= +// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION +//============================================================================= + +// openMSP430 output buses +wire [7:0] per_addr; +wire [15:0] per_din; +wire [1:0] per_wen; +wire [`RAM_MSB:0] ram_addr; +wire [15:0] ram_din; +wire [1:0] ram_wen; +wire [`ROM_MSB:0] rom_addr; +wire [15:0] rom_din_dbg; +wire [1:0] rom_wen_dbg; +wire [13:0] irq_acc; + +// openMSP430 input buses +wire [13:0] irq_bus; +wire [15:0] per_dout; +wire [15:0] ram_dout; +wire [15:0] rom_dout; + +// GPIO +wire [7:0] p1_din; +wire [7:0] p1_dout; +wire [7:0] p1_dout_en; +wire [7:0] p1_sel; +wire [7:0] p2_din; +wire [7:0] p2_dout; +wire [7:0] p2_dout_en; +wire [7:0] p2_sel; +wire [7:0] p3_din; +wire [7:0] p3_dout; +wire [7:0] p3_dout_en; +wire [7:0] p3_sel; +wire [15:0] per_dout_dio; + +// Timer A +wire [15:0] per_dout_tA; + +// 7 segment driver +wire [15:0] per_dout_7seg; + +// Others +wire reset_pin; + + + + +assign clk_sys = CLOCK_24[0]; // no PLL for now + +wire reset_pin_n = KEY[3]; // resets +assign reset_n = reset_pin_n; + + + + + +//============================================================================= +// 4) OPENMSP430 +//============================================================================= + +openMSP430 openMSP430_0 ( + +// OUTPUTs + .aclk_en (aclk_en), // ACLK enable + .dbg_freeze (dbg_freeze), // Freeze peripherals + .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD + .irq_acc (irq_acc), // Interrupt request accepted (one-hot signal) + .mclk (mclk), // Main system clock + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_wen (per_wen), // Peripheral write enable (high active) + .per_en (per_en), // Peripheral enable (high active) + .puc (puc), // Main system reset + .ram_addr (ram_addr), // RAM address + .ram_cen (ram_cen), // RAM chip enable (low active) + .ram_din (ram_din), // RAM data input + .ram_wen (ram_wen), // RAM write enable (low active) + .rom_addr (rom_addr), // ROM address + .rom_cen (rom_cen), // ROM chip enable (low active) + .rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE-- + .rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF-- + .smclk_en (smclk_en), // SMCLK enable + +// INPUTs + .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD + .dco_clk (clk_sys), // Fast oscillator (fast clock) + .irq (irq_bus), // Maskable interrupts + .lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz) + .nmi (nmi), // Non-maskable interrupt (asynchronous) + .per_dout (per_dout), // Peripheral data output + .ram_dout (ram_dout), // RAM data output + .reset_n (reset_n), // Reset Pin (low active) + .rom_dout (rom_dout) // ROM data output +); + + + + + + +//============================================================================= +// 5) OPENMSP430 PERIPHERALS +//============================================================================= + +// +// Digital I/O +//------------------------------- + +gpio #(.P1_EN(1), + .P2_EN(1), + .P3_EN(1), + .P4_EN(0), + .P5_EN(0), + .P6_EN(0)) gpio_0 ( + +// OUTPUTs + .irq_port1 (irq_port1), // Port 1 interrupt + .irq_port2 (irq_port2), // Port 2 interrupt + .p1_dout (p1_dout), // Port 1 data output + .p1_dout_en (p1_dout_en), // Port 1 data output enable + .p1_sel (p1_sel), // Port 1 function select + .p2_dout (p2_dout), // Port 2 data output + .p2_dout_en (p2_dout_en), // Port 2 data output enable + .p2_sel (p2_sel), // Port 2 function select + .p3_dout (p3_dout), // Port 3 data output + .p3_dout_en (p3_dout_en), // Port 3 data output enable + .p3_sel (p3_sel), // Port 3 function select + .p4_dout (), // Port 4 data output + .p4_dout_en (), // Port 4 data output enable + .p4_sel (), // Port 4 function select + .p5_dout (), // Port 5 data output + .p5_dout_en (), // Port 5 data output enable + .p5_sel (), // Port 5 function select + .p6_dout (), // Port 6 data output + .p6_dout_en (), // Port 6 data output enable + .p6_sel (), // Port 6 function select + .per_dout (per_dout_dio), // Peripheral data output + +// INPUTs + .mclk (mclk), // Main system clock + .p1_din (p1_din), // Port 1 data input + .p2_din (p2_din), // Port 2 data input + .p3_din (p3_din), // Port 3 data input + .p4_din (8'h00), // Port 4 data input + .p5_din (8'h00), // Port 5 data input + .p6_din (8'h00), // Port 6 data input + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .puc (puc) // Main system reset +); + +// +// Timer A +//---------------------------------------------- + +timerA timerA_0 ( + +// OUTPUTs + .irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0 + .irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2 + .per_dout (per_dout_tA), // Peripheral data output + .ta_out0 (ta_out0), // Timer A output 0 + .ta_out0_en (ta_out0_en), // Timer A output 0 enable + .ta_out1 (ta_out1), // Timer A output 1 + .ta_out1_en (ta_out1_en), // Timer A output 1 enable + .ta_out2 (ta_out2), // Timer A output 2 + .ta_out2_en (ta_out2_en), // Timer A output 2 enable + +// INPUTs + .aclk_en (aclk_en), // ACLK enable (from CPU) + .dbg_freeze (dbg_freeze), // Freeze Timer A counter + .inclk (inclk), // INCLK external timer clock (SLOW) + .irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted + .mclk (mclk), // Main system clock + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .puc (puc), // Main system reset + .smclk_en (smclk_en), // SMCLK enable (from CPU) + .ta_cci0a (ta_cci0a), // Timer A capture 0 input A + .ta_cci0b (ta_cci0b), // Timer A capture 0 input B + .ta_cci1a (ta_cci1a), // Timer A capture 1 input A + .ta_cci1b (1'b0), // Timer A capture 1 input B + .ta_cci2a (ta_cci2a), // Timer A capture 2 input A + .ta_cci2b (1'b0), // Timer A capture 2 input B + .taclk (taclk) // TACLK external timer clock (SLOW) +); + + +// +// Four-Digit, Seven-Segment LED Display driver +//---------------------------------------------- +wire [3:0] unconnected; +driver_7segment driver_7segment_0 ( + +// OUTPUTs + .per_dout (per_dout_7seg), // Peripheral data output + + .hex0({unconnected[0], HEX0}), + .hex1({unconnected[1], HEX1}), + .hex2({unconnected[2], HEX2}), + .hex3({unconnected[3], HEX3}), + + +// INPUTs + .mclk (mclk), // Main system clock + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_en (per_en), // Peripheral enable (high active) + .per_wen (per_wen), // Peripheral write enable (high active) + .puc (puc) // Main system reset +); + + +// +// Combine peripheral data buses +//------------------------------- + +assign per_dout = per_dout_dio | + per_dout_tA | + per_dout_7seg; + +// +// Assign interrupts +//------------------------------- + +assign nmi = 1'b0; +assign irq_bus = {1'b0, // Vector 13 (0xFFFA) + 1'b0, // Vector 12 (0xFFF8) + 1'b0, // Vector 11 (0xFFF6) + 1'b0, // Vector 10 (0xFFF4) - Watchdog - + irq_ta0, // Vector 9 (0xFFF2) + irq_ta1, // Vector 8 (0xFFF0) + 1'b0, // Vector 7 (0xFFEE) + 1'b0, // Vector 6 (0xFFEC) + 1'b0, // Vector 5 (0xFFEA) + 1'b0, // Vector 4 (0xFFE8) + irq_port2, // Vector 3 (0xFFE6) + irq_port1, // Vector 2 (0xFFE4) + 1'b0, // Vector 1 (0xFFE2) + 1'b0}; // Vector 0 (0xFFE0) + +// +// GPIO Function selection +//-------------------------- + +// P1.0/TACLK I/O pin / Timer_A, clock signal TACLK input +// P1.1/TA0 I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output +// P1.2/TA1 I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output +// P1.3/TA2 I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output +// P1.4/SMCLK I/O pin / SMCLK signal output +// P1.5/TA0 I/O pin / Timer_A, compare: Out0 output +// P1.6/TA1 I/O pin / Timer_A, compare: Out1 output +// P1.7/TA2 I/O pin / Timer_A, compare: Out2 output +wire [7:0] p1_io_mux_b_unconnected; +wire [7:0] p1_io_dout; +wire [7:0] p1_io_dout_en; +wire [7:0] p1_io_din; + +io_mux #8 io_mux_p1 ( + .a_din (p1_din), + .a_dout (p1_dout), + .a_dout_en (p1_dout_en), + + .b_din ({p1_io_mux_b_unconnected[7], + p1_io_mux_b_unconnected[6], + p1_io_mux_b_unconnected[5], + p1_io_mux_b_unconnected[4], + ta_cci2a, + ta_cci1a, + ta_cci0a, + taclk + }), + .b_dout ({ta_out2, + ta_out1, + ta_out0, + (smclk_en & mclk), + ta_out2, + ta_out1, + ta_out0, + 1'b0 + }), + .b_dout_en ({ta_out2_en, + ta_out1_en, + ta_out0_en, + 1'b1, + ta_out2_en, + ta_out1_en, + ta_out0_en, + 1'b0 + }), + + .io_din (p1_io_din), + .io_dout (p1_io_dout), + .io_dout_en (p1_io_dout_en), + + .sel (p1_sel) +); + + + +// P2.0/ACLK I/O pin / ACLK output +// P2.1/INCLK I/O pin / Timer_A, clock signal at INCLK +// P2.2/TA0 I/O pin / Timer_A, capture: CCI0B input +// P2.3/TA1 I/O pin / Timer_A, compare: Out1 output +// P2.4/TA2 I/O pin / Timer_A, compare: Out2 output +wire [7:0] p2_io_mux_b_unconnected; +wire [7:0] p2_io_dout; +wire [7:0] p2_io_dout_en; +wire [7:0] p2_io_din; + +io_mux #8 io_mux_p2 ( + .a_din (p2_din), + .a_dout (p2_dout), + .a_dout_en (p2_dout_en), + + .b_din ({p2_io_mux_b_unconnected[7], + p2_io_mux_b_unconnected[6], + p2_io_mux_b_unconnected[5], + p2_io_mux_b_unconnected[4], + p2_io_mux_b_unconnected[3], + ta_cci0b, + inclk, + p2_io_mux_b_unconnected[0] + }), + .b_dout ({1'b0, + 1'b0, + 1'b0, + ta_out2, + ta_out1, + 1'b0, + 1'b0, + (aclk_en & mclk) + }), + .b_dout_en ({1'b0, + 1'b0, + 1'b0, + ta_out2_en, + ta_out1_en, + 1'b0, + 1'b0, + 1'b1 + }), + + .io_din (p2_io_din), + .io_dout (p2_io_dout), + .io_dout_en (p2_io_dout_en), + + .sel (p2_sel) +); + + + + + + +//============================================================================= +// 6) RAM / ROM +//============================================================================= + +// You can use either synchronous ram16x512 module generated by MegaWizard, +// or ext_de1_sram module accessing to the on-board static asynchronous RAM + +// RAM + +//cyclone's M4k cells - just an example of instantiating 16-bit M4K altera RAM +ram16x512 ram ( + .address (ram_addr[8:0]), + .clken (~ram_cen), + .clock (clk_sys), + .data (ram_din[15:0]), + .q (ram_dout[15:0]), + .wren ( ~(&ram_wen[1:0]) ), + .byteena ( ~ram_wen[1:0] ) +); +/**/ +/* +// DE1's onboard sram - only 512 words used +ext_de1_sram #(.ADDR_WIDTH(9)) ram ( + + .clk(clk_sys), + + .ram_addr(ram_addr[8:0]), + .ram_cen(ram_cen), + .ram_wen(ram_wen[1:0]), + .ram_dout(ram_dout[15:0]), + .ram_din(ram_din[15:0]), + + .SRAM_ADDR(SRAM_ADDR), + .SRAM_DQ(SRAM_DQ), + .SRAM_CE_N(SRAM_CE_N), + .SRAM_OE_N(SRAM_OE_N), + .SRAM_WE_N(SRAM_WE_N), + .SRAM_UB_N(SRAM_UB_N), + .SRAM_LB_N(SRAM_LB_N) +); +*/ + + + +// ROM - DEBUG ACCESS removed. If you need it, use as example original diligent's sources +rom16x2048 rom_0 ( + .clock (clk_sys), + .clken (~rom_cen), + .address (rom_addr[10:0]), + .q ( rom_dout ) +); + + + + + +//============================================================================= +// 7) I/O CELLS +//============================================================================= + +assign p3_din[7:0] = SW[7:0]; + +assign LEDR[7:0] = p3_dout[7:0] & p3_dout_en[7:0]; + + +// RS-232 Port +//---------------------- +// P1.1 (TX) and P2.2 (RX) +assign p1_io_din = 8'h00; +assign p2_io_din[7:3] = 5'h00; +assign p2_io_din[1:0] = 2'h0; + +// Mux the RS-232 port between IO port and the debug interface. +// The mux is controlled with the SW0 switch +wire uart_txd_out = p3_din[0] ? dbg_uart_txd : p1_io_dout[1]; +wire uart_rxd_in; +assign p2_io_din[2] = p3_din[0] ? 1'b1 : uart_rxd_in; +assign dbg_uart_rxd = p3_din[0] ? uart_rxd_in : 1'b1; + + +assign uart_rxd_in = UART_RXD; +assign UART_TXD = uart_txd_out; + + + + + +endmodule +
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ram16x512.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ram16x512.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ram16x512.v (revision 29) @@ -0,0 +1,172 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram16x512.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 6.1 Build 201 11/27/2006 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram16x512 ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [8:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 512, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 9, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "9" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT NODEFVAL byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/ram16x512.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/rom16x2048.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/rom16x2048.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/rom16x2048.v (revision 29) @@ -0,0 +1,159 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rom16x2048.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 6.1 Build 201 11/27/2006 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module rom16x2048 ( + address, + clken, + clock, + q); + + input [10:0] address; + input clken; + input clock; + output [15:0] q; + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .clock0 (clock), + .address_a (address), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({16{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", +`ifdef OPENMSP430_SIMULATION + altsyncram_component.init_file = "./rom.mif", +`else + altsyncram_component.init_file = "../../software/memledtest/memledtest.mif", +`endif + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2048, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.ram_block_type = "M4K", + altsyncram_component.widthad_a = 11, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" +// Retrieval info: PRIVATE: JTAG_ID STRING "ROM" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "../../software/memledtest/memledtest.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "../../software/memledtest/memledtest.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/rom16x2048.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Board_Schematic.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Board_Schematic.pdf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Board_Schematic.pdf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Board_Schematic.pdf (revision 29)
openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Board_Schematic.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Reference_Manual.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Reference_Manual.pdf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Reference_Manual.pdf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Reference_Manual.pdf (revision 29)
openmsp430/trunk/fpga/altera_de1_board/doc/DE1_Reference_Manual.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_User Guide.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/doc/DE1_User Guide.pdf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/doc/DE1_User Guide.pdf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/doc/DE1_User Guide.pdf (revision 29)
openmsp430/trunk/fpga/altera_de1_board/doc/DE1_User Guide.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run_disassemble =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run_disassemble (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run_disassemble (revision 29) @@ -0,0 +1 @@ +msp430-objdump -D rom.elf
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run_disassemble Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run (revision 29) @@ -0,0 +1,3 @@ +#!/bin/csh -f + +../bin/msp430sim memledtest
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/memledtest.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/memledtest.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/memledtest.v (revision 29) @@ -0,0 +1,21 @@ +/*===========================================================================*/ +/* DIGITAL I/O */ +/*---------------------------------------------------------------------------*/ +/* Test the Digital I/O interface. */ +/*===========================================================================*/ + +initial + begin + $display(" ==============================================="); + $display("| START SIMULATION |"); + $display(" ==============================================="); + repeat(5) @(posedge CLOCK_24); + stimulus_done = 0; + + + + + + stimulus_done = 1; + end +
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/memledtest.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f (revision 29) @@ -0,0 +1,86 @@ +//============================================================================= +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//----------------------------------------------------------------------------- +// +// File Name: submit.f +// +// Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//----------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//============================================================================= + ++define+OPENMSP430_SIMULATION + +//============================================================================= +// Altera library +//============================================================================= ++libext+.v + +../../../bench/verilog/altsyncram.v + + +//============================================================================= +// FPGA Specific modules +//============================================================================= + ++incdir+../../../rtl/verilog/ +../../../rtl/verilog/OpenMSP430_fpga.v +../../../rtl/verilog/io_mux.v +../../../rtl/verilog/driver_7segment.v +../../../rtl/verilog/ram16x512.v +../../../rtl/verilog/rom16x2048.v + + +//============================================================================= +// openMSP430 +//============================================================================= + ++incdir+../../../rtl/verilog/openmsp430/ +../../../rtl/verilog/openmsp430/openMSP430.v +../../../rtl/verilog/openmsp430/frontend.v +../../../rtl/verilog/openmsp430/execution_unit.v +../../../rtl/verilog/openmsp430/register_file.v +../../../rtl/verilog/openmsp430/alu.v +../../../rtl/verilog/openmsp430/mem_backbone.v +../../../rtl/verilog/openmsp430/clock_module.v +../../../rtl/verilog/openmsp430/sfr.v +../../../rtl/verilog/openmsp430/dbg.v +../../../rtl/verilog/openmsp430/dbg_hwbrk.v +../../../rtl/verilog/openmsp430/dbg_uart.v +../../../rtl/verilog/openmsp430/watchdog.v +../../../rtl/verilog/openmsp430/periph/gpio.v +../../../rtl/verilog/openmsp430/periph/timerA.v + + +//============================================================================= +// Testbench related +//============================================================================= + ++incdir+../../../bench/verilog/ +../../../bench/verilog/tb_openMSP430_fpga.v +../../../bench/verilog/msp_debug.v +
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/ihex2mem.tcl =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/ihex2mem.tcl (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/ihex2mem.tcl (revision 29) @@ -0,0 +1,153 @@ +#!/usr/bin/tclsh +#------------------------------------------------------------------------------ +# Copyright (C) 2001 Authors +# +# This source file may be used and distributed without restriction provided +# that this copyright statement is not removed from the file and that any +# derivative work contains the original copyright notice and the associated +# disclaimer. +# +# This source file is free software; you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation; either version 2.1 of the License, or +# (at your option) any later version. +# +# This source is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +# License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this source; if not, write to the Free Software Foundation, +# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#------------------------------------------------------------------------------ +# +# File Name: ihex2mem.tcl +# +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# +#------------------------------------------------------------------------------ +# $Rev: 16 $ +# $LastChangedBy: olivier.girard $ +# $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $ +#------------------------------------------------------------------------------ + +############################################################################### +# PARAMETER CHECK # +############################################################################### + +if {$argc != 6} { + puts "ERROR : wrong number of arguments" + puts "USAGE : ihex2mem.tcl -ihex -out -mem_size " + puts "Example : ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size 2048" + exit 1 +} + +# default values +set ihex empty.in +set out empty.out +set mem_size -1 + +# parse arguments +for {set i 0} {$i < $argc} {incr i} { + switch -exact -- [lindex $argv $i] { + -ihex {set ihex [lindex $argv [expr $i+1]]; incr i} + -out {set out [lindex $argv [expr $i+1]]; incr i} + -mem_size {set mem_size [lindex $argv [expr $i+1]]; incr i} + } +} + +# Make sure arugments were specified +if {[string eq $ihex empty.in]} { + puts "IHEX input file isn't specified" + exit 1 +} +if {[string eq $out empty.out]} { + puts "MEMH output file isn't specified" + exit 1 +} +if {[string eq $mem_size -1]} { + puts "Memory size isn't specified" + exit 1 +} + + +############################################################################### +# CONVERSION PROCEDURE # +############################################################################### + +#-----------------------------------------------------------------------------# +# OPEN FILES # +#-----------------------------------------------------------------------------# + +# IHEX Input +if [catch {open $ihex r} f_ihex] { + puts "ERROR Cannot open input file $ihex" + exit 1 +} + +# MEMH Output +if [catch {open $out w } f_out] { + puts "ERROR Cannot create output file $out" + exit 1 +} + + +#-----------------------------------------------------------------------------# +# CONVERSION # +#-----------------------------------------------------------------------------# + + +# Conversions procedure +proc hex2dec { val } { + set val [format "%u" 0x[string trimleft $val]] + return $val +} + + +# Initialize memory array (16 bit words) +set num_word [expr ($mem_size/2)-1] +for {set i 0} {$i <= $num_word} {incr i} { + set mem_arr($i) 0000 +} + + +# Calculate Address offset (offset=(0x10000-memory_size)) +set mem_offset [expr 65536-$mem_size] + + +# Process input file +while {[gets $f_ihex line] >= 0} { + + # Process line + set byte_count [hex2dec [string range $line 1 2]] + set start_addr [expr ([hex2dec [string range $line 3 6]] - $mem_offset)] + set rec_type [string range $line 7 8] + + if {$rec_type == 00} { + for {set i 0} {$i < $byte_count*2} {set i [expr $i+4]} { + set mem_msb [string range $line [expr $i+11] [expr $i+12]] + set mem_lsb [string range $line [expr $i+9] [expr $i+10]] + set addr [expr ($start_addr+$i/2)/2] + set mem_arr($addr) "$mem_msb$mem_lsb" + } + } +} +close $f_ihex + + +# Writing memory array to file +for {set i 0} {$i <= $num_word} {incr i} { + + if {![expr $i%16]} { + puts -nonewline $f_out "\n@[format "%04x" $i] " + } + puts -nonewline $f_out " [format "%02s" $mem_arr($i) ]" +} + +puts $f_out "\n" +close $f_out + +exit 0
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/ihex2mem.tcl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim (revision 29) @@ -0,0 +1,117 @@ +#!/bin/sh +#------------------------------------------------------------------------------ +# Copyright (C) 2001 Authors +# +# This source file may be used and distributed without restriction provided +# that this copyright statement is not removed from the file and that any +# derivative work contains the original copyright notice and the associated +# disclaimer. +# +# This source file is free software; you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation; either version 2.1 of the License, or +# (at your option) any later version. +# +# This source is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +# License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this source; if not, write to the Free Software Foundation, +# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#------------------------------------------------------------------------------ +# +# File Name: msp430sim +# +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# +#------------------------------------------------------------------------------ +# $Rev: 23 $ +# $LastChangedBy: olivier.girard $ +# $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +#------------------------------------------------------------------------------ + +############################################################################### +# Parameter Check # +############################################################################### +EXPECTED_ARGS=1 +if [ $# -ne $EXPECTED_ARGS ]; then + echo "ERROR : wrong number of arguments" + echo "USAGE : msp430sim " + echo "Example : msp430sim leds" + exit 1 +fi + + +############################################################################### +# Check if the required files exist # +############################################################################### +softdir=../../../software/$1; +elffile=../../../software/$1/$1.elf; +miffile=../../../software/$1/$1.mif; +verfile=../src/$1.v; +submitfile=../src/submit.f; +incfile=../../../rtl/verilog/openmsp430/openMSP430_defines.v; + +if [ ! -e $softdir ]; then + echo "Software directory doesn't exist: $softdir" + exit 1 +fi +if [ ! -e $verfile ]; then + echo "Verilog stimulus file $verfile doesn't exist: $verfile" + exit 1 +fi +if [ ! -e $submitfile ]; then + echo "Verilog submit file $submitfile doesn't exist: $submitfile" + exit 1 +fi + + +############################################################################### +# Cleanup # +############################################################################### +echo "Cleanup..." +rm -rf rom.* +rm -rf stimulus.v + + +############################################################################### +# Run simulation # +############################################################################### +echo " =======================================================" +echo "| Start simulation: $1" +echo " =======================================================" + +# Make C program +cd $softdir +make +cd ../../sim/rtl_sim/run/ + +# Create links +ln -s $elffile rom.elf +ln -s $miffile rom.mif +ln -s $verfile stimulus.v + +# Make local copy of the openMSP403 configuration file and remove comments +cp $incfile ./rom.inc +sed -i "/^\/\// s,.*,," rom.inc + +# Get ROM size +romsize=`grep ROM_AWIDTH rom.inc | grep -v ROM_MSB | grep -v ROM_SIZE` +romsize=${romsize##* } +romsize=$((2<<$romsize)) + +# Create IHEX file from ELF +echo "Convert ELF file to IHEX format..." +msp430-objcopy -O ihex rom.elf rom.ihex + +# Generate ROM memory file +echo "Convert IHEX file to Verilog MEMH format..." +../bin/ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size $romsize + +# Start verilog simulation +echo "Start Verilog simulation..." +../bin/rtlsim.sh stimulus.v rom.mem $submitfile
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh (revision 29) @@ -0,0 +1,72 @@ +#!/bin/sh +#------------------------------------------------------------------------------ +# Copyright (C) 2001 Authors +# +# This source file may be used and distributed without restriction provided +# that this copyright statement is not removed from the file and that any +# derivative work contains the original copyright notice and the associated +# disclaimer. +# +# This source file is free software; you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation; either version 2.1 of the License, or +# (at your option) any later version. +# +# This source is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +# License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this source; if not, write to the Free Software Foundation, +# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#------------------------------------------------------------------------------ +# +# File Name: rtlsim.sh +# +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# +#------------------------------------------------------------------------------ +# $Rev: 16 $ +# $LastChangedBy: olivier.girard $ +# $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $ +#------------------------------------------------------------------------------ + +############################################################################### +# Parameter Check # +############################################################################### +EXPECTED_ARGS=3 +if [ $# -ne $EXPECTED_ARGS ]; then + echo "ERROR : wrong number of arguments" + echo "USAGE : rtlsim.sh " + echo "Example : rtlsim.sh ./stimulus.v rom.mem ../src/submit.f" + exit 1 +fi + + +############################################################################### +# Check if the required files exist # +############################################################################### + +if [ ! -e $1 ]; then + echo "Verilog stimulus file $1 doesn't exist" + exit 1 +fi +if [ ! -e $2 ]; then + echo "ROM memory file $2 doesn't exist" + exit 1 +fi +if [ ! -e $3 ]; then + echo "Verilog submit file $3 doesn't exist" + exit 1 +fi + + +############################################################################### +# Start verilog simulation # +############################################################################### +rm -rf simv +iverilog -o simv -c $3 +./simv
openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/OpenMSP430_fpga.qpf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/OpenMSP430_fpga.qpf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/OpenMSP430_fpga.qpf (revision 29) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "6.1" +DATE = "23:43:20 October 13, 2009" + + +# Revisions + +PROJECT_REVISION = "main"
openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/OpenMSP430_fpga.qpf Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof (revision 29)
openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v (revision 29) @@ -0,0 +1,66 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_fpga_top.v +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- + +//============================================================================= +// FPGA Specific modules +//============================================================================= + +`include "../../../rtl/verilog/openMSP430_fpga.v" +`include "../../../rtl/verilog/io_mux.v" +`include "../../../rtl/verilog/driver_7segment.v" +`include "../../../rtl/verilog/ram16x512.v" // altera DE1 specific modules +`include "../../../rtl/verilog/rom16x2048.v" // +`include "../../../rtl/verilog/ext_de1_sram.v" // + + +//============================================================================= +// openMSP430 +//============================================================================= + +`include "../../../rtl/verilog/openmsp430/openMSP430.v" +`include "../../../rtl/verilog/openmsp430/frontend.v" +`include "../../../rtl/verilog/openmsp430/execution_unit.v" +`include "../../../rtl/verilog/openmsp430/register_file.v" +`include "../../../rtl/verilog/openmsp430/alu.v" +`include "../../../rtl/verilog/openmsp430/mem_backbone.v" +`include "../../../rtl/verilog/openmsp430/clock_module.v" +`include "../../../rtl/verilog/openmsp430/dbg.v" +`include "../../../rtl/verilog/openmsp430/dbg_hwbrk.v" +`include "../../../rtl/verilog/openmsp430/dbg_uart.v" +`include "../../../rtl/verilog/openmsp430/sfr.v" +`include "../../../rtl/verilog/openmsp430/watchdog.v" +`include "../../../rtl/verilog/openmsp430/periph/gpio.v" +`include "../../../rtl/verilog/openmsp430/periph/timerA.v" +
openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf (revision 29) @@ -0,0 +1,506 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# main_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name TOP_LEVEL_ENTITY main +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:43:20 OCTOBER 13, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id klok +set_instance_assignment -name CLOCK_SETTINGS klok -to CLOCK_24[0] +set_location_assignment PIN_A13 -to GPIO_0[0] +set_location_assignment PIN_B13 -to GPIO_0[1] +set_location_assignment PIN_A14 -to GPIO_0[2] +set_location_assignment PIN_B14 -to GPIO_0[3] +set_location_assignment PIN_A15 -to GPIO_0[4] +set_location_assignment PIN_B15 -to GPIO_0[5] +set_location_assignment PIN_A16 -to GPIO_0[6] +set_location_assignment PIN_B16 -to GPIO_0[7] +set_location_assignment PIN_A17 -to GPIO_0[8] +set_location_assignment PIN_B17 -to GPIO_0[9] +set_location_assignment PIN_A18 -to GPIO_0[10] +set_location_assignment PIN_B18 -to GPIO_0[11] +set_location_assignment PIN_A19 -to GPIO_0[12] +set_location_assignment PIN_B19 -to GPIO_0[13] +set_location_assignment PIN_A20 -to GPIO_0[14] +set_location_assignment PIN_B20 -to GPIO_0[15] +set_location_assignment PIN_C21 -to GPIO_0[16] +set_location_assignment PIN_C22 -to GPIO_0[17] +set_location_assignment PIN_D21 -to GPIO_0[18] +set_location_assignment PIN_D22 -to GPIO_0[19] +set_location_assignment PIN_E21 -to GPIO_0[20] +set_location_assignment PIN_E22 -to GPIO_0[21] +set_location_assignment PIN_F21 -to GPIO_0[22] +set_location_assignment PIN_F22 -to GPIO_0[23] +set_location_assignment PIN_G21 -to GPIO_0[24] +set_location_assignment PIN_G22 -to GPIO_0[25] +set_location_assignment PIN_J21 -to GPIO_0[26] +set_location_assignment PIN_J22 -to GPIO_0[27] +set_location_assignment PIN_K21 -to GPIO_0[28] +set_location_assignment PIN_K22 -to GPIO_0[29] +set_location_assignment PIN_J19 -to GPIO_0[30] +set_location_assignment PIN_J20 -to GPIO_0[31] +set_location_assignment PIN_J18 -to GPIO_0[32] +set_location_assignment PIN_K20 -to GPIO_0[33] +set_location_assignment PIN_L19 -to GPIO_0[34] +set_location_assignment PIN_L18 -to GPIO_0[35] +set_location_assignment PIN_H12 -to GPIO_1[0] +set_location_assignment PIN_H13 -to GPIO_1[1] +set_location_assignment PIN_H14 -to GPIO_1[2] +set_location_assignment PIN_G15 -to GPIO_1[3] +set_location_assignment PIN_E14 -to GPIO_1[4] +set_location_assignment PIN_E15 -to GPIO_1[5] +set_location_assignment PIN_F15 -to GPIO_1[6] +set_location_assignment PIN_G16 -to GPIO_1[7] +set_location_assignment PIN_F12 -to GPIO_1[8] +set_location_assignment PIN_F13 -to GPIO_1[9] +set_location_assignment PIN_C14 -to GPIO_1[10] +set_location_assignment PIN_D14 -to GPIO_1[11] +set_location_assignment PIN_D15 -to GPIO_1[12] +set_location_assignment PIN_D16 -to GPIO_1[13] +set_location_assignment PIN_C17 -to GPIO_1[14] +set_location_assignment PIN_C18 -to GPIO_1[15] +set_location_assignment PIN_C19 -to GPIO_1[16] +set_location_assignment PIN_C20 -to GPIO_1[17] +set_location_assignment PIN_D19 -to GPIO_1[18] +set_location_assignment PIN_D20 -to GPIO_1[19] +set_location_assignment PIN_E20 -to GPIO_1[20] +set_location_assignment PIN_F20 -to GPIO_1[21] +set_location_assignment PIN_E19 -to GPIO_1[22] +set_location_assignment PIN_E18 -to GPIO_1[23] +set_location_assignment PIN_G20 -to GPIO_1[24] +set_location_assignment PIN_G18 -to GPIO_1[25] +set_location_assignment PIN_G17 -to GPIO_1[26] +set_location_assignment PIN_H17 -to GPIO_1[27] +set_location_assignment PIN_J15 -to GPIO_1[28] +set_location_assignment PIN_H18 -to GPIO_1[29] +set_location_assignment PIN_N22 -to GPIO_1[30] +set_location_assignment PIN_N21 -to GPIO_1[31] +set_location_assignment PIN_P15 -to GPIO_1[32] +set_location_assignment PIN_N15 -to GPIO_1[33] +set_location_assignment PIN_P17 -to GPIO_1[34] +set_location_assignment PIN_P18 -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_G5 -to HEX2[0] +set_location_assignment PIN_G6 -to HEX2[1] +set_location_assignment PIN_C2 -to HEX2[2] +set_location_assignment PIN_C1 -to HEX2[3] +set_location_assignment PIN_E3 -to HEX2[4] +set_location_assignment PIN_E4 -to HEX2[5] +set_location_assignment PIN_D3 -to HEX2[6] +set_location_assignment PIN_F4 -to HEX3[0] +set_location_assignment PIN_D5 -to HEX3[1] +set_location_assignment PIN_D6 -to HEX3[2] +set_location_assignment PIN_J4 -to HEX3[3] +set_location_assignment PIN_L8 -to HEX3[4] +set_location_assignment PIN_F3 -to HEX3[5] +set_location_assignment PIN_D4 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_T22 -to KEY[2] +set_location_assignment PIN_T21 -to KEY[3] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_V22 -to LEDG[2] +set_location_assignment PIN_V21 -to LEDG[3] +set_location_assignment PIN_W22 -to LEDG[4] +set_location_assignment PIN_W21 -to LEDG[5] +set_location_assignment PIN_Y22 -to LEDG[6] +set_location_assignment PIN_Y21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7] +set_location_assignment PIN_D12 -to CLOCK_27[0] +set_location_assignment PIN_E12 -to CLOCK_27[1] +set_location_assignment PIN_B12 -to CLOCK_24[0] +set_location_assignment PIN_A12 -to CLOCK_24[1] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_M21 -to EXT_CLOCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_CLOCK +set_location_assignment PIN_H15 -to PS2_CLK +set_location_assignment PIN_J14 -to PS2_DAT +set_location_assignment PIN_F14 -to UART_RXD +set_location_assignment PIN_G12 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_E8 -to TDI +set_location_assignment PIN_D8 -to TCS +set_location_assignment PIN_C7 -to TCK +set_location_assignment PIN_D7 -to TDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO +set_location_assignment PIN_D9 -to VGA_R[0] +set_location_assignment PIN_C9 -to VGA_R[1] +set_location_assignment PIN_A7 -to VGA_R[2] +set_location_assignment PIN_B7 -to VGA_R[3] +set_location_assignment PIN_B8 -to VGA_G[0] +set_location_assignment PIN_C10 -to VGA_G[1] +set_location_assignment PIN_B9 -to VGA_G[2] +set_location_assignment PIN_A8 -to VGA_G[3] +set_location_assignment PIN_A9 -to VGA_B[0] +set_location_assignment PIN_D11 -to VGA_B[1] +set_location_assignment PIN_A10 -to VGA_B[2] +set_location_assignment PIN_B10 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_HS +set_location_assignment PIN_B11 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_location_assignment PIN_W4 -to DRAM_ADDR[0] +set_location_assignment PIN_W5 -to DRAM_ADDR[1] +set_location_assignment PIN_Y3 -to DRAM_ADDR[2] +set_location_assignment PIN_Y4 -to DRAM_ADDR[3] +set_location_assignment PIN_R6 -to DRAM_ADDR[4] +set_location_assignment PIN_R5 -to DRAM_ADDR[5] +set_location_assignment PIN_P6 -to DRAM_ADDR[6] +set_location_assignment PIN_P5 -to DRAM_ADDR[7] +set_location_assignment PIN_P3 -to DRAM_ADDR[8] +set_location_assignment PIN_N4 -to DRAM_ADDR[9] +set_location_assignment PIN_W3 -to DRAM_ADDR[10] +set_location_assignment PIN_N6 -to DRAM_ADDR[11] +set_location_assignment PIN_U3 -to DRAM_BA_0 +set_location_assignment PIN_V4 -to DRAM_BA_1 +set_location_assignment PIN_T3 -to DRAM_CAS_N +set_location_assignment PIN_N3 -to DRAM_CKE +set_location_assignment PIN_U4 -to DRAM_CLK +set_location_assignment PIN_T6 -to DRAM_CS_N +set_location_assignment PIN_U1 -to DRAM_DQ[0] +set_location_assignment PIN_U2 -to DRAM_DQ[1] +set_location_assignment PIN_V1 -to DRAM_DQ[2] +set_location_assignment PIN_V2 -to DRAM_DQ[3] +set_location_assignment PIN_W1 -to DRAM_DQ[4] +set_location_assignment PIN_W2 -to DRAM_DQ[5] +set_location_assignment PIN_Y1 -to DRAM_DQ[6] +set_location_assignment PIN_Y2 -to DRAM_DQ[7] +set_location_assignment PIN_N1 -to DRAM_DQ[8] +set_location_assignment PIN_N2 -to DRAM_DQ[9] +set_location_assignment PIN_P1 -to DRAM_DQ[10] +set_location_assignment PIN_P2 -to DRAM_DQ[11] +set_location_assignment PIN_R1 -to DRAM_DQ[12] +set_location_assignment PIN_R2 -to DRAM_DQ[13] +set_location_assignment PIN_T1 -to DRAM_DQ[14] +set_location_assignment PIN_T2 -to DRAM_DQ[15] +set_location_assignment PIN_R7 -to DRAM_LDQM +set_location_assignment PIN_T5 -to DRAM_RAS_N +set_location_assignment PIN_M5 -to DRAM_UDQM +set_location_assignment PIN_R8 -to DRAM_WE_N +set_location_assignment PIN_AB20 -to FL_ADDR[0] +set_location_assignment PIN_AA14 -to FL_ADDR[1] +set_location_assignment PIN_Y16 -to FL_ADDR[2] +set_location_assignment PIN_R15 -to FL_ADDR[3] +set_location_assignment PIN_T15 -to FL_ADDR[4] +set_location_assignment PIN_U15 -to FL_ADDR[5] +set_location_assignment PIN_V15 -to FL_ADDR[6] +set_location_assignment PIN_W15 -to FL_ADDR[7] +set_location_assignment PIN_R14 -to FL_ADDR[8] +set_location_assignment PIN_Y13 -to FL_ADDR[9] +set_location_assignment PIN_R12 -to FL_ADDR[10] +set_location_assignment PIN_T12 -to FL_ADDR[11] +set_location_assignment PIN_AB14 -to FL_ADDR[12] +set_location_assignment PIN_AA13 -to FL_ADDR[13] +set_location_assignment PIN_AB13 -to FL_ADDR[14] +set_location_assignment PIN_AA12 -to FL_ADDR[15] +set_location_assignment PIN_AB12 -to FL_ADDR[16] +set_location_assignment PIN_AA20 -to FL_ADDR[17] +set_location_assignment PIN_U14 -to FL_ADDR[18] +set_location_assignment PIN_V14 -to FL_ADDR[19] +set_location_assignment PIN_U13 -to FL_ADDR[20] +set_location_assignment PIN_R13 -to FL_ADDR[21] +set_location_assignment PIN_AB16 -to FL_DQ[0] +set_location_assignment PIN_AA16 -to FL_DQ[1] +set_location_assignment PIN_AB17 -to FL_DQ[2] +set_location_assignment PIN_AA17 -to FL_DQ[3] +set_location_assignment PIN_AB18 -to FL_DQ[4] +set_location_assignment PIN_AA18 -to FL_DQ[5] +set_location_assignment PIN_AB19 -to FL_DQ[6] +set_location_assignment PIN_AA19 -to FL_DQ[7] +set_location_assignment PIN_AA15 -to FL_OE_N +set_location_assignment PIN_W14 -to FL_RST_N +set_location_assignment PIN_Y14 -to FL_WE_N +set_location_assignment PIN_AA3 -to SRAM_ADDR[0] +set_location_assignment PIN_AB3 -to SRAM_ADDR[1] +set_location_assignment PIN_AA4 -to SRAM_ADDR[2] +set_location_assignment PIN_AB4 -to SRAM_ADDR[3] +set_location_assignment PIN_AA5 -to SRAM_ADDR[4] +set_location_assignment PIN_AB10 -to SRAM_ADDR[5] +set_location_assignment PIN_AA11 -to SRAM_ADDR[6] +set_location_assignment PIN_AB11 -to SRAM_ADDR[7] +set_location_assignment PIN_V11 -to SRAM_ADDR[8] +set_location_assignment PIN_W11 -to SRAM_ADDR[9] +set_location_assignment PIN_R11 -to SRAM_ADDR[10] +set_location_assignment PIN_T11 -to SRAM_ADDR[11] +set_location_assignment PIN_Y10 -to SRAM_ADDR[12] +set_location_assignment PIN_U10 -to SRAM_ADDR[13] +set_location_assignment PIN_R10 -to SRAM_ADDR[14] +set_location_assignment PIN_T7 -to SRAM_ADDR[15] +set_location_assignment PIN_Y6 -to SRAM_ADDR[16] +set_location_assignment PIN_Y5 -to SRAM_ADDR[17] +set_location_assignment PIN_AB5 -to SRAM_CE_N +set_location_assignment PIN_AA6 -to SRAM_DQ[0] +set_location_assignment PIN_AB6 -to SRAM_DQ[1] +set_location_assignment PIN_AA7 -to SRAM_DQ[2] +set_location_assignment PIN_AB7 -to SRAM_DQ[3] +set_location_assignment PIN_AA8 -to SRAM_DQ[4] +set_location_assignment PIN_AB8 -to SRAM_DQ[5] +set_location_assignment PIN_AA9 -to SRAM_DQ[6] +set_location_assignment PIN_AB9 -to SRAM_DQ[7] +set_location_assignment PIN_Y9 -to SRAM_DQ[8] +set_location_assignment PIN_W9 -to SRAM_DQ[9] +set_location_assignment PIN_V9 -to SRAM_DQ[10] +set_location_assignment PIN_U9 -to SRAM_DQ[11] +set_location_assignment PIN_R9 -to SRAM_DQ[12] +set_location_assignment PIN_W8 -to SRAM_DQ[13] +set_location_assignment PIN_V8 -to SRAM_DQ[14] +set_location_assignment PIN_U8 -to SRAM_DQ[15] +set_location_assignment PIN_Y7 -to SRAM_LB_N +set_location_assignment PIN_T8 -to SRAM_OE_N +set_location_assignment PIN_W7 -to SRAM_UB_N +set_location_assignment PIN_AA10 -to SRAM_WE_N +set_location_assignment PIN_AB15 -to FL_CE_N +set_location_assignment PIN_U20 -to SD_DAT3 +set_location_assignment PIN_W20 -to SD_DAT +set_location_assignment PIN_Y20 -to SD_CMD +set_location_assignment PIN_V20 -to SD_CLK +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_DQ +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SRAM_DQ +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_ADDR +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_CE_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_WE_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_OE_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_UB_N +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SRAM_LB_N +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name VERILOG_FILE openMSP430_fpga_top.v +set_global_assignment -name CDF_FILE Chain1.cdf +set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\openmsp430/
openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.c =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.c (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.c (revision 29) @@ -0,0 +1,20 @@ +#include "gray.h" + + +unsigned char bin2gray(unsigned char bin) +{ + return bin ^ (bin>>1); +} + +unsigned char gray2bin(unsigned char gray) +{ + unsigned char bin; + + bin = gray ^ (gray>>1); + bin ^= (bin>>2); + bin ^= (bin>>4); + + return bin; +} + +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/hardware.h =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/hardware.h (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/hardware.h (revision 29) @@ -0,0 +1,13 @@ +#ifndef MAIN_H +#define MAIN_H + +#define __msp430_have_port3 +#define __MSP430_HAS_PORT3__ + +#include +#include +#include + + + +#endif // MAIN_H
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/hardware.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.c =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.c (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.c (revision 29) @@ -0,0 +1,224 @@ +/* +********************************************************************************************************* +* +* Multiplexed LED Display Driver +* +* (c) Copyright 2004, modified by John Leung +* Reference: Jean J. Labrosse, Embedded Systems Building Blocks +* All Rights Reserved +* +* Filename : LED.C +* Programmer : John Leung +* Remarks : Modified for SaiWanHo project +* Date : 19th Nov 2004 +* Hardware : PCB 11OCT2004.001 +********************************************************************************************************* +* DESCRIPTION +* +* This module provides an interface to a multiplexed "8 segments x N digits" LED matrix. +* +* To use this driver: +* +* 1) You must define (LED.H): +* +* DISP_N_DIG The total number of segments to display, inc. dp status +* DISP_N_SS The total number of seven-segment digits (modules) +* DISP_PORT1_DIG The address of the DIGITS output port +* DISP_PORT_SEG The address of the SEGMENTS output port +* first_dig_msk The first digit mask for selecting the most significant digit +* +* 2) You must allocate a hardware timer which will interrupt the CPU at a rate of at least: +* +* DISP_N_DIG * 60 (Hz) +* +* The timer interrupt must vector to DispMuxISR (defined in LED_IA.ASM). You MUST write the +* code to clear the interrupt source. The interrupt source must be cleared either in DispMuxISR +* or in DispMuxHandler(). +* +* 3) Adapt DispInitPort(), DispOutSeg() and DispOutDig() for your environment. +********************************************************************************************************* +*/ +#include "7seg.h" + +/* +********************************************************************************************************* +* SEVEN-SEGMENT Digit table +********************************************************************************************************* +*/ + +INT8U * const DispSegTbl[] = { + (INT8U *) &DIGIT3, + (INT8U *) &DIGIT2, + (INT8U *) &DIGIT1, + (INT8U *) &DIGIT0 +}; + +/* +********************************************************************************************************* +* ASCII to SEVEN-SEGMENT conversion table +* a +* ------ +* f | | b +* | g | +* Note: The segments are mapped as follows: ------ +* e | | c +* a b c d e f g | d | +* -- -- -- -- -- -- -- -- ------ +* B7 B6 B5 B4 B3 B2 B1 B0 +********************************************************************************************************* +*/ + +const INT8U DispASCIItoSegTbl[] = {// ASCII to SEVEN-SEGMENT conversion table +0x00, // ' ' +0x00, // '!', No seven-segment conversion for exclamation point +0x44, // '"', Double quote +0x00, // '#', Pound sign +0x00, // '$', No seven-segment conversion for dollar sign +0x00, // '%', No seven-segment conversion for percent sign +0x00, // '&', No seven-segment conversion for ampersand +0x40, // ''', Single quote +0x9C, // '(', Same as '[' +0xF0, // ')', Same as ']' +0x00, // '*', No seven-segment conversion for asterix +0x00, // '+', No seven-segment conversion for plus sign +0x00, // ',', No seven-segment conversion for comma +0x02, // '-', Minus sign +0x00, // '.', No seven-segment conversion for period +0x00, // '/', No seven-segment conversion for slash +0xFC, // '0' +0x60, // '1' +0xDA, // '2' +0xF2, // '3' +0x66, // '4' +0xB6, // '5' +0xBE, // '6' +0xE0, // '7' +0xFE, // '8' +0xF6, // '9' +0x00, // ':', No seven-segment conversion for colon +0x00, // ';', No seven-segment conversion for semi-colon +0x00, // '<', No seven-segment conversion for less-than sign +0x12, // '=', Equal sign +0x00, // '>', No seven-segment conversion for greater-than sign +0xCA, //'?', Question mark +0x00, // '@', No seven-segment conversion for commercial at-sign +0xEE, // 'A' +0x3E, // 'B', Actually displayed as 'b' +0x9C, // 'C' +0x7A, // 'D', Actually displayed as 'd' +0x9E, // 'E' +0x8E, // 'F' +0xBC, // 'G', Actually displayed as 'g' +0x6E, // 'H' +0x60, // 'I', Same as '1' +0x78, // 'J' +0x00, // 'K', No seven-segment conversion +0x1C, // 'L' +0x6E, // 'M', No seven-segment conversion +0x2A, // 'N', Actually displayed as 'n' +0xFC, // 'O', Same as '0' +0xCE, // 'P' +0x00, // 'Q', No seven-segment conversion +0x0A, // 'R', Actually displayed as 'r' +0xB6, // 'S', Same as '5' +0x1E, // 'T', Actually displayed as 't' +0x7C, // 'U' +0x00, // 'V', No seven-segment conversion +0x00, // 'W', No seven-segment conversion +0x00, // 'X', No seven-segment conversion +0x76, // 'Y' +0x00, // 'Z', No seven-segment conversion +0x00, // '[' +0x00, // '\', No seven-segment conversion +0x00, // ']' +0x00, // '^', No seven-segment conversion +0x00, // '_', Underscore +0x00, // '`', No seven-segment conversion for reverse quote +0xFA, // 'a' +0x3E, // 'b' +0x1A, // 'c' +0x7A, // 'd' +0xDE, // 'e' +0x8E, // 'f', Actually displayed as 'F' +0xBC, // 'g' +0x2E, // 'h' +0x20, // 'i' +0x78, // 'j', Actually displayed as 'J' +0x00, // 'k', No seven-segment conversion +0x1C, // 'l', Actually displayed as 'L' +0x00, // 'm', No seven-segment conversion +0x2A, // 'n' +0x3A, // 'o' +0xCE, // 'p', Actually displayed as 'P' +0x00, // 'q', No seven-segment conversion +0x0A, // 'r' +0xB6, // 's', Actually displayed as 'S' +0x1E, // 't' +0x38, // 'u' +0x00, // 'v', No seven-segment conversion +0x00, // 'w', No seven-segment conversion +0x00, // 'x', No seven-segment conversion +0x76, // 'y', Actually displayed as 'Y' +0x00 // 'z', No seven-segment conversion +}; + +/* +********************************************************************************************************* +* DISPLAY ASCII STRING ON SEVEN-SEGMENT DISPLAY +* +* Description: This function is called to display an ASCII string on the seven-segment display. +* Arguments : dig is the position of the first digit where the string will appear: +* 0 for the first seven-segment digit. +* 1 for the second seven-segment digit. +* . . . . . . . +* . . . . . . . +* DISP_N_SS - 1 is the last seven-segment digit. +* s is the ASCII string to display +* Returns : none +* Notes : - Not all ASCII characters can be displayed on a seven-segment display. Consult the +* ASCII to seven-segment conversion table DispASCIItoSegTbl[]. +********************************************************************************************************* +*/ + +void DispStr (INT8U offset, INT8U *s) +{ + int dig = 0; + register INT8U* p; + register INT8U c; + while (dig < DIGIT_NR) { + p = DispSegTbl[dig]; + c = *(offset+s); + *p = DispASCIItoSegTbl[c - 0x20]; + dig++; + s++; + } +} + +void DispWord(INT16U word) +{ + unsigned char *(*p); + + + unsigned int pos, i; + + p=DispSegTbl; + + + for(i=0;i<4;i++) + { + pos = (word>>12)&15; + word<<=4; + + if( pos>9 ) + { + pos = pos-10+'A'-'0'; + } + + *(*p++) = DispASCIItoSegTbl[pos + 0x10]; + } + + + +} + +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.h =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.h (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.h (revision 29) @@ -0,0 +1,8 @@ +#ifndef GRAY_H +#define GRAY_H + +unsigned char bin2gray(unsigned char); +unsigned char gray2bin(unsigned char); + +#endif +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/gray.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.a43 =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.a43 (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.a43 (revision 29) @@ -0,0 +1,53 @@ +:10F0000031400006B240805A20013F4006000F9375 +:10F0100005242F839F4FF6F20002FB233F4081031C +:10F020000F9304241F83CF430602FC233040AAF031 +:10F03000304034F000130F120E120D120C12C29356 +:10F0400000020824C2430002925302021F4202023D +:10F05000B012EAF13C413D413E413F41B1C0F000B8 +:10F06000000000130F120E120D120C12D25386055F +:10F07000F2B0400086050F24F2F03F008605D24230 +:10F08000040219005F420402B01242F25F53B01250 +:10F0900036F2C24F040292C360013C413D413E4101 +:10F0A0003F41B1C0F0000000001331400006B24003 +:10F0B000805A2001C2432100C2432900C2432200DA +:10F0C000C2432A00F2431A00C2432400C2432C0068 +:10F0D000C2432500C2432D00B240185A200182438A +:10F0E0007001B24022026001D2D3000032D23F4010 +:10F0F0000602B012D2F23E40C6033F400602B012F2 +:10F10000E2F23B40E8033F400602B01266F23B5396 +:10F11000FA233B40E8033F40C603B01266F23B537C +:10F12000FA233E40C6033F400602B012B2F20F93EC +:10F130000224D25300023B40E8033F400602B012D3 +:10F1400066F23B53FA23E53F3040F4F2930092001D +:10F150009100900000004400000000409CF000007E +:10F1600000020000FC60DAF266B6BEE0FEF60000C7 +:10F17000001200CA00EE3E9C7A9E8EBC6E60780043 +:10F180001C6E2AFCCE000AB61E7C00000076000031 +:10F190000000000000FA3E1A7ADE8EBC2E207800B5 +:10F1A0001C002A3ACE000AB61E3800000076000085 +:10F1B0000B120A1209120D4E0C434B4F39404CF101 +:10F1C0003A4054F10F4C0F5F0F592E4F0F4D0F5B0C +:10F1D0006F4F0F5ADE4FE0FF00001C531D532C925F +:10F1E000F13B39413A413B4130410B120A120D4F7C +:10F1F0003B404CF10C433A4054F10F4D8F104E4FB1 +:10F2000012C30E100E110E110E113EF00F000D5D07 +:10F210000D5D0D5D0D5D3E900A0002283E50070019 +:10F220003F4B0E5ADF4E100000001C532C92E52B72 +:10F230003A413B4130414E4F12C34E104EEF4F4EBC +:10F2400030414E4F12C34F104FEE4E4F12C34E106F +:10F250004E114FEE4E4F12C34E104E114E114E1125 +:10F260004FEE7FF330410B120A120A4F0B4F1B5324 +:10F270000C4B0E4F3E503F003D4080016F4F6F5C86 +:10F28000CE4F00001C530F4B1E533D5303240B4F16 +:10F290001B53F43F0E4A0F4A3F5080013D403F0050 +:10F2A000EE4F00001F531E533D53FA233A413B419A +:10F2B00030410B120B4F0C4E3D40C0003E4C3F4BBB +:10F2C0000F9E04203D53FA231F43013C0F433B4153 +:10F2D00030413E40C000DFD300001F533E53FB23AC +:10F2E00030413D40C000EE4F00001F531E533D53C0 +:06F2F000FA233041FF3F4C +:06F2F6000100FFFF000013 +:10FFE00030F030F030F030F030F030F030F030F011 +:10FFF00064F030F036F030F030F030F030F000F0F7 +:040000030000F00009 +:00000001FF
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.a43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.h =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.h (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.h (revision 29) @@ -0,0 +1,74 @@ +/* +********************************************************************************************************* +* +* Multiplexed LED Display Driver +* Reference: Jean J. Labrosse, Embedded Systems Building Blocks +* +* Filename : LED.C +* Programmer : John Leung (www.TechToys.com.hk) +* Remarks : Modified for PIC16-LEDSTK1 +* Date : First version 1.0 on 19th Nov 2004 +* Language : CCS C complier for PIC mid-range MCU, PCM version 3.170, under MPLAB IDE 7.01 +* Hardware : PCB 11OCT2004.001, MCU is Microchip's PIC16F877a +* History : Modified for PIC16-LEDSTK1 dated 12 Jan 2006 +********************************************************************************************************* +* DESCRIPTION +* +* This module provides an interface to a multiplexed "7-segments x N digits" LED matrix. +* +* To use this driver: +* +* 1) To use this module, the following parameters under define (LED.H): +* +* DISP_N_DIG The total number of segments to display, inc. dp status +* DISP_N_SS The total number of seven-segment digits, e.g "0" "1" "2" is 3-digit +* DISP_PORT1_DIG The address of the DIGITS output port +* DISP_PORT_SEG The address of the SEGMENTS output port +* first_dig_msk The first digit mask for selecting the most significant digit +* +* 2) Allocate a hardware timer which will interrupt the CPU at a rate of at least: +* +* DISP_N_DIG * 60 (Hz) +* +********************************************************************************************************* +*/ +#ifndef _7SEG_H +#define _7SEG_H + +/* +********************************************************************************************************* +* CONSTANTS +********************************************************************************************************* +*/ +#include +#include +#include + +typedef unsigned char INT8U; +typedef unsigned int INT16U; + + +// Four-Digit, Seven-Segment LED Display driver +#define DIGIT0_ 0x0090 +sfrb (DIGIT0,DIGIT0_); +#define DIGIT1_ 0x0091 +sfrb (DIGIT1,DIGIT1_); +#define DIGIT2_ 0x0092 +sfrb (DIGIT2,DIGIT2_); +#define DIGIT3_ 0x0093 +sfrb (DIGIT3,DIGIT3_); + +#define DIGIT_NR 4 /* Total number of seven-segment digits */ + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ + +void DispStr(INT8U offset, INT8U *s); //API to display an ASCII string + +void DispWord(INT16U word); + + +#endif // _7SEG_H
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/7seg.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld (revision 29) @@ -0,0 +1,235 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430") +OUTPUT_ARCH(msp:110) +MEMORY +{ + text (rx) : ORIGIN = 0xf000, LENGTH = 0x0fe0 + data (rwx) : ORIGIN = 0x0200, LENGTH = 1024 + vectors (rw) : ORIGIN = 0xffe0, LENGTH = 32 + bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K + infomem(rx) : ORIGIN = 0x1000, LENGTH = 256 + infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 256 +} +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + /* Internal text space. */ + .text : + { + . = ALIGN(2); + *(.init) + KEEP(*(.init)) + *(.init0) /* Start here after reset. */ + KEEP(*(.init0)) + *(.init1) /* User definable. */ + KEEP(*(.init1)) + *(.init2) /* Initialize stack. */ + KEEP(*(.init2)) + *(.init3) /* Initialize hardware, user definable. */ + KEEP(*(.init3)) + *(.init4) /* Copy data to .data, clear bss. */ + KEEP(*(.init4)) + *(.init5) /* User definable. */ + KEEP(*(.init5)) + *(.init6) /* C++ constructors. */ + KEEP(*(.init6)) + *(.init7) /* User definable. */ + KEEP(*(.init7)) + *(.init8) /* User definable. */ + KEEP(*(.init8)) + *(.init9) /* Call main(). */ + KEEP(*(.init9)) + __ctors_start = . ; + *(.ctors) + KEEP(*(.ctors)) + __ctors_end = . ; + __dtors_start = . ; + *(.dtors) + KEEP(*(.dtors)) + __dtors_end = . ; + . = ALIGN(2); + *(.text) + . = ALIGN(2); + *(.text.*) + . = ALIGN(2); + *(.fini9) /* Jumps here after main(). User definable. */ + KEEP(*(.fini9)) + *(.fini8) /* User definable. */ + KEEP(*(.fini8)) + *(.fini7) /* User definable. */ + KEEP(*(.fini7)) + *(.fini6) /* C++ destructors. */ + KEEP(*(.fini6)) + *(.fini5) /* User definable. */ + KEEP(*(.fini5)) + *(.fini4) /* User definable. */ + KEEP(*(.fini4)) + *(.fini3) /* User definable. */ + KEEP(*(.fini3)) + *(.fini2) /* User definable. */ + KEEP(*(.fini2)) + *(.fini1) /* User definable. */ + KEEP(*(.fini1)) + *(.fini0) /* Infinite loop after program termination. */ + KEEP(*(.fini0)) + *(.fini) + KEEP(*(.fini)) + _etext = .; + } > text + .data : + { + PROVIDE (__data_start = .) ; + . = ALIGN(2); + *(.data) + *(SORT_BY_ALIGNMENT(.data.*)) + . = ALIGN(2); + *(.gnu.linkonce.d*) + . = ALIGN(2); + _edata = . ; + } > data AT > text + PROVIDE (__data_load_start = LOADADDR(.data) ); + PROVIDE (__data_size = SIZEOF(.data) ); + /* Bootloader. */ + .bootloader : + { + PROVIDE (__boot_start = .) ; + *(.bootloader) + . = ALIGN(2); + *(.bootloader.*) + } > bootloader + /* Information memory. */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + /* Information memory (not loaded into MPU). */ + .infomemnobits : + { + *(.infomemnobits) + . = ALIGN(2); + *(.infomemnobits.*) + } > infomemnobits + .bss : + { + PROVIDE (__bss_start = .) ; + *(.bss) + *(SORT_BY_ALIGNMENT(.bss.*)) + *(COMMON) + PROVIDE (__bss_end = .) ; + _end = . ; + } > data + PROVIDE (__bss_size = SIZEOF(.bss) ); + .noinit : + { + PROVIDE (__noinit_start = .) ; + *(.noinit) + *(.noinit.*) + *(COMMON) + PROVIDE (__noinit_end = .) ; + _end = . ; + } > data + .vectors : + { + PROVIDE (__vectors_start = .) ; + *(.vectors*) + KEEP(*(.vectors*)) + _vectors_end = . ; + } > vectors + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + PROVIDE (__stack = 0x600) ; + PROVIDE (__data_start_rom = _etext) ; + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; + PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ; + PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ; + PROVIDE (__subdevice_has_heap = 0) ; +}
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/README =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/README (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/README (revision 29) @@ -0,0 +1,21 @@ +This project is for altera DE1 implementation of OpenMSP430 core and periphery. +It is adopted from original "leds" project. + +It does simple things using two periodic interrupts (from watchdog and +from timerA), also it tests extensively RAM by creating some continuous +traffic with it. + +It is tuned for non-standard sizes of ROM (4kB or 2kWords) and +RAM (1kB or 512 words), thus it has its own linker script (link.ld). +Also it generates *.mif as a final result to use in Quartus, which, +in turn, is generated from raw *.bin file instead of *.hex. +This is done because Q6.1 can't load byte-wise ihex to the +16bit-wide ROM. + +Warning! You should change the OpenMSP430_defines.v file to adopt for +non-standard memory sizes. + +mifwrite.exe is compiled for win32; you can find its source +in tools/bin + +Any questions? lvd.mhm@gmail.com
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/README Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.c =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.c (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.c (revision 29) @@ -0,0 +1,84 @@ +#include "memtest.h" + + + +void rnd_array( UBYTE * buf ) +// buf points to the array of size $1C0 +{ + + UBYTE *src1, *src2; + UBYTE *dst; + + UWORD loop_ctr; + + + + src1 = buf; + src2 = buf+1; + dst = buf+63; + loop_ctr = 384; + + do + { + *(dst++) = *(src1++) + *(src2++); + } while( --loop_ctr ); + + + + dst = buf; + src1 = buf+384; + loop_ctr = 63; + + do + { + *(dst++) = *(src1++); + } while( --loop_ctr ); +} + +UWORD cmp_array(UBYTE * buf1, UBYTE * buf2) +{ + UWORD loop_ctr; + + UWORD *ptr1, *ptr2; + + ptr1 = (UWORD*)buf1; + ptr2 = (UWORD*)buf2; + + loop_ctr = 384/2; + + do + { + if( *(ptr1++) != *(ptr2++) ) + return 0; + } while( --loop_ctr ); + + return 1; +} + +void init_array(UBYTE * ptr) +{ + UWORD loop_ctr; + + loop_ctr = 384/2; + + do + { + *(ptr++) |= 0x0001; + + } while( --loop_ctr ); +} + + +void copy_array(UBYTE * from, UBYTE * to) +{ + UWORD loop_ctr; + + loop_ctr = 384/2; + + do + { + *(to++) = *(from++); + } while( --loop_ctr ); +} + +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.lst =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.lst (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.lst (revision 29) @@ -0,0 +1,634 @@ + +memledtest.elf: file format elf32-msp430 + +SYMBOL TABLE: +0000f000 l d .text 00000000 .text +00000200 l d .data 00000000 .data +00000206 l d .bss 00000000 .bss +0000ffe0 l d .vectors 00000000 .vectors +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000056 l *ABS* 00000000 DCOCTL +00000057 l *ABS* 00000000 BCSCTL1 +00000058 l *ABS* 00000000 BCSCTL2 +00000128 l *ABS* 00000000 FCTL1 +0000012a l *ABS* 00000000 FCTL2 +0000012c l *ABS* 00000000 FCTL3 +00000054 l *ABS* 00000000 EPCTL +0000012e l *ABS* 00000000 TA0IV +00000160 l *ABS* 00000000 TA0CTL +00000170 l *ABS* 00000000 TA0R +00000162 l *ABS* 00000000 TA0CCTL0 +00000164 l *ABS* 00000000 TA0CCTL1 +00000172 l *ABS* 00000000 TA0CCR0 +00000174 l *ABS* 00000000 TA0CCR1 +00000166 l *ABS* 00000000 TA0CCTL2 +00000176 l *ABS* 00000000 TA0CCR2 +00000020 l *ABS* 00000000 P1IN +00000021 l *ABS* 00000000 P1OUT +00000022 l *ABS* 00000000 P1DIR +00000023 l *ABS* 00000000 P1IFG +00000024 l *ABS* 00000000 P1IES +00000025 l *ABS* 00000000 P1IE +00000026 l *ABS* 00000000 P1SEL +00000028 l *ABS* 00000000 P2IN +00000029 l *ABS* 00000000 P2OUT +0000002a l *ABS* 00000000 P2DIR +0000002b l *ABS* 00000000 P2IFG +0000002c l *ABS* 00000000 P2IES +0000002d l *ABS* 00000000 P2IE +0000002e l *ABS* 00000000 P2SEL +00000059 l *ABS* 00000000 CACTL1 +0000005a l *ABS* 00000000 CACTL2 +0000005b l *ABS* 00000000 CAPD +00000120 l *ABS* 00000000 WDTCTL +00000000 l *ABS* 00000000 IE1 +00000002 l *ABS* 00000000 IFG1 +00000000 l df *ABS* 00000000 main.c +00000202 l O .data 00000002 count.0 +00000204 l O .data 00000001 gray.1 +00000206 l .bss 00000000 array1.2 +000003c6 l .bss 00000000 array2.3 +0000f14c l .text 00000000 Letext +00000000 l df *ABS* 00000000 7seg.c +0000f236 l .text 00000000 Letext +00000000 l df *ABS* 00000000 gray.c +0000f266 l .text 00000000 Letext +00000000 l df *ABS* 00000000 memtest.c +0000f2f4 l .text 00000000 Letext +00000006 g *ABS* 00000000 __data_size +0000f266 g F .text 0000004c rnd_array +0000f2b2 g F .text 00000020 cmp_array +0000f14c g O .text 00000008 DispSegTbl +0000f2f6 g .text 00000000 _etext +00000381 g *ABS* 00000000 __bss_size +0000f2f4 w .text 00000000 __stop_progExec__ +0000f030 g .text 00000000 _unexpected_1_ +0000f030 w .text 00000000 vector_ffe0 +0000f154 g O .text 0000005b DispASCIItoSegTbl +0000f030 w .text 00000000 vector_ffec +0000f064 g .text 00000000 vector_fff0 +0000f2f6 g *ABS* 00000000 __data_load_start +0000f030 g .text 00000000 __dtors_end +0000f236 g F .text 0000000c bin2gray +0000f030 w .text 00000000 vector_fffc +0000f030 w .text 00000000 vector_ffe4 +0000f242 g F .text 00000024 gray2bin +0000ffe0 g O .vectors 00000020 InterruptVectors +00000586 g O .bss 00000001 tctr +0000f01c w .text 00000000 __do_clear_bss +0000f030 w .text 00000000 vector_ffe2 +0000f030 w .text 00000000 vector_ffe8 +0000f034 w .text 00000000 _unexpected_ +0000f030 w .text 00000000 vector_fffa +0000f000 w .text 00000000 _reset_vector__ +0000f030 g .text 00000000 __ctors_start +0000f00a w .text 00000000 __do_copy_data +0000f2d2 g F .text 00000010 init_array +00000206 g .bss 00000000 __bss_start +0000f030 w .text 00000000 vector_ffee +0000f036 g .text 00000000 vector_fff4 +0000f0aa g F .text 000000a2 main +0000f030 w .text 00000000 vector_fff8 +0000f030 w .text 00000000 vector_fff2 +00010000 g .vectors 00000000 _vectors_end +0000f030 w .text 00000000 vector_ffe6 +0000f000 w .text 00000000 __init_stack +0000f030 g .text 00000000 __dtors_start +0000f030 g .text 00000000 __ctors_end +00000600 g *ABS* 00000000 __stack +0000f1ea g F .text 0000004c DispWord +00000206 g .data 00000000 _edata +00000587 g .bss 00000000 _end +00000200 g O .data 00000001 upd_count +0000f2e2 g F .text 00000012 copy_array +0000f030 w .text 00000000 vector_fff6 +0000f1b0 g F .text 0000003a DispStr +0000f004 w .text 00000000 __low_level_init +0000f02c w .text 00000000 __jump_to_main +00000200 g .data 00000000 __data_start +0000f064 g F .text 00000046 INT_Timer_overflow +0000f030 w .text 00000000 vector_ffea +0000f036 g F .text 0000002e INT_Watchdog + + +Disassembly of section .text: + +0000f000 <__init_stack>: + f000: 31 40 00 06 mov #1536, r1 ;#0x0600 + +0000f004 <__low_level_init>: + f004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 + f008: 20 01 + +0000f00a <__do_copy_data>: + f00a: 3f 40 06 00 mov #6, r15 ;#0x0006 + f00e: 0f 93 tst r15 + f010: 05 24 jz $+12 ;abs 0xf01c + f012: 2f 83 decd r15 + f014: 9f 4f f6 f2 mov -3338(r15),512(r15);0xf2f6(r15), 0x0200(r15) + f018: 00 02 + f01a: fb 23 jnz $-8 ;abs 0xf012 + +0000f01c <__do_clear_bss>: + f01c: 3f 40 81 03 mov #897, r15 ;#0x0381 + f020: 0f 93 tst r15 + f022: 04 24 jz $+10 ;abs 0xf02c + f024: 1f 83 dec r15 + f026: cf 43 06 02 mov.b #0, 518(r15);r3 As==00, 0x0206(r15) + f02a: fc 23 jnz $-6 ;abs 0xf024 + +0000f02c <__jump_to_main>: + f02c: 30 40 aa f0 br #0xf0aa + +0000f030 <__ctors_end>: + f030: 30 40 34 f0 br #0xf034 + +0000f034 <_unexpected_>: + f034: 00 13 reti + +0000f036 : + + +volatile unsigned char upd_count=1; + +wakeup interrupt (WDT_VECTOR) INT_Watchdog(void) +{ + f036: 0f 12 push r15 + f038: 0e 12 push r14 + f03a: 0d 12 push r13 + f03c: 0c 12 push r12 + static unsigned int count=0xFFFF; + + if( upd_count ) + f03e: c2 93 00 02 tst.b &0x0200 + f042: 08 24 jz $+18 ;abs 0xf054 + { + upd_count=0; + f044: c2 43 00 02 mov.b #0, &0x0200 ;r3 As==00 + count++; + f048: 92 53 02 02 inc &0x0202 + + DispWord(count); + f04c: 1f 42 02 02 mov &0x0202,r15 + f050: b0 12 ea f1 call #0xf1ea + } +} + f054: 3c 41 pop r12 + f056: 3d 41 pop r13 + f058: 3e 41 pop r14 + f05a: 3f 41 pop r15 + f05c: b1 c0 f0 00 bic #240, 0(r1) ;#0x00f0, 0x0000(r1) + f060: 00 00 + f062: 00 13 reti + +0000f064 : + + +volatile unsigned char tctr; + +wakeup interrupt (TIMERA1_VECTOR) INT_Timer_overflow(void) +{ + f064: 0f 12 push r15 + f066: 0e 12 push r14 + f068: 0d 12 push r13 + f06a: 0c 12 push r12 + static unsigned char gray=0; + + tctr++; + f06c: d2 53 86 05 inc.b &0x0586 + if( tctr&0x40 ) + f070: f2 b0 40 00 bit.b #64, &0x0586 ;#0x0040 + f074: 86 05 + f076: 0f 24 jz $+32 ;abs 0xf096 + { + tctr&=0x3F; + f078: f2 f0 3f 00 and.b #63, &0x0586 ;#0x003f + f07c: 86 05 + + P3OUT = gray; + f07e: d2 42 04 02 mov.b &0x0204,&0x0019 + f082: 19 00 + gray = bin2gray( 1 + gray2bin( gray ) ); + f084: 5f 42 04 02 mov.b &0x0204,r15 + f088: b0 12 42 f2 call #0xf242 + f08c: 5f 53 inc.b r15 + f08e: b0 12 36 f2 call #0xf236 + f092: c2 4f 04 02 mov.b r15, &0x0204 + } + + TACTL &= ~TAIFG; // clear int flag + f096: 92 c3 60 01 bic #1, &0x0160 ;r3 As==01 +} + f09a: 3c 41 pop r12 + f09c: 3d 41 pop r13 + f09e: 3e 41 pop r14 + f0a0: 3f 41 pop r15 + f0a2: b1 c0 f0 00 bic #240, 0(r1) ;#0x00f0, 0x0000(r1) + f0a6: 00 00 + f0a8: 00 13 reti + +0000f0aa
: + + +/** +Main function with some blinking leds +*/ +int main(void) { + f0aa: 31 40 00 06 mov #1536, r1 ;#0x0600 + int i; + + + int o = 0; + + WDTCTL = WDTPW | WDTHOLD; // Disable watchdog timer + f0ae: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 + f0b2: 20 01 + + P1OUT = 0x00; // Port data output + f0b4: c2 43 21 00 mov.b #0, &0x0021 ;r3 As==00 + P2OUT = 0x00; + f0b8: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 + + P1DIR = 0x00; // Port direction register + f0bc: c2 43 22 00 mov.b #0, &0x0022 ;r3 As==00 + P2DIR = 0x00; + f0c0: c2 43 2a 00 mov.b #0, &0x002a ;r3 As==00 + P3DIR = 0xff; + f0c4: f2 43 1a 00 mov.b #-1, &0x001a ;r3 As==11 + + P1IES = 0x00; // Port interrupt enable (0=dis 1=enabled) + f0c8: c2 43 24 00 mov.b #0, &0x0024 ;r3 As==00 + P2IES = 0x00; + f0cc: c2 43 2c 00 mov.b #0, &0x002c ;r3 As==00 + P1IE = 0x00; // Port interrupt Edge Select (0=pos 1=neg) + f0d0: c2 43 25 00 mov.b #0, &0x0025 ;r3 As==00 + P2IE = 0x00; + f0d4: c2 43 2d 00 mov.b #0, &0x002d ;r3 As==00 + + WDTCTL = WDTPW | WDTTMSEL | WDTCNTCL;// | WDTIS1 | WDTIS0 ; // Configure watchdog interrupt + f0d8: b2 40 18 5a mov #23064, &0x0120 ;#0x5a18 + f0dc: 20 01 + + + + TAR = 0x0000; + f0de: 82 43 70 01 mov #0, &0x0170 ;r3 As==00 + TACTL = TASSEL1 | MC1 | TAIE; // run on smclk, no div, count to ffff, interrupt + f0e2: b2 40 22 02 mov #546, &0x0160 ;#0x0222 + f0e6: 60 01 + + + + + IE1 |= 0x01; + f0e8: d2 d3 00 00 bis.b #1, &0x0000 ;r3 As==01 + eint(); //enable interrupts + f0ec: 32 d2 eint + + + + + init_array(array1); + f0ee: 3f 40 06 02 mov #518, r15 ;#0x0206 + f0f2: b0 12 d2 f2 call #0xf2d2 + copy_array(array1,array2); + f0f6: 3e 40 c6 03 mov #966, r14 ;#0x03c6 + f0fa: 3f 40 06 02 mov #518, r15 ;#0x0206 + f0fe: b0 12 e2 f2 call #0xf2e2 + + i=1000; + f102: 3b 40 e8 03 mov #1000, r11 ;#0x03e8 + do + { + rnd_array(array1); + f106: 3f 40 06 02 mov #518, r15 ;#0x0206 + f10a: b0 12 66 f2 call #0xf266 + + } while( --i ); + f10e: 3b 53 add #-1, r11 ;r3 As==11 + f110: fa 23 jnz $-10 ;abs 0xf106 + + + + while (1) + { + i=1000; + f112: 3b 40 e8 03 mov #1000, r11 ;#0x03e8 + do rnd_array(array2); while( --i ); + f116: 3f 40 c6 03 mov #966, r15 ;#0x03c6 + f11a: b0 12 66 f2 call #0xf266 + f11e: 3b 53 add #-1, r11 ;r3 As==11 + f120: fa 23 jnz $-10 ;abs 0xf116 + + if( cmp_array(array1,array2) ) + f122: 3e 40 c6 03 mov #966, r14 ;#0x03c6 + f126: 3f 40 06 02 mov #518, r15 ;#0x0206 + f12a: b0 12 b2 f2 call #0xf2b2 + f12e: 0f 93 tst r15 + f130: 02 24 jz $+6 ;abs 0xf136 + { + upd_count++; + f132: d2 53 00 02 inc.b &0x0200 + } + + i=1000; + f136: 3b 40 e8 03 mov #1000, r11 ;#0x03e8 + do rnd_array(array1); while( --i ); + f13a: 3f 40 06 02 mov #518, r15 ;#0x0206 + f13e: b0 12 66 f2 call #0xf266 + f142: 3b 53 add #-1, r11 ;r3 As==11 + f144: fa 23 jnz $-10 ;abs 0xf13a + f146: e5 3f jmp $-52 ;abs 0xf112 + } +} + f148: 30 40 f4 f2 br #0xf2f4 + +0000f14c : + f14c: 93 00 92 00 91 00 90 00 ........ + +0000f154 : + f154: 00 00 44 00 00 00 00 40 9c f0 00 00 00 02 00 00 ..D....@........ + f164: fc 60 da f2 66 b6 be e0 fe f6 00 00 00 12 00 ca .`..f........... + f174: 00 ee 3e 9c 7a 9e 8e bc 6e 60 78 00 1c 6e 2a fc ..>.z...n`x..n*. + f184: ce 00 0a b6 1e 7c 00 00 00 76 00 00 00 00 00 00 .....|...v...... + f194: 00 fa 3e 1a 7a de 8e bc 2e 20 78 00 1c 00 2a 3a ..>.z.... x...*: + f1a4: ce 00 0a b6 1e 38 00 00 00 76 00 00 .....8...v.. + +0000f1b0 : + f1b0: 0b 12 push r11 + f1b2: 0a 12 push r10 + f1b4: 09 12 push r9 + f1b6: 0d 4e mov r14, r13 + f1b8: 0c 43 clr r12 + f1ba: 4b 4f mov.b r15, r11 + f1bc: 39 40 4c f1 mov #-3764, r9 ;#0xf14c + f1c0: 3a 40 54 f1 mov #-3756, r10 ;#0xf154 + f1c4: 0f 4c mov r12, r15 + f1c6: 0f 5f rla r15 + f1c8: 0f 59 add r9, r15 + f1ca: 2e 4f mov @r15, r14 + f1cc: 0f 4d mov r13, r15 + f1ce: 0f 5b add r11, r15 + f1d0: 6f 4f mov.b @r15, r15 + f1d2: 0f 5a add r10, r15 + f1d4: de 4f e0 ff mov.b -32(r15),0(r14) ;0xffe0(r15), 0x0000(r14) + f1d8: 00 00 + f1da: 1c 53 inc r12 + f1dc: 1d 53 inc r13 + f1de: 2c 92 cmp #4, r12 ;r2 As==10 + f1e0: f1 3b jl $-28 ;abs 0xf1c4 + f1e2: 39 41 pop r9 + f1e4: 3a 41 pop r10 + f1e6: 3b 41 pop r11 + f1e8: 30 41 ret + +0000f1ea : + f1ea: 0b 12 push r11 + f1ec: 0a 12 push r10 + f1ee: 0d 4f mov r15, r13 + f1f0: 3b 40 4c f1 mov #-3764, r11 ;#0xf14c + f1f4: 0c 43 clr r12 + f1f6: 3a 40 54 f1 mov #-3756, r10 ;#0xf154 + f1fa: 0f 4d mov r13, r15 + f1fc: 8f 10 swpb r15 + f1fe: 4e 4f mov.b r15, r14 + f200: 12 c3 clrc + f202: 0e 10 rrc r14 + f204: 0e 11 rra r14 + f206: 0e 11 rra r14 + f208: 0e 11 rra r14 + f20a: 3e f0 0f 00 and #15, r14 ;#0x000f + f20e: 0d 5d rla r13 + f210: 0d 5d rla r13 + f212: 0d 5d rla r13 + f214: 0d 5d rla r13 + f216: 3e 90 0a 00 cmp #10, r14 ;#0x000a + f21a: 02 28 jnc $+6 ;abs 0xf220 + f21c: 3e 50 07 00 add #7, r14 ;#0x0007 + f220: 3f 4b mov @r11+, r15 + f222: 0e 5a add r10, r14 + f224: df 4e 10 00 mov.b 16(r14),0(r15) ;0x0010(r14), 0x0000(r15) + f228: 00 00 + f22a: 1c 53 inc r12 + f22c: 2c 92 cmp #4, r12 ;r2 As==10 + f22e: e5 2b jnc $-52 ;abs 0xf1fa + f230: 3a 41 pop r10 + f232: 3b 41 pop r11 + f234: 30 41 ret + +0000f236 : +#include "hardware.h" +#include "7seg.h" +#include "gray.h" +#include "memtest.h" + + + f236: 4e 4f mov.b r15, r14 + f238: 12 c3 clrc + f23a: 4e 10 rrc.b r14 + f23c: 4e ef xor.b r15, r14 + f23e: 4f 4e mov.b r14, r15 + + f240: 30 41 ret + +0000f242 : + +volatile unsigned char upd_count=1; + + f242: 4e 4f mov.b r15, r14 +wakeup interrupt (WDT_VECTOR) INT_Watchdog(void) +{ + static unsigned int count=0xFFFF; + f244: 12 c3 clrc + f246: 4f 10 rrc.b r15 + f248: 4f ee xor.b r14, r15 + + f24a: 4e 4f mov.b r15, r14 + f24c: 12 c3 clrc + f24e: 4e 10 rrc.b r14 + f250: 4e 11 rra.b r14 + f252: 4f ee xor.b r14, r15 + if( upd_count ) + f254: 4e 4f mov.b r15, r14 + f256: 12 c3 clrc + f258: 4e 10 rrc.b r14 + f25a: 4e 11 rra.b r14 + f25c: 4e 11 rra.b r14 + f25e: 4e 11 rra.b r14 + f260: 4f ee xor.b r14, r15 + { + upd_count=0; + f262: 7f f3 and.b #-1, r15 ;r3 As==11 + count++; + f264: 30 41 ret + +0000f266 : +#include "7seg.h" +#include "gray.h" +#include "memtest.h" + + + + f266: 0b 12 push r11 + f268: 0a 12 push r10 +wakeup interrupt (WDT_VECTOR) INT_Watchdog(void) +{ + static unsigned int count=0xFFFF; + + if( upd_count ) + { + f26a: 0a 4f mov r15, r10 + upd_count=0; + f26c: 0b 4f mov r15, r11 + f26e: 1b 53 inc r11 + f270: 0c 4b mov r11, r12 + count++; + f272: 0e 4f mov r15, r14 + f274: 3e 50 3f 00 add #63, r14 ;#0x003f + + f278: 3d 40 80 01 mov #384, r13 ;#0x0180 + DispWord(count); + } +} + + f27c: 6f 4f mov.b @r15, r15 + f27e: 6f 5c add.b @r12, r15 + f280: ce 4f 00 00 mov.b r15, 0(r14) ;0x0000(r14) + f284: 1c 53 inc r12 + f286: 0f 4b mov r11, r15 + f288: 1e 53 inc r14 + + f28a: 3d 53 add #-1, r13 ;r3 As==11 + f28c: 03 24 jz $+8 ;abs 0xf294 + { + upd_count=0; + count++; + + DispWord(count); + } + f28e: 0b 4f mov r15, r11 + f290: 1b 53 inc r11 + f292: f4 3f jmp $-22 ;abs 0xf27c + + + +volatile unsigned char tctr; + +wakeup interrupt (TIMERA1_VECTOR) INT_Timer_overflow(void) + f294: 0e 4a mov r10, r14 +{ + f296: 0f 4a mov r10, r15 + f298: 3f 50 80 01 add #384, r15 ;#0x0180 + static unsigned char gray=0; + f29c: 3d 40 3f 00 mov #63, r13 ;#0x003f + + tctr++; + if( tctr&0x40 ) + { + f2a0: ee 4f 00 00 mov.b @r15, 0(r14) ;0x0000(r14) + f2a4: 1f 53 inc r15 + f2a6: 1e 53 inc r14 + tctr&=0x3F; + f2a8: 3d 53 add #-1, r13 ;r3 As==11 + f2aa: fa 23 jnz $-10 ;abs 0xf2a0 + + f2ac: 3a 41 pop r10 + f2ae: 3b 41 pop r11 + f2b0: 30 41 ret + +0000f2b2 : + P3OUT = gray; + gray = bin2gray( 1 + gray2bin( gray ) ); + } + f2b2: 0b 12 push r11 + + TACTL &= ~TAIFG; // clear int flag +} + + + f2b4: 0b 4f mov r15, r11 + + f2b6: 0c 4e mov r14, r12 + +/** + f2b8: 3d 40 c0 00 mov #192, r13 ;#0x00c0 +Main function with some blinking leds +*/ +int main(void) { + + f2bc: 3e 4c mov @r12+, r14 + f2be: 3f 4b mov @r11+, r15 + f2c0: 0f 9e cmp r14, r15 + f2c2: 04 20 jnz $+10 ;abs 0xf2cc + + + f2c4: 3d 53 add #-1, r13 ;r3 As==11 + f2c6: fa 23 jnz $-10 ;abs 0xf2bc + + static UBYTE array1[448]; + f2c8: 1f 43 mov #1, r15 ;r3 As==01 + f2ca: 01 3c jmp $+4 ;abs 0xf2ce +/** +Main function with some blinking leds +*/ +int main(void) { + + + f2cc: 0f 43 clr r15 + + + static UBYTE array1[448]; + static UBYTE array2[448]; + f2ce: 3b 41 pop r11 + f2d0: 30 41 ret + +0000f2d2 : + + + + int i; + + + f2d2: 3e 40 c0 00 mov #192, r14 ;#0x00c0 + int o = 0; + + WDTCTL = WDTPW | WDTHOLD; // Disable watchdog timer + + f2d6: df d3 00 00 bis.b #1, 0(r15) ;r3 As==01, 0x0000(r15) + f2da: 1f 53 inc r15 + P1OUT = 0x00; // Port data output + P2OUT = 0x00; + f2dc: 3e 53 add #-1, r14 ;r3 As==11 + f2de: fb 23 jnz $-8 ;abs 0xf2d6 + + f2e0: 30 41 ret + +0000f2e2 : + P2DIR = 0x00; + P3DIR = 0xff; + + P1IES = 0x00; // Port interrupt enable (0=dis 1=enabled) + P2IES = 0x00; + P1IE = 0x00; // Port interrupt Edge Select (0=pos 1=neg) + f2e2: 3d 40 c0 00 mov #192, r13 ;#0x00c0 + P2IE = 0x00; + + WDTCTL = WDTPW | WDTTMSEL | WDTCNTCL;// | WDTIS1 | WDTIS0 ; // Configure watchdog interrupt + + f2e6: ee 4f 00 00 mov.b @r15, 0(r14) ;0x0000(r14) + f2ea: 1f 53 inc r15 + f2ec: 1e 53 inc r14 + + f2ee: 3d 53 add #-1, r13 ;r3 As==11 + f2f0: fa 23 jnz $-10 ;abs 0xf2e6 + + f2f2: 30 41 ret + +0000f2f4 <__stop_progExec__>: + f2f4: ff 3f jmp $+0 ;abs 0xf2f4 +Disassembly of section .vectors: + +0000ffe0 : + ffe0: 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 30 f0 0.0.0.0.0.0.0.0. + fff0: 64 f0 30 f0 36 f0 30 f0 30 f0 30 f0 30 f0 00 f0 d.0.6.0.0.0.0...
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.lst Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.h =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.h (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.h (revision 29) @@ -0,0 +1,15 @@ +#ifndef MEMTEST_H +#define MEMTEST_H + +typedef unsigned char UBYTE; +typedef unsigned int UWORD; + +void rnd_array(UBYTE * buf); +UWORD cmp_array(UBYTE * buf1, UBYTE * buf2); +void init_array(UBYTE * ptr); +void copy_array(UBYTE * from, UBYTE * to); + + + +#endif +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memtest.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/main.c =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/main.c (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/main.c (revision 29) @@ -0,0 +1,121 @@ +#include "hardware.h" +#include "7seg.h" +#include "gray.h" +#include "memtest.h" + + + + +volatile unsigned char upd_count=1; + +wakeup interrupt (WDT_VECTOR) INT_Watchdog(void) +{ + static unsigned int count=0xFFFF; + + if( upd_count ) + { + upd_count=0; + count++; + + DispWord(count); + } +} + + + +volatile unsigned char tctr; + +wakeup interrupt (TIMERA1_VECTOR) INT_Timer_overflow(void) +{ + static unsigned char gray=0; + + tctr++; + if( tctr&0x40 ) + { + tctr&=0x3F; + + P3OUT = gray; + gray = bin2gray( 1 + gray2bin( gray ) ); + } + + TACTL &= ~TAIFG; // clear int flag +} + + + + +/** +Main function with some blinking leds +*/ +int main(void) { + + + + + static UBYTE array1[448]; + static UBYTE array2[448]; + + + + int i; + + + int o = 0; + + WDTCTL = WDTPW | WDTHOLD; // Disable watchdog timer + + P1OUT = 0x00; // Port data output + P2OUT = 0x00; + + P1DIR = 0x00; // Port direction register + P2DIR = 0x00; + P3DIR = 0xff; + + P1IES = 0x00; // Port interrupt enable (0=dis 1=enabled) + P2IES = 0x00; + P1IE = 0x00; // Port interrupt Edge Select (0=pos 1=neg) + P2IE = 0x00; + + WDTCTL = WDTPW | WDTTMSEL | WDTCNTCL;// | WDTIS1 | WDTIS0 ; // Configure watchdog interrupt + + + + TAR = 0x0000; + TACTL = TASSEL1 | MC1 | TAIE; // run on smclk, no div, count to ffff, interrupt + + + + + IE1 |= 0x01; + eint(); //enable interrupts + + + + + init_array(array1); + copy_array(array1,array2); + + i=1000; + do + { + rnd_array(array1); + + } while( --i ); + + + + while (1) + { + i=1000; + do rnd_array(array2); while( --i ); + + if( cmp_array(array1,array2) ) + { + upd_count++; + } + + i=1000; + do rnd_array(array1); while( --i ); + } +} +
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/main.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf (revision 29)
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin (revision 29)
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/makefile =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/makefile (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/makefile (revision 29) @@ -0,0 +1,70 @@ +# makfile configuration +NAME = memledtest +OBJECTS = main.o 7seg.o gray.o memtest.o +CPU = msp430x1121 + +# there is still NO hardware multiplier in openMSP430, unlike in msp430x1121 +CFLAGS = -mmcu=${CPU} -mdisable-hwmul -O2 -Wall -g + +# use custom linker script +LDFLAGS = -mmcu=$(CPU) -Tlink.ld + +#switch the compiler (for the internal make rules) +CC = msp430-gcc +LD = msp430-gcc + + +.PHONY: all FORCE clean download download-jtag download-bsl dist + +#all should be the first target. it's built when make is runwithout args +all: ${NAME}.elf $(NAME).bin ${NAME}.a43 ${NAME}.lst $(NAME).mif + +#confgigure the next line if you want to use the serial download +download: download-uart +#download: download-jtag +#download: download-bsl + +#additional rules for files + +#link everything together +${NAME}.elf: ${OBJECTS} + ${LD} $(LDFLAGS) -o $@ ${OBJECTS} + +# binary image, then .MIF file for quartus +${NAME}.bin: ${NAME}.elf + msp430-objcopy -O binary --gap-fill 255 $^ $@ +$(NAME).mif: $(NAME).bin + ../bin/mifwrite $^ $@ + +# ihex image +${NAME}.a43: ${NAME}.elf + msp430-objcopy -O ihex $^ $@ + +# disassembler file +${NAME}.lst: ${NAME}.elf + msp430-objdump -dSt $^ >$@ + +download-jtag: all + msp430-jtag -e ${NAME}.elf + +download-bsl: all + msp430-bsl -e ${NAME}.elf + +download-uart: all + openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf + +clean: + rm -f ${NAME} ${NAME}.a43 ${NAME}.lst $(NAME).bin $(NAME).mif $(NAME).elf *.o + +#backup archive +dist: + tar czf dist.tgz *.c *.h *.txt makefile + +#dummy target as dependecy if something has to be build everytime +FORCE: + +#project dependencies +main.o: main.c hardware.h 7seg.h +7seg.o: 7seg.c 7seg.h +gray.o: gray.c gray.h +memtest.o: memtest.c memtest.h
openmsp430/trunk/fpga/altera_de1_board/software/memledtest/makefile Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.mif =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.mif (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.mif (revision 29) @@ -0,0 +1,2057 @@ +DEPTH = 2048; +WIDTH = 16; + +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT + BEGIN +[0..7ff] : 0; +0000 : 4031; +0001 : 0600; +0002 : 40b2; +0003 : 5a80; +0004 : 0120; +0005 : 403f; +0006 : 0006; +0007 : 930f; +0008 : 2405; +0009 : 832f; +000a : 4f9f; +000b : f2f6; +000c : 0200; +000d : 23fb; +000e : 403f; +000f : 0381; +0010 : 930f; +0011 : 2404; +0012 : 831f; +0013 : 43cf; +0014 : 0206; +0015 : 23fc; +0016 : 4030; +0017 : f0aa; +0018 : 4030; +0019 : f034; +001a : 1300; +001b : 120f; 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openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.mif Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite (revision 29)
openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.exe =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.exe (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.exe (revision 29)
openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.cpp =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.cpp (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.cpp (revision 29) @@ -0,0 +1,79 @@ +// this prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html +// and slightly changed to satisfy quartus6.1 *.mif eating engine. +// +// it takes binary file of arbitrary length and treating it as collection of 16-bit words, +// writes *.mif file for quartus +// +// + + +#include +#include + +void mifwrite(FILE *in, FILE *out, int offset); + +int main(int argc, char *argv[]) +{ + char *filename; + + if (argc<3) { + printf("usage: mifwrite input_file output_file [offset]\n"); + printf("The default offset is zero"); + return -1; + } + + FILE *in, *out; + filename = argv[1]; + in = fopen(filename,"rb"); + if (!in) { + printf("file: %s not found\n",filename); + return -1; + } + filename = argv[2]; + out = fopen(filename,"wt"); + if (!out) { + printf("file: %s not opened\n",filename); + return -1; + } + int offset = 0; + if (argc>3) sscanf(argv[3],"%x",&offset); + if (offset) printf("address_offset %x\n",offset); + mifwrite(in,out,offset); + return 0; +} + +void mifwrite(FILE *in, FILE *out,int offset) +{ + int count; + unsigned int data; + unsigned int address = 0; + int ndepth; + int nwidth = 16; + + fseek(in,0,SEEK_END); + ndepth = ftell(in)/2; + fseek(in,0,SEEK_SET); + + + fprintf(out,"DEPTH = %d;\n",ndepth); + fprintf(out,"WIDTH = %d;\n\n",nwidth); + fprintf(out,"ADDRESS_RADIX = HEX;\n"); + fprintf(out,"DATA_RADIX = HEX;\n"); + fprintf(out,"CONTENT\n BEGIN\n"); + fprintf(out,"[0..%x] : 0;\n",ndepth-1); + address = 0; + offset = offset>>2; + data=0; + while (count = fread(&data,2,1,in)) { + if (address=ndepth) break; + } + fprintf(out,"END;\n"); + fclose(in); + fclose(out); +}
openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite.cpp Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/fpga/altera_de1_board/README =================================================================== --- openmsp430/trunk/fpga/altera_de1_board/README (nonexistent) +++ openmsp430/trunk/fpga/altera_de1_board/README (revision 29) @@ -0,0 +1,17 @@ +This is OpenMSP430 core+peripherals implementation adapted for Altera DE1 board. + +It is based on original Olivier's adaptation for Diligent S3 board, but has following distinctions: + +1. Fixed 7segment core, since DE1 has non-muxed digits. +2. It is adapted for MegaWizard-generated 16-bit wide on-chip ROMs and RAMs. +3. Debug ROM write is removed (although it shouldn't be a problem to return it back). + Anyway I haven't used any debug features. +4. As an alternative to the embedded synchronous RAM, there is ext_de1_sram module that + allows core to access external on-board static RAM. +5. Core is configured to have non-standard ROM and RAM sizes (4kB and 1kB), so make + sure the OpenMSP430_defines.v file is properly updated +6. There is new software project that uses custom linker script to compile for non-standard + ROM and RAM sizes. + +Any questions? lvd.mhm@gmail.com +
openmsp430/trunk/fpga/altera_de1_board/README Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property

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