URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
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- This comparison shows the changes necessary to convert path
/
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/trunk/rtl/verilog/T6507LP_FSM.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2009/03/09 15:43:46 creep |
// Added the pipelining support for a few addressing modes. Still working on absolute addressing mode. |
// |
// Revision 1.5 2009/03/06 19:58:07 creep |
// Added some simple logic to a few states. Connection with the ALU is pending. |
// |
135,7 → 138,7
FETCH_HIGH: begin |
templow <= data; // data from previous cycle is ready and must be saved |
|
if (immediate) begin |
if (immediate or write) begin |
alu_opcode <= ir; |
alu_a <= data; |
end |
144,6 → 147,7
pc <= {data[4:0], templow}; |
end |
READ_EFFECTIVE: begin |
temphigh <= data; |
address <= {data[4:0], templow}; |
end |
DO_OPERATION: begin |
150,6 → 154,24
alu_opcode <= ir; |
alu_a <= data; |
end |
WRITE_DUMMY: begin |
address <= {temphigh[4:0], templow}; |
data <= data; // TODO: does this works? the spec says this should take 6 cycles... its dumb but we are trying some compatibility here |
control <= WRITE; |
alu_opcode <= ir; |
alu_a <= data; |
end |
WRITE_EFFECTIVE: begin |
if (write) begin |
address <= {data[4:0], templow}; |
end |
else begin |
address <= {temphigh[4:0], templow}; |
end |
|
data <= alu_result; |
control <= WRITE; |
end |
endcase |
end |
end |
179,15 → 201,15
if (jump) begin |
next_state = SET_PC; |
end |
else if (read) begin // (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, NOP) |
else if (read or read_modify_write) begin // TODO: verify if this should stay like this |
// (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, NOP) |
// (ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP) |
// (STA, STX, STY, SAX) |
next_state = READ_EFFECTIVE; |
end |
else if (write) begin |
next_state = WRITE_EFFECTIVE; |
end |
else if (read_modify_write) begin // (ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP) |
next_state = READ_EFFECTIVE; |
end |
else if (write) begin //(STA, STX, STY, SAX) |
|
end |
end |
end |
SET_PC, DO_OPERATION: begin |
197,8 → 219,8
if (read) begin |
next_state = DO_OPERATION; |
end |
else begin |
next_state = |
else if (read_modify_write) begin |
next_state = WRITE_DUMMY; |
end |
end |
endcase |