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Rev 28 → Rev 29

/trunk/rtl/vhdl/T80_MCode.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0238b
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
56,6 → 56,8
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
--
 
library IEEE;
use IEEE.std_logic_1164.all;
64,7 → 66,15
 
entity T80_MCode is
generic(
Mode : integer := 0
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
132,16 → 142,29
cc : bit_vector(2 downto 0)
) return boolean is
begin
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
if Mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
 
begin
300,19 → 323,32
when others => null;
end case;
when "00111010" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
336,20 → 372,34
when others => null;
end case;
when "00110010" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
 
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
377,47 → 427,74
when others => null;
end case;
when "00101010" =>
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
482,41 → 559,87
 
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
-- EX DE,HL
ExchangeDH <= '1';
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
-- EX AF,AF'
ExchangeAF <= '1';
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
-- EXX
ExchangeRS <= '1';
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
 
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
781,115 → 904,186
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(0) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(0) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(6) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(6) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
if Mode = 3 then
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "1010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "1010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
 
-- CALL AND RETURN GROUP
when "11001101" =>
917,33 → 1111,35
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
961,25 → 1157,94
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "1000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "1001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
1002,30 → 1267,34
 
-- INPUT AND OUTPUT GROUP
when "11011011" =>
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
 
------------------------------------------------------------------------------
------------------------------------------------------------------------------
1077,7 → 1346,7
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented)
-- SLL r (Undocumented) / SWAP r
Rot_Op <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
1089,7 → 1358,7
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
1099,9 → 1368,9
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
TStates <= "011";
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
1123,6 → 1392,7
Set_Addr_To <= aXY;
when 2 =>
Bit_Op <= "01";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
1148,6 → 1418,7
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
1175,6 → 1446,7
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
1328,7 → 1600,7
else
IncDec_16 <= "1101";
end if;
if IR(4) = '1' and F(2) = '1' then
if IR(4) = '1' and F(Flag_P) = '1' then
MCycles <= "100";
end if;
when 4 =>
1360,7 → 1632,7
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
if IR(4) = '1' and F(2) = '1' and F(6) = '0' then
if IR(4) = '1' and F(Flag_P) = '1' and F(Flag_Z) = '0' then
MCycles <= "100";
end if;
when 4 =>
1404,6 → 1676,7
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
1417,7 → 1690,6
when others =>
Set_BusB_To <= "1001";
end case;
TStates <= "011";
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
1437,6 → 1709,7
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "1011";
1449,7 → 1722,6
when others =>
Set_BusB_To <= "1001";
end case;
TStates <= "011";
when others =>
end case;
when "01101111" =>
1562,7 → 1834,7
end if;
TStates <= "100";
Write <= '1';
if IR(4) = '1' and F(6) = '0' then
if IR(4) = '1' and F(Flag_Z) = '0' then
MCycles <= "100";
end if;
when 4 =>
1596,7 → 1868,7
IORQ <= '1';
TStates <= "100";
Write <= '1';
if IR(4) = '1' and F(6) = '0' then
if IR(4) = '1' and F(Flag_Z) = '0' then
MCycles <= "100";
end if;
when 4 =>
1618,6 → 1890,42
end if;
end if;
 
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
 
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
Set_Addr_To <= aNone;
if Mode = 1 then
TStates <= "100";
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
end if;
if MCycle = "111" then
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
 
end process;
 
end;
/trunk/rtl/vhdl/T80se.vhd
3,7 → 3,7
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
54,6 → 54,8
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
89,7 → 91,6
 
architecture rtl of T80se is
 
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
124,7 → 125,6
DO => DO,
MC => MCycle,
TS => TState,
False_M1 => False_M1,
IntCycle_n => IntCycle_n);
 
process (RESET_n, CLK_n)
141,7 → 141,7
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" and False_M1 = '0' then
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
/trunk/rtl/vhdl/T80_Pack.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
52,7 → 52,15
 
component T80
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
75,9 → 83,9
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
False_M1 : out std_logic;
IntCycle_n : out std_logic;
IntE : out std_logic
IntE : out std_logic;
Stop : out std_logic
);
end component;
 
85,7 → 93,15
 
component T80_MCode
generic(
Mode : integer := 0
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
147,6 → 163,17
end component;
 
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
/trunk/rtl/vhdl/T80.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
63,6 → 63,8
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
 
library IEEE;
use IEEE.std_logic_1164.all;
71,7 → 73,15
 
entity T80 is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
94,23 → 104,14
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
False_M1 : out std_logic;
IntCycle_n : out std_logic;
IntE : out std_logic
IntE : out std_logic;
Stop : out std_logic
);
end T80;
 
architecture rtl of T80 is
 
constant Flag_C : integer := 0;
constant Flag_N : integer := 1;
constant Flag_P : integer := 2;
constant Flag_X : integer := 3;
constant Flag_H : integer := 4;
constant Flag_Y : integer := 5;
constant Flag_Z : integer := 6;
constant Flag_S : integer := 7;
 
-- Registers
signal ACC, F, B, C, D, E, H, L : std_logic_vector(7 downto 0);
signal Ap, Fp, Bp, Cp, Dp, Ep, Hp, Lp : std_logic_vector(7 downto 0);
137,9 → 138,12
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal XY_Fetch : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
 
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
188,6 → 192,7
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
211,11 → 216,17
 
begin
 
IntE <= IntE_FF1;
 
mcode : T80_MCode
generic map(
Mode => Mode)
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
240,7 → 251,7
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
273,6 → 284,16
Write => Write);
 
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
288,11 → 309,10
F_Out => F_Out,
F_Save => F_Save);
 
T_Res <= '1' when (TState = unsigned(TStates) and XY_Fetch(0) = '0') or
(XY_Fetch(0) = '1' and TState = "111" and Mode = 0) or
(XY_Fetch(0) = '1' and TState = "100" and Mode = 1) else '0';
T_Res <= '1' when TState = unsigned(TStates) else '0';
 
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and ((Set_Addr_To = aXY and IR /= "11001011") or
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
 
352,7 → 372,7
Z16_r <= '0';
end if;
 
if MCycle = "001" and TState(2) = '0' and XY_Fetch(0) = '0' then
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
 
if TState = 2 and Wait_n = '1' then
398,7 → 418,7
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
 
if XY_Fetch(0) = '1' then
if MCycle = "110" then
XY_Ind <= '1';
end if;
 
447,7 → 467,10
end if;
end if;
when aIOA =>
if Mode = 2 then
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
457,8 → 480,14
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
A(15 downto 8) <= B;
A(7 downto 0) <= C;
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= C;
else
A(15 downto 8) <= B;
A(7 downto 0) <= C;
end if;
when aDE =>
A(15 downto 8) <= D;
A(7 downto 0) <= E;
517,7 → 546,7
if TState = 2 and Wait_n = '1' then
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' or XY_Fetch(0) = '1' then
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if I_BTR = '1' then
528,7 → 557,7
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and XY_Fetch = "01" then
if TState = 3 and MCycle = "110" then
if XY_State = "01" then
TmpAddr <= std_logic_vector(signed(IX) + signed(DI_Reg));
end if;
666,10 → 695,19
end if;
 
if (I_DJNZ = '0' and Save_ALU_r = '1') or Bit_Op_r = "01" then
F(7 downto 1) <= (F(7 downto 1) and not F_Save(7 downto 1)) or
(F_Out(7 downto 1) and F_Save(7 downto 1));
if PreserveC_r = '0' and F_Save(0) = '1' then
F(Flag_C) <= F_Out(0);
if Mode = 3 then
F(6) <= (F(6) and not F_Save(1)) or (F_Out(6) and F_Save(1));
F(5) <= (F(5) and not F_Save(4)) or (F_Out(5) and F_Save(4));
F(7) <= (F(7) and not F_Save(6)) or (F_Out(7) and F_Save(6));
if PreserveC_r = '0' and F_Save(0) = '1' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= (F(7 downto 1) and not F_Save(7 downto 1)) or
(F_Out(7 downto 1) and F_Save(7 downto 1));
if PreserveC_r = '0' and F_Save(0) = '1' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
929,16 → 967,18
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
False_M1 <= XY_Fetch(0);
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
 
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
M1_n <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if T_Res = '1' and (MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000")) then
if (T_Res = '1' and (MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000"))) or TState = 0 then
M1_n <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
983,16 → 1023,20
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
BReq_FF <= '0';
Halt_FF <= '0';
BUSAK_n <= '1';
NMICycle <= '0';
IntCycle <= '0';
XY_Fetch <= "00";
IntE_FF1 <= '0';
IntE_FF2 <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
1018,9 → 1062,6
end if;
else
if TState = 2 and Wait_n = '0' then
elsif XY_Fetch = "01" and TState = "100" and Mode = 0 then
XY_Fetch <= "11";
TState <= "011";
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
1030,10 → 1071,18
BUSAK_n <= '0';
else
TState <= "001";
XY_Fetch <= "00";
if NextIs_XY_Fetch = '1' then
XY_Fetch <= "01";
elsif MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000") then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if Set_Addr_To = aNone and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111" and Mode = 0) or
(MCycle = "110" and Prefix /= "01" and Mode = 1) then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
(MCycle = "110" and Prefix = "01") or
(MCycle = "010" and I_DJNZ = '1' and B = "00000000") then
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
1050,7 → 1099,9
end if;
end if;
else
TState <= TState + 1;
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
end if;
1057,4 → 1108,14
end if;
end process;
 
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
 
end;
/trunk/rtl/vhdl/T8080se.vhd
3,7 → 3,7
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
51,6 → 51,8
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
83,7 → 85,6
 
architecture rtl of T8080se is
 
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
140,7 → 141,6
DO => DO_i,
MC => MCycle,
TS => TState,
False_M1 => False_M1,
IntCycle_n => IntCycle_n,
IntE => INTE);
 
154,7 → 154,7
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" and False_M1 = '0' then
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
/trunk/rtl/vhdl/T80_ALU.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
--
48,6 → 48,8
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
 
library IEEE;
use IEEE.std_logic_1164.all;
54,6 → 56,17
use IEEE.numeric_std.all;
 
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
99,15 → 112,6
Res <= std_logic_vector(Res_i(A'length - 1 downto 0));
end;
 
constant Flag_C : integer := 0;
constant Flag_N : integer := 1;
constant Flag_P : integer := 2;
constant Flag_X : integer := 3;
constant Flag_H : integer := 4;
constant Flag_Y : integer := 5;
constant Flag_Z : integer := 6;
constant Flag_S : integer := 7;
 
-- Micro code outputs
signal AALU_Op : std_logic_vector(2 downto 0);
 
321,10 → 325,16
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented)
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
/trunk/rtl/vhdl/T80a.vhd
1,7 → 1,7
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
52,6 → 52,8
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
86,7 → 88,6
 
signal CEN : std_logic;
signal Reset_s : std_logic;
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
139,7 → 140,6
DO => DO,
MC => MCycle,
TS => TState,
False_M1 => False_M1,
IntCycle_n => IntCycle_n);
 
D <= DO when Write = '1' else (others => 'Z');
175,7 → 175,7
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" and False_M1 = '0' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
204,7 → 204,7
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
 
if MCycle = "001" and False_M1 = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
/trunk/rtl/vhdl/T80s.vhd
3,7 → 3,7
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
60,6 → 60,8
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
 
library IEEE;
use IEEE.std_logic_1164.all;
95,7 → 97,6
architecture rtl of T80s is
 
signal CEN : std_logic;
signal False_M1 : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
132,7 → 133,6
DO => DO,
MC => MCycle,
TS => TState,
False_M1 => False_M1,
IntCycle_n => IntCycle_n);
 
process (RESET_n, CLK_n)
148,7 → 148,7
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" and False_M1 = '0' then
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;

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