URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 282 to Rev 283
- ↔ Reverse comparison
Rev 282 → Rev 283
/trunk/COMPILE_LIST
1,7 → 1,7
|
Compile list for the T48 uController project |
============================================ |
Version: $Date: 2006-07-21 23:29:13 $ |
Version: $Date: 2008-04-29 21:16:26 $ |
$Name: not supported by cvs2svn $ |
|
bench/vhdl/if_timing.vhd |
22,13 → 22,9
rtl/vhdl/dmem_ctrl.vhd |
rtl/vhdl/dmem_ctrl-c.vhd |
rtl/vhdl/decoder_pack-p.vhd |
rtl/vhdl/opc_table.vhd |
rtl/vhdl/opc_table-c.vhd |
rtl/vhdl/cond_branch_pack-p.vhd |
rtl/vhdl/alu_pack-p.vhd |
rtl/vhdl/t48_comp_pack-p.vhd |
rtl/vhdl/opc_decoder.vhd |
rtl/vhdl/opc_decoder-c.vhd |
rtl/vhdl/int.vhd |
rtl/vhdl/int-c.vhd |
rtl/vhdl/t48_tb_pack-p.vhd |
/trunk/sim/rtl_sim/Makefile.hier
110,11 → 110,11
$(decoder_pack) |
$(ANALYZE) $< |
|
$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd |
$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd \ |
$(t48_pack) |
$(ANALYZE) $< |
|
$(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \ |
$(opc_decoder_rtl_c0) \ |
$(int_rtl_c0) \ |
$(decoder) |
$(ANALYZE) $< |
139,30 → 139,6
$(int) |
$(ANALYZE) $< |
|
$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \ |
$(decoder_pack) \ |
$(t48_pack) \ |
$(pmem_ctrl_pack) \ |
$(dmem_ctrl_pack) \ |
$(cond_branch_pack) \ |
$(alu_pack) \ |
$(t48_comp_pack) |
$(ANALYZE) $< |
|
$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \ |
$(opc_table_rtl_c0) \ |
$(opc_decoder) |
$(ANALYZE) $< |
|
$(opc_table) : $(RTL_DIR)/opc_table.vhd \ |
$(decoder_pack) \ |
$(t48_pack) |
$(ANALYZE) $< |
|
$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \ |
$(opc_table) |
$(ANALYZE) $< |
|
$(p1) : $(RTL_DIR)/p1.vhd \ |
$(t48_pack) |
$(ANALYZE) $< |
/trunk/sim/rtl_sim/Makefile.ghdl
91,10 → 91,6
p1 = $(LIB_WORK)/p1.o |
timer_rtl_c0 = $(LIB_WORK)/timer-c.o |
timer = $(LIB_WORK)/timer.o |
opc_table_rtl_c0 = $(LIB_WORK)/opc_table-c.o |
opc_table = $(LIB_WORK)/opc_table.o |
opc_decoder_rtl_c0 = $(LIB_WORK)/opc_decoder-c.o |
opc_decoder = $(LIB_WORK)/opc_decoder.o |
int_rtl_c0 = $(LIB_WORK)/int-c.o |
int = $(LIB_WORK)/int.o |
dmem_ctrl_rtl_c0 = $(LIB_WORK)/dmem_ctrl-c.o |
/trunk/syn/t8048/b5x300/gen_ise_project.tcl
1,6 → 1,6
############################################################################### |
# |
# $Id: gen_ise_project.tcl,v 1.1 2008-04-12 21:27:07 arniml Exp $ |
# $Id: gen_ise_project.tcl,v 1.2 2008-04-29 21:16:07 arniml Exp $ |
# |
# Based on |
# Created by Phil Hays, Xilinx |
148,12 → 148,14
|
project set {Optimization Goal} Area -process {Synthesize - XST} |
project set {Optimization Effort} Normal -process {Synthesize - XST} |
project set {Use Synthesis Constraints File} 1 -process {Synthesize - XST} |
|
#project set "Map Effort Level" High |
#project set {Perform Timing-Driven Packing and Placement} 1 |
project set {Place & Route Effort Level (Overall)} Standard |
#project set "Other Place & Route Command Line Options" "-intsyle xflow" |
project set {Generate Post-Place & Route Static Timing Report} true |
project set {Report Uncovered Paths} 10 -process {Generate Post-Place & Route Static Timing} |
project set {Report Unconstrained Paths} 10 -process {Generate Post-Place & Route Static Timing} |
project set {Report Type} {Verbose Report} -process {Generate Post-Place & Route Static Timing} |
project set {Create Binary Configuration File} 1 -process {Generate Programming File} |
|
/trunk/syn/t8048/b5x300/compile_list
8,11 → 8,9
../../../rtl/vhdl/dmem_ctrl_pack-p.vhd |
../../../rtl/vhdl/dmem_ctrl.vhd |
../../../rtl/vhdl/decoder_pack-p.vhd |
../../../rtl/vhdl/opc_table.vhd |
../../../rtl/vhdl/cond_branch_pack-p.vhd |
../../../rtl/vhdl/alu_pack-p.vhd |
../../../rtl/vhdl/t48_comp_pack-p.vhd |
../../../rtl/vhdl/opc_decoder.vhd |
../../../rtl/vhdl/int.vhd |
../../../rtl/vhdl/t48_tb_pack-p.vhd |
../../../rtl/vhdl/decoder.vhd |
/trunk/syn/t8048/jopcyc/t8048.qsf
40,9 → 40,7
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/clock_ctrl.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/cond_branch.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/db_bus.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/opc_table.vhd |
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_comp_pack-p.vhd" |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/opc_decoder.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/decoder.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/dmem_ctrl.vhd |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/int.vhd |
71,5 → 69,3
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" |
set_global_assignment -name FMAX_REQUIREMENT "11 MHz" -section_id xtal |
set_instance_assignment -name CLOCK_SETTINGS xtal -to xtal_i |
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |