URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- This comparison shows the changes necessary to convert path
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- from Rev 283 to Rev 284
- ↔ Reverse comparison
Rev 283 → Rev 284
/trunk/rtl/vhdl/opc_decoder.vhd
File deleted
/trunk/rtl/vhdl/opc_decoder-c.vhd
File deleted
/trunk/rtl/vhdl/opc_table.vhd
File deleted
/trunk/rtl/vhdl/opc_table-c.vhd
File deleted
/trunk/rtl/vhdl/decoder_pack-p.vhd
1,6 → 1,6
------------------------------------------------------------------------------- |
-- |
-- $Id: decoder_pack-p.vhd,v 1.3 2005-06-11 10:08:43 arniml Exp $ |
-- $Id: decoder_pack-p.vhd,v 1.4 2008-04-29 21:19:21 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
8,6 → 8,11
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.t48_pack.word_t; |
|
package t48_decoder_pack is |
|
----------------------------------------------------------------------------- |
71,13 → 76,365
MN_XRL, |
MN_XRL_A_DATA); |
|
type mnemonic_rec_t is |
record |
mnemonic : mnemonic_t; |
multi_cycle : boolean; |
end record; |
|
function decode_opcode_f(opcode : in word_t) return |
mnemonic_rec_t; |
|
end t48_decoder_pack; |
|
|
package body t48_decoder_pack is |
|
function decode_opcode_f(opcode : in word_t) return |
mnemonic_rec_t is |
variable mnemonic_v : mnemonic_t; |
variable multi_cycle_v : boolean; |
variable result_v : mnemonic_rec_t; |
begin |
-- default assignment |
mnemonic_v := MN_NOP; |
multi_cycle_v := false; |
|
case opcode is |
-- Mnemonic ADD --------------------------------------------------------- |
when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr |
"01101100" | "01101101" | "01101110" | "01101111" | -- |
"01100000" | "01100001" | -- ADD A, @ Rr |
"01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr |
"01111100" | "01111101" | "01111110" | "01111111" | -- |
"01110000" | "01110001" => -- ADDC A, @ Rr |
mnemonic_v := MN_ADD; |
|
-- Mnemonic ADD_A_DATA -------------------------------------------------- |
when "00000011" | -- ADD A, data |
"00010011" => -- ADDC A, data |
mnemonic_v := MN_ADD_A_DATA; |
multi_cycle_v := true; |
|
-- Mnemonic ANL --------------------------------------------------------- |
when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr |
"01011100" | "01011101" | "01011110" | "01011111" | -- |
"01010000" | "01010001" => -- ANL A, @ Rr |
mnemonic_v := MN_ANL; |
|
-- Mnemonic ANL_A_DATA -------------------------------------------------- |
when "01010011" => -- ANL A, data |
mnemonic_v := MN_ANL_A_DATA; |
multi_cycle_v := true; |
|
-- Mnemonic ANL_EXT ----------------------------------------------------- |
when "10011000" | -- ANL BUS, data |
"10011001" | "10011010" => -- ANL PP, data |
mnemonic_v := MN_ANL_EXT; |
multi_cycle_v := true; |
|
-- Mnemonic CALL -------------------------------------------------------- |
when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr |
"10010100" | "10110100" | "11010100" | "11110100" => -- |
mnemonic_v := MN_CALL; |
multi_cycle_v := true; |
|
-- Mnemonic CLR_A ------------------------------------------------------- |
when "00100111" => -- CLR A |
mnemonic_v := MN_CLR_A; |
|
-- Mnemonic CLR_C ------------------------------------------------------- |
when "10010111" => -- CLR C |
mnemonic_v := MN_CLR_C; |
|
-- Mnemonic CLR_F ------------------------------------------------------- |
when "10000101" | -- CLR F0 |
"10100101" => |
mnemonic_v := MN_CLR_F; |
|
-- Mnemonic CPL_A ------------------------------------------------------- |
when "00110111" => -- CPL A |
mnemonic_v := MN_CPL_A; |
|
-- Mnemonic CPL_C ------------------------------------------------------- |
when "10100111" => -- CPL C |
mnemonic_v := MN_CPL_C; |
|
-- Mnemonic CPL_F ------------------------------------------------------- |
when "10010101" | -- CPL F0 |
"10110101" => -- CPL F1 |
mnemonic_v := MN_CPL_F; |
|
-- Mnemonic DA ---------------------------------------------------------- |
when "01010111" => -- DA D |
mnemonic_v := MN_DA; |
|
-- Mnemonic DEC --------------------------------------------------------- |
when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr |
"11001100" | "11001101" | "11001110" | "11001111" | -- |
"00000111" => -- DEC A |
mnemonic_v := MN_DEC; |
|
-- Mnemonic DIS_EN_I ---------------------------------------------------- |
when "00010101" | -- DIS I |
"00000101" => -- EN I |
mnemonic_v := MN_DIS_EN_I; |
|
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------ |
when "00110101" | -- DIS TCNTI |
"00100101" => -- EN TCNTI |
mnemonic_v := MN_DIS_EN_TCNTI; |
|
-- Mnemonic DJNZ -------------------------------------------------------- |
when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr |
"11101100" | "11101101" | "11101110" | "11101111" => -- |
mnemonic_v := MN_DJNZ; |
multi_cycle_v := true; |
|
-- Mnemonic ENT0_CLK ---------------------------------------------------- |
when "01110101" => -- ENT0 CLK |
mnemonic_v := MN_ENT0_CLK; |
|
-- Mnemonic IN ---------------------------------------------------------- |
when "00001001" | "00001010" => -- IN A, Pp |
mnemonic_v := MN_IN; |
multi_cycle_v := true; |
|
-- Mnemonic INC --------------------------------------------------------- |
when "00010111" | -- INC A |
"00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr |
"00011100" | "00011101" | "00011110" | "00011111" | -- |
"00010000" | "00010001" => -- INC @ Rr |
mnemonic_v := MN_INC; |
|
-- Mnemonic INS --------------------------------------------------------- |
when "00001000" => -- INS A, BUS |
mnemonic_v := MN_INS; |
multi_cycle_v := true; |
|
-- Mnemonic JBB --------------------------------------------------------- |
when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr |
"10010010" | "10110010" | "11010010" | "11110010" => -- |
mnemonic_v := MN_JBB; |
multi_cycle_v := true; |
|
-- Mnemonic JC ---------------------------------------------------------- |
when "11110110" | -- JC addr |
"11100110" => -- JNC addr |
mnemonic_v := MN_JC; |
multi_cycle_v := true; |
|
-- Mnemonic JF ---------------------------------------------------------- |
when "10110110" | -- JF0 addr |
"01110110" => -- JF1 addr |
mnemonic_v := MN_JF; |
multi_cycle_v := true; |
|
-- Mnemonic JMP --------------------------------------------------------- |
when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr |
"10000100" | "10100100" | "11000100" | "11100100" => -- |
mnemonic_v := MN_JMP; |
multi_cycle_v := true; |
|
-- Mnemonic JMPP -------------------------------------------------------- |
when "10110011" => -- JMPP @ A |
mnemonic_v := MN_JMPP; |
multi_cycle_v := true; |
|
-- Mnemonic JNI --------------------------------------------------------- |
when "10000110" => -- JNI addr |
mnemonic_v := MN_JNI; |
multi_cycle_v := true; |
|
-- Mnemonic JT ---------------------------------------------------------- |
when "00100110" | -- JNT0 addr |
"01000110" | -- JNT1 addr |
"00110110" | -- JT0 addr |
"01010110" => -- JT1 addr |
mnemonic_v := MN_JT; |
multi_cycle_v := true; |
|
-- Mnemonic JTF --------------------------------------------------------- |
when "00010110" => -- JTF addr |
mnemonic_v := MN_JTF; |
multi_cycle_v := true; |
|
-- Mnemonic JZ ---------------------------------------------------------- |
when "10010110" | -- JNZ addr |
"11000110" => -- JZ addr |
mnemonic_v := MN_JZ; |
multi_cycle_v := true; |
|
-- Mnemonic MOV_A_DATA -------------------------------------------------- |
when "00100011" => -- MOV A, data |
mnemonic_v := MN_MOV_A_DATA; |
multi_cycle_v := true; |
|
-- Mnemonic MOV_A_PSW --------------------------------------------------- |
when "11000111" => -- MOV A, PSW |
mnemonic_v := MN_MOV_A_PSW; |
|
-- Mnemonic MOV_A_RR ---------------------------------------------------- |
when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr |
"11111100" | "11111101" | "11111110" | "11111111" | -- |
"11110000" | "11110001" => -- MOV A, @ Rr |
mnemonic_v := MN_MOV_A_RR; |
|
-- Mnemonic MOV_PSW_A --------------------------------------------------- |
when "11010111" => -- MOV PSW, A |
mnemonic_v := MN_MOV_PSW_A; |
|
-- Mnemonic MOV_RR ------------------------------------------------------ |
when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A |
"10101100" | "10101101" | "10101110" | "10101111" | -- |
"10100000" | "10100001" => -- MOV @ Rr, A |
mnemonic_v := MN_MOV_RR; |
|
-- Mnemonic MOV_RR_DATA ------------------------------------------------- |
when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data |
"10111100" | "10111101" | "10111110" | "10111111" | -- |
"10110000" | "10110001" => -- MOV @ Rr, data |
mnemonic_v := MN_MOV_RR_DATA; |
multi_cycle_v := true; |
|
-- Mnemonic MOV_T ------------------------------------------------------- |
when "01100010" | -- MOV T, A |
"01000010" => -- MOV A, T |
mnemonic_v := MN_MOV_T; |
|
-- Mnemonic MOVD_A_PP --------------------------------------------------- |
when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp |
mnemonic_v := MN_MOVD_A_PP; |
multi_cycle_v := true; |
|
-- Mnemonic MOVP -------------------------------------------------------- |
when "10100011" | -- MOVP A, @ A |
"11100011" => -- MOVP3 A, @ A |
mnemonic_v := MN_MOVP; |
multi_cycle_v := true; |
|
-- Mnemonic MOVX -------------------------------------------------------- |
when "10000000" | "10000001" | -- MOVX A, @ Rr |
"10010000" | "10010001" => -- MOVX @ Rr, A |
mnemonic_v := MN_MOVX; |
multi_cycle_v := true; |
|
-- Mnemonic NOP --------------------------------------------------------- |
when "00000000" => -- NOP |
mnemonic_v := MN_NOP; |
|
-- Mnemonic ORL --------------------------------------------------------- |
when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr |
"01001100" | "01001101" | "01001110" | "01001111" | -- |
"01000000" | "01000001" => -- ORL A, @ Rr |
mnemonic_v := MN_ORL; |
|
-- Mnemonic ORL_A_DATA -------------------------------------------------- |
when "01000011" => -- ORL A, data |
mnemonic_v := MN_ORL_A_DATA; |
multi_cycle_v := true; |
|
-- Mnemonic ORL_EXT ----------------------------------------------------- |
when "10001000" | -- ORL BUS, data |
"10001001" | "10001010" => -- ORL Pp, data |
mnemonic_v := MN_ORL_EXT; |
multi_cycle_v := true; |
|
-- Mnemonic OUTD_PP_A --------------------------------------------------- |
when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A |
"10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A |
"10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A |
mnemonic_v := MN_OUTD_PP_A; |
multi_cycle_v := true; |
|
-- Mnemonic OUTL_EXT ---------------------------------------------------- |
when "00111001" | "00111010" | -- OUTL Pp, A |
"00000010" => -- OUTL BUS, A |
mnemonic_v := MN_OUTL_EXT; |
multi_cycle_v := true; |
|
-- Mnemonic RET --------------------------------------------------------- |
when "10000011" | -- RET |
"10010011" => -- RETR |
mnemonic_v := MN_RET; |
multi_cycle_v := true; |
|
-- Mnemonic RL ---------------------------------------------------------- |
when "11100111" | -- RL A |
"11110111" => -- RLC A |
mnemonic_v := MN_RL; |
|
-- Mnemonic RR ---------------------------------------------------------- |
when "01110111" | -- RR A |
"01100111" => -- RRC A |
mnemonic_v := MN_RR; |
|
-- Mnemonic SEL_MB ------------------------------------------------------ |
when "11100101" | -- SEL MB0 |
"11110101" => -- SEL MB1 |
mnemonic_v := MN_SEL_MB; |
|
-- Mnemonic SEL_RB ------------------------------------------------------ |
when "11000101" | -- SEL RB0 |
"11010101" => -- SEL RB1 |
mnemonic_v := MN_SEL_RB; |
|
-- Mnemonic STOP_TCNT --------------------------------------------------- |
when "01100101" => -- STOP TCNT |
mnemonic_v := MN_STOP_TCNT; |
|
-- Mnemonic START ------------------------------------------------------- |
when "01000101" | -- STRT CNT |
"01010101" => -- STRT T |
mnemonic_v := MN_STRT; |
|
-- Mnemonic SWAP -------------------------------------------------------- |
when "01000111" => -- SWAP A |
mnemonic_v := MN_SWAP; |
|
-- Mnemonic XCH --------------------------------------------------------- |
when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr |
"00101100" | "00101101" | "00101110" | "00101111" | -- |
"00100000" | "00100001" | -- XCH A, @ Rr |
"00110000" | "00110001" => -- XCHD A, @ Rr |
mnemonic_v := MN_XCH; |
|
-- Mnemonic XRL --------------------------------------------------------- |
when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr |
"11011100" | "11011101" | "11011110" | "11011111" | -- |
"11010000" | "11010001" => -- XRL A, @ Rr |
mnemonic_v := MN_XRL; |
|
-- Mnemonic XRL_A_DATA -------------------------------------------------- |
when "11010011" => -- XRL A, data |
mnemonic_v := MN_XRL_A_DATA; |
multi_cycle_v := true; |
|
when others => |
-- pragma translate_off |
assert now = 0 ns |
report "Unknown opcode." |
severity warning; |
-- pragma translate_on |
|
end case; |
|
result_v.mnemonic := mnemonic_v; |
result_v.multi_cycle := multi_cycle_v; |
|
return result_v; |
end; |
|
end t48_decoder_pack; |
|
|
------------------------------------------------------------------------------- |
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2005/06/11 10:08:43 arniml |
-- introduce prefix 't48_' for all packages, entities and configurations |
-- |
-- Revision 1.2 2004/03/28 13:09:53 arniml |
-- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A |
-- |
/trunk/rtl/vhdl/decoder-c.vhd
3,7 → 3,7
-- The Decoder unit. |
-- It decodes the instruction opcodes and executes them. |
-- |
-- $Id: decoder-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $ |
-- $Id: decoder-c.vhd,v 1.3 2008-04-29 21:19:21 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
15,10 → 15,6
|
for rtl |
|
for opc_decoder_b: t48_opc_decoder |
use configuration work.t48_opc_decoder_rtl_c0; |
end for; |
|
for int_b: t48_int |
use configuration work.t48_int_rtl_c0; |
end for; |
/trunk/rtl/vhdl/decoder.vhd
3,7 → 3,7
-- The Decoder unit. |
-- It decodes the instruction opcodes and executes them. |
-- |
-- $Id: decoder.vhd,v 1.25 2006-06-20 00:46:03 arniml Exp $ |
-- $Id: decoder.vhd,v 1.26 2008-04-29 21:19:21 arniml Exp $ |
-- |
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) |
-- |
180,7 → 180,7
signal opc_multi_cycle_s : boolean; |
signal opc_read_bus_s : boolean; |
signal opc_inj_int_s : boolean; |
signal opc_opcode_s : word_t; |
signal opc_opcode_q : word_t; |
signal opc_mnemonic_s : mnemonic_t; |
signal last_cycle_s : boolean; |
|
236,6 → 236,10
signal int_pending_s : boolean; |
signal int_in_progress_s : boolean; |
|
-- the mnemonic |
signal mnemonic_rec_s : mnemonic_rec_t; |
signal mnemonic_q : mnemonic_t; |
|
-- pragma translate_off |
signal istrobe_res_q : std_logic; |
signal istrobe_q : std_logic; |
244,27 → 248,62
|
begin |
|
-- pragma translate_off |
|
-- Register Mnemonic -------------------------------------------------------- |
assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0) |
report "register_mnemonic_g must be either 1 or 0!" |
severity failure; |
|
-- pragma translate_on |
|
|
----------------------------------------------------------------------------- |
-- Opcode Decoder |
-- |
mnemonic_rec_s <= decode_opcode_f(opcode => opc_opcode_q); |
-- |
----------------------------------------------------------------------------- |
opc_decoder_b : t48_opc_decoder |
generic map ( |
register_mnemonic_g => register_mnemonic_g |
) |
port map ( |
clk_i => clk_i, |
res_i => res_i, |
en_clk_i => en_clk_i, |
data_i => data_i, |
read_bus_i => opc_read_bus_s, |
inj_int_i => opc_inj_int_s, |
opcode_o => opc_opcode_s, |
mnemonic_o => opc_mnemonic_s, |
multi_cycle_o => opc_multi_cycle_s |
); |
|
|
----------------------------------------------------------------------------- |
-- Process opc_regs |
-- |
-- Purpose: |
-- Implements the opcode and mnemonic registers. |
-- |
opc_regs: process (res_i, clk_i) |
begin |
if res_i = res_active_c then |
opc_opcode_q <= (others => '0'); -- NOP |
mnemonic_q <= MN_NOP; |
|
elsif clk_i'event and clk_i = clk_active_c then |
if en_clk_i then |
|
if opc_read_bus_s then |
opc_opcode_q <= data_i; |
elsif opc_inj_int_s then |
opc_opcode_q <= "00010100"; |
else |
mnemonic_q <= mnemonic_rec_s.mnemonic; |
end if; |
|
end if; |
|
end if; |
|
end process opc_regs; |
-- |
opc_multi_cycle_s <= mnemonic_rec_s.multi_cycle; |
opc_mnemonic_s <= mnemonic_q |
when register_mnemonic_g = 1 else |
mnemonic_rec_s.mnemonic; |
-- |
----------------------------------------------------------------------------- |
|
|
----------------------------------------------------------------------------- |
-- Interrupt Controller. |
----------------------------------------------------------------------------- |
int_b : t48_int |
420,7 → 459,7
clk_mstate_i, |
clk_second_cycle_i, |
cnd_take_branch_i, |
opc_opcode_s, |
opc_opcode_q, |
opc_mnemonic_s, |
psw_carry_i, |
psw_f0_i, |
433,7 → 472,7
procedure address_indirect_3_f is |
begin |
-- apply dmem address from selected register for indirect mode |
if opc_opcode_s(3) = '0' or enable_quartus_bugfix_c then |
if opc_opcode_q(3) = '0' or enable_quartus_bugfix_c then |
dm_read_dmem_o <= true; |
dm_write_dmem_addr_o <= true; |
dm_addr_type_o <= DM_PLAIN; |
508,7 → 547,7
clk_assert_wr_o <= false; |
cnd_branch_cond_o <= COND_ON_BIT; |
cnd_compute_take_o <= false; |
cnd_comp_value_o <= opc_opcode_s(7 downto 5); |
cnd_comp_value_o <= opc_opcode_q(7 downto 5); |
dm_addr_type_o <= DM_REG; |
tim_read_timer_o <= false; |
tim_write_timer_o <= false; |
554,10 → 593,10
-- prepare potential register indirect address mode |
if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then |
data_s <= (others => '0'); |
if opc_opcode_s(3) = '1' then |
data_s(2 downto 0) <= opc_opcode_s(2 downto 0); |
if opc_opcode_q(3) = '1' then |
data_s(2 downto 0) <= opc_opcode_q(2 downto 0); |
else |
data_s(2 downto 0) <= "00" & opc_opcode_s(0); |
data_s(2 downto 0) <= "00" & opc_opcode_q(0); |
end if; |
|
read_dec_s <= true; |
573,7 → 612,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
585,7 → 624,7
when MSTATE5 => |
and_or_xor_add_5_f(alu_op => ALU_ADD); |
|
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
alu_use_carry_o <= true; |
end if; |
|
612,7 → 651,7
when MSTATE3 => |
and_or_xor_add_5_f(alu_op => ALU_ADD); |
|
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
alu_use_carry_o <= true; |
end if; |
|
633,7 → 672,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
678,9 → 717,9
if not clk_second_cycle_i then |
-- read port to Temp Reg |
if clk_mstate_i = MSTATE5 then |
if opc_opcode_s(1 downto 0) = "00" then |
if opc_opcode_q(1 downto 0) = "00" then |
add_read_bus_s <= true; |
elsif opc_opcode_s(1) = '0' then |
elsif opc_opcode_q(1) = '0' then |
p1_read_p1_o <= true; |
p1_read_reg_o <= true; |
else |
709,9 → 748,9
alu_op_o <= ALU_AND; |
alu_read_alu_o <= true; |
|
if opc_opcode_s(1 downto 0) = "00" then |
if opc_opcode_q(1 downto 0) = "00" then |
bus_write_bus_o <= true; |
elsif opc_opcode_s(1) = '0' then |
elsif opc_opcode_q(1) = '0' then |
p1_write_p1_o <= true; |
else |
p2_write_p2_o <= true; |
786,7 → 825,7
read_dec_s <= true; |
if not int_pending_s then |
-- store high part of target address in Program Counter |
data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5); |
data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); |
else |
-- apply high part of vector address manually |
data_s <= (others => '0'); |
821,7 → 860,7
when MN_CLR_F => |
-- store 0 to selected flag |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(5) = '0' then |
if opc_opcode_q(5) = '0' then |
psw_special_data_o <= '0'; |
psw_write_f0_o <= true; |
else |
851,7 → 890,7
when MN_CPL_f => |
-- write inverse of selected flag back to flag |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(5) = '0' then |
if opc_opcode_q(5) = '0' then |
psw_special_data_o <= not psw_f0_i; |
psw_write_f0_o <= true; |
else |
906,7 → 945,7
case clk_mstate_i is |
when MSTATE4 => |
-- DEC Rr: store data from RAM to shadow Accumulator |
if opc_opcode_s(6) = '1' then |
if opc_opcode_q(6) = '1' then |
dm_read_dmem_o <= true; |
alu_write_shadow_o <= true; |
end if; |
915,7 → 954,7
alu_op_o <= ALU_DEC; |
alu_read_alu_o <= true; |
|
if opc_opcode_s(6) = '0' then |
if opc_opcode_q(6) = '0' then |
-- write DEC of Accumulator to Accumulator |
alu_write_accu_o <= true; |
else |
931,7 → 970,7
-- Mnemonic DIS_EN_I ---------------------------------------------------- |
when MN_DIS_EN_I => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
dis_i_s <= true; |
else |
en_i_s <= true; |
941,7 → 980,7
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------ |
when MN_DIS_EN_TCNTI => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
dis_tcnti_s <= true; |
else |
en_tcnti_s <= true; |
996,7 → 1035,7
if clk_second_cycle_i and clk_mstate_i = MSTATE2 then |
alu_write_accu_o <= true; |
|
if opc_opcode_s(1) = '0' then |
if opc_opcode_q(1) = '0' then |
p1_read_p1_o <= true; |
else |
p2_read_p2_o <= true; |
1020,13 → 1059,13
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
when MSTATE4 => |
-- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator |
if opc_opcode_s(3 downto 2) /= "01" then |
if opc_opcode_q(3 downto 2) /= "01" then |
dm_read_dmem_o <= true; |
alu_write_shadow_o <= true; |
end if; |
1035,7 → 1074,7
alu_op_o <= ALU_INC; |
alu_read_alu_o <= true; |
|
if opc_opcode_s(3 downto 2) = "01" then |
if opc_opcode_q(3 downto 2) = "01" then |
-- write INC output of ALU to Accumulator |
alu_write_accu_o <= true; |
else |
1079,7 → 1118,7
-- start branch calculation |
if clk_mstate_i = MSTATE3 then |
cnd_compute_take_o <= true; |
cnd_comp_value_o(0) <= opc_opcode_s(4); |
cnd_comp_value_o(0) <= opc_opcode_q(4); |
end if; |
|
else |
1099,7 → 1138,7
-- start branch calculation |
if clk_mstate_i = MSTATE3 then |
cnd_compute_take_o <= true; |
if opc_opcode_s(7) = '1' then |
if opc_opcode_q(7) = '1' then |
-- JF0 |
cnd_branch_cond_o <= COND_F0; |
else |
1132,7 → 1171,7
|
-- store high part of target address in Program Counter |
when MSTATE2 => |
data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5); |
data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); |
read_dec_s <= true; |
pm_write_pch_o <= true; |
|
1187,7 → 1226,7
-- Mnemonic JT ---------------------------------------------------------- |
when MN_JT => |
assert_psen_s <= true; |
if opc_opcode_s(6) = '0' then |
if opc_opcode_q(6) = '0' then |
cnd_branch_cond_o <= COND_T0; |
else |
cnd_branch_cond_o <= COND_T1; |
1197,7 → 1236,7
-- start branch calculation |
if clk_mstate_i = MSTATE3 then |
cnd_compute_take_o <= true; |
cnd_comp_value_o(0) <= opc_opcode_s(4); |
cnd_comp_value_o(0) <= opc_opcode_q(4); |
end if; |
|
else |
1240,7 → 1279,7
if clk_mstate_i = MSTATE3 then |
alu_read_alu_o <= true; |
cnd_compute_take_o <= true; |
cnd_comp_value_o(0) <= opc_opcode_s(6); |
cnd_comp_value_o(0) <= opc_opcode_q(6); |
end if; |
|
else |
1268,7 → 1307,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
1304,7 → 1343,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
1325,7 → 1364,7
-- read RAM once for indirect address mode |
if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
end if; |
1339,7 → 1378,7
-- Mnemonic MOV_T ------------------------------------------------------- |
when MN_MOV_T => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(5) = '1' then |
if opc_opcode_q(5) = '1' then |
alu_read_alu_o <= true; -- MOV T, A |
tim_write_timer_o <= true; |
else |
1358,9 → 1397,9
when MSTATE3 => |
|
data_s(7 downto 4) <= (others => '0'); |
data_s(1 downto 0) <= opc_opcode_s(1 downto 0); |
data_s(1 downto 0) <= opc_opcode_q(1 downto 0); |
-- decide which 8243 command to use |
case opc_opcode_s(7 downto 4) is |
case opc_opcode_q(7 downto 4) is |
when "1001" => |
data_s(3 downto 2) <= "11"; -- ANLD command |
when "1000" => |
1408,7 → 1447,7
when MSTATE3 => |
data_s <= "0000" & |
"00" & -- 8243 command: read |
opc_opcode_s(1 downto 0); |
opc_opcode_q(1 downto 0); |
read_dec_s <= true; |
p2_write_exp_o <= true; |
|
1459,7 → 1498,7
-- (skip page offset update from Program Counter) |
if clk_mstate_i = MSTATE3 then |
alu_read_alu_o <= true; |
if opc_opcode_s(6) = '0' then |
if opc_opcode_q(6) = '0' then |
pm_addr_type_o <= PM_PAGE; |
else |
pm_addr_type_o <= PM_PAGE3; |
1481,7 → 1520,7
when MN_MOVX => |
bus_bidir_bus_o <= true; |
|
if opc_opcode_s(4) = '0' then |
if opc_opcode_q(4) = '0' then |
clk_assert_rd_o <= true; |
else |
clk_assert_wr_o <= true; |
1497,7 → 1536,7
|
-- store contents of Accumulator to BUS |
when MSTATE5 => |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
alu_read_alu_o <= true; |
bus_write_bus_o <= true; |
end if; |
1508,7 → 1547,7
|
else |
if clk_mstate_i = MSTATE2 then |
if opc_opcode_s(4) = '0' then |
if opc_opcode_q(4) = '0' then |
-- store contents of BUS in Accumulator |
add_read_bus_s <= true; |
alu_write_accu_o <= true; |
1532,7 → 1571,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
1577,9 → 1616,9
if not clk_second_cycle_i then |
-- read port to Temp Reg |
if clk_mstate_i = MSTATE5 then |
if opc_opcode_s(1 downto 0) = "00" then |
if opc_opcode_q(1 downto 0) = "00" then |
add_read_bus_s <= true; |
elsif opc_opcode_s(1) = '0' then |
elsif opc_opcode_q(1) = '0' then |
p1_read_p1_o <= true; |
p1_read_reg_o <= true; |
else |
1608,9 → 1647,9
alu_op_o <= ALU_OR; |
alu_read_alu_o <= true; |
|
if opc_opcode_s(1 downto 0) = "00" then |
if opc_opcode_q(1 downto 0) = "00" then |
bus_write_bus_o <= true; |
elsif opc_opcode_s(1) = '0' then |
elsif opc_opcode_q(1) = '0' then |
p1_write_p1_o <= true; |
else |
p2_write_p2_o <= true; |
1625,7 → 1664,7
|
-- Mnemonic OUTL_EXT ---------------------------------------------------- |
when MN_OUTL_EXT => |
if opc_opcode_s(4) = '0' then |
if opc_opcode_q(4) = '0' then |
clk_assert_wr_o <= true; |
end if; |
|
1633,8 → 1672,8
if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then |
alu_read_alu_o <= true; |
|
if opc_opcode_s(4) = '1' then |
if opc_opcode_s(1) = '0' then |
if opc_opcode_q(4) = '1' then |
if opc_opcode_q(1) = '0' then |
p1_write_p1_o <= true; |
else |
p2_write_p2_o <= true; |
1680,7 → 1719,7
when MSTATE1 => |
dm_read_dmem_o <= true; |
pm_write_pch_o <= true; |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
psw_write_psw_o <= true; |
retr_executed_s <= true; |
end if; |
1702,7 → 1741,7
alu_read_alu_o <= true; |
alu_write_accu_o <= true; |
|
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
psw_special_data_o <= alu_carry_i; |
psw_write_carry_o <= true; |
alu_use_carry_o <= true; |
1716,7 → 1755,7
alu_read_alu_o <= true; |
alu_write_accu_o <= true; |
|
if opc_opcode_s(4) = '0' then |
if opc_opcode_q(4) = '0' then |
psw_special_data_o <= alu_carry_i; |
psw_write_carry_o <= true; |
alu_use_carry_o <= true; |
1726,7 → 1765,7
-- Mnemonic SEL_MB ------------------------------------------------------ |
when MN_SEL_MB => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
set_mb_s <= true; |
else |
clear_mb_s <= true; |
1736,7 → 1775,7
-- Mnemonic SEL_RB ------------------------------------------------------ |
when MN_SEL_RB => |
if clk_mstate_i = MSTATE3 then |
psw_special_data_o <= opc_opcode_s(4); |
psw_special_data_o <= opc_opcode_q(4); |
psw_write_bs_o <= true; |
end if; |
|
1749,7 → 1788,7
-- Mnemonic STRT -------------------------------------------------------- |
when MN_STRT => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
tim_start_t_o <= true; |
else |
tim_start_cnt_o <= true; |
1771,7 → 1810,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
1781,7 → 1820,7
dm_read_dmem_o <= true; |
alu_write_accu_o <= true; |
alu_write_temp_reg_o <= true; |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
-- XCHD |
-- only write lower nibble of Accumulator |
alu_accu_low_o <= true; |
1791,7 → 1830,7
when MSTATE5 => |
dm_write_dmem_s <= true; |
alu_read_alu_o <= true; |
if opc_opcode_s(4) = '1' then |
if opc_opcode_q(4) = '1' then |
-- XCHD |
-- concatenate shadow Accumulator and Temp Reg |
alu_op_o <= ALU_CONCAT; |
1808,7 → 1847,7
-- read RAM once for indirect address mode |
when MSTATE3 => |
if not enable_quartus_bugfix_c or |
opc_opcode_s(3) = '0' then |
opc_opcode_q(3) = '0' then |
address_indirect_3_f; |
end if; |
|
1974,6 → 2013,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.25 2006/06/20 00:46:03 arniml |
-- new input xtal_en_i |
-- |
-- Revision 1.24 2005/11/14 21:12:29 arniml |
-- suppress p2_output_pch_o when MOVX operation is accessing the |
-- external memory |