URL
https://opencores.org/ocsvn/plasma/plasma/trunk
Subversion Repositories plasma
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 284 to Rev 285
- ↔ Reverse comparison
Rev 284 → Rev 285
/trunk/vhdl/mlite_pack.vhd
349,36 → 349,6
data_read : out std_logic_vector(31 downto 0)); |
end component; --ram |
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component ddr_ctrl |
port(clk : in std_logic; |
clk_2x : in std_logic; |
reset_in : in std_logic; |
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address : in std_logic_vector(25 downto 2); |
byte_we : in std_logic_vector(3 downto 0); |
data_w : in std_logic_vector(31 downto 0); |
data_r : out std_logic_vector(31 downto 0); |
active : in std_logic; |
pause : out std_logic; |
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SD_CK_P : out std_logic; --clock_positive |
SD_CK_N : out std_logic; --clock_negative |
SD_CKE : out std_logic; --clock_enable |
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SD_BA : out std_logic_vector(1 downto 0); --bank_address |
SD_A : out std_logic_vector(12 downto 0); --address(row or col) |
SD_CS : out std_logic; --chip_select |
SD_RAS : out std_logic; --row_address_strobe |
SD_CAS : out std_logic; --column_address_strobe |
SD_WE : out std_logic; --write_enable |
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SD_DQ : inout std_logic_vector(15 downto 0); --data |
SD_UDM : out std_logic; --upper_byte_enable |
SD_UDQS : inout std_logic; --upper_data_strobe |
SD_LDM : out std_logic; --low_byte_enable |
SD_LDQS : inout std_logic); --low_data_strobe |
end component; --ddr |
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component uart |
generic(log_file : string := "UNUSED"); |
port(clk : in std_logic; |
393,9 → 363,37
data_avail : out std_logic); |
end component; --uart |
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component eth_dma |
port(clk : in std_logic; --25 MHz |
reset : in std_logic; |
enable_eth : in std_logic; |
select_eth : in std_logic; |
rec_isr : out std_logic; |
send_isr : out std_logic; |
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address : out std_logic_vector(31 downto 2); --to DDR |
byte_we : out std_logic_vector(3 downto 0); |
data_write : out std_logic_vector(31 downto 0); |
data_read : in std_logic_vector(31 downto 0); |
pause_in : in std_logic; |
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mem_address : in std_logic_vector(31 downto 2); --from CPU |
mem_byte_we : in std_logic_vector(3 downto 0); |
data_w : in std_logic_vector(31 downto 0); |
pause_out : out std_logic; |
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E_RX_CLK : in std_logic; --2.5 MHz receive |
E_RX_DV : in std_logic; --data valid |
E_RXD : in std_logic_vector(3 downto 0); --receive nibble |
E_TX_CLK : in std_logic; --2.5 MHz transmit |
E_TX_EN : out std_logic; --transmit enable |
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble |
end component; --eth_dma |
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component plasma |
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; |
log_file : string := "UNUSED"); |
log_file : string := "UNUSED"; |
ethernet : std_logic := '0'); |
port(clk : in std_logic; |
reset : in std_logic; |
uart_write : out std_logic; |
411,6 → 409,36
gpioA_in : in std_logic_vector(31 downto 0)); |
end component; --plasma |
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component ddr_ctrl |
port(clk : in std_logic; |
clk_2x : in std_logic; |
reset_in : in std_logic; |
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address : in std_logic_vector(25 downto 2); |
byte_we : in std_logic_vector(3 downto 0); |
data_w : in std_logic_vector(31 downto 0); |
data_r : out std_logic_vector(31 downto 0); |
active : in std_logic; |
pause : out std_logic; |
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SD_CK_P : out std_logic; --clock_positive |
SD_CK_N : out std_logic; --clock_negative |
SD_CKE : out std_logic; --clock_enable |
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SD_BA : out std_logic_vector(1 downto 0); --bank_address |
SD_A : out std_logic_vector(12 downto 0); --address(row or col) |
SD_CS : out std_logic; --chip_select |
SD_RAS : out std_logic; --row_address_strobe |
SD_CAS : out std_logic; --column_address_strobe |
SD_WE : out std_logic; --write_enable |
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SD_DQ : inout std_logic_vector(15 downto 0); --data |
SD_UDM : out std_logic; --upper_byte_enable |
SD_UDQS : inout std_logic; --upper_data_strobe |
SD_LDM : out std_logic; --low_byte_enable |
SD_LDQS : inout std_logic); --low_data_strobe |
end component; --ddr |
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end; --package mlite_pack |
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