URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- This comparison shows the changes necessary to convert path
/
- from Rev 29 to Rev 30
- ↔ Reverse comparison
Rev 29 → Rev 30
/trunk/rtl/verilog/i2c_master_bit_ctrl.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_bit_ctrl.v,v 1.6 2002-12-26 15:02:32 rherveille Exp $ |
// $Id: i2c_master_bit_ctrl.v,v 1.7 2002-12-26 16:05:12 rherveille Exp $ |
// |
// $Date: 2002-12-26 15:02:32 $ |
// $Revision: 1.6 $ |
// $Date: 2002-12-26 16:05:12 $ |
// $Revision: 1.7 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/12/26 15:02:32 rherveille |
// Core is now a Multimaster I2C controller |
// |
// Revision 1.5 2002/11/30 22:24:40 rherveille |
// Cleaned up code |
// |
224,7 → 227,7
sto_condition <= #1 sSDA & ~dSDA & sSCL; |
end |
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// generate bus busy signal |
// generate i2c bus busy signal |
always @(posedge clk or negedge nReset) |
if(!nReset) |
busy <= #1 1'b0; |
/trunk/rtl/verilog/i2c_master_top.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_top.v,v 1.7 2002-12-26 15:02:32 rherveille Exp $ |
// $Id: i2c_master_top.v,v 1.8 2002-12-26 16:05:12 rherveille Exp $ |
// |
// $Date: 2002-12-26 15:02:32 $ |
// $Revision: 1.7 $ |
// $Date: 2002-12-26 16:05:12 $ |
// $Revision: 1.8 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2002/12/26 15:02:32 rherveille |
// Core is now a Multimaster I2C controller |
// |
// Revision 1.6 2002/11/30 22:24:40 rherveille |
// Cleaned up code |
// |
200,7 → 203,7
cr[7:4] <= #1 4'h0; // clear command bits when done |
// or when aribitration lost |
cr[2:1] <= #1 2'b0; // reserved bits |
cr[0] <= #1 cr[0] & irq_flag; // clear when irq_flag is cleared |
cr[0] <= #1 2'b0; // clear IRQ_ACK bit |
end |
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