Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/Eth/ethmac_100.IP

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/JTAG/jtag_wb.IP

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/NoC/ni_sep.IP

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/mpsoc/lm32_noc.MPSOC

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/traffic_gen.v.old File deleted

an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/traffic_gen.v.old Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/inout_ports.v.classic =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/inout_ports.v.classic (revision 29) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/inout_ports.v.classic (nonexistent) @@ -1,383 +0,0 @@ -`timescale 1ns/1ps - -module inout_ports #( - parameter V = 4, // vc_num_per_port - parameter P = 5, // router port num - parameter B = 4, // buffer space :flit per VC - parameter NX = 4, // number of node in x axis - parameter NY = 4, // number of node in y axis - parameter C = 4, // number of flit class - parameter Fpay = 32, //payload width - parameter CLASS_CONFIG_NUM= 0, - parameter VC_REALLOCATION_TYPE= "NONATOMIC", - parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC" - parameter TOPOLOGY= "MESH",//"MESH","TORUS" - parameter ROUTE_NAME="XY",// "XY", "TRANC_XY" - parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE" - parameter CONGESTION_INDEX = 2,//"CREDIT","VC" - parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive - parameter DEBUG_EN = 1, - parameter AVC_ATOMIC_EN = 1, - parameter ROUTE_SUBFUNC = "XY", - parameter CONGw = 2 - -) -( - current_x, - current_y, - // to/from neighboring router - flit_in_all, - flit_in_we_all, - credit_out_all, - credit_in_all, - congestion_in_all, - congestion_out_all, - - // from vc/sw allocator - ovc_allocated_all, - granted_ovc_num_all, - ivc_num_getting_sw_grant, - ivc_num_getting_ovc_grant, - spec_ovc_num_all, - nonspec_first_arbiter_granted_ivc_all, - spec_first_arbiter_granted_ivc_all, - nonspec_granted_dest_port_all, - spec_granted_dest_port_all, - granted_dest_port_all, - any_ivc_sw_request_granted_all, - - // to vc/sw allocator - dest_port_all, - ovc_is_assigned_all, - ivc_request_all, - assigned_ovc_not_full_all, - masked_ovc_request_all, - lk_destination_all, - - - // to crossbar - flit_out_all, - clk,reset - -); - - function integer log2; - input integer number; begin - log2=0; - while(2**log2

an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/inout_ports.v.classic Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/routing.v =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/routing.v (revision 29) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/routing.v (revision 30) @@ -683,7 +683,7 @@ input [Xw-1 :0] current_x; input [Yw-1 :0] current_y; - input [Yw-1 :0] dest_x; + input [Xw-1 :0] dest_x; input [Yw-1 :0] dest_y; output [DSTw-1 :0] destport; @@ -961,7 +961,7 @@ input [Xw-1 :0] current_x; input [Yw-1 :0] current_y; - input [Yw-1 :0] dest_x; + input [Xw-1 :0] dest_x; input [Yw-1 :0] dest_y; output [P_1-1 :0] destport;

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_noc/ss_allocator.v

267,9 → 267,7

localparam SSA_EN = ((ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;

//header packet filds width

279,6 → 277,11

X_Y_IN_HDR_WIDTH =4,

SW_LOC =V_GLOBAL/V,

V_LOCAL =V_GLOBAL%V;

localparam SSA_EN = ((ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;

input [Fw-1 : 0] flit_in;

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/eth

90,8 → 90,8

int ${IP}_rx_len;

unsigned char ${IP}_tx_packet[1536]; //max length

unsigned char ${IP}_rx_packet[1536];

unsigned char * ethmac_tx_data= & ethmac_tx_packet[HDR_LEN];

unsigned char * ethmac_rx_data= & ethmac_rx_packet[HDR_LEN];

unsigned char * ${IP}_tx_data= & ${IP}_tx_packet[HDR_LEN];

unsigned char * ${IP}_rx_data= & ${IP}_rx_packet[HDR_LEN];

void ${IP}_recv_ack(void)

{

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/eth_generic_ram.v

0,0 → 1,105

/****************

*simple_dual_port_ram

*

*****************/

// Quartus II Verilog Template

// Simple Dual Port RAM with separate read/write addresses and

// single read/write clock

module eth_simple_dual_port_ram #(

parameter Dw=8,

parameter Aw=6

)

(

data,

read_addr,

write_addr,

we,

clk,

q

);

input [Dw-1 :0] data;

input [Aw-1 :0] read_addr;

input [Aw-1 :0] write_addr;

input we;

input clk;

output reg [Dw-1 :0] q;

// Declare the RAM variable

reg [Dw-1:0] ram [2**Aw-1:0];

always @ (posedge clk)

begin

// Write

if (we)

ram[write_addr] <= data;

// Read (if read_addr == write_addr, return OLD data). To return

// NEW data, use = (blocking write) rather than <= (non-blocking write)

// in the write assignment. NOTE: NEW data may require extra bypass

// logic around the RAM.

q <= ram[read_addr];

end

endmodule

/*****************************

single_port_ram

*****************************/

// Quartus II Verilog Template

// Single port RAM with single read/write address

module eth_single_port_ram #(

parameter Dw=8,

parameter Aw=6

)

(

data,

addr,

we,

clk,

q

);

input [(Dw-1):0] data;

input [(Aw-1):0] addr;

input we, clk;

output [(Dw-1):0] q;

// Declare the RAM variable

reg [Dw-1:0] ram[2**Aw-1:0];

// Variable to hold the registered read address

reg [Aw-1:0] addr_reg;

always @ (posedge clk)

begin

// Write

if (we)

ram[addr] <= data;

addr_reg <= addr;

end

// Continuous assignment implies read returns NEW data.

// This is the natural behavior of the TriMatrix memory

// blocks in Single Port mode.

assign q = ram[addr_reg];

endmodule

an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/eth_generic_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v (revision 29) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v (revision 30) @@ -176,7 +176,7 @@ ); */ - simple_dual_port_ram + eth_simple_dual_port_ram #( .Dw(DATA_WIDTH), .Aw(CNT_WIDTH-1)

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v

254,7 → 254,7

);

single_port_ram #(

eth_single_port_ram #(

.Dw(32),

.Aw(8)

)

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/old_ni.v File deleted

an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/old_ni.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/bak =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/bak (revision 29) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/bak (nonexistent) @@ -1,834 +0,0 @@ -/************************************** -* Module: ni -* Date:2015-03-30 -* Author: alireza -* -* Description: -***************************************/ - - -/********************************************************************** - File: ni.v - - Copyright (C) 2013 Alireza Monemi - - This AUTOram is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This AUTOram is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this AUTOram. If not, see . - - - Purpose: - A DMA based NI for connecting the NoC router to a processor. The NI has 3 - memory mapped registers: - // ni status register - STATUS_ADDR = 0, - // update memory pinter, packet size and send packet read command. If memory pointer and packet size width are smaller than COMB_MEM_PTR_W and COMB_PCK_SIZE_W respectively. - RD_MEM_PCKSIZ_ADDR = 1, - // update memory pinter, packet size and send packet write command. If memory pointer and packet size width are smaller than COMB_MEM_PTR_W and COMB_PCK_SIZE_W respectively. - WR_MEM_PCKSIZ_ADDR = 2, - //update packet size - PCK_SIZE_ADDR = 3, - //update the memory pointer address and send read command. The packet size must be updated before setting this register. use it when memory pointer width is larger than COMB_MEM_PTR_W - RD_MEM_ADDR = 4, - //update the memory pointer address and send write command. The packet size must be updated before setting this register. use it when memory pointer width is larger than COMB_MEM_PTR_W - WR_MEM_ADDR = 5; - - status_reg - bit_loc flag_name - 12 rsv_pck_isr - 11 rd_done_isr - 10 wr_done_isr - 9 rsv_pck_int_en - 8 rd_done_int_en - 7 wr_done_int_en - 6 all_vcs_full - 5 any_vc_has_data - 4 rd_no_pck_err - 3 rd_ovr_size_err - 2 rd_done - 1 wr_done - 0 busy - - - - RD/WR registers ={pck_size_next,memory_ptr_next} - - Info: monemi@fkegraduate.utm.my - *************************************************************************/ - - -`timescale 1ns/1ps - - - -module ni #( - - parameter V = 4, // V - parameter P = 5, // router port num - parameter B = 4, // buffer space :flit per VC - parameter NX = 2, // number of node in x axis - parameter NY = 2, // number of node in y axis - parameter Fpay = 32, - parameter TOPOLOGY = "MESH",//"MESH","TORUS" - parameter ROUTE_TYPE = "DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE" - parameter ROUTE_NAME = "XY", - parameter DEBUG_EN = 1, - - parameter COMB_MEM_PTR_W=20, - parameter COMB_PCK_SIZE_W= 12, - - //wishbone port parameters - parameter Dw = 32, - parameter S_Aw = 3, - parameter M_Aw = 32, - parameter TAGw = 3, - parameter SELw = 4 - - - ) - ( - - reset, - clk, - - //noc interface - current_x, - current_y, - flit_out, - flit_out_wr, - credit_in, - flit_in, - flit_in_wr, - credit_out, - - //wishbone slave interface signals - s_dat_i, - s_sel_i, - s_addr_i, - s_cti_i, - s_stb_i, - s_cyc_i, - s_we_i, - s_dat_o, - s_ack_o, - s_err_o, - s_rty_o, - - - - //wishbone master interface signals - m_sel_o, - m_dat_o, - m_addr_o, - m_cti_o, - m_stb_o, - m_cyc_o, - m_we_o, - m_dat_i, - m_ack_i, - m_err_i, - m_rty_i, - //intruupt interface - irq - - -); - - function integer log2; - input integer number; begin - log2=0; - while(2**log2

an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/bak Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/sub_ni_rd.v =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/sub_ni_rd.v (revision 29) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/sub_ni_rd.v (revision 30) @@ -356,6 +356,7 @@ reg [Vw-1 :0] cand_rd_vc_binary; wire [V-1 :0] cand_rd_vc_onehot; + wire [V-1 :0] rd_vc_not_empty; assign {wb_v_addr_binary, wb_wr_rd_addr, wb_general_reg_addr} = s_addr_i[3+Vw :0]; @@ -683,7 +684,7 @@ ); - + assign rd_vc_not_empty = ififo_vc_not_empty; @@ -705,3 +706,5 @@ + +

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ni/sub_ni_wr.v

156,7 → 156,8

localparam P_1 = P-1 ,

Fw = 2+V+Fpay, //flit width

Xw = log2(NX),

Yw = log2(NY);

Yw = log2(NY),

Vw = (V>1) ? log2(V) : 1;

//wishbone slave addresses

415,7 → 416,7

//status register

assign wr_busy = ps!=IDEAL;

assign status_reg = {/*rd_vc_not_empty*/{Vw{1'b0}},wr_vc_not_empty,/*rsv_pck_isr*/1'b0, /*rd_done_isr*/1'b0,wr_done_isr,/*rsv_pck_int_en*/1'b0,/*rd_done_int_en*/1'b0,wr_done_int_en,all_vcs_full,/*any_vc_has_data*/1'b0,/*rd_no_pck_err*/1'b0,/*rd_ovr_size_err*/1'b0,/*rd_done*/1'b0,wr_done,/*rd_busy*/,wr_busy};

assign status_reg = {/*rd_vc_not_empty*/{Vw{1'b0}}, wr_vc_not_empty,/*rsv_pck_isr*/1'b0, /*rd_done_isr*/1'b0, wr_done_isr,/*rsv_pck_int_en*/1'b0,/*rd_done_int_en*/1'b0,wr_done_int_en,all_vcs_full,/*any_vc_has_data*/1'b0,/*rd_no_pck_err*/1'b0,/*rd_ovr_size_err*/1'b0,/*rd_done*/1'b0,wr_done,/*rd_busy*/1'b0,wr_busy};

assign s_dat_o = status_reg;

reg [M_Aw-1 : 0] m_addr;

696,3 → 697,4

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_verilator/testbench.cpp

150,7 → 150,7

traffic[i]->current_x = x;

traffic[i]->current_y = y;

traffic[i]->start=0;

traffic[i]->pck_size=PACKET_SIZE;

traffic[i]->pck_size_in=PACKET_SIZE;

traffic[i]->ratio=ratio;

traffic[i]->pck_class_in= pck_class_in_gen( i);

pck_dst_gen ( x,y,i, &dest_x, &dest_y);