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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

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Rev 29 → Rev 30

/ft816float/trunk/rtl/verilog2/fpdivr16.v
25,22 → 25,22
// ============================================================================
 
module fpdivr16(clk, ld, a, b, q, r, done, lzcnt);
parameter FPWID1 = 112;
localparam REM = FPWID1 % 4;
localparam FPWID = ((FPWID1*4)+3)/4;
localparam DMSB = FPWID-1;
parameter WID1 = 112;
localparam REM = WID1 % 4;
localparam WID = ((WID1*4)+3)/4;
localparam DMSB = WID-1;
input clk;
input ld;
input [FPWID-1:0] a;
input [FPWID-1:0] b;
output reg [FPWID*2-1:0] q = 1'd0;
output reg [FPWID-1:0] r = 1'd0;
input [WID-1:0] a;
input [WID-1:0] b;
output reg [WID*2-1:0] q = 1'd0;
output reg [WID-1:0] r = 1'd0;
output reg done = 1'd0;
output reg [7:0] lzcnt = 1'd0;
 
initial begin
if (FPWID % 4) begin
$display("fpdvir16: FPWIDth must be a multiple of four.");
if (WID % 4) begin
$display("fpdvir16: Width must be a multiple of four.");
$finish;
end
end
54,23 → 54,23
reg [DMSB+1:0] r1 = 1'd0,r2 = 1'd0,r3 = 1'd0,r4 = 1'd0;
reg gotnz = 0;
 
assign maxcnt = FPWID*2/4-1;
assign maxcnt = WID*2/4-1;
always @*
b0 = b <= {rxx,q[FPWID*2-1]};
b0 = b <= {rxx,q[WID*2-1]};
always @*
r1 = b0 ? {rxx,q[FPWID*2-1]} - b : {rxx,q[FPWID*2-1]};
r1 = b0 ? {rxx,q[WID*2-1]} - b : {rxx,q[WID*2-1]};
always @*
b1 = b <= {r1,q[FPWID*2-2]};
b1 = b <= {r1,q[WID*2-2]};
always @*
r2 = b1 ? {r1,q[FPWID*2-2]} - b : {r1,q[FPWID*2-2]};
r2 = b1 ? {r1,q[WID*2-2]} - b : {r1,q[WID*2-2]};
always @*
b2 = b <= {r2,q[FPWID*2-3]};
b2 = b <= {r2,q[WID*2-3]};
always @*
r3 = b2 ? {r2,q[FPWID*2-3]} - b : {r2,q[FPWID*2-3]};
r3 = b2 ? {r2,q[WID*2-3]} - b : {r2,q[WID*2-3]};
always @*
b3 = b <= {r3,q[FPWID*2-4]};
b3 = b <= {r3,q[WID*2-4]};
always @*
r4 = b3 ? {r3,q[FPWID*2-4]} - b : {r3,q[FPWID*2-4]};
r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
 
reg [2:0] state = 0;
 
78,18 → 78,10
begin
done <= 1'b0;
case(state)
3'd0:
if (ld) begin
lzcnt <= 0;
gotnz <= 0;
cnt <= maxcnt;
q <= {(a << REM),{FPWID{1'b0}}};
rxx <= {FPWID{1'b0}};
state <= 1;
end
3'd0: ;
3'd1:
if (!cnt[8]) begin
q[FPWID*2-1:4] <= q[FPWID*2-5:0];
q[WID*2-1:4] <= q[WID*2-5:0];
q[3] <= b0;
q[2] <= b1;
q[1] <= b2;
118,7 → 110,15
end
default: state <= 1'd0;
endcase
if (ld) begin
lzcnt <= 0;
gotnz <= 1'b0;
cnt <= {1'b0,maxcnt};
q <= {(a << REM),{WID{1'b0}}};
rxx <= {WID{1'b0}};
state <= 3'd1;
end
end
 
endmodule
 
/ft816float/trunk/rtl/verilog2/isqrt.v
1,3 → 1,4
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2010-2019 Robert Finch, Waterloo
9,7 → 10,7
// - integer square root
// - uses the standard long form calc.
// - geared towards use in an floating point unit
// - calculates to FPWID fractional precision (double FPWIDth output)
// - calculates to WID fractional precision (double width output)
//
//
// This source file is free software: you can redistribute it and/or modify
28,8 → 29,8
// ============================================================================
 
module isqrt(rst, clk, ce, ld, a, o, done);
parameter FPWID = 32;
localparam MSB = FPWID-1;
parameter WID = 32;
localparam MSB = WID-1;
parameter IDLE=3'd0;
parameter CALC=3'd1;
parameter DONE=3'd2;
38,20 → 39,20
input ce;
input ld;
input [MSB:0] a;
output [FPWID*2-1:0] o;
output [WID*2-1:0] o;
output done;
 
reg [2:0] state;
reg [FPWID*2:0] root;
wire [FPWID*2-1:0] testDiv;
reg [FPWID*2-1:0] remLo;
reg [FPWID*2-1:0] remHi;
reg [WID*2:0] root;
wire [WID*2-1:0] testDiv;
reg [WID*2-1:0] remLo;
reg [WID*2-1:0] remHi;
 
wire cnt_done;
assign testDiv = {root[FPWID*2-2:0],1'b1};
wire [FPWID*2-1:0] remHiShift = {remHi[FPWID*2-3:0],remLo[FPWID*2-1:FPWID*2-2]};
assign testDiv = {root[WID*2-2:0],1'b1};
wire [WID*2-1:0] remHiShift = {remHi[WID*2-3:0],remLo[WID*2-1:WID*2-2]};
wire doesGoInto = remHiShift >= testDiv;
assign o = root[FPWID*2:1];
assign o = root[WID*2:1];
 
// Iteration counter
reg [7:0] cnt;
58,46 → 59,50
 
always @(posedge clk)
if (rst) begin
cnt <= FPWID*2;
remLo <= {FPWID*2{1'b0}};
remHi <= {FPWID*2{1'b0}};
root <= {FPWID*2+1{1'b0}};
cnt <= WID*2;
remLo <= {WID*2{1'b0}};
remHi <= {WID*2{1'b0}};
root <= {WID*2+1{1'b0}};
state <= IDLE;
end
else if (ce) begin
if (!cnt_done)
cnt <= cnt + 8'd1;
case(state)
IDLE:
if (ld) begin
cnt <= 8'd0;
state <= CALC;
remLo <= {a,32'h0};
remHi <= {FPWID*2{1'b0}};
root <= {FPWID*2+1{1'b0}};
else
begin
if (ce) begin
if (!cnt_done)
cnt <= cnt + 8'd1;
case(state)
IDLE: ;
CALC:
if (!cnt_done) begin
// Shift the remainder low
remLo <= {remLo[WID*2-3:0],2'd0};
// Shift the remainder high
remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
// Shift the root
root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
end
else begin
cnt <= 8'h00;
state <= DONE;
end
DONE:
begin
cnt <= cnt + 8'd1;
if (cnt == 8'd6)
state <= IDLE;
end
default: state <= IDLE;
endcase
if (ld) begin
cnt <= 8'd0;
state <= CALC;
remLo <= {a,32'd0};
remHi <= {WID*2{1'b0}};
root <= {WID*2+1{1'b0}};
end
end
CALC:
if (!cnt_done) begin
// Shift the remainder low
remLo <= {remLo[FPWID*2-3:0],2'd0};
// Shift the remainder high
remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
// Shift the root
root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
end
else begin
cnt <= 8'h00;
state <= DONE;
end
DONE:
begin
cnt <= cnt + 8'd1;
if (cnt == 8'd6)
state <= IDLE;
end
endcase
end
assign cnt_done = (cnt==FPWID);
assign cnt_done = (cnt==WID);
assign done = state==DONE;
 
endmodule

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