OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/trunk/sim/rtl_sim/log/example_pci_tb.log
0,0 → 1,2902
************************ PCI IP Core Testbench Test results ************************
 
*****************************************************************************************
At time 98835000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 99300000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 99735000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 100200000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 101595000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 102165000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 102825000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 103515000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 104175000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 105700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 105700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 105700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 105700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 106300000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 107700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 107700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 107700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 107700000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 108300000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 111300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 111300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 111300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 111300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 112000000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 112635000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 113220000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 113820000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 114825000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 115420000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 117105000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 117580000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 118005000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 118480000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 119895000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 120465000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 121125000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 121815000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 122475000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 124000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 124000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 124000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 124000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 124600000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 126000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 126000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 126000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 126000000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 126600000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 129600000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 129600000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 129600000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 129600000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 130300000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 130935000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 131520000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 132120000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 133125000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 133720000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 135405000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 135880000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 136305000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 136780000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 138195000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 138765000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 139425000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 140115000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 140775000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 142300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 142300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 142300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 142300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 142900000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 144300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 144300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 144300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 144300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 144900000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 147900000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 147900000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 147900000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 147900000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 148600000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 149235000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 149820000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 150420000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 151425000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 152020000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 153400000
Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 153500000
Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 153700000
Test ERRONEOUS CAB MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 154580000
Test ERRONEOUS I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 154680000
Test ERRONEOUS I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 154780000
Test CAB I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 154880000
Test CAB I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 155240000
Test ERRONEOUS WB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 155360000
Test ERRONEOUS WB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 155480000
Test WB CAB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 155600000
Test WB CAB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 158145000
Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 158460000
Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 158540000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 158820000
Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 159945000
Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 161080000
Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 161800000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 162060000
Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 166180000
Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 166440000
Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 167880000
Test CHECK NORMAL READ AFTER ERROR TERMINATED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 168160000
Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 169780000
Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 170040000
Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 171855000
Test TARGET ABORT ERROR ON SINGLE WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 172185000
Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 172700000
Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 172980000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 173260000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 173520000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 174435000
Test TARGET ABORT ERROR ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 174720000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 175260000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 175540000
Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 177645000
Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 177940000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 178480000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 178560000
Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 179320000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 180060000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 180940000
Test TARGET ABORT DURING SINGLE MEMORY READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 181200000
Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 181480000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 181960000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 182800000
Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 183060000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 184320000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 185540000
Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 185820000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 187080000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 187725000
Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 188020000
Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 188560000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 188820000
Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 189480000
Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 192945000
Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 193300000
Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 193995000
Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 194340000
Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 194955000
Test MASTER WRITE WITH NO PARITY ERRORS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 195400000
Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 196360000
Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 196520000
Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 196800000
Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 197280000
Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 197660000
Test CLEARANCE OF PARITY INTERRUPT STATUSES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 198240000
Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 198420000
Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 198700000
Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 199180000
Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 200140000
Test MASTER READ TRANSACTION WITH NO PARITY ERRORS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 200400000
Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 200680000
Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 201375000
Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 201660000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 202275000
Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 202605000
Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 202900000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 203385000
Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 203580000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 203860000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 204340000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 204887000
Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 205080000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 205360000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 205840000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 206445000
Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 206640000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 206920000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 207400000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 207885000
Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 208080000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 208360000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 208840000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 209325000
Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 209520000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 209800000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 210280000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 210975000
Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 211160000
Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 211440000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 211920000
Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 212535000
Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 212865000
Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 213160000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 213645000
Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 213840000
Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 214120000
Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 214635000
Test EXTERNAL WRITE WITH NO PARITY ERRORS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 214820000
Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 215100000
Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 215580000
Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 217065000
Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 217260000
Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 217540000
Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 218020000
Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 218925000
Test PARITY ERROR HANDLING ON TARGET READ REFERENCE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 219120000
Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGET
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 219400000
Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 219880000
Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 222945000
Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 223185000
Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 223425000
Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 223935000
Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRY
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 224205000
Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 224445000
Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 225075000
Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 225315000
Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 225945000
Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 226515000
Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 226905000
Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 227625000
Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 227865000
Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 228705000
Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 231615000
Test FULL WRITE FIFO BURST RETRIED FIRST TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 231885000
Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 232305000
Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 232725000
Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 241515000
Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 260520000
Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 261420000
Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIME
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 266020000
Test BURST READ WITH DISCONNECT ON FIRST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 266820000
Test BURST READ WITH DISCONNECT AFTER FIRST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 267520000
Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 268660000
Test BURST READ WITH NORMAL TERMINATION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 270060000
Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 270660000
Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 277840000
Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALID
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 278620000
Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALID
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 279400000
Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZERO
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 280395000
Test LATENCY TIMER OPERATION ON PCI MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 284080000
Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 284920000
Test LATENCY TIMER OPERATION DURING MASTER READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 285820000
Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 286600000
Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 287200000
Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 318495000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 319040000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 319515000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 320040000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 321465000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 322095000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 322725000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 323415000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 324105000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 325680000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 325680000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 325680000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 325680000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 326380000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 327780000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 327780000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 327780000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 327780000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 328480000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 331480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 331480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 331480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 331480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 332180000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 332805000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 333400000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 334000000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 334995000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 335580000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 337305000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 337840000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 338295000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 338840000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 340275000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 340875000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 341535000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 342225000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 342885000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 344480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 344480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 344480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 344480000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 345180000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 346580000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 346580000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 346580000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 346580000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 347280000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 350280000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 350280000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 350280000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 350280000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 350980000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 351615000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 352200000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 352800000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 353805000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 354400000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 356115000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 356660000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 357135000
Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 357660000
Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 359085000
Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 359715000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 360345000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 361035000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 361725000
Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 363300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 363300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 363300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 363300000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 364000000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 365400000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 365400000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 365400000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 365400000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 366100000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 369100000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 369100000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 369100000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 369100000
Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 369800000
Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 370425000
Test I/O WRITE TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 371020000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 371620000
Test I/O READ TRANSACTION FROM WB TO PCI TEST
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 372615000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 373200000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 374580000
Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 374680000
Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 374880000
Test ERRONEOUS CAB MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 375760000
Test ERRONEOUS I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 375860000
Test ERRONEOUS I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 375960000
Test CAB I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 376060000
Test CAB I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 376420000
Test ERRONEOUS WB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 376540000
Test ERRONEOUS WB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 376660000
Test WB CAB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 376780000
Test WB CAB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 379335000
Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 379680000
Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 379760000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 380040000
Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 381165000
Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 382300000
Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 383020000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 383280000
Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 387500000
Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 387780000
Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 389320000
Test CHECK NORMAL READ AFTER ERROR TERMINATED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 389580000
Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 391200000
Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 391480000
Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 393315000
Test TARGET ABORT ERROR ON SINGLE WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 393675000
Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 394140000
Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 394420000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 394680000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 394960000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 395925000
Test TARGET ABORT ERROR ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 396220000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 396760000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 397020000
Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 399195000
Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 399480000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 400020000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 400100000
Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 400860000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 401640000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 402520000
Test TARGET ABORT DURING SINGLE MEMORY READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 402780000
Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 403060000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 403540000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 404380000
Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 404640000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 406000000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 407320000
Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 407580000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 408940000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 409575000
Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 409860000
Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 410400000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 410680000
Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 411340000
Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 414825000
Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 415180000
Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 415905000
Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 416260000
Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 416895000
Test MASTER WRITE WITH NO PARITY ERRORS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 417340000
Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 418300000
Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 418460000
Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
.
.
.
 
*****************************************************************************************
At time 1960240000
Test CHECK MAXIMUM IMAGE SIZE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1961700000
Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1961820000
Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1962020000
Test ERRONEOUS CAB MEMORY READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963060000
Test ERRONEOUS I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963180000
Test ERRONEOUS I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963280000
Test CAB I/O WRITE TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963380000
Test CAB I/O READ TO WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963800000
Test ERRONEOUS WB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1963940000
Test ERRONEOUS WB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1964060000
Test WB CAB CONFIGURATION WRITE ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1964180000
Test WB CAB CONFIGURATION READ ACCESS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1966935000
Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1967300000
Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1967380000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1967660000
Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1968885000
Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1970120000
Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1970900000
Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1971180000
Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1975460000
Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1975760000
Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1977320000
Test CHECK NORMAL READ AFTER ERROR TERMINATED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1977620000
Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1979240000
Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1979540000
Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1981455000
Test TARGET ABORT ERROR ON SINGLE WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1981845000
Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1982360000
Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1982660000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1982960000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1983260000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1984335000
Test TARGET ABORT ERROR ON CAB MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1984640000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1985240000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1985540000
Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1987755000
Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1988060000
Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1988660000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1988740000
Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1989540000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1990340000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1991360000
Test TARGET ABORT DURING SINGLE MEMORY READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1991660000
Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1991960000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1992480000
Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1993360000
Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1993640000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1995020000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1996260000
Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1996560000
Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1997920000
Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1998585000
Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1998900000
Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1999500000
Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 1999800000
Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 2000480000
Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE
reported *SUCCESSFULL*!
*****************************************************************************************
.
.
.
 
*****************************************************************************************
At time 5175780000
Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEARED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5176900000
Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFER
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5177220000
Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5177640000
Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WB
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5179380000
Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFER
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5179720000
Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5180040000
Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WB
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5180380000
Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WB
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5180780000
Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WB
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5181255000
Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WB
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5181320000
Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEARED
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5184680000
Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5187690000
Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5190200000
Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5193210000
Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTES
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5195160000
Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5195500000
Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5195580000
Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 5196360000
Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONE
reported *SUCCESSFULL*!
*****************************************************************************************
.
.
.
 
*****************************************************************************************
At time 35435595000
Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35435805000
Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATION
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35436615000
Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35437060000
Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTS
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35442465000
Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGET
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35445045000
Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGET
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35446240000
Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35450840000
Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGET
reported *SUCCESSFULL*!
*****************************************************************************************
*****************************************************************************************
At time 35453520000
Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVE
reported *SUCCESSFULL*!
*****************************************************************************************
******************************* PCI Testcase summary *******************************
Tests performed: 36000
Failed tests : 0
Successfull tests: 36000
******************************* PCI Testcase summary *******************************
trunk/sim/rtl_sim/log/example_pci_tb.log Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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