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Rev 29 → Rev 30
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/variants/T6502/T6502_defines.v
1,13 → 1,15
`define VARIANT T6502 |
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`define CORE _core |
`define FSM _fsm |
`define ALU _alu |
`define CORE _core |
`define FSM _fsm |
`define ALU _alu |
`define INST_DECODE _inst_decode |
`define STATE _state |
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`define CDE cde |
`define SRAM _sram |
`define CDE cde |
`define SRAM _sram |
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`define IO_MODULE io_module |
`define IO_MODULE io_module |
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//////////////////////////////////////////////////////////////////////////// |
//// //// |
172,33 → 174,26
`define ASL_ABS 8'h0E |
`define ASL_ABX 8'h1E |
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`define BCC_REL 8'h90 |
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`define BCS_REL 8'hB0 |
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`define BEQ_REL 8'hF0 |
`define BMI_REL 8'h30 |
`define BNE_REL 8'hD0 |
`define BPL_REL 8'h10 |
`define BVC_REL 8'h50 |
`define BVS_REL 8'h70 |
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`define BIT_ZPG 8'h24 |
`define BIT_ABS 8'h2C |
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`define BMI_REL 8'h30 |
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`define BNE_REL 8'hD0 |
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`define BPL_REL 8'h10 |
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`define BRK_IMP 8'h00 |
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`define BVC_REL 8'h50 |
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`define BVS_REL 8'h70 |
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`define CLC_IMP 8'h18 |
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`define CLD_IMP 8'hD8 |
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`define CLI_IMP 8'h58 |
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`define CLV_IMP 8'hB8 |
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`define CMP_IMM 8'hC9 |
247,7 → 242,11
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`define JMP_ABS 8'h4C |
`define JMP_IND 8'h6C |
`define JMP_ABX 8'h7C |
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`define JSR_ABS 8'h20 |
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`define LDA_IMM 8'hA9 |
289,13 → 288,11
`define ORA_IDY 8'h11 |
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`define PHA_IMP 8'h48 |
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`define PHP_IMP 8'h08 |
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`define PLA_IMP 8'h68 |
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`define PLP_IMP 8'h28 |
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`define ROL_ACC 8'h2A |
`define ROL_ZPG 8'h26 |
`define ROL_ZPX 8'h36 |
322,11 → 319,10
`define SBC_IDY 8'hF1 |
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`define SEC_IMP 8'h38 |
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`define SED_IMP 8'hF8 |
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`define SEI_IMP 8'h78 |
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`define STA_ZPG 8'h85 |
`define STA_ZPX 8'h95 |
`define STA_ABS 8'h8D |
344,15 → 340,10
`define STY_ABS 8'h8C |
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`define TAX_IMP 8'hAA |
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`define TAY_IMP 8'hA8 |
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`define TSX_IMP 8'hBA |
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`define TXA_IMP 8'h8A |
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`define TXS_IMP 8'h9A |
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`define TYA_IMP 8'h98 |
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/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502.v
17,18 → 17,16
parameter RX_FIFO_SIZE = 3, |
parameter RX_FIFO_WORDS= 8, |
parameter STARTUP = "NONE", |
parameter FONT = "NONE", |
parameter BOOT = 16'hf000 |
parameter FONT = "NONE" |
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) ( |
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input wire clk, |
input wire reset, |
input wire enable, |
output wire [7:0] write_data, |
output wire [15:0] addr_pin, |
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output wire [15:0] addr_pin, |
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output wire txd_pad_out, |
input wire rxd_pad_in, |
55,12 → 53,12
input wire [3:0] ext_irq_in, |
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output wire [2:0] vgared_pad_out, |
output wire [2:0] vgagreen_pad_out, |
output wire [1:0] vgablue_pad_out, |
output wire [2:0] vgared_pad_out, |
output wire [2:0] vgagreen_pad_out, |
output wire [1:0] vgablue_pad_out, |
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output wire hsync_n_pad_out, |
output wire vsync_n_pad_out |
output wire hsync_n_pad_out, |
output wire vsync_n_pad_out |
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68,6 → 66,10
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); |
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wire [7:0] write_data; |
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wire [15:0] pc; |
wire [7:0] read_data; |
wire [7:0] flash_data; |
79,7 → 81,7
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wire we_pin; |
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assign rd_pin = !we_pin; |
assign rd_pin = !we_pin && (!reset); |
assign din = sram_data & flash_data & read_data; |
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92,27 → 94,39
if(addr_pin[15:12] == 4'b0000) |
begin |
CS0 = 1'b1; |
CS = 1'b0; |
end |
else |
begin |
CS0 = 1'b0; |
end |
end |
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always@(*) |
begin |
if(addr_pin[15:12] == 4'b1111) |
begin |
CS0 = 1'b0; |
CS = 1'b1; |
end |
else |
begin |
CS0 = 1'b0; |
CS = 1'b0; |
end |
end |
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reg enable; |
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always@(posedge clk) |
if(reset) enable <= 1'b0; |
else enable <= !enable; |
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`VARIANT`CORE |
#(.BOOT(BOOT)) |
core ( |
.clk ( clk ), |
.reset ( reset ), |
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_state.v
0,0 → 1,524
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`include "T6502_defines.v" |
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module `VARIANT`STATE |
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( |
input wire clk, |
input wire reset, |
input wire enable, |
input wire tsx, |
input wire immediate, |
input wire zero_page, |
input wire zero_page_indexed, |
input wire absolute, |
input wire absolute_indexed, |
input wire relative, |
input wire brk, |
input wire rts, |
input wire pha, |
input wire php, |
input wire indirectx, |
input wire indirecty, |
input wire branch_inst, |
input wire page_crossed, |
input wire jump_indirect, |
input wire jump, |
input wire write, |
input wire read_modify_write, |
input wire read, |
input wire jsr, |
input wire pla, |
input wire plp, |
input wire rti, |
input wire accumulator, |
input wire implied, |
input wire txs, |
input wire nop, |
input wire invalid, |
input wire [7:0] temp_data, |
input wire [7:0] data_in, |
input wire [7:0] sp, |
input wire [7:0] ir, |
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output reg [4:0] state, |
output reg [7:0] alu_opcode, |
output reg [7:0] alu_a, |
output reg alu_enable |
); |
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// FSM states. If aiming for less power consumption try gray coding. |
localparam FETCH_OP = 5'b00000; |
localparam FETCH_LOW = 5'b00010; |
localparam FETCH_HIGH = 5'b00011; |
localparam READ_MEM = 5'b00100; |
localparam DUMMY_WRT_CALC = 5'b00101; |
localparam WRITE_MEM = 5'b00110; |
localparam FETCH_OP_CALC_PARAM = 5'b00111; |
localparam READ_MEM_CALC_INDEX = 5'b01000; |
localparam FETCH_HIGH_CALC_INDEX = 5'b01001; |
localparam READ_MEM_FIX_ADDR = 5'b01010; |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011; |
localparam FETCH_OP_FIX_PC = 5'b01100; |
localparam READ_FROM_POINTER = 5'b01101; |
localparam READ_FROM_POINTER_X = 5'b01110; |
localparam READ_FROM_POINTER_X1 = 5'b01111; |
localparam PUSH_PCH = 5'b10000; |
localparam PUSH_PCL = 5'b10001; |
localparam PUSH_STATUS = 5'b10010; |
localparam FETCH_PCL = 5'b10011; |
localparam FETCH_PCH = 5'b10100; |
localparam INCREMENT_SP = 5'b10101; |
localparam PULL_STATUS = 5'b10110; |
localparam PULL_PCL = 5'b10111; |
localparam PULL_PCH = 5'b11000; |
localparam INCREMENT_PC = 5'b11001; |
localparam PUSH_REGISTER = 5'b11010; |
localparam PULL_REGISTER = 5'b11011; |
localparam DUMMY = 5'b11100; |
localparam RESET = 5'b11111; |
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// rw_mem signals |
localparam MEM_READ = 1'b0; |
localparam MEM_WRITE = 1'b1; |
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reg [4:0] next_state; |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
state <= 5'h0d; |
end |
else if(!enable) |
begin |
state <= state ; |
end |
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else state <= next_state; |
end // always @ (posedge clk ) |
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always @ (*) |
begin // this is the next_state logic and the combinational output logic always block |
alu_opcode = 8'h00; |
alu_a = 8'h00; |
alu_enable = 1'b0; |
next_state = RESET; // these lines prevents latches |
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if (invalid == 1'b1) |
begin |
next_state = FETCH_OP; |
end |
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else |
case (state) |
RESET: |
begin |
if (1) |
begin |
next_state = FETCH_OP; |
end |
end |
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FETCH_OP: |
begin |
next_state = FETCH_LOW; |
end |
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FETCH_OP_CALC_PARAM: |
begin |
next_state = FETCH_LOW; |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = temp_data; |
end |
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FETCH_LOW: |
begin |
if (accumulator || implied || txs) |
begin |
if (!nop) |
begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
end |
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next_state = FETCH_OP; |
end |
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else |
if (tsx) |
begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = FETCH_OP; |
alu_a = sp[7:0]; |
end |
else |
if (immediate) |
begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
else |
if (zero_page) |
begin |
if (read || read_modify_write) |
begin |
next_state = READ_MEM; |
end |
else |
if (write) |
begin |
next_state = WRITE_MEM; |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = 8'h00; |
end |
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end // if (zero_page) |
else |
if (zero_page_indexed) |
begin |
next_state = READ_MEM_CALC_INDEX; |
end |
else |
if (absolute || jump_indirect) |
begin |
next_state = FETCH_HIGH; |
if (write) |
begin // this is being done one cycle early but i have checked and the ALU will still work properly |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = 8'h00; |
end |
end // if (absolute || jump_indirect) |
else |
if (absolute_indexed) |
begin |
next_state = FETCH_HIGH_CALC_INDEX; |
end |
else |
if (relative) |
begin |
next_state = FETCH_OP_EVAL_BRANCH; |
end |
else |
if (indirectx || indirecty) |
begin |
next_state = READ_FROM_POINTER; |
end |
else |
begin // all the special instructions will fall here |
if (brk) |
begin |
next_state = PUSH_PCH; |
end |
else |
if (rti || rts) |
begin |
next_state = INCREMENT_SP; |
end |
else |
if (pha) |
begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = PUSH_REGISTER; |
end |
else |
if (php) |
begin |
next_state = PUSH_REGISTER; |
end |
else |
if (pla || plp) |
begin |
next_state = INCREMENT_SP; |
end |
else |
begin // jsr |
next_state = DUMMY; |
end |
end // else: !if(indirectx || indirecty) |
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end // case: FETCH_LOW |
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READ_FROM_POINTER: |
begin |
if (indirectx) |
begin |
next_state = READ_FROM_POINTER_X; |
end |
else |
begin // indirecty and jump indirect falls here |
next_state = READ_FROM_POINTER_X1; |
end |
end // case: READ_FROM_POINTER |
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READ_FROM_POINTER_X: |
begin |
next_state = READ_FROM_POINTER_X1; |
end |
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READ_FROM_POINTER_X1: |
begin |
if (jump_indirect) |
begin |
next_state = FETCH_OP; |
end |
else |
if (indirecty) |
begin |
next_state = READ_MEM_FIX_ADDR; |
end |
else |
begin |
if (read) |
begin // no instruction using pointers is from type read_modify_write |
next_state = READ_MEM; |
end |
else |
if (write) |
begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = WRITE_MEM; |
end |
end |
end // case: READ_FROM_POINTER_X1 |
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FETCH_OP_EVAL_BRANCH: |
begin |
if (branch_inst) |
begin |
next_state = FETCH_OP; //??????????? |
end |
else |
begin |
next_state = FETCH_LOW; |
end |
end // case: FETCH_OP_EVAL_BRANCH |
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FETCH_OP_FIX_PC: |
begin |
if (page_crossed) |
begin |
next_state = FETCH_OP; |
end |
else |
begin |
next_state = FETCH_LOW; |
end |
end // case: FETCH_OP_FIX_PC |
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FETCH_HIGH_CALC_INDEX: |
begin |
next_state = READ_MEM_FIX_ADDR; |
end |
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READ_MEM_FIX_ADDR: |
begin |
if (read) |
begin |
if (page_crossed) |
begin |
next_state = READ_MEM; |
end |
else |
begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
end |
else |
if (read_modify_write) |
begin |
next_state = READ_MEM; |
end |
else |
if (write) |
begin |
next_state = WRITE_MEM; |
alu_enable = 1'b1; |
alu_opcode = ir; |
end |
end // case: READ_MEM_FIX_ADDR |
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FETCH_HIGH: |
begin |
if (jump_indirect) |
begin |
next_state = READ_FROM_POINTER; |
end |
else |
if (jump) |
begin |
next_state = FETCH_OP; |
end |
else |
if (read || read_modify_write) |
begin |
next_state = READ_MEM; |
end |
else |
if (write) |
begin |
next_state = WRITE_MEM; |
end |
end // case: FETCH_HIGH |
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READ_MEM_CALC_INDEX: begin |
if (read || read_modify_write) begin |
next_state = READ_MEM; |
end |
else if (write) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = WRITE_MEM; |
end |
else begin |
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end |
end |
READ_MEM: begin |
if (read) begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
else if (read_modify_write) begin |
next_state = DUMMY_WRT_CALC; |
end |
end |
DUMMY_WRT_CALC: begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = data_in; |
next_state = WRITE_MEM; |
end |
WRITE_MEM: begin |
next_state = FETCH_OP; |
end |
PUSH_PCH: begin |
next_state = PUSH_PCL; |
end |
PUSH_PCL: begin |
if (jsr) begin |
next_state = FETCH_HIGH; |
end |
else begin |
next_state = PUSH_STATUS; |
end |
end |
PUSH_STATUS: begin |
next_state = FETCH_PCL; |
end |
FETCH_PCL: begin |
next_state = FETCH_PCH; |
end |
FETCH_PCH: begin |
next_state = FETCH_OP; |
end |
INCREMENT_SP: begin |
if (rti) begin |
next_state = PULL_STATUS; |
end |
else if (pla || plp) begin |
next_state = PULL_REGISTER; |
end |
else begin // rts |
next_state = PULL_PCL; |
end |
end |
PULL_STATUS: begin |
next_state = PULL_PCL; |
end |
PULL_PCL: begin |
next_state = PULL_PCH; |
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if (rti) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = temp_data; |
end |
end |
PULL_PCH: begin |
if (rti) begin |
next_state = FETCH_OP; |
end |
else begin // rts |
next_state = INCREMENT_PC; |
end |
end |
INCREMENT_PC: begin |
next_state = FETCH_OP; |
end |
PUSH_REGISTER: begin |
next_state = FETCH_OP; |
end |
PULL_REGISTER: begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
DUMMY: begin |
next_state = PUSH_PCH; |
end |
default: begin |
next_state = RESET; |
end |
endcase |
end |
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endmodule |
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/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_inst_decode.v
0,0 → 1,657
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`include "T6502_defines.v" |
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module `VARIANT`INST_DECODE |
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( |
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input wire clk, |
input wire reset, |
input wire enable, |
input wire [7:0] alu_status, // alu status register |
input wire [7:0] ir, // instruction register |
input wire [4:0] state, // state |
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// wiring that simplifies the FSM logic by simplifying the addressing modes |
output reg absolute, |
output reg absolute_indexed, |
output reg accumulator, |
output reg immediate, |
output reg implied, |
output reg indirectx, |
output reg indirecty, |
output reg relative, |
output reg zero_page, |
output reg zero_page_indexed, |
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// regs that store the type of operation. again, this simplifies the FSM a lot. |
output reg read, |
output reg read_modify_write, |
output reg write, |
output reg jump, |
output reg jump_indirect, |
output reg index_is_x, |
output reg index_is_branch, |
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// regs for the special instructions |
output reg brk, |
output reg rti, |
output reg rts, |
output reg pha, |
output reg php, |
output reg pla, |
output reg plp, |
output reg jsr, |
output reg tsx, |
output reg txs, |
output reg nop, |
output reg invalid, |
output reg branch_inst // a simple reg that is asserted everytime a branch will be executed. |
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); |
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// FSM states. If aiming for less power consumption try gray coding. |
localparam FETCH_OP = 5'b00000; |
localparam FETCH_LOW = 5'b00010; |
localparam FETCH_HIGH = 5'b00011; |
localparam READ_MEM = 5'b00100; |
localparam DUMMY_WRT_CALC = 5'b00101; |
localparam WRITE_MEM = 5'b00110; |
localparam FETCH_OP_CALC_PARAM = 5'b00111; |
localparam READ_MEM_CALC_INDEX = 5'b01000; |
localparam FETCH_HIGH_CALC_INDEX = 5'b01001; |
localparam READ_MEM_FIX_ADDR = 5'b01010; |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011; |
localparam FETCH_OP_FIX_PC = 5'b01100; |
localparam READ_FROM_POINTER = 5'b01101; |
localparam READ_FROM_POINTER_X = 5'b01110; |
localparam READ_FROM_POINTER_X1 = 5'b01111; |
localparam PUSH_PCH = 5'b10000; |
localparam PUSH_PCL = 5'b10001; |
localparam PUSH_STATUS = 5'b10010; |
localparam FETCH_PCL = 5'b10011; |
localparam FETCH_PCH = 5'b10100; |
localparam INCREMENT_SP = 5'b10101; |
localparam PULL_STATUS = 5'b10110; |
localparam PULL_PCL = 5'b10111; |
localparam PULL_PCH = 5'b11000; |
localparam INCREMENT_PC = 5'b11001; |
localparam PUSH_REGISTER = 5'b11010; |
localparam PULL_REGISTER = 5'b11011; |
localparam DUMMY = 5'b11100; |
localparam RESET = 5'b11111; |
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// rw_mem signals |
localparam MEM_READ = 1'b0; |
localparam MEM_WRITE = 1'b1; |
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// this always block is responsible for updating the address mode and the type of operation being done |
always @ (*) |
begin |
absolute = 1'b0; |
absolute_indexed = 1'b0; |
accumulator = 1'b0; |
immediate = 1'b0; |
implied = 1'b0; |
indirectx = 1'b0; |
indirecty = 1'b0; |
relative = 1'b0; |
zero_page = 1'b0; |
zero_page_indexed = 1'b0; |
index_is_x = 1'b0; |
index_is_branch = 1'b0; |
read = 1'b0; |
read_modify_write = 1'b0; |
write = 1'b0; |
jump = 1'b0; |
jump_indirect = 1'b0; |
branch_inst = 1'b0; |
brk = 1'b0; |
rti = 1'b0; |
rts = 1'b0; |
pha = 1'b0; |
php = 1'b0; |
pla = 1'b0; |
plp = 1'b0; |
jsr = 1'b0; |
tsx = 1'b0; |
txs = 1'b0; |
nop = 1'b0; |
invalid = 1'b0; |
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case (ir) |
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`CLC_IMP, |
`CLD_IMP, |
`CLI_IMP, |
`CLV_IMP, |
`DEX_IMP, |
`DEY_IMP, |
`INX_IMP, |
`INY_IMP, |
`SEC_IMP, |
`SED_IMP, |
`SEI_IMP, |
`TAX_IMP, |
`TAY_IMP, |
`TXA_IMP, |
`TYA_IMP: |
begin |
implied = 1'b1; |
end |
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`NOP_IMP: |
begin |
implied = 1'b1; |
nop = 1'b1; |
end |
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`ASL_ACC, |
`LSR_ACC, |
`ROL_ACC, |
`ROR_ACC: |
begin |
accumulator = 1'b1; |
end |
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`ADC_IMM, |
`AND_IMM, |
`CMP_IMM, |
`CPX_IMM, |
`CPY_IMM, |
`EOR_IMM, |
`LDA_IMM, |
`LDX_IMM, |
`LDY_IMM, |
`ORA_IMM, |
`SBC_IMM: |
begin |
immediate = 1'b1; |
end |
|
|
`ADC_ZPG, |
`AND_ZPG, |
`ASL_ZPG, |
`BIT_ZPG, |
`CMP_ZPG, |
`CPX_ZPG, |
`CPY_ZPG, |
`DEC_ZPG, |
`EOR_ZPG, |
`INC_ZPG, |
`LDA_ZPG, |
`LDX_ZPG, |
`LDY_ZPG, |
`LSR_ZPG, |
`ORA_ZPG, |
`ROL_ZPG, |
`ROR_ZPG, |
`SBC_ZPG, |
`STA_ZPG, |
`STX_ZPG, |
`STY_ZPG: |
begin |
zero_page = 1'b1; |
end |
|
|
`ADC_ZPX, |
`AND_ZPX, |
`ASL_ZPX, |
`CMP_ZPX, |
`DEC_ZPX, |
`EOR_ZPX, |
`INC_ZPX, |
`LDA_ZPX, |
`LDY_ZPX, |
`LSR_ZPX, |
`ORA_ZPX, |
`ROL_ZPX, |
`ROR_ZPX, |
`SBC_ZPX, |
`STA_ZPX, |
`STY_ZPX: |
begin |
zero_page_indexed = 1'b1; |
index_is_x = 1'b1; |
end |
|
|
`LDX_ZPY, |
`STX_ZPY: |
begin |
zero_page_indexed = 1'b1; |
index_is_x = 1'b0; |
end |
|
|
|
`BCC_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (!alu_status[`C]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BCC_REL |
|
|
|
`BCS_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (alu_status[`C]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BCS_REL |
|
|
|
`BEQ_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (alu_status[`Z]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BEQ_REL |
|
|
|
`BNE_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (alu_status[`Z] == 1'b0) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BNE_REL |
|
|
|
`BPL_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (!alu_status[`N]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BPL_REL |
|
|
|
`BMI_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (alu_status[`N]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BMI_REL |
|
|
|
`BVC_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (!alu_status[`V]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BVC_REL |
|
|
|
`BVS_REL: |
begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
if (alu_status[`V]) |
begin |
branch_inst = 1'b1; |
end |
else |
begin |
branch_inst = 1'b0; |
end |
end // case: `BVS_REL |
|
`ADC_ABS, |
`AND_ABS, |
`ASL_ABS, |
`BIT_ABS, |
`CMP_ABS, |
`CPX_ABS, |
`CPY_ABS, |
`DEC_ABS, |
`EOR_ABS, |
`INC_ABS, |
`LDA_ABS, |
`LDX_ABS, |
`LDY_ABS, |
`LSR_ABS, |
`ORA_ABS, |
`ROL_ABS, |
`ROR_ABS, |
`SBC_ABS, |
`STA_ABS, |
`STX_ABS, |
`STY_ABS: |
begin |
absolute = 1'b1; |
end // case: `ADC_ABS,... |
|
|
`ADC_ABX, |
`AND_ABX, |
`ASL_ABX, |
`CMP_ABX, |
`DEC_ABX, |
`EOR_ABX, |
`INC_ABX, |
`LDA_ABX, |
`LDY_ABX, |
`LSR_ABX, |
`ORA_ABX, |
`ROL_ABX, |
`ROR_ABX, |
`SBC_ABX, |
`STA_ABX: |
begin |
absolute_indexed = 1'b1; |
index_is_x = 1'b1; |
end // case: `ADC_ABX,... |
|
`ADC_ABY, |
`AND_ABY, |
`CMP_ABY, |
`EOR_ABY, |
`LDA_ABY, |
`LDX_ABY, |
`ORA_ABY, |
`SBC_ABY, |
`STA_ABY: |
begin |
absolute_indexed = 1'b1; |
index_is_x = 1'b0; |
end // case: `ADC_ABY,... |
|
`ADC_IDX, |
`AND_IDX, |
`CMP_IDX, |
`EOR_IDX, |
`LDA_IDX, |
`ORA_IDX, |
`SBC_IDX, |
`STA_IDX: |
begin |
indirectx = 1'b1; |
index_is_x = 1'b1; |
end // case: `ADC_IDX,... |
|
`ADC_IDY, |
`AND_IDY, |
`CMP_IDY, |
`EOR_IDY, |
`LDA_IDY, |
`ORA_IDY, |
`SBC_IDY, |
`STA_IDY: |
begin |
indirecty = 1'b1; |
index_is_x = 1'b0; |
end // case: `ADC_IDY,... |
|
`JMP_ABS: |
begin |
absolute = 1'b1; |
jump = 1'b1; |
end |
|
`JMP_ABX: |
begin |
absolute_indexed = 1'b1; |
index_is_x = 1'b1; |
jump = 1'b1; |
end |
|
|
`JMP_IND: |
begin |
jump_indirect = 1'b1; |
end |
|
`BRK_IMP: |
begin |
brk = 1'b1; |
end |
|
`RTI_IMP: |
begin |
rti = 1'b1; |
end |
|
`RTS_IMP: |
begin |
rts = 1'b1; |
end |
|
`PHA_IMP: |
begin |
pha = 1'b1; |
end |
|
`PHP_IMP: |
begin |
php = 1'b1; |
end |
|
`PLA_IMP: |
begin |
pla = 1'b1; |
end |
|
`PLP_IMP: |
begin |
plp = 1'b1; |
end |
|
`JSR_ABS: |
begin |
jsr = 1'b1; |
jump = 1'b1; |
end |
|
`TSX_IMP: |
begin |
tsx = 1'b1; |
end |
|
`TXS_IMP: |
begin |
txs = 1'b1; |
end |
|
default: |
begin |
index_is_x = 1'b1; |
|
if (reset == 1'b0 && state != FETCH_OP_FIX_PC) |
begin // the processor is NOT being reset neither it is fixing the pc |
invalid = 1'b1; |
end |
end |
|
endcase |
|
|
|
|
case (ir) |
`ASL_ACC, |
`ASL_ZPG, |
`ASL_ZPX, |
`ASL_ABS, |
`ASL_ABX, |
`LSR_ACC, |
`LSR_ZPG, |
`LSR_ZPX, |
`LSR_ABS, |
`LSR_ABX, |
`ROL_ACC, |
`ROL_ZPG, |
`ROL_ZPX, |
`ROL_ABS, |
`ROL_ABX, |
`ROR_ACC, |
`ROR_ZPG, |
`ROR_ZPX, |
`ROR_ABS, |
`ROR_ABX, |
`INC_ZPG, |
`INC_ZPX, |
`INC_ABS, |
`INC_ABX, |
`DEC_ZPG, |
`DEC_ZPX, |
`DEC_ABS, |
`DEC_ABX: |
begin |
read_modify_write = 1'b1; |
end // case: `ASL_ACC,... |
|
`STA_ZPG, |
`STA_ZPX, |
`STA_ABS, |
`STA_ABX, |
`STA_ABY, |
`STA_IDX, |
`STA_IDY, |
`STX_ZPG, |
`STX_ZPY, |
`STX_ABS, |
`STY_ZPG, |
`STY_ZPX, |
`STY_ABS: |
begin |
write = 1'b1; |
end // case: `STA_ZPG,... |
|
default: |
begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes |
read = 1'b1; |
end |
endcase |
end |
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endmodule |
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/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu.v
14,6 → 14,7
input wire [7:0] alu_opcode, |
input wire [7:0] alu_a, |
|
output reg [7:0] raw_result, |
output reg [7:0] alu_result, |
output reg [7:0] alu_status, |
output reg [7:0] alu_x, |
42,6 → 43,12
reg [7:0] AL; |
reg [7:0] AH; |
|
|
always@(*) raw_result = result[7:0]; |
|
|
|
|
always @ (posedge clk ) |
begin |
if (reset) begin |
60,7 → 67,7
end |
|
else |
if ( !enable ) begin |
if (!enable ) begin |
alu_result <= alu_result; |
alu_status <= alu_status; |
A <= A; |
113,9 → 120,11
end |
`STX_ZPG, `STX_ZPY, `STX_ABS : begin |
alu_x <= result[7:0]; |
alu_result <= result[7:0]; |
end |
`STY_ZPG, `STY_ZPX, `STY_ABS : begin |
alu_y <= result[7:0]; |
alu_result <= result[7:0]; |
end |
`SEC_IMP : begin |
alu_status[`C] <= 1'b1; |
176,26 → 185,17
end |
|
always @ (*) begin |
op1 = A; |
op2 = alu_a; |
result = {2'd0, A[7:0]}; |
result[9:8] = 2'b00; |
STATUS[`N] = alu_status[`N]; |
STATUS[`C] = alu_status[`C]; |
STATUS[`V] = alu_status[`V]; |
STATUS[`B] = alu_status[`B]; |
STATUS[`I] = alu_status[`I]; |
STATUS[`D] = alu_status[`D]; |
STATUS[`Z] = alu_status[`Z]; |
STATUS[5] = 1'b1; |
op1 = A; |
op2 = alu_a; |
result = {2'd0, A[7:0]}; |
STATUS = alu_status; |
bcdl = 8'd0; |
bcdh = 8'd0; |
bcdh2 = 8'd0; |
AL = 8'd0; |
AH = 8'd0; |
|
bcdl = 8'd0; |
bcdh = 8'd0; |
bcdh2 = 8'd0; |
AL = 8'd0; |
AH = 8'd0; |
|
if (alu_enable == 1'b1) begin |
if (alu_enable) begin |
case (alu_opcode) |
// BIT - Bit Test |
`BIT_ZPG, `BIT_ABS: begin |
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_fsm.v
3,25 → 3,28
|
module `VARIANT`FSM |
|
#(parameter BOOT= 16'hf000) |
|
( |
|
input wire clk, |
input wire reset, |
input wire enable, |
input wire [7:0] alu_result, // result from alu operation |
input wire [7:0] alu_status, // alu status register |
input wire [7:0] data_in, // data that comes from the bus controller |
input wire [7:0] alu_x, // alu x index register |
input wire [7:0] alu_y, // alu y index register |
input wire clk, |
input wire reset, |
input wire enable, |
input wire [7:0] alu_result, // result from alu operation |
input wire [7:0] raw_result, // unlatched result from alu operation |
input wire [7:0] alu_status, // alu status register |
input wire [7:0] data_in, // data that comes from the bus controller |
input wire [7:0] alu_x, // alu x index register |
input wire [7:0] alu_y, // alu y index register |
|
output reg [15:0] address, // system bus address |
output reg [15:0] pc, // program counter |
output reg rw_mem, // read = 0, write = 1 |
output reg [7:0] data_out, // data that will be written somewhere else |
output reg [7:0] alu_opcode, // current opcode |
output reg [7:0] alu_a, // extra operand sent to the alu |
output reg alu_enable // a flag that when high tells the alu when to perform the operations |
output reg [7:0] ir, // instruction register |
output wire [4:0] state, // current and next state registers |
output reg [15:0] address, // system bus address |
output reg [15:0] pc, // program counter |
output reg rw_mem, // read = 0, write = 1 |
output reg [7:0] data_out, // data that will be written somewhere else |
output wire [7:0] alu_opcode, // current opcode |
output wire [7:0] alu_a, // extra operand sent to the alu |
output wire alu_enable // a flag that when high tells the alu when to perform the operations |
|
|
|
32,1104 → 35,164
|
|
|
// FSM states. If aiming for less power consumption try gray coding. |
//localparam FETCH_OP_CALC = 5'b00001; this was never used |
localparam FETCH_OP = 5'b00000; |
localparam FETCH_LOW = 5'b00010; |
localparam FETCH_HIGH = 5'b00011; |
localparam READ_MEM = 5'b00100; |
localparam DUMMY_WRT_CALC = 5'b00101; |
localparam WRITE_MEM = 5'b00110; |
localparam FETCH_OP_CALC_PARAM = 5'b00111; |
localparam READ_MEM_CALC_INDEX = 5'b01000; |
localparam FETCH_HIGH_CALC_INDEX = 5'b01001; |
localparam READ_MEM_FIX_ADDR = 5'b01010; |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011; |
localparam FETCH_OP_FIX_PC = 5'b01100; |
localparam READ_FROM_POINTER = 5'b01101; |
localparam READ_FROM_POINTER_X = 5'b01110; |
localparam READ_FROM_POINTER_X1 = 5'b01111; |
localparam PUSH_PCH = 5'b10000; |
localparam PUSH_PCL = 5'b10001; |
localparam PUSH_STATUS = 5'b10010; |
localparam FETCH_PCL = 5'b10011; |
localparam FETCH_PCH = 5'b10100; |
localparam INCREMENT_SP = 5'b10101; |
localparam PULL_STATUS = 5'b10110; |
localparam PULL_PCL = 5'b10111; |
localparam PULL_PCH = 5'b11000; |
localparam INCREMENT_PC = 5'b11001; |
localparam PUSH_REGISTER = 5'b11010; |
localparam PULL_REGISTER = 5'b11011; |
localparam DUMMY = 5'b11100; |
localparam RESET = 5'b11111; |
// FSM states. If aiming for less power consumption try gray coding. |
localparam FETCH_OP = 5'b00000; |
localparam FETCH_LOW = 5'b00010; |
localparam FETCH_HIGH = 5'b00011; |
localparam READ_MEM = 5'b00100; |
localparam DUMMY_WRT_CALC = 5'b00101; |
localparam WRITE_MEM = 5'b00110; |
localparam FETCH_OP_CALC_PARAM = 5'b00111; |
localparam READ_MEM_CALC_INDEX = 5'b01000; |
localparam FETCH_HIGH_CALC_INDEX = 5'b01001; |
localparam READ_MEM_FIX_ADDR = 5'b01010; |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011; |
localparam FETCH_OP_FIX_PC = 5'b01100; |
localparam READ_FROM_POINTER = 5'b01101; |
localparam READ_FROM_POINTER_X = 5'b01110; |
localparam READ_FROM_POINTER_X1 = 5'b01111; |
localparam PUSH_PCH = 5'b10000; |
localparam PUSH_PCL = 5'b10001; |
localparam PUSH_STATUS = 5'b10010; |
localparam FETCH_PCL = 5'b10011; |
localparam FETCH_PCH = 5'b10100; |
localparam INCREMENT_SP = 5'b10101; |
localparam PULL_STATUS = 5'b10110; |
localparam PULL_PCL = 5'b10111; |
localparam PULL_PCH = 5'b11000; |
localparam INCREMENT_PC = 5'b11001; |
localparam PUSH_REGISTER = 5'b11010; |
localparam PULL_REGISTER = 5'b11011; |
localparam DUMMY = 5'b11100; |
localparam RESET = 5'b11111; |
|
|
|
// rw_mem signals |
localparam MEM_READ = 1'b0; |
localparam MEM_WRITE = 1'b1; |
// rw_mem signals |
localparam MEM_READ = 1'b0; |
localparam MEM_WRITE = 1'b1; |
|
|
reg [7:0] sp; // stack pointer. 9 bits wide. |
reg [7:0] ir; // instruction register |
reg [15:0] temp_addr; // temporary address |
reg [7:0] temp_data; // temporary data |
reg [7:0] sp; // stack pointer. 9 bits wide. |
reg [15:0] temp_addr; // temporary address |
reg [7:0] temp_data; // temporary data |
|
reg [4:0] state, next_state; // current and next state registers |
reg [7:0] index; // will be assigned with either X or Y |
|
// wiring that simplifies the FSM logic by simplifying the addressing modes |
reg absolute; |
reg absolute_indexed; |
reg accumulator; |
reg immediate; |
reg implied; |
reg indirectx; |
reg indirecty; |
reg relative; |
reg zero_page; |
reg zero_page_indexed; |
reg [7:0] index; // will be assigned with either X or Y |
|
// regs that store the type of operation. again, this simplifies the FSM a lot. |
reg read; |
reg read_modify_write; |
reg write; |
reg jump; |
reg jump_indirect; |
reg index_is_x; |
reg index_is_branch; |
// wiring that simplifies the FSM logic by simplifying the addressing modes |
wire absolute; |
wire absolute_indexed; |
wire accumulator; |
wire immediate; |
wire implied; |
wire indirectx; |
wire indirecty; |
wire relative; |
wire zero_page; |
wire zero_page_indexed; |
|
// regs for the special instructions |
reg brk; |
reg rti; |
reg rts; |
reg pha; |
reg php; |
reg pla; |
reg plp; |
reg jsr; |
reg tsx; |
reg txs; |
reg nop; |
|
reg invalid; |
// regs that store the type of operation. again, this simplifies the FSM a lot. |
wire read; |
wire read_modify_write; |
wire write; |
wire jump; |
wire jump_indirect; |
wire index_is_x; |
wire index_is_branch; |
|
wire [15:0] next_pc; // a simple logic to add one to the PC |
assign next_pc = pc + 16'b0000000000000001; |
// regs for the special instructions |
wire brk; |
wire rti; |
wire rts; |
wire pha; |
wire php; |
wire pla; |
wire plp; |
wire jsr; |
wire tsx; |
wire txs; |
wire nop; |
|
wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer |
assign sp_plus_one = {1'b1, sp[7:0] + 8'b00000001}; |
wire invalid; |
wire branch_inst; // a simple reg that is asserted everytime a branch will be executed. |
|
wire [8:0] sp_minus_one; |
assign sp_minus_one = {1'b1, sp[7:0] - 8'b00000001}; |
|
reg [15:0] address_plus_index; // this two registers are used when the instruction uses indexing. |
reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry. |
|
reg branch; // a simple reg that is asserted everytime a branch will be executed. |
|
wire [15:0] next_pc; // a simple logic to add one to the PC |
assign next_pc = pc + 16'b0000000000000001; |
|
// this is the combinational logic related to indexed instructions |
always @(*) begin |
address_plus_index = 16'h0000; |
page_crossed = 1'b0; |
wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer |
assign sp_plus_one = {1'b1, sp[7:0] + 8'b00000001}; |
|
case (state) |
READ_MEM_FIX_ADDR, FETCH_HIGH_CALC_INDEX: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
address_plus_index[15:8] = temp_addr[15:8] + page_crossed; |
end |
READ_FROM_POINTER_X1: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
address_plus_index[15:8] = data_in[7:0]; |
end |
FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin |
if (branch) begin address_plus_index = pc[15:0] + {{8{index[7]}},index}; // ??????????? |
// warning: pc might feed these lines twice and cause branch failure |
end // solution: add a temp reg i guess |
end |
|
READ_FROM_POINTER: begin |
if (indirectx) begin |
{page_crossed, address_plus_index[7:0]} = temp_data + index; |
//address_plus_index[12:8] = 5'b00000; // already assigned earlier at this block |
end |
else if (jump_indirect) begin |
address_plus_index[7:0] = temp_addr[7:0] + 8'h01; |
//address_plus_index[12:8] = 5'b00000; |
end |
else begin // indirecty falls here |
address_plus_index[7:0] = temp_data + 8'h01; |
//address_plus_index[12:8] = 5'b00000; |
end |
end |
|
READ_FROM_POINTER_X: begin |
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01; |
//address_plus_index[12:8] = 5'b00000; |
end |
wire [8:0] sp_minus_one; |
assign sp_minus_one = {1'b1, sp[7:0] - 8'b00000001}; |
|
READ_MEM_CALC_INDEX: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
//address_plus_index[12:8] = 5'b00000; |
end |
endcase |
end |
reg [15:0] address_plus_index; // this two registers are used when the instruction uses indexing. |
reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry. |
|
|
reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles |
|
always @ (posedge clk ) begin // sequencial always block |
if (reset) begin |
// all registers must assume default values |
pc <= BOOT; // TODO: this is written somewhere. something about a reset vector. must be checked. |
sp <= 9'b111111111; // the default is 'h1FF |
ir <= 8'h00; |
temp_addr <= 16'h0000; |
temp_data <= 8'h00; |
state <= RESET; |
// registered outputs also receive default values |
address <= BOOT; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
rst_counter <= 3'h0; |
index <= 8'h00; |
end // if (reset) |
else if(!enable) |
begin |
pc <= pc; |
sp <= sp; |
ir <= ir; |
temp_addr <= temp_addr; |
temp_data <= temp_data; |
state <= state ; |
address <= address; |
rw_mem <= rw_mem; |
data_out <= data_out; |
rst_counter <= rst_counter; |
index <= index; |
end |
|
|
|
else begin |
state <= next_state; |
|
case (state) |
RESET: begin // The processor was reset |
rst_counter <= rst_counter + 3'b001; |
//sp <= 9'b111111111; // this prevents flipflops with different drivers |
//$write("under reset"); |
end |
/* |
FETCH_OP: executed when the processor was reset or the last instruction could not fetch. |
FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining) |
*/ |
FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening! |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
ir <= data_in; |
end |
/* |
in this state the opcode is already known so truly execution begins. |
all instructions execute this cycle. |
*/ |
FETCH_LOW: begin |
//$display("index_is_x = %b",index_is_x); |
if (index_is_x == 1'b1) begin |
index <= alu_x; |
//$display("alu_x = %d",alu_x); |
end |
else begin |
index <= alu_y; |
//$display("alu_y = %d",alu_y); |
end |
if (index_is_branch) begin |
index <= data_in; // ?????????????? |
end |
if (accumulator || implied || txs || tsx) begin |
pc <= pc; // is this better? |
address <= pc; |
rw_mem <= MEM_READ; |
|
if (txs) begin |
sp[7:0] <= alu_x; |
end |
//alu_a |
end |
else if (immediate || relative) begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
temp_data <= data_in; // the follow-up byte is saved in temp_data |
end |
else if (absolute || absolute_indexed || jump_indirect) begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
temp_addr <= {{5{1'b0}},data_in}; |
temp_data <= 8'h00; |
end |
else if (zero_page) begin |
pc <= next_pc; |
address <= {{8{1'b0}},data_in}; |
temp_addr <= {{8{1'b0}},data_in}; |
|
if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
else if (zero_page_indexed) begin |
pc <= next_pc; |
address <= {{8{1'b0}}, data_in}; |
temp_addr <= {{8{1'b0}}, data_in}; |
rw_mem <= MEM_READ; |
end |
else if (indirectx || indirecty) begin |
pc <= next_pc; |
address <= data_in; |
temp_data <= data_in; |
rw_mem <= MEM_READ; |
end |
else begin // the special instructions will fall here: BRK, RTI, RTS... |
if (brk) begin |
pc <= next_pc; |
address <= sp; |
data_out <= pc[15:8]; |
rw_mem <= MEM_WRITE; |
end |
else if (rti || rts) begin |
address <= sp; |
rw_mem <= MEM_READ; |
end |
else if (pha || php) begin |
pc <= pc; |
address <= sp; |
data_out <= (pha) ? alu_result : alu_status; |
rw_mem <= MEM_WRITE; |
end |
else if (pla || plp) begin |
pc <= pc; |
address <= sp; |
rw_mem <= MEM_READ; |
end |
else if (invalid) begin |
address <= pc; |
rw_mem <= MEM_READ; |
end |
else begin // jsr |
address <= sp; |
rw_mem <= MEM_READ; |
temp_addr <= {{8{1'b0}}, data_in}; |
pc <= next_pc; |
end |
end |
end |
FETCH_HIGH_CALC_INDEX: begin |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], address_plus_index[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
// this cycle fetchs the next operand while still evaluating if a branch occurred. |
FETCH_OP_EVAL_BRANCH: begin |
if (branch) begin |
pc <= address_plus_index[15:0]; // ??????????? |
address <= address_plus_index[15:0]; // ??????????????? |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
else begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
ir <= data_in; |
end |
end |
// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100 |
FETCH_OP_FIX_PC: begin |
if (page_crossed) begin |
pc[15:8] <= address_plus_index[15:8]; |
address[15:8] <= address_plus_index[15:8]; |
end |
else begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
ir <= data_in; |
end |
end |
// several instructions ocupy 3 bytes in memory. this cycle reads the third byte. |
FETCH_HIGH: begin |
if (jump) begin |
pc <= {data_in[7:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte |
address <= {data_in[7:0], temp_addr[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
else begin |
if (write) begin |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0],temp_addr[7:0]}; |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin // read_modify_write or just read |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0],temp_addr[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
end |
// read memory at address |
READ_MEM: begin |
if (read_modify_write) begin |
pc <= pc; |
address <= temp_addr; |
rw_mem <= MEM_WRITE; |
temp_data <= data_in; |
data_out <= data_in; // writeback the same value |
end |
else begin |
pc <= pc; |
address <= pc; |
temp_data <= data_in; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
READ_MEM_CALC_INDEX: begin |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
|
if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
|
end |
READ_MEM_FIX_ADDR: begin |
if (read) begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
|
if (page_crossed) begin // fix address |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
end |
else begin |
address <= pc; |
temp_data <= data_in; |
end |
end |
else if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
|
end |
else begin // read modify write |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
end |
end |
// some instructions have a dummy write cycle. this is it. |
DUMMY_WRT_CALC: begin |
pc <= pc; |
address <= temp_addr; |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
WRITE_MEM: begin |
pc <= pc; |
address <= pc; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
READ_FROM_POINTER: begin |
if (jump_indirect) begin |
pc[7:0] <= data_in; |
rw_mem <= MEM_READ; |
address <= address_plus_index; |
end |
else begin |
pc <= pc; |
rw_mem <= MEM_READ; |
|
if (indirectx) begin |
address <= address_plus_index; |
end |
else begin // indirecty falls here |
address <= address_plus_index; |
temp_addr <= {{8{1'b0}}, data_in}; |
end |
end |
end |
READ_FROM_POINTER_X: begin |
pc <= pc; |
address <= address_plus_index; |
temp_addr[7:0] <= data_in; |
rw_mem <= MEM_READ; |
end |
READ_FROM_POINTER_X1: begin |
if (jump_indirect) begin |
pc[15:8] <= data_in[7:0]; |
rw_mem <= MEM_READ; |
address <= {data_in[7:0], pc[7:0]}; |
end |
else if (indirectx) begin |
address <= {data_in[7:0], temp_addr[7:0]}; |
if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin |
rw_mem <= MEM_READ; |
end |
end |
else begin // indirecty falls here |
address <= address_plus_index; |
temp_addr[15:8] <= data_in; |
rw_mem <= MEM_READ; |
end |
end |
PUSH_PCH: begin // this is probably wrong |
pc <= pc; |
address <= sp_minus_one; |
data_out <= pc[7:0]; |
rw_mem <= MEM_WRITE; |
sp <= sp_minus_one; |
end |
PUSH_PCL: begin |
if (jsr) begin |
pc <= pc; |
address <= pc; |
rw_mem <= MEM_READ; |
sp <= sp_minus_one; |
end |
else begin |
pc <= pc; |
address <= sp_minus_one; |
data_out <= alu_status; |
rw_mem <= MEM_WRITE; |
sp <= sp_minus_one; |
end |
end |
PUSH_STATUS: begin |
address <= 13'h1FFE; |
rw_mem <= MEM_READ; |
sp <= sp_minus_one; |
end |
FETCH_PCL: begin |
pc[7:0] <= data_in; |
address <= 13'h1FFF; |
rw_mem <= MEM_READ; |
end |
FETCH_PCH: begin |
pc[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], pc[7:0]}; |
rw_mem <= MEM_READ; |
end |
INCREMENT_SP: begin |
sp <= sp_plus_one; |
address <= sp_plus_one; |
end |
PULL_STATUS: begin |
sp <= sp_plus_one; |
address <= sp_plus_one; |
temp_data <= data_in; |
end |
PULL_PCL: begin |
sp <= sp_plus_one; |
address <= sp_plus_one; |
pc[7:0] <= data_in; |
end |
PULL_PCH: begin |
pc[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], pc[7:0]}; |
end |
INCREMENT_PC: begin |
pc <= next_pc; |
address <= next_pc; |
end |
PUSH_REGISTER: begin |
pc <= pc; |
address <= pc; |
sp <= sp_minus_one; |
rw_mem <= MEM_READ; |
temp_data <= data_in; |
end |
PULL_REGISTER: begin |
pc <= pc; |
address <= pc; |
temp_data <= data_in; |
end |
DUMMY: begin |
address <= {8'h01,sp}; |
rw_mem <= MEM_WRITE; |
data_out <= pc[15:8]; |
end |
default: begin |
//$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef |
//$finish(0); |
end |
|
endcase |
end |
end |
|
|
always @ (*) begin // this is the next_state logic and the combinational output logic always block |
alu_opcode = 8'h00; |
alu_a = 8'h00; |
alu_enable = 1'b0; |
next_state = RESET; // these lines prevents latches |
// this is the combinational logic related to indexed instructions |
always @(*) begin |
address_plus_index = 16'h0000; |
page_crossed = 1'b0; |
|
if (invalid == 1'b1) begin |
next_state = FETCH_OP; |
end |
else case (state) |
RESET: begin |
if (rst_counter == 3'd6) begin |
next_state = FETCH_OP; |
end |
end |
FETCH_OP: begin |
next_state = FETCH_LOW; |
end |
FETCH_OP_CALC_PARAM: begin |
next_state = FETCH_LOW; |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = temp_data; |
end |
FETCH_LOW: begin |
if (accumulator || implied || txs) begin |
if (!nop) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
end |
next_state = FETCH_OP; |
end |
else if (tsx) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = FETCH_OP; |
alu_a = sp[7:0]; |
end |
else if (immediate) begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
else if (zero_page) begin |
if (read || read_modify_write) begin |
next_state = READ_MEM; |
end |
else if (write) begin |
next_state = WRITE_MEM; |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = 8'h00; |
end |
else begin |
//$write("unknown behavior"); |
//$finish(0); |
end |
end |
else if (zero_page_indexed) begin |
next_state = READ_MEM_CALC_INDEX; |
end |
else if (absolute || jump_indirect) begin |
next_state = FETCH_HIGH; |
if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = 8'h00; |
end |
end |
else if (absolute_indexed) begin |
next_state = FETCH_HIGH_CALC_INDEX; |
end |
else if (relative) begin |
next_state = FETCH_OP_EVAL_BRANCH; |
end |
else if (indirectx || indirecty) begin |
next_state = READ_FROM_POINTER; |
end |
else begin // all the special instructions will fall here |
if (brk) begin |
next_state = PUSH_PCH; |
end |
else if (rti || rts) begin |
next_state = INCREMENT_SP; |
end |
else if (pha) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
//alu_a = 8'h00; |
next_state = PUSH_REGISTER; |
end |
else if (php) begin |
next_state = PUSH_REGISTER; |
end |
else if (pla || plp) begin |
next_state = INCREMENT_SP; |
end |
else begin // jsr |
next_state = DUMMY; |
end |
end |
end |
READ_FROM_POINTER: begin |
if (indirectx) begin |
next_state = READ_FROM_POINTER_X; |
end |
else begin // indirecty and jump indirect falls here |
next_state = READ_FROM_POINTER_X1; |
end |
end |
READ_FROM_POINTER_X: begin |
next_state = READ_FROM_POINTER_X1; |
end |
READ_FROM_POINTER_X1: begin |
if (jump_indirect) begin |
next_state = FETCH_OP; |
end |
else if (indirecty) begin |
next_state = READ_MEM_FIX_ADDR; |
end |
else begin |
if (read) begin // no instruction using pointers is from type read_modify_write |
next_state = READ_MEM; |
end |
else if (write) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = WRITE_MEM; |
end |
end |
end |
FETCH_OP_EVAL_BRANCH: begin |
if (branch) begin |
next_state = FETCH_OP; //??????????? |
end |
else begin |
next_state = FETCH_LOW; |
end |
end |
FETCH_OP_FIX_PC: begin |
if (page_crossed) begin |
next_state = FETCH_OP; |
end |
else begin |
next_state = FETCH_LOW; |
end |
end |
FETCH_HIGH_CALC_INDEX: begin |
next_state = READ_MEM_FIX_ADDR; |
end |
READ_MEM_FIX_ADDR: begin |
if (read) begin |
if (page_crossed) begin |
next_state = READ_MEM; |
end |
else begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
end |
else if (read_modify_write) begin |
next_state = READ_MEM; |
end |
else if (write) begin |
next_state = WRITE_MEM; |
alu_enable = 1'b1; |
alu_opcode = ir; |
end |
else begin |
//$write("unknown behavior"); |
//$finish(0); |
end |
end |
FETCH_HIGH: begin |
if (jump_indirect) begin |
next_state = READ_FROM_POINTER; |
end |
else if (jump) begin |
next_state = FETCH_OP; |
end |
else if (read || read_modify_write) begin |
next_state = READ_MEM; |
end |
else if (write) begin |
next_state = WRITE_MEM; |
end |
else begin |
//$write("unknown behavior"); |
//$finish(0); |
end |
end |
READ_MEM_CALC_INDEX: begin |
if (read || read_modify_write) begin |
next_state = READ_MEM; |
end |
else if (write) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
next_state = WRITE_MEM; |
end |
else begin |
//$write("unknown behavior"); |
//$finish(0); |
end |
end |
READ_MEM: begin |
if (read) begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
else if (read_modify_write) begin |
next_state = DUMMY_WRT_CALC; |
end |
end |
DUMMY_WRT_CALC: begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = data_in; |
next_state = WRITE_MEM; |
end |
WRITE_MEM: begin |
next_state = FETCH_OP; |
end |
PUSH_PCH: begin |
next_state = PUSH_PCL; |
end |
PUSH_PCL: begin |
if (jsr) begin |
next_state = FETCH_HIGH; |
end |
else begin |
next_state = PUSH_STATUS; |
end |
end |
PUSH_STATUS: begin |
next_state = FETCH_PCL; |
end |
FETCH_PCL: begin |
next_state = FETCH_PCH; |
end |
FETCH_PCH: begin |
next_state = FETCH_OP; |
end |
INCREMENT_SP: begin |
if (rti) begin |
next_state = PULL_STATUS; |
end |
else if (pla || plp) begin |
next_state = PULL_REGISTER; |
end |
else begin // rts |
next_state = PULL_PCL; |
end |
end |
PULL_STATUS: begin |
next_state = PULL_PCL; |
end |
PULL_PCL: begin |
next_state = PULL_PCH; |
case (state) |
READ_MEM_FIX_ADDR, |
FETCH_HIGH_CALC_INDEX: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
address_plus_index[15:8] = temp_addr[15:8] + page_crossed; |
end |
READ_FROM_POINTER_X1: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
address_plus_index[15:8] = data_in[7:0]; |
end |
FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin |
if (branch_inst) begin address_plus_index = pc[15:0] + {{8{index[7]}},index}; // ??????????? |
// warning: pc might feed these lines twice and cause branch failure |
end // solution: add a temp reg i guess |
end |
|
READ_FROM_POINTER: begin |
if (indirectx) begin |
{page_crossed, address_plus_index[7:0]} = temp_data + index; |
|
if (rti) begin |
alu_opcode = ir; |
alu_enable = 1'b1; |
alu_a = temp_data; |
end |
end |
PULL_PCH: begin |
if (rti) begin |
next_state = FETCH_OP; |
end |
else begin // rts |
next_state = INCREMENT_PC; |
end |
end |
INCREMENT_PC: begin |
next_state = FETCH_OP; |
end |
PUSH_REGISTER: begin |
next_state = FETCH_OP; |
end |
PULL_REGISTER: begin |
next_state = FETCH_OP_CALC_PARAM; |
end |
DUMMY: begin |
next_state = PUSH_PCH; |
end |
default: begin |
next_state = RESET; |
end |
endcase |
end |
end |
else if (jump_indirect) begin |
address_plus_index[15:0] = temp_addr[15:0] + 16'h01; |
|
// this always block is responsible for updating the address mode and the type of operation being done |
always @ (*) begin // |
absolute = 1'b0; |
absolute_indexed = 1'b0; |
accumulator = 1'b0; |
immediate = 1'b0; |
implied = 1'b0; |
indirectx = 1'b0; |
indirecty = 1'b0; |
relative = 1'b0; |
zero_page = 1'b0; |
zero_page_indexed = 1'b0; |
index_is_x = 1'b0; |
index_is_branch = 1'b0; |
|
//index = 8'h00; |
end |
else begin // indirecty falls here |
address_plus_index[7:0] = temp_data + 8'h01; |
|
read = 1'b0; |
read_modify_write = 1'b0; |
write = 1'b0; |
jump = 1'b0; |
jump_indirect = 1'b0; |
branch = 1'b0; |
end |
end |
|
READ_FROM_POINTER_X: begin |
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01; |
|
brk = 1'b0; |
rti = 1'b0; |
rts = 1'b0; |
pha = 1'b0; |
php = 1'b0; |
pla = 1'b0; |
plp = 1'b0; |
jsr = 1'b0; |
tsx = 1'b0; |
txs = 1'b0; |
nop = 1'b0; |
end |
|
invalid = 1'b0; |
READ_MEM_CALC_INDEX: begin |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index; |
|
case (ir) |
`CLC_IMP, `CLD_IMP, `CLI_IMP, `CLV_IMP, `DEX_IMP, `DEY_IMP, `INX_IMP, `INY_IMP, `SEC_IMP, `SED_IMP, `SEI_IMP, `TAX_IMP, |
`TAY_IMP, `TXA_IMP, `TYA_IMP: begin |
implied = 1'b1; |
end |
`NOP_IMP: begin |
implied = 1'b1; |
nop = 1'b1; |
end |
`ASL_ACC, `LSR_ACC, `ROL_ACC, `ROR_ACC: begin |
accumulator = 1'b1; |
end |
`ADC_IMM, `AND_IMM, `CMP_IMM, `CPX_IMM, `CPY_IMM, `EOR_IMM, `LDA_IMM, `LDX_IMM, `LDY_IMM, `ORA_IMM, `SBC_IMM: begin |
immediate = 1'b1; |
end |
`ADC_ZPG, `AND_ZPG, `ASL_ZPG, `BIT_ZPG, `CMP_ZPG, `CPX_ZPG, `CPY_ZPG, `DEC_ZPG, `EOR_ZPG, `INC_ZPG, `LDA_ZPG, `LDX_ZPG, `LDY_ZPG, |
`LSR_ZPG, `ORA_ZPG, `ROL_ZPG, `ROR_ZPG, `SBC_ZPG, `STA_ZPG, `STX_ZPG, `STY_ZPG: begin |
zero_page = 1'b1; |
end |
`ADC_ZPX, `AND_ZPX, `ASL_ZPX, `CMP_ZPX, `DEC_ZPX, `EOR_ZPX, `INC_ZPX, `LDA_ZPX, `LDY_ZPX, `LSR_ZPX, `ORA_ZPX, `ROL_ZPX, `ROR_ZPX, |
`SBC_ZPX, `STA_ZPX, `STY_ZPX: begin |
zero_page_indexed = 1'b1; |
index_is_x = 1'b1; |
//index = alu_x; |
end |
`LDX_ZPY, `STX_ZPY: begin |
zero_page_indexed = 1'b1; |
index_is_x = 1'b0; |
//index = alu_y; |
end |
`BCC_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (!alu_status[`C]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BCS_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
end |
endcase |
end |
|
if (alu_status[`C]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BEQ_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (alu_status[`Z]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BNE_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (alu_status[`Z] == 1'b0) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BPL_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (!alu_status[`N]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BMI_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (alu_status[`N]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BVC_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (!alu_status[`V]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`BVS_REL: begin |
relative = 1'b1; |
index_is_branch = 1'b1; |
//index = temp_data; |
|
if (alu_status[`V]) begin |
branch = 1'b1; |
end |
else begin |
branch = 1'b0; |
end |
end |
`ADC_ABS, `AND_ABS, `ASL_ABS, `BIT_ABS, `CMP_ABS, `CPX_ABS, `CPY_ABS, `DEC_ABS, `EOR_ABS, `INC_ABS, `LDA_ABS, |
`LDX_ABS, `LDY_ABS, `LSR_ABS, `ORA_ABS, `ROL_ABS, `ROR_ABS, `SBC_ABS, `STA_ABS, `STX_ABS, `STY_ABS: begin |
absolute = 1'b1; |
end |
`ADC_ABX, `AND_ABX, `ASL_ABX, `CMP_ABX, `DEC_ABX, `EOR_ABX, `INC_ABX, `LDA_ABX, `LDY_ABX, `LSR_ABX, `ORA_ABX, `ROL_ABX, `ROR_ABX, |
`SBC_ABX, `STA_ABX: begin |
absolute_indexed = 1'b1; |
index_is_x = 1'b1; |
end |
`ADC_ABY, `AND_ABY, `CMP_ABY, `EOR_ABY, `LDA_ABY, `LDX_ABY, `ORA_ABY, `SBC_ABY, `STA_ABY: begin |
absolute_indexed = 1'b1; |
index_is_x = 1'b0; |
end |
`ADC_IDX, `AND_IDX, `CMP_IDX, `EOR_IDX, `LDA_IDX, `ORA_IDX, `SBC_IDX, `STA_IDX: begin |
indirectx = 1'b1; |
index_is_x = 1'b1; |
end |
`ADC_IDY, `AND_IDY, `CMP_IDY, `EOR_IDY, `LDA_IDY, `ORA_IDY, `SBC_IDY, `STA_IDY: begin |
indirecty = 1'b1; |
index_is_x = 1'b0; |
end |
`JMP_ABS: begin |
absolute = 1'b1; |
jump = 1'b1; |
end |
`JMP_IND: begin |
jump_indirect = 1'b1; |
end |
`BRK_IMP: begin |
brk = 1'b1; |
end |
`RTI_IMP: begin |
rti = 1'b1; |
end |
`RTS_IMP: begin |
rts = 1'b1; |
end |
`PHA_IMP: begin |
pha = 1'b1; |
end |
`PHP_IMP: begin |
php = 1'b1; |
end |
`PLA_IMP: begin |
pla = 1'b1; |
end |
`PLP_IMP: begin |
plp = 1'b1; |
end |
`JSR_ABS: begin |
jsr = 1'b1; |
jump = 1'b1; |
end |
`TSX_IMP: begin |
tsx = 1'b1; |
end |
`TXS_IMP: begin |
txs = 1'b1; |
end |
default: begin |
index_is_x = 1'b1; |
//$write("state : %b", state); |
if (reset == 1'b0 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc |
invalid = 1'b1; |
|
end |
end |
endcase |
|
case (ir) |
`ASL_ACC, `ASL_ZPG, `ASL_ZPX, `ASL_ABS, `ASL_ABX, `LSR_ACC, `LSR_ZPG, `LSR_ZPX, `LSR_ABS, `LSR_ABX, `ROL_ACC, `ROL_ZPG, `ROL_ZPX, `ROL_ABS, |
`ROL_ABX, `ROR_ACC, `ROR_ZPG, `ROR_ZPX, `ROR_ABS, `ROR_ABX, `INC_ZPG, `INC_ZPX, `INC_ABS, `INC_ABX, `DEC_ZPG, `DEC_ZPX, `DEC_ABS, |
`DEC_ABX: begin |
read_modify_write = 1'b1; |
end |
`STA_ZPG, `STA_ZPX, `STA_ABS, `STA_ABX, `STA_ABY, `STA_IDX, `STA_IDY, `STX_ZPG, `STX_ZPY, `STX_ABS, `STY_ZPG, `STY_ZPX, `STY_ABS: begin |
write = 1'b1; |
end |
default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes |
read = 1'b1; |
end |
endcase |
end |
|
|
|
1148,12 → 211,552
|
|
|
always @ (posedge clk ) begin // sequencial always block |
if (reset) begin |
// all registers must assume default values |
pc <= 16'h0000; // TODO: this is written somewhere. something about a reset vector. must be checked. |
sp <= 8'b11111111; // the default is 'h1FF |
ir <= 8'h6c; |
temp_addr <= 16'hfffc; |
temp_data <= 8'h00; |
// registered outputs also receive default values |
address <= 16'hfffc; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
index <= 8'h00; |
end // if (reset) |
else if(!enable) |
begin |
pc <= pc; |
sp <= sp; |
ir <= ir; |
temp_addr <= temp_addr; |
temp_data <= temp_data; |
address <= address; |
rw_mem <= rw_mem; |
data_out <= data_out; |
index <= index; |
end |
|
else begin |
case (state) |
/* |
FETCH_OP: executed when the processor was reset or the last instruction could not fetch. |
FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining) |
*/ |
FETCH_OP, |
FETCH_OP_CALC_PARAM: |
begin // this is the pipeline happening! |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
ir <= data_in; |
end |
/* |
in this state the opcode is already known so truly execution begins. |
all instructions execute this cycle. |
*/ |
FETCH_LOW: |
begin |
|
if (index_is_branch) index <= data_in; |
else |
if (index_is_x == 1'b1) index <= alu_x; |
else index <= alu_y; |
|
if (accumulator || implied || txs || tsx) |
begin |
pc <= pc; // is this better? |
address <= pc; |
rw_mem <= MEM_READ; |
if (txs) sp[7:0] <= alu_x; |
//alu_a |
end |
else |
if (immediate || relative) |
begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
temp_data <= data_in; // the follow-up byte is saved in temp_data |
end |
else |
if (absolute || absolute_indexed || jump_indirect) |
begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
temp_addr <= {{8{1'b0}},data_in}; |
temp_data <= 8'h00; |
end |
else |
if (zero_page) |
begin |
pc <= next_pc; |
address <= {{8{1'b0}},data_in}; |
temp_addr <= {{8{1'b0}},data_in}; |
|
if (write) |
begin |
rw_mem <= MEM_WRITE; |
data_out <= raw_result; // ????????? |
end |
else |
begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
else |
if (zero_page_indexed) |
begin |
pc <= next_pc; |
address <= {{8{1'b0}}, data_in}; |
temp_addr <= {{8{1'b0}}, data_in}; |
rw_mem <= MEM_READ; |
end |
else |
if (indirectx || indirecty) |
begin |
pc <= next_pc; |
address <= data_in; |
temp_data <= data_in; |
rw_mem <= MEM_READ; |
end |
else |
begin // the special instructions will fall here: BRK, RTI, RTS... |
if (brk) |
begin |
pc <= next_pc; |
address <= {8'h01,sp}; |
data_out <= pc[15:8]; |
rw_mem <= MEM_WRITE; |
end |
else |
if (rti || rts) |
begin |
address <= {8'h01,sp}; |
rw_mem <= MEM_READ; |
end |
else |
if (pha || php) |
begin |
pc <= pc; |
address <= {8'h01,sp}; |
data_out <= (pha) ? raw_result : alu_status; |
rw_mem <= MEM_WRITE; |
end |
else |
if (pla || plp) |
begin |
pc <= pc; |
address <= {8'h01,sp}; |
rw_mem <= MEM_READ; |
end |
else |
if (invalid) |
begin |
address <= pc; |
rw_mem <= MEM_READ; |
end |
else |
begin // jsr |
address <= {8'h01,sp}; |
rw_mem <= MEM_READ; |
temp_addr <= {{8{1'b0}}, data_in}; |
pc <= next_pc; |
end |
end |
end |
FETCH_HIGH_CALC_INDEX: |
begin |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], address_plus_index[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
// this cycle fetchs the next operand while still evaluating if a branch occurred. |
FETCH_OP_EVAL_BRANCH: |
begin |
if (branch_inst) |
begin |
pc <= address_plus_index[15:0]; // ??????????? |
address <= address_plus_index[15:0]; // ??????????????? |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
else |
begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
ir <= data_in; |
end |
end |
// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100 |
FETCH_OP_FIX_PC: |
begin |
if (page_crossed) |
begin |
pc[15:8] <= address_plus_index[15:8]; |
address[15:8] <= address_plus_index[15:8]; |
end |
else |
begin |
pc <= next_pc; |
address <= next_pc; |
rw_mem <= MEM_READ; |
ir <= data_in; |
end |
end |
// several instructions occupy 3 bytes in memory. this cycle reads the third byte. |
FETCH_HIGH: |
begin |
if (jump) |
begin |
pc <= {data_in[7:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte |
address <= {data_in[7:0], temp_addr[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
else |
begin |
if (write) |
begin |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0],temp_addr[7:0]}; |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else |
begin // read_modify_write or just read |
pc <= next_pc; |
temp_addr[15:8] <= data_in[7:0]; |
address <= {data_in[7:0],temp_addr[7:0]}; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
end |
|
|
// read memory at address |
READ_MEM: begin |
if (read_modify_write) begin |
pc <= pc; |
address <= temp_addr; |
rw_mem <= MEM_READ; // ?????????????? |
temp_data <= data_in; |
data_out <= data_in; // writeback the same value |
end |
else begin |
pc <= pc; |
address <= pc; |
temp_data <= data_in; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
end |
READ_MEM_CALC_INDEX: begin |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
|
if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
|
end |
READ_MEM_FIX_ADDR: begin |
if (read) begin |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
|
if (page_crossed) begin // fix address |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
end |
else begin |
address <= pc; |
temp_data <= data_in; |
end |
end |
else if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
|
end |
else begin // read modify write |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
address <= address_plus_index; |
temp_addr <= address_plus_index; |
end |
end |
// some instructions have a dummy write cycle. this is it. |
DUMMY_WRT_CALC: begin |
pc <= pc; |
address <= temp_addr; |
rw_mem <= MEM_WRITE; |
data_out <= raw_result; |
end |
WRITE_MEM: begin |
pc <= pc; |
address <= pc; |
rw_mem <= MEM_READ; |
data_out <= 8'h00; |
end |
READ_FROM_POINTER: begin |
if (jump_indirect) begin |
pc[7:0] <= data_in; |
rw_mem <= MEM_READ; |
address <= address_plus_index; |
end |
else begin |
pc <= pc; |
rw_mem <= MEM_READ; |
|
if (indirectx) begin |
address <= address_plus_index; |
end |
else begin // indirecty falls here |
address <= address_plus_index; |
temp_addr <= {{8{1'b0}}, data_in}; |
end |
end |
end |
READ_FROM_POINTER_X: begin |
pc <= pc; |
address <= address_plus_index; |
temp_addr[7:0] <= data_in; |
rw_mem <= MEM_READ; |
end |
READ_FROM_POINTER_X1: begin |
if (jump_indirect) begin |
pc[15:8] <= data_in[7:0]; |
rw_mem <= MEM_READ; |
address <= {data_in[7:0], pc[7:0]}; |
end |
else if (indirectx) begin |
address <= {data_in[7:0], temp_addr[7:0]}; |
if (write) begin |
rw_mem <= MEM_WRITE; |
data_out <= alu_result; |
end |
else begin |
rw_mem <= MEM_READ; |
end |
end |
else begin // indirecty falls here |
address <= address_plus_index; |
temp_addr[15:8] <= data_in; |
rw_mem <= MEM_READ; |
end |
end |
PUSH_PCH: begin // this is probably wrong |
pc <= pc; |
address <= sp_minus_one; |
data_out <= pc[7:0]; |
rw_mem <= MEM_WRITE; |
sp <= sp_minus_one[7:0]; |
end |
PUSH_PCL: begin |
if (jsr) begin |
pc <= pc; |
address <= pc; |
rw_mem <= MEM_READ; |
sp <= sp_minus_one[7:0]; |
end |
else begin |
pc <= pc; |
address <= sp_minus_one; |
data_out <= alu_status; |
rw_mem <= MEM_WRITE; |
sp <= sp_minus_one[7:0]; |
end |
end |
PUSH_STATUS: begin |
address <= 16'hFFFE; |
rw_mem <= MEM_READ; |
sp <= sp_minus_one[7:0]; |
end |
FETCH_PCL: begin |
pc[7:0] <= data_in; |
address <= 16'hFFFF; |
rw_mem <= MEM_READ; |
end |
FETCH_PCH: begin |
pc[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], pc[7:0]}; |
rw_mem <= MEM_READ; |
end |
INCREMENT_SP: begin |
sp <= sp_plus_one; |
address <= sp_plus_one; |
end |
PULL_STATUS: begin |
sp <= sp_plus_one[7:0]; |
address <= sp_plus_one; |
temp_data <= data_in; |
end |
PULL_PCL: begin |
sp <= sp_plus_one[7:0]; |
address <= sp_plus_one; |
pc[7:0] <= data_in; |
end |
PULL_PCH: begin |
pc[15:8] <= data_in[7:0]; |
address <= {data_in[7:0], pc[7:0]}; |
end |
INCREMENT_PC: begin |
pc <= next_pc; |
address <= next_pc; |
end |
PUSH_REGISTER: begin |
pc <= pc; |
address <= pc; |
sp <= sp_minus_one[7:0]; |
rw_mem <= MEM_READ; |
temp_data <= data_in; |
end |
PULL_REGISTER: begin |
pc <= pc; |
address <= pc; |
temp_data <= data_in; |
end |
DUMMY: begin |
address <= {8'h01,sp}; |
rw_mem <= MEM_WRITE; |
data_out <= pc[15:8]; |
end |
default: begin |
|
end |
|
endcase |
end |
end |
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|
`VARIANT`INST_DECODE |
inst_decode |
|
( |
|
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.alu_status ( alu_status ), |
.ir ( ir ), |
.state ( state ), |
.absolute ( absolute ), |
.absolute_indexed ( absolute_indexed ), |
.accumulator ( accumulator ), |
.immediate ( immediate ), |
.implied ( implied ), |
.indirectx ( indirectx ), |
.indirecty ( indirecty ), |
.relative ( relative ), |
.zero_page ( zero_page ), |
.zero_page_indexed ( zero_page_indexed ), |
.read ( read ), |
.read_modify_write ( read_modify_write ), |
.write ( write ), |
.jump ( jump ), |
.jump_indirect ( jump_indirect ), |
.index_is_x ( index_is_x ), |
.index_is_branch ( index_is_branch ), |
.brk ( brk ), |
.rti ( rti ), |
.rts ( rts ), |
.pha ( pha ), |
.php ( php ), |
.pla ( pla ), |
.plp ( plp ), |
.jsr ( jsr ), |
.tsx ( tsx ), |
.txs ( txs ), |
.nop ( nop ), |
.invalid ( invalid ), |
.branch_inst ( branch_inst ) |
); |
|
|
|
`VARIANT`STATE |
state_fsm |
( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.tsx ( tsx ), |
.immediate ( immediate ), |
.zero_page ( zero_page ), |
.zero_page_indexed ( zero_page_indexed ), |
.absolute ( absolute ), |
.absolute_indexed ( absolute_indexed ), |
.relative ( relative ), |
.brk ( brk ), |
.rts ( rts ), |
.pha ( pha ), |
.php ( php ), |
.indirectx ( indirectx ), |
.jump_indirect ( jump_indirect ), |
.indirecty ( indirecty ), |
.branch_inst ( branch_inst ), |
.page_crossed ( page_crossed ), |
.jump ( jump ), |
.write ( write ), |
.read_modify_write ( read_modify_write ), |
.read ( read ), |
.jsr ( jsr ), |
.pla ( pla ), |
.plp ( plp ), |
.rti ( rti ), |
.accumulator ( accumulator ), |
.implied ( implied ), |
.txs ( txs ), |
.nop ( nop ), |
.invalid ( invalid ), |
.temp_data ( temp_data ), |
.data_in ( data_in ), |
.sp ( sp ), |
.ir ( ir ), |
|
.state ( state ), |
.alu_opcode ( alu_opcode ), |
.alu_a ( alu_a ), |
.alu_enable ( alu_enable ) |
); |
|
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`ifndef SYNTHESIS |
|
|
1277,6 → 880,7
`INY_IMP: instr_string = "INY_IMP"; |
`JMP_ABS: instr_string = "JMP_ABS"; |
`JMP_IND: instr_string = "JMP_IND"; |
`JMP_ABX: instr_string = "JMP_ABX"; |
`JSR_ABS: instr_string = "JSR_ABS"; |
`LDA_IMM: instr_string = "LDA_IMM"; |
`LDA_ZPG: instr_string = "LDA_ZPG"; |
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_core.v
2,7 → 2,6
|
|
module `VARIANT`CORE |
#(parameter BOOT = 16'hf000) |
|
( |
|
18,8 → 17,52
); |
|
|
// FSM states. If aiming for less power consumption try gray coding. |
localparam FETCH_OP = 5'b00000; |
localparam FETCH_LOW = 5'b00010; |
localparam FETCH_HIGH = 5'b00011; |
localparam READ_MEM = 5'b00100; |
localparam DUMMY_WRT_CALC = 5'b00101; |
localparam WRITE_MEM = 5'b00110; |
localparam FETCH_OP_CALC_PARAM = 5'b00111; |
localparam READ_MEM_CALC_INDEX = 5'b01000; |
localparam FETCH_HIGH_CALC_INDEX = 5'b01001; |
localparam READ_MEM_FIX_ADDR = 5'b01010; |
localparam FETCH_OP_EVAL_BRANCH = 5'b01011; |
localparam FETCH_OP_FIX_PC = 5'b01100; |
localparam READ_FROM_POINTER = 5'b01101; |
localparam READ_FROM_POINTER_X = 5'b01110; |
localparam READ_FROM_POINTER_X1 = 5'b01111; |
localparam PUSH_PCH = 5'b10000; |
localparam PUSH_PCL = 5'b10001; |
localparam PUSH_STATUS = 5'b10010; |
localparam FETCH_PCL = 5'b10011; |
localparam FETCH_PCH = 5'b10100; |
localparam INCREMENT_SP = 5'b10101; |
localparam PULL_STATUS = 5'b10110; |
localparam PULL_PCL = 5'b10111; |
localparam PULL_PCH = 5'b11000; |
localparam INCREMENT_PC = 5'b11001; |
localparam PUSH_REGISTER = 5'b11010; |
localparam PULL_REGISTER = 5'b11011; |
localparam DUMMY = 5'b11100; |
localparam RESET = 5'b11111; |
|
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// rw_mem signals |
localparam MEM_READ = 1'b0; |
localparam MEM_WRITE = 1'b1; |
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wire [7:0] ir; |
wire [4:0] state; |
wire [7:0] alu_result; |
wire [7:0] raw_result; |
wire [7:0] alu_status; |
wire [7:0] alu_x; |
wire [7:0] alu_y; |
29,37 → 72,1132
|
|
`VARIANT`FSM |
#(.BOOT(BOOT)) |
t6502_fsm( |
.clk (clk), |
.reset (reset), |
.enable (enable), |
.alu_result (alu_result), |
.alu_status (alu_status), |
.data_in (data_in), |
.alu_x (alu_x), |
.alu_y (alu_y), |
.address (address), |
.pc (pc), |
.rw_mem (rw_mem), |
.data_out (data_out), |
.alu_opcode (alu_opcode), |
.alu_a (alu_a), |
.alu_enable (alu_enable) |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.alu_result ( alu_result ), |
.raw_result ( raw_result ), |
.alu_status ( alu_status ), |
.data_in ( data_in ), |
.alu_x ( alu_x ), |
.alu_y ( alu_y ), |
.address ( address ), |
.pc ( pc ), |
.ir ( ir ), |
.state ( state ), |
.rw_mem ( rw_mem ), |
.data_out ( data_out ), |
.alu_opcode ( alu_opcode ), |
.alu_a ( alu_a ), |
.alu_enable ( alu_enable ) |
); |
|
`VARIANT`ALU t6502_alu ( |
.clk (clk), |
.reset (reset), |
.enable (enable), |
.alu_enable (alu_enable), |
.alu_result (alu_result), |
.alu_status (alu_status), |
.alu_opcode (alu_opcode), |
.alu_a (alu_a), |
.alu_x (alu_x), |
.alu_y (alu_y) |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.alu_enable ( alu_enable ), |
.alu_result ( alu_result ), |
.raw_result ( raw_result ), |
.alu_status ( alu_status ), |
.alu_opcode ( alu_opcode ), |
.alu_a ( alu_a ), |
.alu_x ( alu_x ), |
.alu_y ( alu_y ) |
); |
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`ifndef SYNTHESIS |
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reg [7*8-1:0] instr_string; |
reg [151:0] instr_used; |
|
reg [21*8-1:0] state_string; |
|
reg [28:0] state_used; |
|
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initial |
begin |
instr_used = 152'b0; |
state_used = 29'b0; |
end |
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always @(*) begin |
case (state) |
FETCH_OP: begin |
state_string = "FETCH_OP "; |
state_used = 29'b00000000000000000000000000001 | state_used; |
end |
FETCH_LOW: begin |
state_string = "FETCH_LOW "; |
state_used = 29'b00000000000000000000000000010 | state_used; |
end |
FETCH_HIGH: begin |
state_string = "FETCH_HIGH "; |
state_used = 29'b00000000000000000000000000100 | state_used; |
end |
READ_MEM: begin |
state_string = "READ_MEM "; |
state_used = 29'b00000000000000000000000001000 | state_used; |
end |
DUMMY_WRT_CALC: begin |
state_string = "DUMMY_WRT_CALC "; |
state_used = 29'b00000000000000000000000010000 | state_used; |
end |
WRITE_MEM: begin |
state_string = "WRITE_MEM "; |
state_used = 29'b00000000000000000000000100000 | state_used; |
end |
FETCH_OP_CALC_PARAM: begin |
state_string = "FETCH_OP_CALC_PARAM "; |
state_used = 29'b00000000000000000000001000000 | state_used; |
end |
READ_MEM_CALC_INDEX: begin |
state_string = "READ_MEM_CALC_INDEX "; |
state_used = 29'b00000000000000000000010000000 | state_used; |
end |
FETCH_HIGH_CALC_INDEX: begin |
state_string = "FETCH_HIGH_CALC_INDEX"; |
state_used = 29'b00000000000000000000100000000 | state_used; |
end |
READ_MEM_FIX_ADDR: begin |
state_string = "READ_MEM_FIX_ADDR "; |
state_used = 29'b00000000000000000001000000000 | state_used; |
end |
FETCH_OP_EVAL_BRANCH: begin |
state_string = "FETCH_OP_EVAL_BRANCH "; |
state_used = 29'b00000000000000000010000000000 | state_used; |
end |
FETCH_OP_FIX_PC: begin |
state_string = "FETCH_OP_FIX_PC "; |
state_used = 29'b00000000000000000100000000000 | state_used; |
end |
READ_FROM_POINTER: begin |
state_string = "READ_FROM_POINTER "; |
state_used = 29'b00000000000000001000000000000 | state_used; |
end |
READ_FROM_POINTER_X: begin |
state_string = "READ_FROM_POINTER_X "; |
state_used = 29'b00000000000000010000000000000 | state_used; |
end |
READ_FROM_POINTER_X1: begin |
state_string = "READ_FROM_POINTER_X1 "; |
state_used = 29'b00000000000000100000000000000 | state_used; |
end |
PUSH_PCH: begin |
state_string = "PUSH_PCH "; |
state_used = 29'b00000000000001000000000000000 | state_used; |
end |
PUSH_PCL: begin |
state_string = "PUSH_PCL "; |
state_used = 29'b00000000000010000000000000000 | state_used; |
end |
PUSH_STATUS: begin |
state_string = "PUSH_STATUS "; |
state_used = 29'b00000000000100000000000000000 | state_used; |
end |
FETCH_PCL: begin |
state_string = "FETCH_PCL "; |
state_used = 29'b00000000001000000000000000000 | state_used; |
end |
FETCH_PCH: begin |
state_string = "FETCH_PCH "; |
state_used = 29'b00000000010000000000000000000 | state_used; |
end |
INCREMENT_SP: begin |
state_string = "INCREMENT_SP "; |
state_used = 29'b00000000100000000000000000000 | state_used; |
end |
PULL_STATUS: begin |
state_string = "PULL_STATUS "; |
state_used = 29'b00000001000000000000000000000 | state_used; |
end |
PULL_PCL: begin |
state_string = "PULL_PCL "; |
state_used = 29'b00000010000000000000000000000 | state_used; |
end |
PULL_PCH: begin |
state_string = "PULL_PCH "; |
state_used = 29'b00000100000000000000000000000 | state_used; |
end |
INCREMENT_PC: begin |
state_string = "INCREMENT_PC "; |
state_used = 29'b00001000000000000000000000000 | state_used; |
end |
PUSH_REGISTER: begin |
state_string = "PUSH_REGISTER "; |
state_used = 29'b00010000000000000000000000000 | state_used; |
end |
PULL_REGISTER: begin |
state_string = "PULL_REGISTER "; |
state_used = 29'b00100000000000000000000000000 | state_used; |
end |
DUMMY: begin |
state_string = "DUMMY "; |
state_used = 29'b01000000000000000000000000000 | state_used; |
end |
|
RESET: begin |
state_string = "RESET "; |
state_used = 29'b10000000000000000000000000000| state_used; |
end |
|
default: begin |
state_string = "-XXXXXX- "; |
end |
endcase |
|
end |
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always @(*) begin |
case (ir) |
`ADC_IMM: |
begin |
instr_string = "ADC_IMM"; |
instr_used[000] = 1'b1; |
end |
|
`ADC_ZPG: |
begin |
instr_string = "ADC_ZPG"; |
instr_used[001] = 1'b1; |
end |
|
`ADC_ZPX: |
begin |
instr_string = "ADC_ZPX"; |
instr_used[002] = 1'b1; |
end |
|
`ADC_ABS: |
begin |
instr_string = "ADC_ABS"; |
instr_used[003] = 1'b1; |
end |
|
`ADC_ABX: |
begin |
instr_string = "ADC_ABX"; |
instr_used[004] = 1'b1; |
end |
|
`ADC_ABY: |
begin |
instr_string = "ADC_ABY"; |
instr_used[005] = 1'b1; |
end |
|
`ADC_IDX: |
begin |
instr_string = "ADC_IDX"; |
instr_used[006] = 1'b1; |
end |
|
`ADC_IDY: |
begin |
instr_string = "ADC_IDY"; |
instr_used[007] = 1'b1; |
end |
|
`AND_IMM: |
begin |
instr_string = "AND_IMM"; |
instr_used[008] = 1'b1; |
end |
|
`AND_ZPG: |
begin |
instr_string = "AND_ZPG"; |
instr_used[009] = 1'b1; |
end |
|
`AND_ZPX: |
begin |
instr_string = "AND_ZPX"; |
instr_used[010] = 1'b1; |
end |
|
`AND_ABS: |
begin |
instr_string = "AND_ABS"; |
instr_used[011] = 1'b1; |
end |
|
`AND_ABX: |
begin |
instr_string = "AND_ABX"; |
instr_used[012] = 1'b1; |
end |
|
`AND_ABY: |
begin |
instr_string = "AND_ABY"; |
instr_used[013] = 1'b1; |
end |
|
`AND_IDX: |
begin |
instr_string = "AND_IDX"; |
instr_used[014] = 1'b1; |
end |
|
`AND_IDY: |
begin |
instr_string = "AND_IDY"; |
instr_used[015] = 1'b1; |
end |
|
`ASL_ACC: |
begin |
instr_string = "ASL_ACC"; |
instr_used[016] = 1'b1; |
end |
|
`ASL_ZPG: |
begin |
instr_string = "ASL_ZPG"; |
instr_used[017] = 1'b1; |
end |
|
`ASL_ZPX: |
begin |
instr_string = "ASL_ZPX"; |
instr_used[018] = 1'b1; |
end |
|
`ASL_ABS: |
begin |
instr_string = "ASL_ABS"; |
instr_used[019] = 1'b1; |
end |
|
`ASL_ABX: |
begin |
instr_string = "ASL_ABX"; |
instr_used[020] = 1'b1; |
end |
|
`BCC_REL: |
begin |
instr_string = "BCC_REL"; |
instr_used[021] = 1'b1; |
end |
|
`BCS_REL: |
begin |
instr_string = "BCS_REL"; |
instr_used[022] = 1'b1; |
end |
|
`BEQ_REL: |
begin |
instr_string = "BEQ_REL"; |
instr_used[023] = 1'b1; |
end |
|
`BIT_ZPG: |
begin |
instr_string = "BIT_ZPG"; |
instr_used[024] = 1'b1; |
end |
|
`BIT_ABS: |
begin |
instr_string = "BIT_ABS"; |
instr_used[025] = 1'b1; |
end |
|
`BMI_REL: |
begin |
instr_string = "BMI_REL"; |
instr_used[026] = 1'b1; |
end |
|
`BNE_REL: |
begin |
instr_string = "BNE_REL"; |
instr_used[027] = 1'b1; |
end |
|
`BPL_REL: |
begin |
instr_string = "BPL_REL"; |
instr_used[028] = 1'b1; |
end |
|
`BRK_IMP: |
begin |
instr_string = "BRK_IMP"; |
instr_used[029] = 1'b1; |
end |
|
`BVC_REL: |
begin |
instr_string = "BVC_REL"; |
instr_used[030] = 1'b1; |
end |
|
`BVS_REL: |
begin |
instr_string = "BVS_REL"; |
instr_used[031] = 1'b1; |
end |
|
`CLC_IMP: |
begin |
instr_string = "CLC_IMP"; |
instr_used[032] = 1'b1; |
end |
|
`CLD_IMP: |
begin |
instr_string = "CLD_IMP"; |
instr_used[033] = 1'b1; |
end |
|
`CLI_IMP: |
begin |
instr_string = "CLI_IMP"; |
instr_used[034] = 1'b1; |
end |
|
`CLV_IMP: |
begin |
instr_string = "CLV_IMP"; |
instr_used[035] = 1'b1; |
end |
|
`CMP_IMM: |
begin |
instr_string = "CMP_IMM"; |
instr_used[036] = 1'b1; |
end |
|
`CMP_ZPG: |
begin |
instr_string = "CMP_ZPG"; |
instr_used[037] = 1'b1; |
end |
|
`CMP_ZPX: |
begin |
instr_string = "CMP_ZPX"; |
instr_used[038] = 1'b1; |
end |
|
`CMP_ABS: |
begin |
instr_string = "CMP_ABS"; |
instr_used[039] = 1'b1; |
end |
|
`CMP_ABX: |
begin |
instr_string = "CMP_ABX"; |
instr_used[040] = 1'b1; |
end |
|
`CMP_ABY: |
begin |
instr_string = "CMP_ABY"; |
instr_used[041] = 1'b1; |
end |
|
`CMP_IDX: |
begin |
instr_string = "CMP_IDX"; |
instr_used[042] = 1'b1; |
end |
|
`CMP_IDY: |
begin |
instr_string = "CMP_IDY"; |
instr_used[043] = 1'b1; |
end |
|
`CPX_IMM: |
begin |
instr_string = "CPX_IMM"; |
instr_used[044] = 1'b1; |
end |
|
`CPX_ZPG: |
begin |
instr_string = "CPX_ZPG"; |
instr_used[045] = 1'b1; |
end |
|
`CPX_ABS: |
begin |
instr_string = "CPX_ABS"; |
instr_used[046] = 1'b1; |
end |
|
`CPY_IMM: |
begin |
instr_string = "CPY_IMM"; |
instr_used[047] = 1'b1; |
end |
|
`CPY_ZPG: |
begin |
instr_string = "CPY_ZPG"; |
instr_used[048] = 1'b1; |
end |
|
`CPY_ABS: |
begin |
instr_string = "CPY_ABS"; |
instr_used[049] = 1'b1; |
end |
|
`DEC_ZPG: |
begin |
instr_string = "DEC_ZPG"; |
instr_used[050] = 1'b1; |
end |
|
`DEC_ZPX: |
begin |
instr_string = "DEC_ZPX"; |
instr_used[051] = 1'b1; |
end |
|
`DEC_ABS: |
begin |
instr_string = "DEC_ABS"; |
instr_used[052] = 1'b1; |
end |
|
`DEC_ABX: |
begin |
instr_string = "DEC_ABX"; |
instr_used[053] = 1'b1; |
end |
|
`DEX_IMP: |
begin |
instr_string = "DEX_IMP"; |
instr_used[054] = 1'b1; |
end |
|
`DEY_IMP: |
begin |
instr_string = "DEY_IMP"; |
instr_used[055] = 1'b1; |
end |
|
`EOR_IMM: |
begin |
instr_string = "EOR_IMM"; |
instr_used[056] = 1'b1; |
end |
|
`EOR_ZPG: |
begin |
instr_string = "EOR_ZPG"; |
instr_used[057] = 1'b1; |
end |
|
`EOR_ZPX: |
begin |
instr_string = "EOR_ZPX"; |
instr_used[058] = 1'b1; |
end |
|
`EOR_ABS: |
begin |
instr_string = "EOR_ABS"; |
instr_used[059] = 1'b1; |
end |
|
`EOR_ABX: |
begin |
instr_string = "EOR_ABX"; |
instr_used[060] = 1'b1; |
end |
|
`EOR_ABY: |
begin |
instr_string = "EOR_ABY"; |
instr_used[061] = 1'b1; |
end |
|
`EOR_IDX: |
begin |
instr_string = "EOR_IDX"; |
instr_used[062] = 1'b1; |
end |
|
`EOR_IDY: |
begin |
instr_string = "EOR_IDY"; |
instr_used[063] = 1'b1; |
end |
|
`INC_ZPG: |
begin |
instr_string = "INC_ZPG"; |
instr_used[064] = 1'b1; |
end |
|
`INC_ZPX: |
begin |
instr_string = "INC_ZPX"; |
instr_used[065] = 1'b1; |
end |
|
`INC_ABS: |
begin |
instr_string = "INC_ABS"; |
instr_used[066] = 1'b1; |
end |
|
`INC_ABX: |
begin |
instr_string = "INC_ABX"; |
instr_used[067] = 1'b1; |
end |
|
`INX_IMP: |
begin |
instr_string = "INX_IMP"; |
instr_used[068] = 1'b1; |
end |
|
`INY_IMP: |
begin |
instr_string = "INY_IMP"; |
instr_used[069] = 1'b1; |
end |
|
`JMP_ABS: |
begin |
instr_string = "JMP_ABS"; |
instr_used[070] = 1'b1; |
end |
|
`JMP_IND: |
begin |
instr_string = "JMP_IND"; |
instr_used[071] = 1'b1; |
end |
|
`JSR_ABS: |
begin |
instr_string = "JSR_ABS"; |
instr_used[072] = 1'b1; |
end |
|
`LDA_IMM: |
begin |
instr_string = "LDA_IMM"; |
instr_used[073] = 1'b1; |
end |
|
`LDA_ZPG: |
begin |
instr_string = "LDA_ZPG"; |
instr_used[074] = 1'b1; |
end |
|
`LDA_ZPX: |
begin |
instr_string = "LDA_ZPX"; |
instr_used[075] = 1'b1; |
end |
|
`LDA_ABS: |
begin |
instr_string = "LDA_ABS"; |
instr_used[076] = 1'b1; |
end |
|
`LDA_ABX: |
begin |
instr_string = "LDA_ABX"; |
instr_used[077] = 1'b1; |
end |
|
`LDA_ABY: |
begin |
instr_string = "LDA_ABY"; |
instr_used[078] = 1'b1; |
end |
|
`LDA_IDX: |
begin |
instr_string = "LDA_IDX"; |
instr_used[079] = 1'b1; |
end |
|
`LDA_IDY: |
begin |
instr_string = "LDA_IDY"; |
instr_used[080] = 1'b1; |
end |
|
`LDX_IMM: |
begin |
instr_string = "LDX_IMM"; |
instr_used[081] = 1'b1; |
end |
|
`LDX_ZPG: |
begin |
instr_string = "LDX_ZPG"; |
instr_used[082] = 1'b1; |
end |
|
`LDX_ZPY: |
begin |
instr_string = "LDX_ZPY"; |
instr_used[083] = 1'b1; |
end |
|
`LDX_ABS: |
begin |
instr_string = "LDX_ABS"; |
instr_used[084] = 1'b1; |
end |
|
`LDX_ABY: |
begin |
instr_string = "LDX_ABY"; |
instr_used[085] = 1'b1; |
end |
|
`LDY_IMM: |
begin |
instr_string = "LDY_IMM"; |
instr_used[086] = 1'b1; |
end |
|
`LDY_ZPG: |
begin |
instr_string = "LDY_ZPG"; |
instr_used[087] = 1'b1; |
end |
|
`LDY_ZPX: |
begin |
instr_string = "LDY_ZPX"; |
instr_used[088] = 1'b1; |
end |
|
`LDY_ABS: |
begin |
instr_string = "LDY_ABS"; |
instr_used[089] = 1'b1; |
end |
|
`LDY_ABX: |
begin |
instr_string = "LDY_ABX"; |
instr_used[090] = 1'b1; |
end |
|
`LSR_ACC: |
begin |
instr_string = "LSR_ACC"; |
instr_used[091] = 1'b1; |
end |
|
`LSR_ZPG: |
begin |
instr_string = "LSR_ZPG"; |
instr_used[092] = 1'b1; |
end |
|
`LSR_ZPX: |
begin |
instr_string = "LSR_ZPX"; |
instr_used[093] = 1'b1; |
end |
|
`LSR_ABS: |
begin |
instr_string = "LSR_ABS"; |
instr_used[094] = 1'b1; |
end |
|
`LSR_ABX: |
begin |
instr_string = "LSR_ABX"; |
instr_used[095] = 1'b1; |
end |
|
`NOP_IMP: |
begin |
instr_string = "NOP_IMP"; |
instr_used[096] = 1'b1; |
end |
|
`ORA_IMM: |
begin |
instr_string = "ORA_IMM"; |
instr_used[097] = 1'b1; |
end |
|
`ORA_ZPG: |
begin |
instr_string = "ORA_ZPG"; |
instr_used[098] = 1'b1; |
end |
|
`ORA_ZPX: |
begin |
instr_string = "ORA_ZPX"; |
instr_used[099] = 1'b1; |
end |
|
`ORA_ABS: |
begin |
instr_string = "ORA_ABS"; |
instr_used[100] = 1'b1; |
end |
|
`ORA_ABX: |
begin |
instr_string = "ORA_ABX"; |
instr_used[101] = 1'b1; |
end |
|
`ORA_ABY: |
begin |
instr_string = "ORA_ABY"; |
instr_used[102] = 1'b1; |
end |
|
`ORA_IDX: |
begin |
instr_string = "ORA_IDX"; |
instr_used[103] = 1'b1; |
end |
|
`ORA_IDY: |
begin |
instr_string = "ORA_IDY"; |
instr_used[104] = 1'b1; |
end |
|
`PHA_IMP: |
begin |
instr_string = "PHA_IMP"; |
instr_used[105] = 1'b1; |
end |
|
`PHP_IMP: |
begin |
instr_string = "PHP_IMP"; |
instr_used[106] = 1'b1; |
end |
|
`PLA_IMP: |
begin |
instr_string = "PLA_IMP"; |
instr_used[107] = 1'b1; |
end |
|
`PLP_IMP: |
begin |
instr_string = "PLP_IMP"; |
instr_used[108] = 1'b1; |
end |
|
`ROL_ACC: |
begin |
instr_string = "ROL_ACC"; |
instr_used[109] = 1'b1; |
end |
|
`ROL_ZPG: |
begin |
instr_string = "ROL_ZPG"; |
instr_used[110] = 1'b1; |
end |
|
`ROL_ZPX: |
begin |
instr_string = "ROL_ZPX"; |
instr_used[111] = 1'b1; |
end |
|
`ROL_ABS: |
begin |
instr_string = "ROL_ABS"; |
instr_used[112] = 1'b1; |
end |
|
`ROL_ABX: |
begin |
instr_string = "ROL_ABX"; |
instr_used[113] = 1'b1; |
end |
|
`ROR_ACC: |
begin |
instr_string = "ROR_ACC"; |
instr_used[114] = 1'b1; |
end |
|
`ROR_ZPG: |
begin |
instr_string = "ROR_ZPG"; |
instr_used[115] = 1'b1; |
end |
|
`ROR_ZPX: |
begin |
instr_string = "ROR_ZPX"; |
instr_used[116] = 1'b1; |
end |
|
`ROR_ABS: |
begin |
instr_string = "ROR_ABS"; |
instr_used[117] = 1'b1; |
end |
|
`ROR_ABX: |
begin |
instr_string = "ROR_ABX"; |
instr_used[118] = 1'b1; |
end |
|
`RTI_IMP: |
begin |
instr_string = "RTI_IMP"; |
instr_used[119] = 1'b1; |
end |
|
`RTS_IMP: |
begin |
instr_string = "RTS_IMP"; |
instr_used[120] = 1'b1; |
end |
|
`SBC_IMM: |
begin |
instr_string = "SBC_IMM"; |
instr_used[121] = 1'b1; |
end |
|
`SBC_ZPG: |
begin |
instr_string = "SBC_ZPG"; |
instr_used[122] = 1'b1; |
end |
|
`SBC_ZPX: |
begin |
instr_string = "SBC_ZPX"; |
instr_used[123] = 1'b1; |
end |
|
`SBC_ABS: |
begin |
instr_string = "SBC_ABS"; |
instr_used[124] = 1'b1; |
end |
|
`SBC_ABX: |
begin |
instr_string = "SBC_ABX"; |
instr_used[125] = 1'b1; |
end |
|
`SBC_ABY: |
begin |
instr_string = "SBC_ABY"; |
instr_used[126] = 1'b1; |
end |
|
`SBC_IDX: |
begin |
instr_string = "SBC_IDX"; |
instr_used[127] = 1'b1; |
end |
|
`SBC_IDY: |
begin |
instr_string = "SBC_IDY"; |
instr_used[128] = 1'b1; |
end |
|
`SEC_IMP: |
begin |
instr_string = "SEC_IMP"; |
instr_used[129] = 1'b1; |
end |
|
`SED_IMP: |
begin |
instr_string = "SED_IMP"; |
instr_used[130] = 1'b1; |
end |
|
`SEI_IMP: |
begin |
instr_string = "SEI_IMP"; |
instr_used[131] = 1'b1; |
end |
|
`STA_ZPG: |
begin |
instr_string = "STA_ZPG"; |
instr_used[132] = 1'b1; |
end |
|
`STA_ZPX: |
begin |
instr_string = "STA_ZPX"; |
instr_used[133] = 1'b1; |
end |
|
`STA_ABS: |
begin |
instr_string = "STA_ABS"; |
instr_used[134] = 1'b1; |
end |
|
`STA_ABX: |
begin |
instr_string = "STA_ABX"; |
instr_used[135] = 1'b1; |
end |
|
`STA_ABY: |
begin |
instr_string = "STA_ABY"; |
instr_used[136] = 1'b1; |
end |
|
`STA_IDX: |
begin |
instr_string = "STA_IDX"; |
instr_used[137] = 1'b1; |
end |
|
`STA_IDY: |
begin |
instr_string = "STA_IDY"; |
instr_used[138] = 1'b1; |
end |
|
`STX_ZPG: |
begin |
instr_string = "STX_ZPG"; |
instr_used[139] = 1'b1; |
end |
|
`STX_ZPY: |
begin |
instr_string = "STX_ZPY"; |
instr_used[140] = 1'b1; |
end |
|
`STX_ABS: |
begin |
instr_string = "STX_ABS"; |
instr_used[141] = 1'b1; |
end |
|
`STY_ZPG: |
begin |
instr_string = "STY_ZPG"; |
instr_used[142] = 1'b1; |
end |
|
`STY_ZPX: |
begin |
instr_string = "STY_ZPX"; |
instr_used[143] = 1'b1; |
end |
|
`STY_ABS: |
begin |
instr_string = "STY_ABS"; |
instr_used[144] = 1'b1; |
end |
|
`TAX_IMP: |
begin |
instr_string = "TAX_IMP"; |
instr_used[145] = 1'b1; |
end |
|
`TAY_IMP: |
begin |
instr_string = "TAY_IMP"; |
instr_used[146] = 1'b1; |
end |
|
`TSX_IMP: |
begin |
instr_string = "TSX_IMP"; |
instr_used[147] = 1'b1; |
end |
|
`TXA_IMP: |
begin |
instr_string = "TXA_IMP"; |
instr_used[148] = 1'b1; |
end |
|
`TXS_IMP: |
begin |
instr_string = "TXS_IMP"; |
instr_used[149] = 1'b1; |
end |
|
`TYA_IMP: |
begin |
instr_string = "TYA_IMP"; |
instr_used[150] = 1'b1; |
end |
|
`JMP_ABX: |
begin |
instr_string = "JMP_ABX"; |
instr_used[151] = 1'b1; |
end |
|
|
default: instr_string = "XXX_XXX"; |
endcase |
|
end |
|
|
|
|
|
|
`endif // `ifndef SYNTHESIS |
|
|
|
|
|
|
|
|
endmodule |
/socgen/trunk/projects/Mos6502/ip/T6502/doc/Readme.txt
2,7 → 2,7
|
|
|
This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor. It had some documentation and a test suite that was somewhat working. |
This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor and uses it as a 6502. It had some documentation and a test suite that was somewhat working. |
|
I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made: |
|
20,7 → 20,7
|
Each test is in it's own subdirectory and any needed code is assembled and loaded into sram |
|
5) Design had no reset/interrupt vectors. Changed reset vector to a parameter. May add interupt(s) later. |
5) Design had no reset/interrupt vectors. Added reset vector. May add interupt(s) later. |
|
6) Added enable logic so that it could work with synchronous sram |
|
28,6 → 28,10
CLC followed by BCC missed the offset by one clock cycle. |
JSR doesn't push high address on stack. puts wrong data in page 00 |
Branch backwards doesn't work. |
read/modify/write did not work |
pha pushed onto page 0 |
pha data latched one clock to late |
jmp indirect didn't work |
|
|
This appears to be a work in progress with numerous issues. I fixed enough of them so that I can |
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/TB.defs
2,6 → 2,6
|
`define ROM_WORDS 4096 |
`define ROM_ADD 12 |
`define ROM_FILE "../../../../../../Mos6502/sw/Prog/Prog.abs" |
`define ROM_FILE "../../../../../../Mos6502/sw/prog_test/prog_test.abs" |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dut
1,8 → 1,5
|
wire [15:0] addr; |
|
|
|
wire serial_txd; |
wire serial_rxd; |
|
9,9 → 6,9
|
|
|
wire [7:0] Status; |
wire [7:0] gpio_0_out; |
wire [7:0] gpio_1_out; |
|
|
wire ps2_clk_in; |
wire ps2_data_in; |
wire ps2_clk_oe; |
25,11 → 22,7
|
|
|
reg enable; |
|
always@(posedge clk) |
if(reset) enable <= 1'b1; |
else enable <= !enable; |
|
|
T6502 |
36,9 → 29,7
|
#(.ROM_WORDS(`ROM_WORDS), |
.ROM_ADD (`ROM_ADD), |
.ROM_FILE (`ROM_FILE), |
.BOOT (16'hf000) |
|
.ROM_FILE (`ROM_FILE) |
) |
|
dut |
45,15 → 36,15
( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.addr_pin ( ), |
|
.gpio_0_out ( Status ), |
.gpio_0_in ( Status ), |
.gpio_0_out ( gpio_0_out ), |
.gpio_0_in ( gpio_0_out ), |
.gpio_0_oe ( ), |
.gpio_0_lat ( ), |
|
.gpio_1_out ( ), |
.gpio_1_in ( 8'h00 ), |
.gpio_1_out ( gpio_1_out ), |
.gpio_1_in ( gpio_1_out ), |
.gpio_1_oe ( ), |
.gpio_1_lat ( ), |
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/liblist
0,0 → 1,8
`include "../../lib/cde_sram/cde_sram.v" |
`include "../../lib/cde_divider/cde_divider.v" |
`include "../../lib/cde_fifo/cde_fifo.v" |
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" |
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" |
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/TB.defs
0,0 → 1,7
`define TIMEOUT 800000 |
|
`define ROM_WORDS 4096 |
`define ROM_ADD 12 |
`define ROM_FILE "../../../../../../Mos6502/sw/prog_1_test/prog_1_test.abs" |
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/test_define
0,0 → 1,15
initial |
begin |
$display(" "); |
$display(" ==================================================="); |
$display(" Test Start"); |
$display(" ==================================================="); |
$display(" "); |
cg.next(20); |
cg.reset_off; |
cg.next(9000); |
cg.exit; |
end |
|
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/dmp_define
0,0 → 1,7
$dumpfile ("TestBench.vcd"); |
$dumpvars (0, TB); |
|
|
|
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/filelist
0,0 → 1,9
`include "../../../rtl/gen/sim/T6502.v" |
`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" |
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" |
`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" |
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
|
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/modellist
0,0 → 1,5
`include "../../bench/verilog/models/clock_gen.v" |
|
`include "../../bench/verilog/models/ps2_model.v" |
`include "../../bench/verilog/models/iobuftri.v" |
`include "../../bench/verilog/models/uart_model.v" |
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/dut
0,0 → 1,116
|
|
wire serial_txd; |
wire serial_rxd; |
|
|
|
|
wire [7:0] gpio_0_out; |
wire [7:0] gpio_1_out; |
|
wire ps2_clk_in; |
wire ps2_data_in; |
wire ps2_clk_oe; |
wire ps2_data_oe; |
|
|
wire ps2_clk; |
wire ps2_data; |
|
|
|
|
|
|
|
|
T6502 |
|
#(.ROM_WORDS(`ROM_WORDS), |
.ROM_ADD (`ROM_ADD), |
.ROM_FILE (`ROM_FILE) |
) |
|
dut |
( |
.clk ( clk ), |
.reset ( reset ), |
.addr_pin ( ), |
|
.gpio_0_out ( gpio_0_out ), |
.gpio_0_in ( gpio_0_out ), |
.gpio_0_oe ( ), |
.gpio_0_lat ( ), |
|
.gpio_1_out ( gpio_1_out ), |
.gpio_1_in ( gpio_1_out ), |
.gpio_1_oe ( ), |
.gpio_1_lat ( ), |
|
.ps2_clk_oe ( ps2_clk_oe ), |
.ps2_clk_in ( ps2_clk_in ), |
.ps2_data_oe ( ps2_data_oe ), |
.ps2_data_in ( ps2_data_in ), |
|
.txd_pad_out ( serial_txd ), |
.rxd_pad_in ( serial_rxd ), |
.cts_pad_in ( loop ), |
.rts_pad_out ( loop ) |
); |
|
|
|
|
|
|
|
iobuftri |
data_tri_buf |
( |
.i ( 1'b0 ), |
.oe ( ps2_data_oe ), |
.o ( ps2_data_in ), |
.pad ( ps2_data ) |
); |
|
|
iobuftri |
clk_tri_buf |
( |
.i ( 1'b0 ), |
.oe ( ps2_clk_oe ), |
.o ( ps2_clk_in ), |
.pad ( ps2_clk ) |
); |
|
|
|
pullup ua0(ps2_clk); |
pullup ua1(ps2_data); |
|
|
ps2_model |
#(.CLKCNT(10'h177)) |
ps2_model |
( |
.clk ( clk ), |
.reset ( reset ), |
.ps2_clk ( ps2_clk ), |
.ps2_data ( ps2_data ) |
|
|
|
); |
|
|
|
|
|
uart_model #(.CLKCNT(4'hc)) |
uart_model ( |
.clk ( clk ), |
.reset ( reset ), |
.txd_in ( serial_txd ), |
.rxd_out ( serial_rxd ) |
); |
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dut
1,8 → 1,8
|
wire [15:0] addr; |
|
|
|
|
wire serial_txd; |
wire serial_rxd; |
|
25,11 → 25,7
|
|
|
reg enable; |
|
always@(posedge clk) |
if(reset) enable <= 1'b1; |
else enable <= !enable; |
|
|
T6502 |
36,9 → 32,9
|
#(.ROM_WORDS(`ROM_WORDS), |
.ROM_ADD (`ROM_ADD), |
.ROM_FILE (`ROM_FILE), |
.BOOT (16'hf800) |
.ROM_FILE (`ROM_FILE) |
|
|
) |
|
dut |
45,7 → 41,7
( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.addr_pin ( ), |
|
.gpio_0_out ( Status ), |
.gpio_0_in ( Status ), |
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/core.v
File deleted
\ No newline at end of file
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/bsdl/xc3s1200e_fg320_1532.bsd
File deleted
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/bsdl/xc3s1200e_fg320_1532.bsd
0,0 → 1,1591
--$ XILINX$RCSfile: xc3s1200e_fg320_1532.bsd,v $ |
--$ XILINX$Revision: 1.2.124.1 $ |
|
--################################################################### |
-- WARNING !!!! .. This is a 1532 PROTOTYPE BDSL file. |
--################################################################### |
-- |
-- It should not be be used in place of, or along side of 1149.1 bsdl files. |
-- |
-- This file conforms to the unapproved IEEE Standard 1532 BSDL draft |
-- Standard. It may not function as expected with IEEE 1149.1 BSDL |
-- and is subject to change pending the ratification of the 1532 Standard |
-- by the IEEE. When denoted as FINAL, it has been verified |
-- syntactically, and against hardware. |
-- |
-- Prototype 1532 BSDL file for device XC3S1200E, package FG320 |
-- Xilinx, Inc. $State: Exp $ $Date: 2008/07/07 22:23:21 $ |
-- |
-- Generated by BSDLnet bsdlnet Version 1.40 |
------------------------------------------------------------------------ |
-- Modification History |
-- | Generated on 05/28/08 |
-- | CR # 471899 |
-- | Details - Initial Release using BSDLnet. |
-- | Added 'attribute COMPLIANCE_PATTERNS' & changed boundary |
-- | register attribute to internal for PROG_B & PUDC_B. |
------------------------------------------------------------------------ |
-- |
-- createBSDL template $RCSfile: xc3s1200e_fg320_1532.bsd,v $ $Revision: 1.2.124.1 $ $Date: 2008/07/07 22:23:21 $ |
-- |
--################################################################### |
-- |
-- |
-- For technical support, contact Xilinx on the web at: |
-- |
-- http://support.xilinx.com |
-- |
-- Technical support can also take place via email or phone at: |
-- |
-- North America 1-800-255-7778 hotline@xilinx.com |
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com |
-- France (33) 1 3463 0100 frhelp@xilinx.com |
-- Germany (49) 89 991 54930 dlhelp@xilinx.com |
-- Japan (81) 3-3297-9163 jhotline@xilinx.com |
-- |
-- |
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect |
-- the post-configuration JTAG behavior (if any), edit this file as described |
-- below. Many of these changes are demonstrated by commented-out template |
-- lines preceeding the lines they would replace: |
-- |
-- 1. Set disable result of all pads as configured. |
-- 2. Set safe state of boundary cells as necessary. |
-- 3. Rename entity if necessary to avoid name collisions. |
-- 4. Modify USERCODE value in USERCODE_REGISTER declaration. |
-- |
--###################################################################-- |
|
---------------------------------- |
|
-- BSDL File for 1532 Standard. |
|
---------------------------------- |
|
entity XC3S1200E_FG320 is |
|
-- Generic Parameter |
|
generic (PHYSICAL_PIN_MAP : string := "FG320" ); |
|
-- Logical Port Description |
|
port ( |
A10: inout bit; -- PAD40 |
A11: inout bit; -- PAD49 |
A12: inout bit; -- PAD54 |
A13: inout bit; -- PAD59 |
A14: inout bit; -- PAD62 |
A16: inout bit; -- PAD76 |
A4: inout bit; -- PAD5 |
A6: inout bit; -- PAD14 |
A7: inout bit; -- PAD20 |
A8: inout bit; -- PAD28 |
B10: inout bit; -- PAD41 |
B11: inout bit; -- PAD42 |
B13: inout bit; -- PAD58 |
B14: inout bit; -- PAD63 |
B16: inout bit; -- PAD77 |
B4: inout bit; -- PAD4 |
B6: inout bit; -- PAD15 |
C1: inout bit; -- PAD304 |
C11: inout bit; -- PAD48 |
C14: inout bit; -- PAD72 |
C17: inout bit; -- PAD80 |
C18: inout bit; -- PAD81 |
C2: inout bit; -- PAD303 |
C3: inout bit; -- PAD2 |
C4: inout bit; -- PAD6 |
C5: inout bit; -- PAD8 |
C7: inout bit; -- PAD27 |
C9: inout bit; -- PAD37 |
D1: inout bit; -- PAD302 |
D10: inout bit; -- PAD44 |
D11: inout bit; -- PAD47 |
D13: inout bit; -- PAD57 |
D14: inout bit; -- PAD73 |
D16: inout bit; -- PAD82 |
D17: inout bit; -- PAD83 |
D2: inout bit; -- PAD301 |
D4: inout bit; -- PAD298 |
D5: inout bit; -- PAD7 |
D6: inout bit; -- PAD12 |
D7: inout bit; -- PAD26 |
D9: inout bit; -- PAD36 |
DONE: inout bit; |
E1: inout bit; -- PAD296 |
E10: inout bit; -- PAD43 |
E11: inout bit; -- PAD51 |
E12: inout bit; -- PAD55 |
E13: inout bit; -- PAD71 |
E15: inout bit; -- PAD85 |
E16: inout bit; -- PAD84 |
E2: inout bit; -- PAD297 |
E3: inout bit; -- PAD291 |
E4: inout bit; -- PAD292 |
E6: inout bit; -- PAD11 |
E7: inout bit; -- PAD21 |
E8: inout bit; -- PAD30 |
E9: inout bit; -- PAD34 |
F1: inout bit; -- PAD287 |
F11: inout bit; -- PAD50 |
F12: inout bit; -- PAD56 |
F14: inout bit; -- PAD92 |
F15: inout bit; -- PAD93 |
F17: inout bit; -- PAD99 |
F18: inout bit; -- PAD100 |
F2: inout bit; -- PAD286 |
F7: inout bit; -- PAD22 |
F8: inout bit; -- PAD29 |
F9: inout bit; -- PAD33 |
G13: inout bit; -- PAD97 |
G14: inout bit; -- PAD98 |
G15: inout bit; -- PAD103 |
G16: inout bit; -- PAD102 |
G3: inout bit; -- PAD285 |
G4: inout bit; -- PAD284 |
G5: inout bit; -- PAD281 |
G6: inout bit; -- PAD282 |
G9: inout bit; -- PAD35 |
GND: linkage bit_vector (1 to 28); |
H1: inout bit; -- PAD274 |
H14: inout bit; -- PAD105 |
H15: inout bit; -- PAD104 |
H16: inout bit; -- PAD108 |
H17: inout bit; -- PAD107 |
H2: inout bit; -- PAD275 |
H3: inout bit; -- PAD276 |
H4: inout bit; -- PAD277 |
H5: inout bit; -- PAD279 |
H6: inout bit; -- PAD280 |
IPAD10: in bit; |
IPAD101: in bit; |
IPAD106: in bit; |
IPAD111: in bit; |
IPAD116: in bit; |
IPAD121: in bit; |
IPAD126: in bit; |
IPAD131: in bit; |
IPAD136: in bit; |
IPAD141: in bit; |
IPAD148: in bit; |
IPAD155: in bit; |
IPAD161: in bit; |
IPAD162: in bit; |
IPAD183: in bit; |
IPAD184: in bit; |
IPAD190: in bit; |
IPAD191: in bit; |
IPAD197: in bit; |
IPAD198: in bit; |
IPAD204: in bit; |
IPAD205: in bit; |
IPAD226: in bit; |
IPAD227: in bit; |
IPAD230: in bit; |
IPAD231: in bit; |
IPAD238: in bit; |
IPAD243: in bit; |
IPAD248: in bit; |
IPAD253: in bit; |
IPAD258: in bit; |
IPAD263: in bit; |
IPAD268: in bit; |
IPAD273: in bit; |
IPAD278: in bit; |
IPAD283: in bit; |
IPAD288: in bit; |
IPAD293: in bit; |
IPAD3: in bit; |
IPAD300: in bit; |
IPAD31: in bit; |
IPAD32: in bit; |
IPAD38: in bit; |
IPAD39: in bit; |
IPAD45: in bit; |
IPAD46: in bit; |
IPAD52: in bit; |
IPAD53: in bit; |
IPAD74: in bit; |
IPAD75: in bit; |
IPAD78: in bit; |
IPAD79: in bit; |
IPAD86: in bit; |
IPAD9: in bit; |
IPAD91: in bit; |
IPAD96: in bit; |
J1: inout bit; -- PAD270 |
J12: inout bit; -- PAD110 |
J13: inout bit; -- PAD109 |
J14: inout bit; -- PAD112 |
J15: inout bit; -- PAD113 |
J16: inout bit; -- PAD114 |
J17: inout bit; -- PAD115 |
J2: inout bit; -- PAD269 |
J4: inout bit; -- PAD271 |
J5: inout bit; -- PAD272 |
K12: inout bit; -- PAD119 |
K13: inout bit; -- PAD120 |
K14: inout bit; -- PAD117 |
K15: inout bit; -- PAD118 |
K3: inout bit; -- PAD267 |
K4: inout bit; -- PAD266 |
K5: inout bit; -- PAD264 |
K6: inout bit; -- PAD265 |
L1: inout bit; -- PAD262 |
L15: inout bit; -- PAD124 |
L16: inout bit; -- PAD125 |
L17: inout bit; -- PAD122 |
L18: inout bit; -- PAD123 |
L2: inout bit; -- PAD261 |
L3: inout bit; -- PAD260 |
L4: inout bit; -- PAD259 |
L5: inout bit; -- PAD256 |
L6: inout bit; -- PAD257 |
M10: inout bit; -- PAD186 |
M13: inout bit; -- PAD134 |
M14: inout bit; -- PAD135 |
M15: inout bit; -- PAD130 |
M16: inout bit; -- PAD129 |
M18: inout bit; -- PAD127 |
M3: inout bit; -- PAD254 |
M4: inout bit; -- PAD255 |
M5: inout bit; -- PAD252 |
M6: inout bit; -- PAD251 |
M9: inout bit; -- PAD195 |
N10: inout bit; -- PAD185 |
N11: inout bit; -- PAD181 |
N12: inout bit; -- PAD171 |
N14: inout bit; -- PAD139 |
N15: inout bit; -- PAD140 |
N18: inout bit; -- PAD128 |
N4: inout bit; -- PAD250 |
N5: inout bit; -- PAD249 |
N7: inout bit; -- PAD208 |
N8: inout bit; -- PAD202 |
N9: inout bit; -- PAD196 |
P1: inout bit; -- PAD244 |
P10: inout bit; -- PAD188 |
P11: inout bit; -- PAD182 |
P12: inout bit; -- PAD170 |
P13: inout bit; -- PAD167 |
P16: inout bit; -- PAD142 |
P17: inout bit; -- PAD133 |
P18: inout bit; -- PAD132 |
P2: inout bit; -- PAD245 |
P3: inout bit; -- PAD242 |
P4: inout bit; -- PAD241 |
P6: inout bit; -- PAD214 |
P7: inout bit; -- PAD207 |
P8: inout bit; -- PAD203 |
P9: inout bit; -- PAD201 |
PROG_B: in bit; |
PUDC_B: in bit; -- PAD1 |
R10: inout bit; -- PAD189 |
R11: inout bit; -- PAD180 |
R12: inout bit; -- PAD173 |
R13: inout bit; -- PAD166 |
R14: inout bit; -- PAD159 |
R15: inout bit; -- PAD147 |
R16: inout bit; -- PAD146 |
R18: inout bit; -- PAD150 |
R2: inout bit; -- PAD234 |
R3: inout bit; -- PAD235 |
R5: inout bit; -- PAD222 |
R6: inout bit; -- PAD215 |
R8: inout bit; -- PAD200 |
R9: inout bit; -- PAD194 |
T1: inout bit; -- PAD232 |
T12: inout bit; -- PAD174 |
T14: inout bit; -- PAD160 |
T15: inout bit; -- PAD158 |
T16: inout bit; -- PAD154 |
T17: inout bit; -- PAD151 |
T18: inout bit; -- PAD149 |
T2: inout bit; -- PAD233 |
T3: inout bit; -- PAD228 |
T4: inout bit; -- PAD224 |
T5: inout bit; -- PAD221 |
T8: inout bit; -- PAD199 |
TCK: in bit; |
TDI: in bit; |
TDO: out bit; |
TMS: in bit; |
U13: inout bit; -- PAD172 |
U15: inout bit; -- PAD156 |
U16: inout bit; -- PAD153 |
U18: inout bit; -- PAD152 |
U3: inout bit; -- PAD229 |
U4: inout bit; -- PAD225 |
U5: inout bit; -- PAD223 |
U6: inout bit; -- PAD209 |
U9: inout bit; -- PAD193 |
V11: inout bit; -- PAD187 |
V12: inout bit; -- PAD179 |
V13: inout bit; -- PAD178 |
V15: inout bit; -- PAD157 |
V5: inout bit; -- PAD211 |
V6: inout bit; -- PAD210 |
V7: inout bit; -- PAD206 |
V9: inout bit; -- PAD192 |
VCCAUX: linkage bit_vector (1 to 8); |
VCCINT: linkage bit_vector (1 to 8); |
VCCO_0: linkage bit_vector (1 to 5); |
VCCO_1: linkage bit_vector (1 to 5); |
VCCO_2: linkage bit_vector (1 to 5); |
VCCO_3: linkage bit_vector (1 to 5) |
); --end port list |
|
-- Use Statements |
|
use STD_1149_1_2001.all; |
use STD_1532_2002.all; |
|
-- Component Conformance Statement(s) |
|
attribute COMPONENT_CONFORMANCE of XC3S1200E_FG320 : entity is |
"STD_1149_1_2001"; |
|
-- Device Package Pin Mappings |
|
attribute PIN_MAP of XC3S1200E_FG320 : entity is PHYSICAL_PIN_MAP; |
|
constant FG320: PIN_MAP_STRING:= |
"A10:A10," & |
"A11:A11," & |
"A12:A12," & |
"A13:A13," & |
"A14:A14," & |
"A16:A16," & |
"A4:A4," & |
"A6:A6," & |
"A7:A7," & |
"A8:A8," & |
"B10:B10," & |
"B11:B11," & |
"B13:B13," & |
"B14:B14," & |
"B16:B16," & |
"B4:B4," & |
"B6:B6," & |
"C1:C1," & |
"C11:C11," & |
"C14:C14," & |
"C17:C17," & |
"C18:C18," & |
"C2:C2," & |
"C3:C3," & |
"C4:C4," & |
"C5:C5," & |
"C7:C7," & |
"C9:C9," & |
"D1:D1," & |
"D10:D10," & |
"D11:D11," & |
"D13:D13," & |
"D14:D14," & |
"D16:D16," & |
"D17:D17," & |
"D2:D2," & |
"D4:D4," & |
"D5:D5," & |
"D6:D6," & |
"D7:D7," & |
"D9:D9," & |
"DONE:V17," & |
"E1:E1," & |
"E10:E10," & |
"E11:E11," & |
"E12:E12," & |
"E13:E13," & |
"E15:E15," & |
"E16:E16," & |
"E2:E2," & |
"E3:E3," & |
"E4:E4," & |
"E6:E6," & |
"E7:E7," & |
"E8:E8," & |
"E9:E9," & |
"F1:F1," & |
"F11:F11," & |
"F12:F12," & |
"F14:F14," & |
"F15:F15," & |
"F17:F17," & |
"F18:F18," & |
"F2:F2," & |
"F7:F7," & |
"F8:F8," & |
"F9:F9," & |
"G13:G13," & |
"G14:G14," & |
"G15:G15," & |
"G16:G16," & |
"G3:G3," & |
"G4:G4," & |
"G5:G5," & |
"G6:G6," & |
"G9:G9," & |
"GND:(A1,A18,B2,B17,C10,G7,G12,H8,H9,H10," & |
"H11,J3,J8,J11,K8,K11,K16,L8,L9,L10," & |
"L11,M7,M12,T9,U2,U17,V1,V18)," & |
"H1:H1," & |
"H14:H14," & |
"H15:H15," & |
"H16:H16," & |
"H17:H17," & |
"H2:H2," & |
"H3:H3," & |
"H4:H4," & |
"H5:H5," & |
"H6:H6," & |
"IPAD10:A5," & |
"IPAD101:H13," & |
"IPAD106:G18," & |
"IPAD111:H18," & |
"IPAD116:K18," & |
"IPAD121:K17," & |
"IPAD126:L13," & |
"IPAD131:L14," & |
"IPAD136:N17," & |
"IPAD141:P15," & |
"IPAD148:R17," & |
"IPAD155:V16," & |
"IPAD161:U14," & |
"IPAD162:V14," & |
"IPAD183:U11," & |
"IPAD184:T11," & |
"IPAD190:T10," & |
"IPAD191:U10," & |
"IPAD197:V8," & |
"IPAD198:U8," & |
"IPAD204:R7," & |
"IPAD205:T7," & |
"IPAD226:V3," & |
"IPAD227:V4," & |
"IPAD230:V2," & |
"IPAD231:U1," & |
"IPAD238:R1," & |
"IPAD243:R4," & |
"IPAD248:N2," & |
"IPAD253:N1," & |
"IPAD258:M1," & |
"IPAD263:K7," & |
"IPAD268:K2," & |
"IPAD273:J6," & |
"IPAD278:J7," & |
"IPAD283:G1," & |
"IPAD288:F5," & |
"IPAD293:F4," & |
"IPAD3:A3," & |
"IPAD300:D3," & |
"IPAD31:D8," & |
"IPAD32:C8," & |
"IPAD38:B9," & |
"IPAD39:B8," & |
"IPAD45:G10," & |
"IPAD46:F10," & |
"IPAD52:D12," & |
"IPAD53:C12," & |
"IPAD74:A15," & |
"IPAD75:B15," & |
"IPAD78:C15," & |
"IPAD79:B18," & |
"IPAD86:D18," & |
"IPAD9:B5," & |
"IPAD91:E17," & |
"IPAD96:E18," & |
"J1:J1," & |
"J12:J12," & |
"J13:J13," & |
"J14:J14," & |
"J15:J15," & |
"J16:J16," & |
"J17:J17," & |
"J2:J2," & |
"J4:J4," & |
"J5:J5," & |
"K12:K12," & |
"K13:K13," & |
"K14:K14," & |
"K15:K15," & |
"K3:K3," & |
"K4:K4," & |
"K5:K5," & |
"K6:K6," & |
"L1:L1," & |
"L15:L15," & |
"L16:L16," & |
"L17:L17," & |
"L18:L18," & |
"L2:L2," & |
"L3:L3," & |
"L4:L4," & |
"L5:L5," & |
"L6:L6," & |
"M10:M10," & |
"M13:M13," & |
"M14:M14," & |
"M15:M15," & |
"M16:M16," & |
"M18:M18," & |
"M3:M3," & |
"M4:M4," & |
"M5:M5," & |
"M6:M6," & |
"M9:M9," & |
"N10:N10," & |
"N11:N11," & |
"N12:N12," & |
"N14:N14," & |
"N15:N15," & |
"N18:N18," & |
"N4:N4," & |
"N5:N5," & |
"N7:N7," & |
"N8:N8," & |
"N9:N9," & |
"P1:P1," & |
"P10:P10," & |
"P11:P11," & |
"P12:P12," & |
"P13:P13," & |
"P16:P16," & |
"P17:P17," & |
"P18:P18," & |
"P2:P2," & |
"P3:P3," & |
"P4:P4," & |
"P6:P6," & |
"P7:P7," & |
"P8:P8," & |
"P9:P9," & |
"PROG_B:B1," & |
"PUDC_B:B3," & |
"R10:R10," & |
"R11:R11," & |
"R12:R12," & |
"R13:R13," & |
"R14:R14," & |
"R15:R15," & |
"R16:R16," & |
"R18:R18," & |
"R2:R2," & |
"R3:R3," & |
"R5:R5," & |
"R6:R6," & |
"R8:R8," & |
"R9:R9," & |
"T1:T1," & |
"T12:T12," & |
"T14:T14," & |
"T15:T15," & |
"T16:T16," & |
"T17:T17," & |
"T18:T18," & |
"T2:T2," & |
"T3:T3," & |
"T4:T4," & |
"T5:T5," & |
"T8:T8," & |
"TCK:A17," & |
"TDI:A2," & |
"TDO:C16," & |
"TMS:D15," & |
"U13:U13," & |
"U15:U15," & |
"U16:U16," & |
"U18:U18," & |
"U3:U3," & |
"U4:U4," & |
"U5:U5," & |
"U6:U6," & |
"U9:U9," & |
"V11:V11," & |
"V12:V12," & |
"V13:V13," & |
"V15:V15," & |
"V5:V5," & |
"V6:V6," & |
"V7:V7," & |
"V9:V9," & |
"VCCAUX:(B7,B12,G2,G17,M2,M17,U7,U12)," & |
"VCCINT:(E5,E14,F6,F13,N6,N13,P5,P14)," & |
"VCCO_0:(A9,C6,C13,G8,G11)," & |
"VCCO_1:(F16,H12,J18,L12,N16)," & |
"VCCO_2:(M8,M11,T6,T13,V10)," & |
"VCCO_3:(F3,H7,K1,L7,N3)"; |
|
|
-- Scan Port Identification |
|
attribute TAP_SCAN_OUT of TDO : signal is true; |
attribute TAP_SCAN_IN of TDI : signal is true; |
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both); |
attribute TAP_SCAN_MODE of TMS : signal is true; |
|
-- Compliance-Enable Description |
|
attribute COMPLIANCE_PATTERNS of XC3S1200E_FG320 : entity is |
"(PROG_B, PUDC_B) (10)"; |
|
-- Instruction Register Description |
|
attribute INSTRUCTION_LENGTH of XC3S1200E_FG320 : entity is 6; |
|
attribute INSTRUCTION_OPCODE of XC3S1200E_FG320 : entity is |
|
"EXTEST (001111)," & |
"SAMPLE (000001)," & |
"PRELOAD (000001)," & -- Same as SAMPLE |
"USER1 (000010)," & -- Not available until after configuration |
"USER2 (000011)," & -- Not available until after configuration |
"CFG_OUT (000100)," & -- Not available during configuration with another mode. |
"CFG_IN (000101)," & -- Not available during configuration with another mode. |
"INTEST (000111)," & |
"USERCODE (001000)," & |
"IDCODE (001001)," & |
"HIGHZ (001010)," & |
"JPROGRAM (001011)," & -- Not available during configuration with another mode. |
"JSTART (001100)," & -- Not available during configuration with another mode. |
"JSHUTDOWN (001101)," & -- Not available during configuration with another mode. |
"BYPASS (111111)," & |
"ISC_ENABLE (010000)," & |
"ISC_PROGRAM (010001)," & |
"ISC_NOOP (010100)," & |
"ISC_READ (010101)," & |
"ISC_DISABLE (010110)"; |
|
attribute INSTRUCTION_CAPTURE of XC3S1200E_FG320 : entity is |
-- Bit 5 is 1 when DONE is released (part of startup sequence) |
-- Bit 4 is 1 if house-cleaning is complete |
-- Bit 3 is ISC_Enabled |
-- Bit 2 is ISC_Done |
"XXXX01" ; |
|
attribute INSTRUCTION_PRIVATE of XC3S1200E_FG320 : entity is |
"USER1," & |
"USER2," & |
"CFG_OUT," & |
"CFG_IN," & |
"JPROGRAM," & |
"JSTART," & |
"JSHUTDOWN," & |
"ISC_ENABLE," & |
"ISC_PROGRAM," & |
"ISC_NOOP," & |
"ISC_READ," & |
"ISC_DISABLE"; |
|
-- Optional Register Description |
|
attribute IDCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXX" & -- version |
"0001110" & -- family |
"000101110" & -- array size |
"00001001001" & -- manufacturer |
"1"; -- required by 1149.1 |
|
|
attribute USERCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; |
|
-- Register Access Description |
|
attribute REGISTER_ACCESS of XC3S1200E_FG320 : entity is |
"TEST1[8] (USER1)," & |
"TEST2[16] (USER2)," & |
"DEVICE_ID (USERCODE,IDCODE)," & |
"BYPASS (BYPASS,HIGHZ,JPROGRAM,JSTART,JSHUTDOWN)," & |
"CFG_DATA[3838752] (CFG_IN)," & |
"ISC_PDATA[16] (ISC_PROGRAM),"& |
"ISC_RDATA[16] (ISC_READ),"& |
"ISC_DEFAULT[5] (ISC_NOOP)," & |
"ISC_CONFIG[5] (ISC_ENABLE,ISC_DISABLE)," & |
"BOUNDARY (EXTEST, SAMPLE, PRELOAD, INTEST)"; |
|
-- Boundary-Scan Register Description |
|
attribute BOUNDARY_LENGTH of XC3S1200E_FG320 : entity is 772; |
|
attribute BOUNDARY_REGISTER of XC3S1200E_FG320 : entity is |
-- cellnum (type, port, function, safe[, ccell, disval, disrslt]) |
" 771 (BC_2, IPAD79, input, X)," & |
" 770 (BC_2, C17, input, X)," & -- PAD80 |
" 769 (BC_2, C17, output3, X, 768, 1, PULL1)," & -- PAD80 |
" 768 (BC_2, *, controlr, 1)," & |
" 767 (BC_2, C18, input, X)," & -- PAD81 |
" 766 (BC_2, C18, output3, X, 765, 1, PULL1)," & -- PAD81 |
" 765 (BC_2, *, controlr, 1)," & |
" 764 (BC_2, D16, input, X)," & -- PAD82 |
" 763 (BC_2, D16, output3, X, 762, 1, PULL1)," & -- PAD82 |
" 762 (BC_2, *, controlr, 1)," & |
" 761 (BC_2, D17, input, X)," & -- PAD83 |
" 760 (BC_2, D17, output3, X, 759, 1, PULL1)," & -- PAD83 |
" 759 (BC_2, *, controlr, 1)," & |
" 758 (BC_2, E16, input, X)," & -- PAD84 |
" 757 (BC_2, E16, output3, X, 756, 1, PULL1)," & -- PAD84 |
" 756 (BC_2, *, controlr, 1)," & |
" 755 (BC_2, E15, input, X)," & -- PAD85 |
" 754 (BC_2, E15, output3, X, 753, 1, PULL1)," & -- PAD85 |
" 753 (BC_2, *, controlr, 1)," & |
" 752 (BC_2, IPAD86, input, X)," & |
" 751 (BC_2, *, internal, X)," & -- PAD87.I |
" 750 (BC_2, *, internal, X)," & -- PAD87.O |
" 749 (BC_2, *, internal, 1)," & -- PAD87.T |
" 748 (BC_2, *, internal, X)," & -- PAD88.I |
" 747 (BC_2, *, internal, X)," & -- PAD88.O |
" 746 (BC_2, *, internal, 1)," & -- PAD88.T |
" 745 (BC_2, *, internal, X)," & -- PAD89.I |
" 744 (BC_2, *, internal, X)," & -- PAD89.O |
" 743 (BC_2, *, internal, 1)," & -- PAD89.T |
" 742 (BC_2, *, internal, X)," & -- PAD90.I |
" 741 (BC_2, *, internal, X)," & -- PAD90.O |
" 740 (BC_2, *, internal, 1)," & -- PAD90.T |
" 739 (BC_2, IPAD91, input, X)," & |
" 738 (BC_2, F14, input, X)," & -- PAD92 |
" 737 (BC_2, F14, output3, X, 736, 1, PULL1)," & -- PAD92 |
" 736 (BC_2, *, controlr, 1)," & |
" 735 (BC_2, F15, input, X)," & -- PAD93 |
" 734 (BC_2, F15, output3, X, 733, 1, PULL1)," & -- PAD93 |
" 733 (BC_2, *, controlr, 1)," & |
" 732 (BC_2, *, internal, X)," & -- PAD94.I |
" 731 (BC_2, *, internal, X)," & -- PAD94.O |
" 730 (BC_2, *, internal, 1)," & -- PAD94.T |
" 729 (BC_2, *, internal, X)," & -- PAD95.I |
" 728 (BC_2, *, internal, X)," & -- PAD95.O |
" 727 (BC_2, *, internal, 1)," & -- PAD95.T |
" 726 (BC_2, IPAD96, input, X)," & |
" 725 (BC_2, G13, input, X)," & -- PAD97 |
" 724 (BC_2, G13, output3, X, 723, 1, PULL1)," & -- PAD97 |
" 723 (BC_2, *, controlr, 1)," & |
" 722 (BC_2, G14, input, X)," & -- PAD98 |
" 721 (BC_2, G14, output3, X, 720, 1, PULL1)," & -- PAD98 |
" 720 (BC_2, *, controlr, 1)," & |
" 719 (BC_2, F17, input, X)," & -- PAD99 |
" 718 (BC_2, F17, output3, X, 717, 1, PULL1)," & -- PAD99 |
" 717 (BC_2, *, controlr, 1)," & |
" 716 (BC_2, F18, input, X)," & -- PAD100 |
" 715 (BC_2, F18, output3, X, 714, 1, PULL1)," & -- PAD100 |
" 714 (BC_2, *, controlr, 1)," & |
" 713 (BC_2, IPAD101, input, X)," & |
" 712 (BC_2, G16, input, X)," & -- PAD102 |
" 711 (BC_2, G16, output3, X, 710, 1, PULL1)," & -- PAD102 |
" 710 (BC_2, *, controlr, 1)," & |
" 709 (BC_2, G15, input, X)," & -- PAD103 |
" 708 (BC_2, G15, output3, X, 707, 1, PULL1)," & -- PAD103 |
" 707 (BC_2, *, controlr, 1)," & |
" 706 (BC_2, H15, input, X)," & -- PAD104 |
" 705 (BC_2, H15, output3, X, 704, 1, PULL1)," & -- PAD104 |
" 704 (BC_2, *, controlr, 1)," & |
" 703 (BC_2, H14, input, X)," & -- PAD105 |
" 702 (BC_2, H14, output3, X, 701, 1, PULL1)," & -- PAD105 |
" 701 (BC_2, *, controlr, 1)," & |
" 700 (BC_2, IPAD106, input, X)," & |
" 699 (BC_2, H17, input, X)," & -- PAD107 |
" 698 (BC_2, H17, output3, X, 697, 1, PULL1)," & -- PAD107 |
" 697 (BC_2, *, controlr, 1)," & |
" 696 (BC_2, H16, input, X)," & -- PAD108 |
" 695 (BC_2, H16, output3, X, 694, 1, PULL1)," & -- PAD108 |
" 694 (BC_2, *, controlr, 1)," & |
" 693 (BC_2, J13, input, X)," & -- PAD109 |
" 692 (BC_2, J13, output3, X, 691, 1, PULL1)," & -- PAD109 |
" 691 (BC_2, *, controlr, 1)," & |
" 690 (BC_2, J12, input, X)," & -- PAD110 |
" 689 (BC_2, J12, output3, X, 688, 1, PULL1)," & -- PAD110 |
" 688 (BC_2, *, controlr, 1)," & |
" 687 (BC_2, IPAD111, input, X)," & |
" 686 (BC_2, J14, input, X)," & -- PAD112 |
" 685 (BC_2, J14, output3, X, 684, 1, PULL1)," & -- PAD112 |
" 684 (BC_2, *, controlr, 1)," & |
" 683 (BC_2, J15, input, X)," & -- PAD113 |
" 682 (BC_2, J15, output3, X, 681, 1, PULL1)," & -- PAD113 |
" 681 (BC_2, *, controlr, 1)," & |
" 680 (BC_2, J16, input, X)," & -- PAD114 |
" 679 (BC_2, J16, output3, X, 678, 1, PULL1)," & -- PAD114 |
" 678 (BC_2, *, controlr, 1)," & |
" 677 (BC_2, J17, input, X)," & -- PAD115 |
" 676 (BC_2, J17, output3, X, 675, 1, PULL1)," & -- PAD115 |
" 675 (BC_2, *, controlr, 1)," & |
" 674 (BC_2, IPAD116, input, X)," & |
" 673 (BC_2, K14, input, X)," & -- PAD117 |
" 672 (BC_2, K14, output3, X, 671, 1, PULL1)," & -- PAD117 |
" 671 (BC_2, *, controlr, 1)," & |
" 670 (BC_2, K15, input, X)," & -- PAD118 |
" 669 (BC_2, K15, output3, X, 668, 1, PULL1)," & -- PAD118 |
" 668 (BC_2, *, controlr, 1)," & |
" 667 (BC_2, K12, input, X)," & -- PAD119 |
" 666 (BC_2, K12, output3, X, 665, 1, PULL1)," & -- PAD119 |
" 665 (BC_2, *, controlr, 1)," & |
" 664 (BC_2, K13, input, X)," & -- PAD120 |
" 663 (BC_2, K13, output3, X, 662, 1, PULL1)," & -- PAD120 |
" 662 (BC_2, *, controlr, 1)," & |
" 661 (BC_2, IPAD121, input, X)," & |
" 660 (BC_2, L17, input, X)," & -- PAD122 |
" 659 (BC_2, L17, output3, X, 658, 1, PULL1)," & -- PAD122 |
" 658 (BC_2, *, controlr, 1)," & |
" 657 (BC_2, L18, input, X)," & -- PAD123 |
" 656 (BC_2, L18, output3, X, 655, 1, PULL1)," & -- PAD123 |
" 655 (BC_2, *, controlr, 1)," & |
" 654 (BC_2, L15, input, X)," & -- PAD124 |
" 653 (BC_2, L15, output3, X, 652, 1, PULL1)," & -- PAD124 |
" 652 (BC_2, *, controlr, 1)," & |
" 651 (BC_2, L16, input, X)," & -- PAD125 |
" 650 (BC_2, L16, output3, X, 649, 1, PULL1)," & -- PAD125 |
" 649 (BC_2, *, controlr, 1)," & |
" 648 (BC_2, IPAD126, input, X)," & |
" 647 (BC_2, M18, input, X)," & -- PAD127 |
" 646 (BC_2, M18, output3, X, 645, 1, PULL1)," & -- PAD127 |
" 645 (BC_2, *, controlr, 1)," & |
" 644 (BC_2, N18, input, X)," & -- PAD128 |
" 643 (BC_2, N18, output3, X, 642, 1, PULL1)," & -- PAD128 |
" 642 (BC_2, *, controlr, 1)," & |
" 641 (BC_2, M16, input, X)," & -- PAD129 |
" 640 (BC_2, M16, output3, X, 639, 1, PULL1)," & -- PAD129 |
" 639 (BC_2, *, controlr, 1)," & |
" 638 (BC_2, M15, input, X)," & -- PAD130 |
" 637 (BC_2, M15, output3, X, 636, 1, PULL1)," & -- PAD130 |
" 636 (BC_2, *, controlr, 1)," & |
" 635 (BC_2, IPAD131, input, X)," & |
" 634 (BC_2, P18, input, X)," & -- PAD132 |
" 633 (BC_2, P18, output3, X, 632, 1, PULL1)," & -- PAD132 |
" 632 (BC_2, *, controlr, 1)," & |
" 631 (BC_2, P17, input, X)," & -- PAD133 |
" 630 (BC_2, P17, output3, X, 629, 1, PULL1)," & -- PAD133 |
" 629 (BC_2, *, controlr, 1)," & |
" 628 (BC_2, M13, input, X)," & -- PAD134 |
" 627 (BC_2, M13, output3, X, 626, 1, PULL1)," & -- PAD134 |
" 626 (BC_2, *, controlr, 1)," & |
" 625 (BC_2, M14, input, X)," & -- PAD135 |
" 624 (BC_2, M14, output3, X, 623, 1, PULL1)," & -- PAD135 |
" 623 (BC_2, *, controlr, 1)," & |
" 622 (BC_2, IPAD136, input, X)," & |
" 621 (BC_2, *, internal, X)," & -- PAD137.I |
" 620 (BC_2, *, internal, X)," & -- PAD137.O |
" 619 (BC_2, *, internal, 1)," & -- PAD137.T |
" 618 (BC_2, *, internal, X)," & -- PAD138.I |
" 617 (BC_2, *, internal, X)," & -- PAD138.O |
" 616 (BC_2, *, internal, 1)," & -- PAD138.T |
" 615 (BC_2, N14, input, X)," & -- PAD139 |
" 614 (BC_2, N14, output3, X, 613, 1, PULL1)," & -- PAD139 |
" 613 (BC_2, *, controlr, 1)," & |
" 612 (BC_2, N15, input, X)," & -- PAD140 |
" 611 (BC_2, N15, output3, X, 610, 1, PULL1)," & -- PAD140 |
" 610 (BC_2, *, controlr, 1)," & |
" 609 (BC_2, IPAD141, input, X)," & |
" 608 (BC_2, P16, input, X)," & -- PAD142 |
" 607 (BC_2, P16, output3, X, 606, 1, PULL1)," & -- PAD142 |
" 606 (BC_2, *, controlr, 1)," & |
" 605 (BC_2, *, internal, X)," & -- PAD143.I |
" 604 (BC_2, *, internal, X)," & -- PAD143.O |
" 603 (BC_2, *, internal, 1)," & -- PAD143.T |
" 602 (BC_2, *, internal, X)," & -- PAD144.I |
" 601 (BC_2, *, internal, X)," & -- PAD144.O |
" 600 (BC_2, *, internal, 1)," & -- PAD144.T |
" 599 (BC_2, *, internal, X)," & -- PAD145.I |
" 598 (BC_2, *, internal, X)," & -- PAD145.O |
" 597 (BC_2, *, internal, 1)," & -- PAD145.T |
" 596 (BC_2, R16, input, X)," & -- PAD146 |
" 595 (BC_2, R16, output3, X, 594, 1, PULL1)," & -- PAD146 |
" 594 (BC_2, *, controlr, 1)," & |
" 593 (BC_2, R15, input, X)," & -- PAD147 |
" 592 (BC_2, R15, output3, X, 591, 1, PULL1)," & -- PAD147 |
" 591 (BC_2, *, controlr, 1)," & |
" 590 (BC_2, IPAD148, input, X)," & |
" 589 (BC_2, T18, input, X)," & -- PAD149 |
" 588 (BC_2, T18, output3, X, 587, 1, PULL1)," & -- PAD149 |
" 587 (BC_2, *, controlr, 1)," & |
" 586 (BC_2, R18, input, X)," & -- PAD150 |
" 585 (BC_2, R18, output3, X, 584, 1, PULL1)," & -- PAD150 |
" 584 (BC_2, *, controlr, 1)," & |
" 583 (BC_2, T17, input, X)," & -- PAD151 |
" 582 (BC_2, T17, output3, X, 581, 1, PULL1)," & -- PAD151 |
" 581 (BC_2, *, controlr, 1)," & |
" 580 (BC_2, U18, input, X)," & -- PAD152 |
" 579 (BC_2, U18, output3, X, 578, 1, PULL1)," & -- PAD152 |
" 578 (BC_2, *, controlr, 1)," & |
" 577 (BC_2, DONE, input, X)," & |
" 576 (BC_2, DONE, output3, X, 575, 1, PULL1)," & |
" 575 (BC_2, *, controlr, 1)," & |
" 574 (BC_2, U16, input, X)," & -- PAD153 |
" 573 (BC_2, U16, output3, X, 572, 1, PULL1)," & -- PAD153 |
" 572 (BC_2, *, controlr, 1)," & |
" 571 (BC_2, T16, input, X)," & -- PAD154 |
" 570 (BC_2, T16, output3, X, 569, 1, PULL1)," & -- PAD154 |
" 569 (BC_2, *, controlr, 1)," & |
" 568 (BC_2, IPAD155, input, X)," & |
" 567 (BC_2, U15, input, X)," & -- PAD156 |
" 566 (BC_2, U15, output3, X, 565, 1, PULL1)," & -- PAD156 |
" 565 (BC_2, *, controlr, 1)," & |
" 564 (BC_2, V15, input, X)," & -- PAD157 |
" 563 (BC_2, V15, output3, X, 562, 1, PULL1)," & -- PAD157 |
" 562 (BC_2, *, controlr, 1)," & |
" 561 (BC_2, T15, input, X)," & -- PAD158 |
" 560 (BC_2, T15, output3, X, 559, 1, PULL1)," & -- PAD158 |
" 559 (BC_2, *, controlr, 1)," & |
" 558 (BC_2, R14, input, X)," & -- PAD159 |
" 557 (BC_2, R14, output3, X, 556, 1, PULL1)," & -- PAD159 |
" 556 (BC_2, *, controlr, 1)," & |
" 555 (BC_2, T14, input, X)," & -- PAD160 |
" 554 (BC_2, T14, output3, X, 553, 1, PULL1)," & -- PAD160 |
" 553 (BC_2, *, controlr, 1)," & |
" 552 (BC_2, IPAD161, input, X)," & |
" 551 (BC_2, IPAD162, input, X)," & |
" 550 (BC_2, *, internal, X)," & -- PAD163.I |
" 549 (BC_2, *, internal, X)," & -- PAD163.O |
" 548 (BC_2, *, internal, 1)," & -- PAD163.T |
" 547 (BC_2, *, internal, X)," & -- PAD164.I |
" 546 (BC_2, *, internal, X)," & -- PAD164.O |
" 545 (BC_2, *, internal, 1)," & -- PAD164.T |
" 544 (BC_2, *, internal, X)," & -- PAD165.I |
" 543 (BC_2, *, internal, X)," & -- PAD165.O |
" 542 (BC_2, *, internal, 1)," & -- PAD165.T |
" 541 (BC_2, R13, input, X)," & -- PAD166 |
" 540 (BC_2, R13, output3, X, 539, 1, PULL1)," & -- PAD166 |
" 539 (BC_2, *, controlr, 1)," & |
" 538 (BC_2, P13, input, X)," & -- PAD167 |
" 537 (BC_2, P13, output3, X, 536, 1, PULL1)," & -- PAD167 |
" 536 (BC_2, *, controlr, 1)," & |
" 535 (BC_2, *, internal, X)," & -- IPAD168 |
" 534 (BC_2, *, internal, X)," & -- IPAD169 |
" 533 (BC_2, P12, input, X)," & -- PAD170 |
" 532 (BC_2, P12, output3, X, 531, 1, PULL1)," & -- PAD170 |
" 531 (BC_2, *, controlr, 1)," & |
" 530 (BC_2, N12, input, X)," & -- PAD171 |
" 529 (BC_2, N12, output3, X, 528, 1, PULL1)," & -- PAD171 |
" 528 (BC_2, *, controlr, 1)," & |
" 527 (BC_2, U13, input, X)," & -- PAD172 |
" 526 (BC_2, U13, output3, X, 525, 1, PULL1)," & -- PAD172 |
" 525 (BC_2, *, controlr, 1)," & |
" 524 (BC_2, R12, input, X)," & -- PAD173 |
" 523 (BC_2, R12, output3, X, 522, 1, PULL1)," & -- PAD173 |
" 522 (BC_2, *, controlr, 1)," & |
" 521 (BC_2, T12, input, X)," & -- PAD174 |
" 520 (BC_2, T12, output3, X, 519, 1, PULL1)," & -- PAD174 |
" 519 (BC_2, *, controlr, 1)," & |
" 518 (BC_2, *, internal, X)," & -- IPAD175 |
" 517 (BC_2, *, internal, X)," & -- IPAD176 |
" 516 (BC_2, *, internal, X)," & -- PAD177.I |
" 515 (BC_2, *, internal, X)," & -- PAD177.O |
" 514 (BC_2, *, internal, 1)," & -- PAD177.T |
" 513 (BC_2, V13, input, X)," & -- PAD178 |
" 512 (BC_2, V13, output3, X, 511, 1, PULL1)," & -- PAD178 |
" 511 (BC_2, *, controlr, 1)," & |
" 510 (BC_2, V12, input, X)," & -- PAD179 |
" 509 (BC_2, V12, output3, X, 508, 1, PULL1)," & -- PAD179 |
" 508 (BC_2, *, controlr, 1)," & |
" 507 (BC_2, R11, input, X)," & -- PAD180 |
" 506 (BC_2, R11, output3, X, 505, 1, PULL1)," & -- PAD180 |
" 505 (BC_2, *, controlr, 1)," & |
" 504 (BC_2, N11, input, X)," & -- PAD181 |
" 503 (BC_2, N11, output3, X, 502, 1, PULL1)," & -- PAD181 |
" 502 (BC_2, *, controlr, 1)," & |
" 501 (BC_2, P11, input, X)," & -- PAD182 |
" 500 (BC_2, P11, output3, X, 499, 1, PULL1)," & -- PAD182 |
" 499 (BC_2, *, controlr, 1)," & |
" 498 (BC_2, IPAD183, input, X)," & |
" 497 (BC_2, IPAD184, input, X)," & |
" 496 (BC_2, N10, input, X)," & -- PAD185 |
" 495 (BC_2, N10, output3, X, 494, 1, PULL1)," & -- PAD185 |
" 494 (BC_2, *, controlr, 1)," & |
" 493 (BC_2, M10, input, X)," & -- PAD186 |
" 492 (BC_2, M10, output3, X, 491, 1, PULL1)," & -- PAD186 |
" 491 (BC_2, *, controlr, 1)," & |
" 490 (BC_2, V11, input, X)," & -- PAD187 |
" 489 (BC_2, V11, output3, X, 488, 1, PULL1)," & -- PAD187 |
" 488 (BC_2, *, controlr, 1)," & |
" 487 (BC_2, P10, input, X)," & -- PAD188 |
" 486 (BC_2, P10, output3, X, 485, 1, PULL1)," & -- PAD188 |
" 485 (BC_2, *, controlr, 1)," & |
" 484 (BC_2, R10, input, X)," & -- PAD189 |
" 483 (BC_2, R10, output3, X, 482, 1, PULL1)," & -- PAD189 |
" 482 (BC_2, *, controlr, 1)," & |
" 481 (BC_2, IPAD190, input, X)," & |
" 480 (BC_2, IPAD191, input, X)," & |
" 479 (BC_2, V9, input, X)," & -- PAD192 |
" 478 (BC_2, V9, output3, X, 477, 1, PULL1)," & -- PAD192 |
" 477 (BC_2, *, controlr, 1)," & |
" 476 (BC_2, U9, input, X)," & -- PAD193 |
" 475 (BC_2, U9, output3, X, 474, 1, PULL1)," & -- PAD193 |
" 474 (BC_2, *, controlr, 1)," & |
" 473 (BC_2, R9, input, X)," & -- PAD194 |
" 472 (BC_2, R9, output3, X, 471, 1, PULL1)," & -- PAD194 |
" 471 (BC_2, *, controlr, 1)," & |
" 470 (BC_2, M9, input, X)," & -- PAD195 |
" 469 (BC_2, M9, output3, X, 468, 1, PULL1)," & -- PAD195 |
" 468 (BC_2, *, controlr, 1)," & |
" 467 (BC_2, N9, input, X)," & -- PAD196 |
" 466 (BC_2, N9, output3, X, 465, 1, PULL1)," & -- PAD196 |
" 465 (BC_2, *, controlr, 1)," & |
" 464 (BC_2, IPAD197, input, X)," & |
" 463 (BC_2, IPAD198, input, X)," & |
" 462 (BC_2, T8, input, X)," & -- PAD199 |
" 461 (BC_2, T8, output3, X, 460, 1, PULL1)," & -- PAD199 |
" 460 (BC_2, *, controlr, 1)," & |
" 459 (BC_2, R8, input, X)," & -- PAD200 |
" 458 (BC_2, R8, output3, X, 457, 1, PULL1)," & -- PAD200 |
" 457 (BC_2, *, controlr, 1)," & |
" 456 (BC_2, P9, input, X)," & -- PAD201 |
" 455 (BC_2, P9, output3, X, 454, 1, PULL1)," & -- PAD201 |
" 454 (BC_2, *, controlr, 1)," & |
" 453 (BC_2, N8, input, X)," & -- PAD202 |
" 452 (BC_2, N8, output3, X, 451, 1, PULL1)," & -- PAD202 |
" 451 (BC_2, *, controlr, 1)," & |
" 450 (BC_2, P8, input, X)," & -- PAD203 |
" 449 (BC_2, P8, output3, X, 448, 1, PULL1)," & -- PAD203 |
" 448 (BC_2, *, controlr, 1)," & |
" 447 (BC_2, IPAD204, input, X)," & |
" 446 (BC_2, IPAD205, input, X)," & |
" 445 (BC_2, V7, input, X)," & -- PAD206 |
" 444 (BC_2, V7, output3, X, 443, 1, PULL1)," & -- PAD206 |
" 443 (BC_2, *, controlr, 1)," & |
" 442 (BC_2, P7, input, X)," & -- PAD207 |
" 441 (BC_2, P7, output3, X, 440, 1, PULL1)," & -- PAD207 |
" 440 (BC_2, *, controlr, 1)," & |
" 439 (BC_2, N7, input, X)," & -- PAD208 |
" 438 (BC_2, N7, output3, X, 437, 1, PULL1)," & -- PAD208 |
" 437 (BC_2, *, controlr, 1)," & |
" 436 (BC_2, U6, input, X)," & -- PAD209 |
" 435 (BC_2, U6, output3, X, 434, 1, PULL1)," & -- PAD209 |
" 434 (BC_2, *, controlr, 1)," & |
" 433 (BC_2, V6, input, X)," & -- PAD210 |
" 432 (BC_2, V6, output3, X, 431, 1, PULL1)," & -- PAD210 |
" 431 (BC_2, *, controlr, 1)," & |
" 430 (BC_2, V5, input, X)," & -- PAD211 |
" 429 (BC_2, V5, output3, X, 428, 1, PULL1)," & -- PAD211 |
" 428 (BC_2, *, controlr, 1)," & |
" 427 (BC_2, *, internal, X)," & -- IPAD212 |
" 426 (BC_2, *, internal, X)," & -- IPAD213 |
" 425 (BC_2, P6, input, X)," & -- PAD214 |
" 424 (BC_2, P6, output3, X, 423, 1, PULL1)," & -- PAD214 |
" 423 (BC_2, *, controlr, 1)," & |
" 422 (BC_2, R6, input, X)," & -- PAD215 |
" 421 (BC_2, R6, output3, X, 420, 1, PULL1)," & -- PAD215 |
" 420 (BC_2, *, controlr, 1)," & |
" 419 (BC_2, *, internal, X)," & -- PAD216.I |
" 418 (BC_2, *, internal, X)," & -- PAD216.O |
" 417 (BC_2, *, internal, 1)," & -- PAD216.T |
" 416 (BC_2, *, internal, X)," & -- PAD217.I |
" 415 (BC_2, *, internal, X)," & -- PAD217.O |
" 414 (BC_2, *, internal, 1)," & -- PAD217.T |
" 413 (BC_2, *, internal, X)," & -- PAD218.I |
" 412 (BC_2, *, internal, X)," & -- PAD218.O |
" 411 (BC_2, *, internal, 1)," & -- PAD218.T |
" 410 (BC_2, *, internal, X)," & -- IPAD219 |
" 409 (BC_2, *, internal, X)," & -- IPAD220 |
" 408 (BC_2, T5, input, X)," & -- PAD221 |
" 407 (BC_2, T5, output3, X, 406, 1, PULL1)," & -- PAD221 |
" 406 (BC_2, *, controlr, 1)," & |
" 405 (BC_2, R5, input, X)," & -- PAD222 |
" 404 (BC_2, R5, output3, X, 403, 1, PULL1)," & -- PAD222 |
" 403 (BC_2, *, controlr, 1)," & |
" 402 (BC_2, U5, input, X)," & -- PAD223 |
" 401 (BC_2, U5, output3, X, 400, 1, PULL1)," & -- PAD223 |
" 400 (BC_2, *, controlr, 1)," & |
" 399 (BC_2, T4, input, X)," & -- PAD224 |
" 398 (BC_2, T4, output3, X, 397, 1, PULL1)," & -- PAD224 |
" 397 (BC_2, *, controlr, 1)," & |
" 396 (BC_2, U4, input, X)," & -- PAD225 |
" 395 (BC_2, U4, output3, X, 394, 1, PULL1)," & -- PAD225 |
" 394 (BC_2, *, controlr, 1)," & |
" 393 (BC_2, IPAD226, input, X)," & |
" 392 (BC_2, IPAD227, input, X)," & |
" 391 (BC_2, T3, input, X)," & -- PAD228 |
" 390 (BC_2, T3, output3, X, 389, 1, PULL1)," & -- PAD228 |
" 389 (BC_2, *, controlr, 1)," & |
" 388 (BC_2, U3, input, X)," & -- PAD229 |
" 387 (BC_2, U3, output3, X, 386, 1, PULL1)," & -- PAD229 |
" 386 (BC_2, *, controlr, 1)," & |
" 385 (BC_2, IPAD230, input, X)," & |
" 384 (BC_2, IPAD231, input, X)," & |
" 383 (BC_2, T1, input, X)," & -- PAD232 |
" 382 (BC_2, T1, output3, X, 381, 1, PULL1)," & -- PAD232 |
" 381 (BC_2, *, controlr, 1)," & |
" 380 (BC_2, T2, input, X)," & -- PAD233 |
" 379 (BC_2, T2, output3, X, 378, 1, PULL1)," & -- PAD233 |
" 378 (BC_2, *, controlr, 1)," & |
" 377 (BC_2, R2, input, X)," & -- PAD234 |
" 376 (BC_2, R2, output3, X, 375, 1, PULL1)," & -- PAD234 |
" 375 (BC_2, *, controlr, 1)," & |
" 374 (BC_2, R3, input, X)," & -- PAD235 |
" 373 (BC_2, R3, output3, X, 372, 1, PULL1)," & -- PAD235 |
" 372 (BC_2, *, controlr, 1)," & |
" 371 (BC_2, *, internal, X)," & -- PAD236.I |
" 370 (BC_2, *, internal, X)," & -- PAD236.O |
" 369 (BC_2, *, internal, 1)," & -- PAD236.T |
" 368 (BC_2, *, internal, X)," & -- PAD237.I |
" 367 (BC_2, *, internal, X)," & -- PAD237.O |
" 366 (BC_2, *, internal, 1)," & -- PAD237.T |
" 365 (BC_2, IPAD238, input, X)," & |
" 364 (BC_2, *, internal, X)," & -- PAD239.I |
" 363 (BC_2, *, internal, X)," & -- PAD239.O |
" 362 (BC_2, *, internal, 1)," & -- PAD239.T |
" 361 (BC_2, *, internal, X)," & -- PAD240.I |
" 360 (BC_2, *, internal, X)," & -- PAD240.O |
" 359 (BC_2, *, internal, 1)," & -- PAD240.T |
" 358 (BC_2, P4, input, X)," & -- PAD241 |
" 357 (BC_2, P4, output3, X, 356, 1, PULL1)," & -- PAD241 |
" 356 (BC_2, *, controlr, 1)," & |
" 355 (BC_2, P3, input, X)," & -- PAD242 |
" 354 (BC_2, P3, output3, X, 353, 1, PULL1)," & -- PAD242 |
" 353 (BC_2, *, controlr, 1)," & |
" 352 (BC_2, IPAD243, input, X)," & |
" 351 (BC_2, P1, input, X)," & -- PAD244 |
" 350 (BC_2, P1, output3, X, 349, 1, PULL1)," & -- PAD244 |
" 349 (BC_2, *, controlr, 1)," & |
" 348 (BC_2, P2, input, X)," & -- PAD245 |
" 347 (BC_2, P2, output3, X, 346, 1, PULL1)," & -- PAD245 |
" 346 (BC_2, *, controlr, 1)," & |
" 345 (BC_2, *, internal, X)," & -- PAD246.I |
" 344 (BC_2, *, internal, X)," & -- PAD246.O |
" 343 (BC_2, *, internal, 1)," & -- PAD246.T |
" 342 (BC_2, *, internal, X)," & -- PAD247.I |
" 341 (BC_2, *, internal, X)," & -- PAD247.O |
" 340 (BC_2, *, internal, 1)," & -- PAD247.T |
" 339 (BC_2, IPAD248, input, X)," & |
" 338 (BC_2, N5, input, X)," & -- PAD249 |
" 337 (BC_2, N5, output3, X, 336, 1, PULL1)," & -- PAD249 |
" 336 (BC_2, *, controlr, 1)," & |
" 335 (BC_2, N4, input, X)," & -- PAD250 |
" 334 (BC_2, N4, output3, X, 333, 1, PULL1)," & -- PAD250 |
" 333 (BC_2, *, controlr, 1)," & |
" 332 (BC_2, M6, input, X)," & -- PAD251 |
" 331 (BC_2, M6, output3, X, 330, 1, PULL1)," & -- PAD251 |
" 330 (BC_2, *, controlr, 1)," & |
" 329 (BC_2, M5, input, X)," & -- PAD252 |
" 328 (BC_2, M5, output3, X, 327, 1, PULL1)," & -- PAD252 |
" 327 (BC_2, *, controlr, 1)," & |
" 326 (BC_2, IPAD253, input, X)," & |
" 325 (BC_2, M3, input, X)," & -- PAD254 |
" 324 (BC_2, M3, output3, X, 323, 1, PULL1)," & -- PAD254 |
" 323 (BC_2, *, controlr, 1)," & |
" 322 (BC_2, M4, input, X)," & -- PAD255 |
" 321 (BC_2, M4, output3, X, 320, 1, PULL1)," & -- PAD255 |
" 320 (BC_2, *, controlr, 1)," & |
" 319 (BC_2, L5, input, X)," & -- PAD256 |
" 318 (BC_2, L5, output3, X, 317, 1, PULL1)," & -- PAD256 |
" 317 (BC_2, *, controlr, 1)," & |
" 316 (BC_2, L6, input, X)," & -- PAD257 |
" 315 (BC_2, L6, output3, X, 314, 1, PULL1)," & -- PAD257 |
" 314 (BC_2, *, controlr, 1)," & |
" 313 (BC_2, IPAD258, input, X)," & |
" 312 (BC_2, L4, input, X)," & -- PAD259 |
" 311 (BC_2, L4, output3, X, 310, 1, PULL1)," & -- PAD259 |
" 310 (BC_2, *, controlr, 1)," & |
" 309 (BC_2, L3, input, X)," & -- PAD260 |
" 308 (BC_2, L3, output3, X, 307, 1, PULL1)," & -- PAD260 |
" 307 (BC_2, *, controlr, 1)," & |
" 306 (BC_2, L2, input, X)," & -- PAD261 |
" 305 (BC_2, L2, output3, X, 304, 1, PULL1)," & -- PAD261 |
" 304 (BC_2, *, controlr, 1)," & |
" 303 (BC_2, L1, input, X)," & -- PAD262 |
" 302 (BC_2, L1, output3, X, 301, 1, PULL1)," & -- PAD262 |
" 301 (BC_2, *, controlr, 1)," & |
" 300 (BC_2, IPAD263, input, X)," & |
" 299 (BC_2, K5, input, X)," & -- PAD264 |
" 298 (BC_2, K5, output3, X, 297, 1, PULL1)," & -- PAD264 |
" 297 (BC_2, *, controlr, 1)," & |
" 296 (BC_2, K6, input, X)," & -- PAD265 |
" 295 (BC_2, K6, output3, X, 294, 1, PULL1)," & -- PAD265 |
" 294 (BC_2, *, controlr, 1)," & |
" 293 (BC_2, K4, input, X)," & -- PAD266 |
" 292 (BC_2, K4, output3, X, 291, 1, PULL1)," & -- PAD266 |
" 291 (BC_2, *, controlr, 1)," & |
" 290 (BC_2, K3, input, X)," & -- PAD267 |
" 289 (BC_2, K3, output3, X, 288, 1, PULL1)," & -- PAD267 |
" 288 (BC_2, *, controlr, 1)," & |
" 287 (BC_2, IPAD268, input, X)," & |
" 286 (BC_2, J2, input, X)," & -- PAD269 |
" 285 (BC_2, J2, output3, X, 284, 1, PULL1)," & -- PAD269 |
" 284 (BC_2, *, controlr, 1)," & |
" 283 (BC_2, J1, input, X)," & -- PAD270 |
" 282 (BC_2, J1, output3, X, 281, 1, PULL1)," & -- PAD270 |
" 281 (BC_2, *, controlr, 1)," & |
" 280 (BC_2, J4, input, X)," & -- PAD271 |
" 279 (BC_2, J4, output3, X, 278, 1, PULL1)," & -- PAD271 |
" 278 (BC_2, *, controlr, 1)," & |
" 277 (BC_2, J5, input, X)," & -- PAD272 |
" 276 (BC_2, J5, output3, X, 275, 1, PULL1)," & -- PAD272 |
" 275 (BC_2, *, controlr, 1)," & |
" 274 (BC_2, IPAD273, input, X)," & |
" 273 (BC_2, H1, input, X)," & -- PAD274 |
" 272 (BC_2, H1, output3, X, 271, 1, PULL1)," & -- PAD274 |
" 271 (BC_2, *, controlr, 1)," & |
" 270 (BC_2, H2, input, X)," & -- PAD275 |
" 269 (BC_2, H2, output3, X, 268, 1, PULL1)," & -- PAD275 |
" 268 (BC_2, *, controlr, 1)," & |
" 267 (BC_2, H3, input, X)," & -- PAD276 |
" 266 (BC_2, H3, output3, X, 265, 1, PULL1)," & -- PAD276 |
" 265 (BC_2, *, controlr, 1)," & |
" 264 (BC_2, H4, input, X)," & -- PAD277 |
" 263 (BC_2, H4, output3, X, 262, 1, PULL1)," & -- PAD277 |
" 262 (BC_2, *, controlr, 1)," & |
" 261 (BC_2, IPAD278, input, X)," & |
" 260 (BC_2, H5, input, X)," & -- PAD279 |
" 259 (BC_2, H5, output3, X, 258, 1, PULL1)," & -- PAD279 |
" 258 (BC_2, *, controlr, 1)," & |
" 257 (BC_2, H6, input, X)," & -- PAD280 |
" 256 (BC_2, H6, output3, X, 255, 1, PULL1)," & -- PAD280 |
" 255 (BC_2, *, controlr, 1)," & |
" 254 (BC_2, G5, input, X)," & -- PAD281 |
" 253 (BC_2, G5, output3, X, 252, 1, PULL1)," & -- PAD281 |
" 252 (BC_2, *, controlr, 1)," & |
" 251 (BC_2, G6, input, X)," & -- PAD282 |
" 250 (BC_2, G6, output3, X, 249, 1, PULL1)," & -- PAD282 |
" 249 (BC_2, *, controlr, 1)," & |
" 248 (BC_2, IPAD283, input, X)," & |
" 247 (BC_2, G4, input, X)," & -- PAD284 |
" 246 (BC_2, G4, output3, X, 245, 1, PULL1)," & -- PAD284 |
" 245 (BC_2, *, controlr, 1)," & |
" 244 (BC_2, G3, input, X)," & -- PAD285 |
" 243 (BC_2, G3, output3, X, 242, 1, PULL1)," & -- PAD285 |
" 242 (BC_2, *, controlr, 1)," & |
" 241 (BC_2, F2, input, X)," & -- PAD286 |
" 240 (BC_2, F2, output3, X, 239, 1, PULL1)," & -- PAD286 |
" 239 (BC_2, *, controlr, 1)," & |
" 238 (BC_2, F1, input, X)," & -- PAD287 |
" 237 (BC_2, F1, output3, X, 236, 1, PULL1)," & -- PAD287 |
" 236 (BC_2, *, controlr, 1)," & |
" 235 (BC_2, IPAD288, input, X)," & |
" 234 (BC_2, *, internal, X)," & -- PAD289.I |
" 233 (BC_2, *, internal, X)," & -- PAD289.O |
" 232 (BC_2, *, internal, 1)," & -- PAD289.T |
" 231 (BC_2, *, internal, X)," & -- PAD290.I |
" 230 (BC_2, *, internal, X)," & -- PAD290.O |
" 229 (BC_2, *, internal, 1)," & -- PAD290.T |
" 228 (BC_2, E3, input, X)," & -- PAD291 |
" 227 (BC_2, E3, output3, X, 226, 1, PULL1)," & -- PAD291 |
" 226 (BC_2, *, controlr, 1)," & |
" 225 (BC_2, E4, input, X)," & -- PAD292 |
" 224 (BC_2, E4, output3, X, 223, 1, PULL1)," & -- PAD292 |
" 223 (BC_2, *, controlr, 1)," & |
" 222 (BC_2, IPAD293, input, X)," & |
" 221 (BC_2, *, internal, X)," & -- PAD294.I |
" 220 (BC_2, *, internal, X)," & -- PAD294.O |
" 219 (BC_2, *, internal, 1)," & -- PAD294.T |
" 218 (BC_2, *, internal, X)," & -- PAD295.I |
" 217 (BC_2, *, internal, X)," & -- PAD295.O |
" 216 (BC_2, *, internal, 1)," & -- PAD295.T |
" 215 (BC_2, E1, input, X)," & -- PAD296 |
" 214 (BC_2, E1, output3, X, 213, 1, PULL1)," & -- PAD296 |
" 213 (BC_2, *, controlr, 1)," & |
" 212 (BC_2, E2, input, X)," & -- PAD297 |
" 211 (BC_2, E2, output3, X, 210, 1, PULL1)," & -- PAD297 |
" 210 (BC_2, *, controlr, 1)," & |
" 209 (BC_2, D4, input, X)," & -- PAD298 |
" 208 (BC_2, D4, output3, X, 207, 1, PULL1)," & -- PAD298 |
" 207 (BC_2, *, controlr, 1)," & |
" 206 (BC_2, *, internal, X)," & -- PAD299.I |
" 205 (BC_2, *, internal, X)," & -- PAD299.O |
" 204 (BC_2, *, internal, 1)," & -- PAD299.T |
" 203 (BC_2, IPAD300, input, X)," & |
" 202 (BC_2, D2, input, X)," & -- PAD301 |
" 201 (BC_2, D2, output3, X, 200, 1, PULL1)," & -- PAD301 |
" 200 (BC_2, *, controlr, 1)," & |
" 199 (BC_2, D1, input, X)," & -- PAD302 |
" 198 (BC_2, D1, output3, X, 197, 1, PULL1)," & -- PAD302 |
" 197 (BC_2, *, controlr, 1)," & |
" 196 (BC_2, C2, input, X)," & -- PAD303 |
" 195 (BC_2, C2, output3, X, 194, 1, PULL1)," & -- PAD303 |
" 194 (BC_2, *, controlr, 1)," & |
" 193 (BC_2, C1, input, X)," & -- PAD304 |
" 192 (BC_2, C1, output3, X, 191, 1, PULL1)," & -- PAD304 |
" 191 (BC_2, *, controlr, 1)," & |
" 190 (BC_2, *, internal, 1)," & -- PROG_B |
" 189 (BC_2, *, internal, 1)," & -- PUDC_B |
" 188 (BC_2, *, internal, 1)," & -- PUDC_B |
" 187 (BC_2, *, internal, 1)," & -- PUDC_B |
" 186 (BC_2, C3, input, X)," & -- PAD2 |
" 185 (BC_2, C3, output3, X, 184, 1, PULL1)," & -- PAD2 |
" 184 (BC_2, *, controlr, 1)," & |
" 183 (BC_2, IPAD3, input, X)," & |
" 182 (BC_2, B4, input, X)," & -- PAD4 |
" 181 (BC_2, B4, output3, X, 180, 1, PULL1)," & -- PAD4 |
" 180 (BC_2, *, controlr, 1)," & |
" 179 (BC_2, A4, input, X)," & -- PAD5 |
" 178 (BC_2, A4, output3, X, 177, 1, PULL1)," & -- PAD5 |
" 177 (BC_2, *, controlr, 1)," & |
" 176 (BC_2, C4, input, X)," & -- PAD6 |
" 175 (BC_2, C4, output3, X, 174, 1, PULL1)," & -- PAD6 |
" 174 (BC_2, *, controlr, 1)," & |
" 173 (BC_2, D5, input, X)," & -- PAD7 |
" 172 (BC_2, D5, output3, X, 171, 1, PULL1)," & -- PAD7 |
" 171 (BC_2, *, controlr, 1)," & |
" 170 (BC_2, C5, input, X)," & -- PAD8 |
" 169 (BC_2, C5, output3, X, 168, 1, PULL1)," & -- PAD8 |
" 168 (BC_2, *, controlr, 1)," & |
" 167 (BC_2, IPAD9, input, X)," & |
" 166 (BC_2, IPAD10, input, X)," & |
" 165 (BC_2, E6, input, X)," & -- PAD11 |
" 164 (BC_2, E6, output3, X, 163, 1, PULL1)," & -- PAD11 |
" 163 (BC_2, *, controlr, 1)," & |
" 162 (BC_2, D6, input, X)," & -- PAD12 |
" 161 (BC_2, D6, output3, X, 160, 1, PULL1)," & -- PAD12 |
" 160 (BC_2, *, controlr, 1)," & |
" 159 (BC_2, *, internal, X)," & -- PAD13.I |
" 158 (BC_2, *, internal, X)," & -- PAD13.O |
" 157 (BC_2, *, internal, 1)," & -- PAD13.T |
" 156 (BC_2, A6, input, X)," & -- PAD14 |
" 155 (BC_2, A6, output3, X, 154, 1, PULL1)," & -- PAD14 |
" 154 (BC_2, *, controlr, 1)," & |
" 153 (BC_2, B6, input, X)," & -- PAD15 |
" 152 (BC_2, B6, output3, X, 151, 1, PULL1)," & -- PAD15 |
" 151 (BC_2, *, controlr, 1)," & |
" 150 (BC_2, *, internal, X)," & -- IPAD16 |
" 149 (BC_2, *, internal, X)," & -- IPAD17 |
" 148 (BC_2, *, internal, X)," & -- PAD18.I |
" 147 (BC_2, *, internal, X)," & -- PAD18.O |
" 146 (BC_2, *, internal, 1)," & -- PAD18.T |
" 145 (BC_2, *, internal, X)," & -- PAD19.I |
" 144 (BC_2, *, internal, X)," & -- PAD19.O |
" 143 (BC_2, *, internal, 1)," & -- PAD19.T |
" 142 (BC_2, A7, input, X)," & -- PAD20 |
" 141 (BC_2, A7, output3, X, 140, 1, PULL1)," & -- PAD20 |
" 140 (BC_2, *, controlr, 1)," & |
" 139 (BC_2, E7, input, X)," & -- PAD21 |
" 138 (BC_2, E7, output3, X, 137, 1, PULL1)," & -- PAD21 |
" 137 (BC_2, *, controlr, 1)," & |
" 136 (BC_2, F7, input, X)," & -- PAD22 |
" 135 (BC_2, F7, output3, X, 134, 1, PULL1)," & -- PAD22 |
" 134 (BC_2, *, controlr, 1)," & |
" 133 (BC_2, *, internal, X)," & -- IPAD23 |
" 132 (BC_2, *, internal, X)," & -- IPAD24 |
" 131 (BC_2, *, internal, X)," & -- PAD25.I |
" 130 (BC_2, *, internal, X)," & -- PAD25.O |
" 129 (BC_2, *, internal, 1)," & -- PAD25.T |
" 128 (BC_2, D7, input, X)," & -- PAD26 |
" 127 (BC_2, D7, output3, X, 126, 1, PULL1)," & -- PAD26 |
" 126 (BC_2, *, controlr, 1)," & |
" 125 (BC_2, C7, input, X)," & -- PAD27 |
" 124 (BC_2, C7, output3, X, 123, 1, PULL1)," & -- PAD27 |
" 123 (BC_2, *, controlr, 1)," & |
" 122 (BC_2, A8, input, X)," & -- PAD28 |
" 121 (BC_2, A8, output3, X, 120, 1, PULL1)," & -- PAD28 |
" 120 (BC_2, *, controlr, 1)," & |
" 119 (BC_2, F8, input, X)," & -- PAD29 |
" 118 (BC_2, F8, output3, X, 117, 1, PULL1)," & -- PAD29 |
" 117 (BC_2, *, controlr, 1)," & |
" 116 (BC_2, E8, input, X)," & -- PAD30 |
" 115 (BC_2, E8, output3, X, 114, 1, PULL1)," & -- PAD30 |
" 114 (BC_2, *, controlr, 1)," & |
" 113 (BC_2, IPAD31, input, X)," & |
" 112 (BC_2, IPAD32, input, X)," & |
" 111 (BC_2, F9, input, X)," & -- PAD33 |
" 110 (BC_2, F9, output3, X, 109, 1, PULL1)," & -- PAD33 |
" 109 (BC_2, *, controlr, 1)," & |
" 108 (BC_2, E9, input, X)," & -- PAD34 |
" 107 (BC_2, E9, output3, X, 106, 1, PULL1)," & -- PAD34 |
" 106 (BC_2, *, controlr, 1)," & |
" 105 (BC_2, G9, input, X)," & -- PAD35 |
" 104 (BC_2, G9, output3, X, 103, 1, PULL1)," & -- PAD35 |
" 103 (BC_2, *, controlr, 1)," & |
" 102 (BC_2, D9, input, X)," & -- PAD36 |
" 101 (BC_2, D9, output3, X, 100, 1, PULL1)," & -- PAD36 |
" 100 (BC_2, *, controlr, 1)," & |
" 99 (BC_2, C9, input, X)," & -- PAD37 |
" 98 (BC_2, C9, output3, X, 97, 1, PULL1)," & -- PAD37 |
" 97 (BC_2, *, controlr, 1)," & |
" 96 (BC_2, IPAD38, input, X)," & |
" 95 (BC_2, IPAD39, input, X)," & |
" 94 (BC_2, A10, input, X)," & -- PAD40 |
" 93 (BC_2, A10, output3, X, 92, 1, PULL1)," & -- PAD40 |
" 92 (BC_2, *, controlr, 1)," & |
" 91 (BC_2, B10, input, X)," & -- PAD41 |
" 90 (BC_2, B10, output3, X, 89, 1, PULL1)," & -- PAD41 |
" 89 (BC_2, *, controlr, 1)," & |
" 88 (BC_2, B11, input, X)," & -- PAD42 |
" 87 (BC_2, B11, output3, X, 86, 1, PULL1)," & -- PAD42 |
" 86 (BC_2, *, controlr, 1)," & |
" 85 (BC_2, E10, input, X)," & -- PAD43 |
" 84 (BC_2, E10, output3, X, 83, 1, PULL1)," & -- PAD43 |
" 83 (BC_2, *, controlr, 1)," & |
" 82 (BC_2, D10, input, X)," & -- PAD44 |
" 81 (BC_2, D10, output3, X, 80, 1, PULL1)," & -- PAD44 |
" 80 (BC_2, *, controlr, 1)," & |
" 79 (BC_2, IPAD45, input, X)," & |
" 78 (BC_2, IPAD46, input, X)," & |
" 77 (BC_2, D11, input, X)," & -- PAD47 |
" 76 (BC_2, D11, output3, X, 75, 1, PULL1)," & -- PAD47 |
" 75 (BC_2, *, controlr, 1)," & |
" 74 (BC_2, C11, input, X)," & -- PAD48 |
" 73 (BC_2, C11, output3, X, 72, 1, PULL1)," & -- PAD48 |
" 72 (BC_2, *, controlr, 1)," & |
" 71 (BC_2, A11, input, X)," & -- PAD49 |
" 70 (BC_2, A11, output3, X, 69, 1, PULL1)," & -- PAD49 |
" 69 (BC_2, *, controlr, 1)," & |
" 68 (BC_2, F11, input, X)," & -- PAD50 |
" 67 (BC_2, F11, output3, X, 66, 1, PULL1)," & -- PAD50 |
" 66 (BC_2, *, controlr, 1)," & |
" 65 (BC_2, E11, input, X)," & -- PAD51 |
" 64 (BC_2, E11, output3, X, 63, 1, PULL1)," & -- PAD51 |
" 63 (BC_2, *, controlr, 1)," & |
" 62 (BC_2, IPAD52, input, X)," & |
" 61 (BC_2, IPAD53, input, X)," & |
" 60 (BC_2, A12, input, X)," & -- PAD54 |
" 59 (BC_2, A12, output3, X, 58, 1, PULL1)," & -- PAD54 |
" 58 (BC_2, *, controlr, 1)," & |
" 57 (BC_2, E12, input, X)," & -- PAD55 |
" 56 (BC_2, E12, output3, X, 55, 1, PULL1)," & -- PAD55 |
" 55 (BC_2, *, controlr, 1)," & |
" 54 (BC_2, F12, input, X)," & -- PAD56 |
" 53 (BC_2, F12, output3, X, 52, 1, PULL1)," & -- PAD56 |
" 52 (BC_2, *, controlr, 1)," & |
" 51 (BC_2, D13, input, X)," & -- PAD57 |
" 50 (BC_2, D13, output3, X, 49, 1, PULL1)," & -- PAD57 |
" 49 (BC_2, *, controlr, 1)," & |
" 48 (BC_2, B13, input, X)," & -- PAD58 |
" 47 (BC_2, B13, output3, X, 46, 1, PULL1)," & -- PAD58 |
" 46 (BC_2, *, controlr, 1)," & |
" 45 (BC_2, A13, input, X)," & -- PAD59 |
" 44 (BC_2, A13, output3, X, 43, 1, PULL1)," & -- PAD59 |
" 43 (BC_2, *, controlr, 1)," & |
" 42 (BC_2, *, internal, X)," & -- IPAD60 |
" 41 (BC_2, *, internal, X)," & -- IPAD61 |
" 40 (BC_2, A14, input, X)," & -- PAD62 |
" 39 (BC_2, A14, output3, X, 38, 1, PULL1)," & -- PAD62 |
" 38 (BC_2, *, controlr, 1)," & |
" 37 (BC_2, B14, input, X)," & -- PAD63 |
" 36 (BC_2, B14, output3, X, 35, 1, PULL1)," & -- PAD63 |
" 35 (BC_2, *, controlr, 1)," & |
" 34 (BC_2, *, internal, X)," & -- PAD64.I |
" 33 (BC_2, *, internal, X)," & -- PAD64.O |
" 32 (BC_2, *, internal, 1)," & -- PAD64.T |
" 31 (BC_2, *, internal, X)," & -- PAD65.I |
" 30 (BC_2, *, internal, X)," & -- PAD65.O |
" 29 (BC_2, *, internal, 1)," & -- PAD65.T |
" 28 (BC_2, *, internal, X)," & -- PAD66.I |
" 27 (BC_2, *, internal, X)," & -- PAD66.O |
" 26 (BC_2, *, internal, 1)," & -- PAD66.T |
" 25 (BC_2, *, internal, X)," & -- IPAD67 |
" 24 (BC_2, *, internal, X)," & -- IPAD68 |
" 23 (BC_2, *, internal, X)," & -- PAD69.I |
" 22 (BC_2, *, internal, X)," & -- PAD69.O |
" 21 (BC_2, *, internal, 1)," & -- PAD69.T |
" 20 (BC_2, *, internal, X)," & -- PAD70.I |
" 19 (BC_2, *, internal, X)," & -- PAD70.O |
" 18 (BC_2, *, internal, 1)," & -- PAD70.T |
" 17 (BC_2, E13, input, X)," & -- PAD71 |
" 16 (BC_2, E13, output3, X, 15, 1, PULL1)," & -- PAD71 |
" 15 (BC_2, *, controlr, 1)," & |
" 14 (BC_2, C14, input, X)," & -- PAD72 |
" 13 (BC_2, C14, output3, X, 12, 1, PULL1)," & -- PAD72 |
" 12 (BC_2, *, controlr, 1)," & |
" 11 (BC_2, D14, input, X)," & -- PAD73 |
" 10 (BC_2, D14, output3, X, 9, 1, PULL1)," & -- PAD73 |
" 9 (BC_2, *, controlr, 1)," & |
" 8 (BC_2, IPAD74, input, X)," & |
" 7 (BC_2, IPAD75, input, X)," & |
" 6 (BC_2, A16, input, X)," & -- PAD76 |
" 5 (BC_2, A16, output3, X, 4, 1, PULL1)," & -- PAD76 |
" 4 (BC_2, *, controlr, 1)," & |
" 3 (BC_2, B16, input, X)," & -- PAD77 |
" 2 (BC_2, B16, output3, X, 1, 1, PULL1)," & -- PAD77 |
" 1 (BC_2, *, controlr, 1)," & |
" 0 (BC_2, IPAD78, input, X)"; |
|
|
attribute ISC_PIN_BEHAVIOR of XC3S1200E_FG320 : entity is |
"HIGHZ" ; -- clamp behavior |
-- no status |
|
attribute ISC_STATUS of XC3S1200E_FG320 : entity is |
"NOT IMPLEMENTED" ; |
|
attribute ISC_BLANK_USERCODE of XC3S1200E_FG320 : entity is |
"00000000000000000000000000000000"; |
|
attribute ISC_FLOW of XC3S1200E_FG320 : entity is |
-- Enable program |
"flow_enable " & |
"initialize " & |
" (ISC_ENABLE 5:00 wait TCK 16)," & |
|
"flow_disable " & |
"initialize " & |
" (ISC_DISABLE wait TCK 16)" & |
" (BYPASS 1:0 wait TCK 1)," & |
|
"flow_program(array) " & |
"Repeat 239922 " & |
" (ISC_PROGRAM 16:? wait TCK 1 )," & |
|
"flow_program(legacy) " & |
"Initialize " & |
" (JSHUTDOWN wait TCK 16)" & |
" (CFG_IN 3838752:? wait TCK 1)" & |
" (JSTART wait TCK 32)" & |
" (BYPASS 1:0 wait TCK 1)," & |
|
"flow_verify(idcode) " & |
"initialize " & |
" (IDCODE wait TCK 1 32:01C2E093*0FFFFFFF)," & |
|
"flow_read(usercode) " & |
"initialize " & |
" (USERCODE wait TCK 1 32:!)," & |
|
"flow_read(idcode) " & |
"initialize " & |
" (IDCODE wait TCK 1 32:!)," & |
|
"flow_program_done " & |
"initialize " & |
" (BYPASS wait TCK 1)," & |
|
"flow_error_exit " & |
"initialize " & |
" (BYPASS wait TCK 1)"; |
|
attribute ISC_PROCEDURE of XC3S1200E_FG320 : entity is |
"proc_enable = (flow_enable)," & |
"proc_disable = (flow_disable)," & |
"proc_program = (flow_program(array))," & |
"proc_program(legacy) = (flow_program(legacy))," & |
"proc_verify(idcode) = (flow_verify(idcode))," & |
"proc_read(idcode) = (flow_read(idcode))," & |
"proc_read(usercode) = (flow_read(usercode))," & |
"proc_program_done = (flow_program_done)," & |
"proc_error_exit = (flow_error_exit)"; |
|
attribute ISC_ACTION of XC3S1200E_FG320 : entity is |
"program = (proc_verify(idcode) recommended," & |
" proc_enable, proc_program," & |
" proc_disable)," & |
"program(lgcy) = (proc_verify(idcode) recommended," & |
" proc_enable, proc_program(legacy)," & |
" proc_disable)," & |
"verify(idcode) = (proc_verify(idcode))," & |
"read(idcode) = (proc_read(idcode))," & |
"read(usercode) = (proc_read(usercode))"; |
|
-- Design Warning Section |
|
attribute DESIGN_WARNING of XC3S1200E_FG320 : entity is |
"This is a preliminary BSDL file which has not been verified." & |
"This BSDL file must be modified by the FPGA designer in order to" & |
"reflect post-configuration behavior (if any)." & |
"To avoid losing the current configuration, the PROG_B should be" & |
"kept high. If the PROG_B pin goes low by any means," & |
"the configuration will be cleared." & |
"PROG_B can only be captured, not updated." & |
"The value at the pin is always used by the device." & |
"PUDC_B can be captured and updated." & |
"The value at the pin is always used by the device" & |
"before configuration is done." & |
"During pre-configuration, the disable result of a 3-stated" & |
"I/O in this file corresponds to PUDC_B being low" & |
"or during EXTEST instruction." & |
"When PUDC_B is high AND during SAMPLE instruction, change" & |
"all PULL1s to PULL0s." & |
"After configuration, the disable result only depends on" & |
"the individual IO configuration setting." & |
"In EXTEST, output and tristate values are not captured in the" & |
"Capture-DR state - those register cells are unchanged." & |
"In INTEST, the pin input values are not captured in the" & |
"Capture-DR state - those register cells are unchanged." & |
"The output and tristate capture values are not valid until after" & |
"the device is configured." & |
"The tristate control value is not captured properly when" & |
"GTS is activated."; |
|
end XC3S1200E_FG320; |
|
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/debug/impact_bat
0,0 → 1,6
setMode -bs |
setCable -port svf -file ../debug/bitstream.svf |
addDevice -p 1 -file Board_Design_jtag.bit |
program -p 1 |
closeCable |
quit |
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/debug/fpga_load
0,0 → 1,6
bsdl path ../bsdl;../target/bsdl; |
cable usbblaster |
detect |
part 1 |
svf bitstream.svf |
|
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/filelist
0,0 → 1,28
verilog work ./target/Pad_Ring.v |
|
|
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v |
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v |
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v |
|
|
|
verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v |
verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v |
verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v |
verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v |
|
|
verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v |
verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v |
verilog work ./target/lib/syn/cde_jtag/cde_jtag.v |
verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v |
verilog work ./target/lib/syn/cde_sram/cde_sram.v |
verilog work ./target/lib/syn/cde_fifo/cde_fifo.v |
verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v |
verilog work ./target/lib/syn/cde_divider/cde_divider.v |
verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v |
verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v |
|
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/core.v
0,0 → 1,157
|
|
|
|
|
|
// Declare I/O Port connections |
|
|
wire clk = ck25MHz; |
|
wire [7:0] rx_data; |
wire read; |
|
|
|
|
wire sync; |
wire rd; |
wire wr; |
|
wire [7:0] write_data; |
wire [15:0] addr_pin; |
|
|
|
wire [7:0] data; |
wire baud_clk; |
|
|
|
wire [7:0] gpio_0_out; |
wire [7:0] gpio_1_out; |
|
|
assign rs_tx_pad_out = rs_rx_pad_in; |
|
|
|
|
assign jtag_user1_cap = jtag_user1_upd; |
assign jtag_user2_cap = addr_pin; |
|
assign PosD = {gpio_0_out,gpio_1_out}; |
assign PosL = 8'h12; |
|
|
|
assign ja_1_pad_out = 1'b0; |
assign ja_2_pad_out = reset; |
assign ja_3_pad_out = one_usec; |
assign ja_4_pad_out = 1'b0 ; |
|
assign ja_7_pad_out = 1'b0; |
assign ja_8_pad_out = 1'b0; |
assign ja_9_pad_out = 1'b0; |
assign ja_10_pad_out = 1'b0; |
|
|
|
assign jb_1_pad_out = 1'b0; |
assign jb_2_pad_out = 1'b0; |
assign jb_3_pad_out = 1'b0; |
assign jb_4_pad_out = 1'b0; |
|
|
assign jb_7_pad_out = 1'b0; |
assign jb_8_pad_out = 1'b0; |
assign jb_9_pad_out = 1'b0; |
assign jb_10_pad_out = 1'b0; |
|
|
assign jc_1_pad_out = 1'b1; |
assign jc_2_pad_out = 1'b0; |
assign jc_3_pad_out = 1'b1; |
assign jc_4_pad_out = 1'b0; |
|
assign jc_7_pad_out = 1'b1; |
assign jc_8_pad_out = 1'b0; |
assign jc_9_pad_out = 1'b1; |
assign jc_10_pad_out = 1'b0; |
|
|
|
|
|
wire [9:0] xpos; |
|
|
|
|
|
|
|
|
|
|
|
T6502 #( |
.ROM_WORDS (`ROM_WORDS), |
.ROM_ADD (`ROM_ADD), |
.RAM_WORDS (4096), |
.ROM_FILE (`ROM_FILE), |
.STARTUP (`STARTUP), |
.FONT (`FONT) |
) |
cpu ( |
.clk ( ck25MHz ), |
.reset ( reset ), |
.addr_pin ( addr_pin ), |
|
|
.ext_irq_in ( 4'h0 ), |
|
.gpio_0_out ( gpio_0_out ), |
.gpio_0_in ( 8'h00 ), |
.gpio_0_oe ( ), |
.gpio_0_lat ( ), |
|
.gpio_1_out ( gpio_1_out ), |
.gpio_1_in ( 8'h00 ), |
.gpio_1_oe ( ), |
.gpio_1_lat ( ), |
|
|
.ps2_data_oe ( ps2_data_pad_oe ), |
.ps2_data_in ( ps2_data_pad_in ), |
.ps2_clk_oe ( ps2_clk_pad_oe ), |
.ps2_clk_in ( ps2_clk_pad_in ), |
|
|
|
.txd_pad_out ( txd_pad_out ), |
.rxd_pad_in ( rxd_pad_in ), |
.cts_pad_in ( cts_pad_in ), |
.rts_pad_out ( rts_pad_out ), |
|
.vgared_pad_out ( vgared_pad_out[2:0] ), |
.vgagreen_pad_out ( vgagreen_pad_out[2:0] ), |
.vgablue_pad_out ( vgablue_pad_out[1:0] ), |
|
.hsync_n_pad_out ( hsync_pad_out ), |
.vsync_n_pad_out ( vsync_pad_out ) |
|
|
|
|
); |
|
|
|
|
|
|
|
|
|
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/Makefile
0,0 → 1,4
include ../../../../bin/Makefile.root |
include ./target/Makefile.brd |
Design=T6502_io_poll |
|
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/def_file
0,0 → 1,18
`define SYNTHESIS |
`define ROM_FILE "../../../../../../../projects/Mos6502/sw/io_poll/io_poll.abs" |
`define ROM_WORDS 2048 |
`define ROM_ADD 11 |
`define MODULE_NAME Nexys2_T6502_io_poll |
|
`define STARTUP "../../../../../../../projects/Mos6502/sw/vga_startup_screen/vga_startup_screen.abs" |
|
`define FONT "../../../../../../../projects/Mos6502/sw/vga_font/vga_font.abs" |
|
|
|
`define JTAG_USER1_WIDTH 8 |
`define JTAG_USER1_RESET 8'h12 |
|
`define JTAG_USER2_WIDTH 16 |
`define JTAG_USER2_RESET 16'h0000 |
|
/socgen/trunk/projects/Mos6502/sw/prog_1_test/prog_1_test.asm
0,0 → 1,78
|
|
cpu 6502 |
output HEX |
|
|
|
io_base = $8000 ; |
|
io_gpio_0 = $02 ; |
io_gpio_1 = $06 ; |
|
io_tim0_start = $10 ; |
io_tim0_count = $12 ; |
io_tim0_end = $14 ; |
|
io_tim1_start = $18 ; |
io_tim1_count = $1A ; |
io_tim1_end = $1C ; |
|
io_uart_xmt = $20 ; |
io_uart_rcv = $22 ; |
io_uart_cnt = $24 ; |
io_uart_stat = $26 ; |
|
|
io_pic_int = $30 ; |
io_pic_irq_en = $32 ; |
io_pic_nmi_en = $34 ; |
io_pic_irq_ac = $36 ; |
io_pic_nmi_ac = $38 ; |
|
io_ps2_data = $40 ; |
io_ps2_stat = $42 ; |
io_ps2_cntrl = $44 ; |
io_ps2_xpos = $46 ; |
io_ps2_ypos = $48 ; |
|
|
io_utim_lat = $50 ; |
io_utim_cnt = $52 ; |
|
io_vga_ascii = $60 ; |
io_vga_addl = $62 ; |
io_vga_addh = $64 ; |
io_vga_cntrl = $66 ; |
|
* = $f000 ; assemble at $f000 |
code |
.start nop |
lda #$01 |
sta io_base+io_gpio_0 |
lda #$02 |
sta io_base+io_gpio_1 |
ldx #$55 |
txa |
pha |
pla |
sta io_base+io_gpio_1 |
.lab_100 jmp .lab_100 |
|
|
|
* = $fffa ; vectors |
|
|
|
dw .start ; |
dw .start ; |
dw .start ; |
|
code |
|
|
|
|
|
|
/socgen/trunk/projects/Mos6502/sw/prog_1_test/Makefile
0,0 → 1,7
include ../../bin/Makefile.root |
code=prog_1_test |
|
all:asm_6502 |
|
|
|
/socgen/trunk/projects/Mos6502/sw/prog_test/prog_test.asm
0,0 → 1,1316
|
|
cpu 6502 |
output HEX |
|
|
|
io_base = $8000 ; |
|
io_gpio_0 = $02 ; |
io_gpio_1 = $06 ; |
|
io_tim0_start = $10 ; |
io_tim0_count = $12 ; |
io_tim0_end = $14 ; |
|
io_tim1_start = $18 ; |
io_tim1_count = $1A ; |
io_tim1_end = $1C ; |
|
io_uart_xmt = $20 ; |
io_uart_rcv = $22 ; |
io_uart_cnt = $24 ; |
io_uart_stat = $26 ; |
|
|
io_pic_int = $30 ; |
io_pic_irq_en = $32 ; |
io_pic_nmi_en = $34 ; |
io_pic_irq_ac = $36 ; |
io_pic_nmi_ac = $38 ; |
|
io_ps2_data = $40 ; |
io_ps2_stat = $42 ; |
io_ps2_cntrl = $44 ; |
io_ps2_xpos = $46 ; |
io_ps2_ypos = $48 ; |
|
|
io_utim_lat = $50 ; |
io_utim_cnt = $52 ; |
|
io_vga_ascii = $60 ; |
io_vga_addl = $62 ; |
io_vga_addh = $64 ; |
io_vga_cntrl = $66 ; |
|
* = $f000 ; assemble at $f000 |
code |
|
.start nop |
lda #$00 |
sta $04 |
sta $05 |
sta $06 |
sta $07 |
lda #$00 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
lda #$01 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
jmp .lab_00 |
lda #$00 |
jmp .lab_100 |
.lab_00 lda #$01 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
lda #$02 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
clc |
bcc .lab_01 |
lda #$01 |
jmp .lab_100 |
.lab_01 lda #$03 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
sec |
bcc .lab_02 |
jmp .lab_025 |
.lab_02 lda #$02 |
jmp .lab_100 |
.lab_025 lda #$04 |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
sec |
bcs .lab_03 |
lda #$01 |
jmp .lab_100 |
|
.lab_03 clc |
bcs .lab_04 |
jmp .lab_045 |
.lab_04 lda #$02 |
jmp .lab_100 |
.lab_045 lda #$05 |
sta io_base+io_gpio_0 |
lda #$05 |
cmp #$04 |
beq .lab_05 |
cmp #$05 |
beq .lab_06 |
.lab_05 lda #$03 |
jmp .lab_100 |
.lab_06 lda #$06 |
sta io_base+io_gpio_0 |
lda #$c4 |
cmp #$e4 |
bne .lab_07 |
lda #$04 |
jmp .lab_100 |
.lab_07 cmp #$C4 |
bne .lab_08 |
jmp .lab_085 |
.lab_08 lda #$05 |
jmp .lab_100 |
.lab_085 lda #$07 |
sta io_base+io_gpio_0 |
ldx #$42 |
cpx #$32 |
beq .lab_09 |
cpx #$42 |
beq .lab_10 |
.lab_09 lda #$06 |
jmp .lab_100 |
.lab_10 lda #$08 |
sta io_base+io_gpio_0 |
ldy #$C3 |
cpy #$D3 |
beq .lab_11 |
cpy #$C3 |
beq .lab_12 |
.lab_11 lda #$07 |
jmp .lab_100 |
.lab_12 lda #$09 |
sta io_base+io_gpio_0 |
ldx #$00 |
dex |
cpx #$FF |
beq .lab_13 |
lda #$08 |
jmp .lab_100 |
.lab_13 lda #$0A |
sta io_base+io_gpio_0 |
ldy #$00 |
dey |
cpy #$FF |
beq .lab_14 |
lda #$09 |
jmp .lab_100 |
.lab_14 lda #$0B |
sta io_base+io_gpio_0 |
ldx #$0F |
inx |
cpx #$10 |
beq .lab_15 |
lda #$10 |
jmp .lab_100 |
.lab_15 lda #$0C |
sta io_base+io_gpio_0 |
ldy #$7F |
iny |
cpy #$80 |
beq .lab_16 |
lda #$11 |
jmp .lab_100 |
.lab_16 lda #$0D |
sta io_base+io_gpio_0 |
lda #$ED |
jsr .lab_165 |
cmp #$42 |
beq .lab_17 |
lda #$12 |
jmp .lab_100 |
.lab_165 lda #$42 |
rts |
.lab_17 lda #$0E |
sta io_base+io_gpio_0 |
lda #$35 |
tax |
cpx #$35 |
beq .lab_18 |
lda #$12 |
jmp .lab_100 |
.lab_18 lda #$0F |
sta io_base+io_gpio_0 |
lda #$76 |
tay |
cpy #$76 |
beq .lab_19 |
lda #$13 |
jmp .lab_100 |
.lab_19 lda #$10 |
sta io_base+io_gpio_0 |
ldx #$52 |
txa |
cmp #$52 |
beq .lab_20 |
lda #$14 |
jmp .lab_100 |
.lab_20 lda #$11 |
sta io_base+io_gpio_0 |
ldy #$52 |
tya |
cmp #$52 |
beq .lab_21 |
lda #$15 |
jmp .lab_100 |
.lab_21 lda #$12 |
sta io_base+io_gpio_0 |
clc |
lda #$23 |
adc #$45 |
cmp #$68 |
beq .lab_22 |
lda #$16 |
jmp .lab_100 |
.lab_22 sec |
lda #$42 |
adc #$63 |
cmp #$A6 |
beq .lab_23 |
lda #$17 |
jmp .lab_100 |
.lab_23 lda #$13 |
sta io_base+io_gpio_0 |
lda #$36 |
and #$f0 |
cmp #$30 |
beq .lab_24 |
lda #$18 |
jmp .lab_100 |
.lab_24 lda #$14 |
sta io_base+io_gpio_0 |
clc |
lda #$36 |
asl a |
cmp #$6C |
beq .lab_25 |
lda #$19 |
jmp .lab_100 |
.lab_25 lda #$15 |
sta io_base+io_gpio_0 |
lda #$89 |
eor #$96 |
cmp #$1F |
beq .lab_26 |
lda #$20 |
jmp .lab_100 |
.lab_26 lda #$16 |
sta io_base+io_gpio_0 |
clc |
lda #$52 |
lsr a |
cmp #$29 |
beq .lab_27 |
lda #$21 |
jmp .lab_100 |
.lab_27 lda #$17 |
sta io_base+io_gpio_0 |
lda #$B6 |
ora #$4D |
cmp #$FF |
beq .lab_28 |
lda #$22 |
jmp .lab_100 |
.lab_28 lda #$18 |
sta io_base+io_gpio_0 |
clc |
lda #$23 |
rol a |
cmp #$46 |
beq .lab_29 |
lda #$23 |
jmp .lab_100 |
.lab_29 sec |
lda #$42 |
rol a |
cmp #$85 |
beq .lab_30 |
lda #$24 |
jmp .lab_100 |
.lab_30 lda #$19 |
sta io_base+io_gpio_0 |
clc |
lda #$23 |
ror a |
cmp #$11 |
beq .lab_31 |
lda #$25 |
jmp .lab_100 |
.lab_31 sec |
lda #$42 |
ror a |
cmp #$A1 |
beq .lab_32 |
lda #$26 |
jmp .lab_100 |
.lab_32 lda #$20 |
sta io_base+io_gpio_0 |
sec |
lda #$86 |
sbc #$45 |
cmp #$41 |
beq .lab_33 |
lda #$27 |
jmp .lab_100 |
.lab_33 clc |
lda #$89 |
sbc #$23 |
cmp #$65 |
beq .lab_34 |
lda #$28 |
jmp .lab_100 |
.lab_34 lda #$21 |
sta io_base+io_gpio_0 |
lda #$42 |
sta $0200 |
lda #$9F |
sta $0201 |
lda $0200 |
cmp #$42 |
beq .lab_35 |
lda #$29 |
jmp .lab_100 |
.lab_35 lda $0201 |
cmp #$9F |
beq .lab_36 |
lda #$30 |
jmp .lab_100 |
.lab_36 lda #$22 |
sta io_base+io_gpio_0 |
lda #$94 |
sta $0201 |
lda #$41 |
sta $0200 |
lda #$53 |
clc |
adc $0200 |
cmp $0201 |
beq .lab_37 |
lda #$31 |
jmp .lab_100 |
.lab_37 lda #$8D |
sta $0201 |
lda #$98 |
sta $0200 |
lda #$F4 |
sec |
adc $0200 |
cmp $0201 |
beq .lab_38 |
lda #$32 |
jmp .lab_100 |
.lab_38 lda #$23 |
sta io_base+io_gpio_0 |
ldy #$84 |
sty $0201 |
ldx #$B4 |
stx $0200 |
lda #$86 |
and $0200 |
cmp $0201 |
beq .lab_39 |
lda #$33 |
jmp .lab_100 |
.lab_39 lda #$24 |
sta io_base+io_gpio_0 |
ldx #$55 |
stx $0200 |
asl $0200 |
lda $0200 |
cmp #$AA |
beq .lab_40 |
lda #$34 |
jmp .lab_100 |
.lab_40 lda #$25 |
sta io_base+io_gpio_0 |
lda #$53 |
sta $0200 |
lda #$00 |
ldx #$53 |
cpx $0200 |
beq .lab_41 |
lda #$35 |
jmp .lab_100 |
.lab_41 lda #$26 |
sta io_base+io_gpio_0 |
lda #$45 |
sta $0200 |
lda #$00 |
ldy #$45 |
cpy $0200 |
beq .lab_42 |
lda #$36 |
jmp .lab_100 |
.lab_42 lda #$27 |
sta io_base+io_gpio_0 |
lda #$EF |
sta $0200 |
dec $0200 |
lda #$EE |
cmp $0200 |
beq .lab_43 |
lda #$37 |
jmp .lab_100 |
.lab_43 lda #$01 |
sta $0200 |
dec $0200 |
beq .lab_44 |
lda #$38 |
jmp .lab_100 |
.lab_44 lda #$28 |
sta io_base+io_gpio_0 |
lda #$EF |
sta $0200 |
inc $0200 |
lda #$F0 |
cmp $0200 |
beq .lab_45 |
lda #$39 |
jmp .lab_100 |
.lab_45 lda #$FF |
sta $0200 |
inc $0200 |
beq .lab_46 |
lda #$40 |
jmp .lab_100 |
.lab_46 lda #$29 |
sta io_base+io_gpio_0 |
ldy #$32 |
sty $0201 |
ldx #$B4 |
stx $0200 |
lda #$86 |
eor $0200 |
cmp $0201 |
beq .lab_47 |
lda #$41 |
jmp .lab_100 |
.lab_47 lda #$2A |
sta io_base+io_gpio_0 |
ldy #$B6 |
sty $0201 |
ldx #$B4 |
stx $0200 |
lda #$86 |
ora $0200 |
cmp $0201 |
beq .lab_48 |
lda #$42 |
jmp .lab_100 |
.lab_48 lda #$2B |
sta io_base+io_gpio_0 |
clc |
ldx #$AA |
stx $0200 |
rol $0200 |
bcs .lab_49 |
lda #$43 |
jmp .lab_100 |
.lab_49 lda $0200 |
cmp #$54 |
beq .lab_50 |
lda #$44 |
jmp .lab_100 |
.lab_50 lda #$2C |
sta io_base+io_gpio_0 |
clc |
ldx #$55 |
stx $0200 |
ror $0200 |
bcs .lab_51 |
lda #$45 |
jmp .lab_100 |
.lab_51 lda $0200 |
cmp #$2A |
beq .lab_52 |
lda #$46 |
jmp .lab_100 |
.lab_52 lda #$2D |
sta io_base+io_gpio_0 |
ldx #$96 |
stx $0200 |
lsr $0200 |
lda $0200 |
cmp #$4B |
beq .lab_53 |
lda #$47 |
jmp .lab_100 |
.lab_53 lda #$2E |
sta io_base+io_gpio_0 |
ldx #$42 |
stx $0200 |
ldx #$9F |
stx $0201 |
ldx $0200 |
cpx #$42 |
beq .lab_54 |
lda #$48 |
jmp .lab_100 |
.lab_54 ldx $0201 |
cpx #$9F |
beq .lab_55 |
lda #$49 |
jmp .lab_100 |
.lab_55 lda #$2F |
sta io_base+io_gpio_0 |
ldy #$34 |
sty $0200 |
ldy #$75 |
sty $0201 |
ldy $0200 |
cpy #$34 |
beq .lab_56 |
lda #$4A |
jmp .lab_100 |
.lab_56 ldy $0201 |
cpy #$75 |
beq .lab_57 |
lda #$4B |
jmp .lab_100 |
.lab_57 lda #$30 |
sta io_base+io_gpio_0 |
lda #$12 |
sta $0201 |
lda #$41 |
sta $0200 |
lda #$53 |
sec |
sbc $0200 |
cmp $0201 |
beq .lab_58 |
lda #$4C |
jmp .lab_100 |
.lab_58 lda #$5B |
sta $0201 |
lda #$98 |
sta $0200 |
lda #$F4 |
clc |
sbc $0200 |
cmp $0201 |
beq .lab_59 |
lda #$4D |
jmp .lab_100 |
.lab_59 lda #$31 |
sta io_base+io_gpio_0 |
lda #$42 |
pha |
lda #$ED |
pha |
lda #$BE |
pha |
lda #$00 |
pla |
cmp #$BE |
bne .lab_60 |
pla |
cmp #$ED |
bne .lab_60 |
pla |
cmp #$42 |
bne .lab_60 |
jmp .lab_605 |
.lab_60 lda #$4E |
jmp .lab_100 |
.lab_605 lda #$32 |
sta io_base+io_gpio_0 |
ldx #$00 |
clc |
lda #$03 |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
adc #$07 |
inx |
sta $0200,X |
ldx #$00 |
clc |
lda $0200,X |
cmp #$03 |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$0A |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$11 |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$18 |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$1F |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$26 |
bne .lab_61 |
inx |
lda $0200,X |
cmp #$2D |
bne .lab_61 |
jmp .lab_615 |
.lab_61 lda #$4F |
jmp .lab_100 |
.lab_615 lda #$33 |
sta io_base+io_gpio_0 |
ldy #$00 |
clc |
lda #$03 |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
adc #$07 |
iny |
sta $0200,Y |
ldy #$00 |
clc |
lda $0200,Y |
cmp #$03 |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$0A |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$11 |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$18 |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$1F |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$26 |
bne .lab_62 |
iny |
lda $0200,Y |
cmp #$2D |
bne .lab_62 |
jmp .lab_625 |
.lab_62 lda #$50 |
jmp .lab_100 |
.lab_625 lda #$34 |
sta io_base+io_gpio_0 |
lda #$52 |
sta $0200 |
lda #$24 |
sta $0201 |
lda #$78 |
sta $0202 |
lda #$00 |
ldx #$00 |
clc |
adc $0200,X |
clc |
inx |
adc $0200,X |
clc |
inx |
adc $0200,X |
cmp #$EE |
beq .lab_63 |
lda #$51 |
jmp .lab_100 |
.lab_63 lda #$35 |
sta io_base+io_gpio_0 |
lda #$68 |
sta $0200 |
lda #$13 |
sta $0201 |
lda #$95 |
sta $0202 |
lda #$00 |
ldy #$00 |
clc |
adc $0200,Y |
clc |
iny |
adc $0200,Y |
clc |
iny |
adc $0200,Y |
cmp #$10 |
beq .lab_64 |
lda #$52 |
jmp .lab_100 |
.lab_64 lda #$36 |
sta io_base+io_gpio_0 |
lda #$34 |
sta $0200 |
lda #$54 |
sta $0201 |
lda #$97 |
sta $0202 |
lda #$FF |
ldy #$00 |
and $0200,Y |
iny |
and $0200,Y |
iny |
and $0200,Y |
cmp #$14 |
beq .lab_65 |
lda #$53 |
jmp .lab_100 |
.lab_65 lda #$37 |
sta io_base+io_gpio_0 |
lda #$34 |
sta $0200 |
lda #$54 |
sta $0201 |
lda #$97 |
sta $0202 |
lda #$FF |
ldx #$00 |
and $0200,X |
inx |
and $0200,X |
inx |
and $0200,X |
cmp #$14 |
beq .lab_66 |
lda #$54 |
jmp .lab_100 |
.lab_66 lda #$38 |
sta io_base+io_gpio_0 |
lda #$64 |
sta $00 |
lda #$39 |
clc |
adc $00 |
cmp #$9D |
beq .lab_67 |
lda #$55 |
jmp .lab_100 |
.lab_67 lda #$39 |
sta io_base+io_gpio_0 |
lda #$95 |
sta $00 |
lda #$76 |
sta $01 |
lda #$45 |
sta $02 |
ldx #$00 |
lda #$00 |
clc |
adc $00,X |
inx |
clc |
adc $00,X |
inx |
clc |
adc $00,X |
cmp #$50 |
beq .lab_68 |
lda #$56 |
jmp .lab_100 |
.lab_68 lda #$3A |
sta io_base+io_gpio_0 |
lda #$64 |
sta $00 |
lda #$39 |
and $00 |
cmp #$20 |
beq .lab_69 |
lda #$57 |
jmp .lab_100 |
.lab_69 lda #$3B |
sta io_base+io_gpio_0 |
lda #$95 |
sta $00 |
lda #$76 |
sta $01 |
lda #$45 |
sta $02 |
ldx #$00 |
lda #$FF |
and $00,X |
inx |
and $00,X |
inx |
and $00,X |
cmp #$04 |
beq .lab_70 |
lda #$58 |
jmp .lab_100 |
.lab_70 lda #$3C |
sta io_base+io_gpio_0 |
lda #$97 |
sta $0200 |
lda #$78 |
sta $0201 |
lda #$45 |
sta $0202 |
ldx #$00 |
lda #$97 |
cmp $0200,X |
bne .lab_71 |
lda #$78 |
inx |
cmp $0200,X |
bne .lab_71 |
lda #$45 |
inx |
cmp $0200,X |
bne .lab_71 |
jmp .lab_715 |
.lab_71 lda #$59 |
jmp .lab_100 |
.lab_715 lda #$3D |
sta io_base+io_gpio_0 |
lda #$97 |
sta $0200 |
lda #$78 |
sta $0201 |
lda #$45 |
sta $0202 |
ldy #$00 |
lda #$97 |
cmp $0200,Y |
bne .lab_72 |
lda #$78 |
iny |
cmp $0200,Y |
bne .lab_72 |
lda #$45 |
iny |
cmp $0200,Y |
bne .lab_72 |
jmp .lab_725 |
.lab_72 lda #$5A |
jmp .lab_100 |
.lab_725 lda #$3E |
sta io_base+io_gpio_0 |
lda #$97 |
sta $0200 |
lda #$78 |
sta $0201 |
lda #$45 |
sta $0202 |
ldx #$00 |
lda #$97 |
cmp $0200,X |
bne .lab_73 |
lda #$78 |
inx |
cmp $0200,X |
bne .lab_73 |
lda #$45 |
inx |
cmp $0200,X |
bne .lab_73 |
jmp .lab_735 |
.lab_73 lda #$5B |
jmp .lab_100 |
.lab_735 lda #$3F |
sta io_base+io_gpio_0 |
lda #$95 |
sta $02 |
lda #$00 |
lda #$95 |
cmp $02 |
beq .lab_74 |
lda #$5C |
jmp .lab_100 |
.lab_74 lda #$75 |
sta $02 |
lda #$67 |
cmp $02 |
bne .lab_75 |
lda #$5D |
jmp .lab_100 |
.lab_75 lda #$40 |
sta io_base+io_gpio_0 |
lda #$36 |
sta $02 |
lda #$00 |
ldx #$36 |
cpx $02 |
beq .lab_76 |
lda #$5E |
jmp .lab_100 |
.lab_76 lda #$57 |
sta $02 |
ldx #$39 |
cpx $02 |
bne .lab_77 |
lda #$5F |
jmp .lab_100 |
.lab_77 lda #$41 |
sta io_base+io_gpio_0 |
lda #$75 |
sta $02 |
lda #$00 |
ldy #$75 |
cpy $02 |
beq .lab_78 |
lda #$60 |
jmp .lab_100 |
.lab_78 lda #$43 |
sta $02 |
ldy #$24 |
cpy $02 |
bne .lab_79 |
lda #$61 |
jmp .lab_100 |
.lab_79 lda #$42 |
sta io_base+io_gpio_0 |
nop ; was cli |
lda #$00 |
sta $05 |
lda #$01 |
sta $04 |
lda #$10 |
|
|
sta io_base+io_tim0_end |
sta io_base+io_tim0_start |
ldx #$00 |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
cpx #$10 |
beq .lab_80 |
lda #$62 |
jmp .lab_100 |
.lab_80 lda $05 |
cmp #$00 ; was 1 if int serviced |
beq .lab_81 |
lda #$63 |
jmp .lab_100 |
.lab_81 nop ; was sei to disable interrupt |
lda #$00 |
sta $05 |
lda #$01 |
sta $04 |
lda #$10 |
sta io_base+io_tim0_end |
sta io_base+io_tim0_start |
ldx #$00 |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
cpx #$10 |
beq .lab_82 |
lda #$62 |
jmp .lab_100 |
.lab_82 lda $05 |
cmp #$00 |
beq .lab_83 |
lda #$63 |
jmp .lab_100 |
.lab_83 lda #$00 |
sta $04 |
sta io_base+io_tim0_end |
lda #$43 |
sta io_base+io_gpio_0 |
lda #$00 |
sta $07 |
lda #$01 |
sta $06 |
lda #$10 |
sta io_base+io_tim0_end ; change to tim1 for nmi |
sta io_base+io_tim0_start ; change to tim1 for nmi |
ldx #$00 |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
inx |
cpx #$10 |
beq .lab_84 |
lda #$64 |
jmp .lab_100 |
.lab_84 lda $07 |
cmp #$00 ; change to 1 if nmi serviced |
beq .lab_85 |
lda #$65 |
jmp .lab_100 |
.lab_85 lda #$00 |
sta $06 |
sta io_base+io_tim1_end |
lda #$44 |
sta io_base+io_gpio_0 |
jmp .lab_865 |
.lab_86 jmp .lab_866 |
.lab_865 sec |
bcs .lab_86 |
nop |
nop |
nop |
lda #$66 |
jmp .lab_100 |
.lab_866 lda #$45 |
sta io_base+io_gpio_0 |
sec |
lda #$34 |
sbc #$75 |
bcc .lab_87 |
lda #$67 |
jmp .lab_100 |
.lab_87 lda #$46 |
sta io_base+io_gpio_0 |
tsx |
stx $00 |
lda #$42 |
pha |
lda #$00 |
tsx |
inx |
lda $0100,X |
cmp #$42 |
beq .lab_88 |
lda #$68 |
jmp .lab_100 |
.lab_88 lda #$69 |
sta $0112 |
lda #$00 |
ldx #$11 |
txs |
pla |
cmp #$69 |
beq .lab_89 |
lda #$69 |
jmp .lab_100 |
|
;; Break test |
;; |
.lab_89 ldx $00 |
txs |
lda #$47 |
sta io_base+io_gpio_0 |
lda #$04 ; keep int disabled |
pha |
plp |
stx $08 |
lda #$00 |
sta $05 |
lda #$01 |
sta $04 |
sta $06 |
ldx #$59 |
brk ; was brk |
inx |
lda #$00 |
sta $04 |
lda $05 |
cmp #$01 ; was 1 if brk taken |
beq .lab_92 |
lda #$70 |
jmp .lab_100 |
|
.lab_92 lda #$48 |
sta io_base+io_gpio_0 |
lda #$53 |
sta $30 |
lda #$00 |
ldx #$40 |
lda $F0,X |
cmp #$53 |
beq .lab_93 |
lda #$73 |
jmp .lab_100 |
.lab_93 lda #$49 |
sta io_base+io_gpio_0 |
clc |
lda #$FF |
adc #$01 |
bcs .lab_94 |
lda #$74 |
jmp .lab_100 |
.lab_94 lda #$4A |
sta io_base+io_gpio_0 |
sec |
lda #$7F |
sbc #$7E |
bvc .lab_95 |
lda #$75 |
jmp .lab_100 |
.lab_95 lda #$4B |
sta io_base+io_gpio_0 |
lda #$FF |
pha |
plp |
php |
pla |
cmp #$FF |
beq .lab_96 |
lda #$76 |
jmp .lab_100 |
.lab_96 lda #$4C |
sta io_base+io_gpio_0 |
lda #$40 |
ldx #$00 |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
inx |
lsr a |
sta $0200,X |
ldx #$00 |
asl $0200,X |
inx |
asl $0200,X |
inx |
asl $0200,X |
inx |
asl $0200,X |
inx |
asl $0200,X |
inx |
asl $0200,X |
inx |
asl $0200,X |
lda #$00 |
cld |
clc |
adc $0200 |
adc $0201 |
adc $0202 |
adc $0203 |
adc $0204 |
adc $0205 |
adc $0206 |
cmp #$FE |
beq .lab_97 |
lda #$77 |
jmp .lab_100 |
.lab_97 lda #$4D |
sta io_base+io_gpio_0 |
ldx #$42 |
ldy #$00 |
stx $0200 |
ldx #$9F |
stx $0201 |
ldx $0200,Y |
cpx #$42 |
beq .lab_98 |
lda #$48 |
jmp .lab_100 |
.lab_98 ldx $0201,Y |
cpx #$9F |
beq .lab_99 |
lda #$78 |
jmp .lab_100 |
;; pass end loop |
.lab_99 sei |
lda #$FF |
sta io_base+io_gpio_0 |
lda io_base+io_gpio_0 |
lda #$F0 |
sta io_base |
lda io_base |
jmp .lab_99 |
|
;; error end loop |
.lab_100 sei |
sta io_base+io_gpio_1 |
lda io_base+io_gpio_1 |
jmp .lab_100 |
|
;; Interrupt service routine |
.nmi_vec pha |
txa |
pha |
tya |
pha |
tsx |
inx |
inx |
inx |
inx |
lda $0100,X |
sta $08 |
lda $04 |
cmp #$00 |
bne .lab_101 |
lda #$E0 |
jmp .lab_100 |
.lab_101 sta io_base+io_tim0_end |
inc $05 |
pla |
tay |
pla |
tax |
pla |
rti |
|
;; Interrupt service routine |
|
.irq_vec pha |
txa |
pha |
tya |
pha |
lda $06 |
cmp #$00 |
bne .lab_102 |
lda #$E0 |
jmp .lab_100 |
.lab_102 sta io_base+io_tim1_end |
inc $07 |
inc $05 |
pla |
tay |
pla |
tax |
pla |
rti |
|
|
|
|
* = $fffa ; vectors |
|
|
|
dw .nmi_vec ; |
dw .start ; |
dw .irq_vec ; |
|
code |
|
|
|
|
|
|
/socgen/trunk/projects/Mos6502/sw/prog_test/Makefile
0,0 → 1,7
include ../../bin/Makefile.root |
code=prog_test |
|
all:asm_6502 |
|
|
|
/socgen/trunk/projects/Mos6502/sw/tim_1/tim_1.asm
14,7 → 14,7
io_tim0_end = $14 ; |
|
io_tim1_start = $18 ; |
io_tim0_count = $1A ; |
io_tim1_count = $1A ; |
io_tim1_end = $1C ; |
|
io_uart_xmt = $20 ; |