URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 29 to Rev 30
- ↔ Reverse comparison
Rev 29 → Rev 30
/tinycpu/trunk/testbench/core_tb.vhd
145,6 → 145,8
assert(DebugTR='1') report "ALU compare is not correct for less than" severity error; |
|
--now test bitwise |
MemIn <= x"0E50"; --mov IP, 0x50 -- do this just so we can count IP easily |
wait for 10 ns; |
MemIn <= x"00F0"; --mov r0, 0xFO |
wait for 10 ns; |
MemIn <= x"0218"; --mov r1, 0x18 |
151,9 → 153,12
wait for 10 ns; |
MemIn <= "0100000000010001"; --or r0, r1 (r0 = r0 or r1) |
wait for 10 ns; |
wait for 10 ns; --wait for settling |
assert(DebugR0 = x"F8") report "ALU OR is not correct" severity error; |
MemIn <= x"1070"; --mov [r0], 0x70 -- for debugging |
wait for 20 ns; |
assert( MemAddr=x"0156") report "Fetching is wrong after WaitForAlu" severity error; |
MemIn <= x"0070"; --mov r0, 0x70 -- for debugging |
wait for 10 ns; |
assert( MemAddr=x"0158") report "IP increment is wrong after WaitForAlu" severity error; |
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|
-- summary of testbench |
/tinycpu/trunk/src/alu.vhd
28,6 → 28,7
TR <= TRData; |
process(DataIn1, DataIn2, Op) |
begin |
--TRData <='0'; --default |
case Op is |
--bitwise operations |
when "00000" => --and |
/tinycpu/trunk/src/core.vhd
87,7 → 87,8
Firstfetch3, |
Execute, |
WaitForMemory, |
HoldMemory |
HoldMemory, |
WaitForAlu -- wait for settling is needed when using the ALU |
); |
signal state: ProcessorState; |
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated |
145,6 → 146,7
|
signal UsuallySS: std_logic_vector(3 downto 0); |
signal UsuallyDS: std_logic_vector(3 downto 0); |
signal aluregisterout: std_logic_vector(3 downto 0); |
begin |
reg: registerfile port map( |
WriteEnable => regWE, |
277,6 → 279,13
FetchEn <= '1'; |
IpAddend <= x"02"; |
SpAddend <= x"00"; |
elsif state=WaitForAlu then |
state <= Execute; |
regIn(to_integer(unsigned(AluRegisterOut))) <= AluOut; |
regWE(to_integer(unsigned(AluRegisterOut))) <= '1'; |
FetchEN <= '1'; |
IPAddend <= x"02"; |
SPAddend <= x"00"; |
end if; |
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|
315,11 → 324,16
AluIn1 <= regOut(to_integer(unsigned(bankreg1))); |
AluIn2 <= regOut(to_integer(unsigned(bankreg2))); |
when "0100" => --group 4 bitwise operations |
--setup wait state |
State <= WaitForAlu; |
FetchEN <= '0'; |
IPAddend <= x"00"; |
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us |
AluIn1 <= regOut(to_integer(unsigned(bankreg1))); |
AluIn2 <= regOut(to_integer(unsigned(bankreg2))); |
regIn(to_integer(unsigned(bankreg1))) <= AluOut; |
regWE(to_integer(unsigned(bankreg1))) <= '1'; |
AluRegisterOut <= bankreg1; |
--regIn(to_integer(unsigned(bankreg1))) <= AluOut; |
--regWE(to_integer(unsigned(bankreg1))) <= '1'; |
when "0101" => --group 5 |
case opreg3 is |
when "000" => --subgroup 5-0 |
/tinycpu/trunk/docs/design.md.txt
6,6 → 6,15
4. use a small amount of "rich" instructions to do powerful things |
5. 1 instruction per clock cycle |
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BIG CHANGE: |
So, apparently making a single-cycle CPU is extremely hard... so instead, we'll be striving for a 2-cycle CPU. |
Usual cycles: |
1-cycle: mov, jmp, etc general data movement |
2-cycle: ALU operations |
1-cycle with memory wait(so really 2 cycle): all instructions that reference memory |
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Relative moves: |
In order to provide uesfulness to the segment-carryover feature, there are a few options for moving a "relative" amount to a register, including IP and SP |
A relative move differs in most of the opcodes in that the relative factor is treated as a signed value. |