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Rev 29 → Rev 30

/trunk/rtl/verilog/vga_top.v File deleted
/trunk/rtl/verilog/vga_fifo.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_fifo.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_fifo.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
134,6 → 134,7
 
// status flags
assign empty = !(|fifo_cnt);
assign hfull = fifo_cnt[AWIDTH -1];
assign hfull = fifo_cnt[AWIDTH -1] | fifo_cnt[AWIDTH];
assign full = fifo_cnt[AWIDTH];
endmodule
 
/trunk/rtl/verilog/vga_wb_master.v
1,6 → 1,6
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant VGA/LCD Core; Wishbone Master ////
//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
//// Wishbone master interface ////
//// ////
//// Author: Richard Herveille ////
11,8 → 11,8
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_master.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_wb_master.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
49,9 → 49,12
// $Log: not supported by cvs2svn $
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw, VBAa, VBAb, Thgate, Tvgate,
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,
cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
VBAa, VBAb, Thgate, Tvgate,
stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
clut_req, clut_ack, clut_adr, clut_q);
 
86,6 → 89,15
input ctrl_vbsw; // enable video bank switching
input ctrl_cbsw; // enable clut bank switching
 
input cursor0_en; // enable hardware cursor0
input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
input [31:11] cursor0_ba; // cursor0 video memory base address
input cursor0_ld; // reload cursor0 from video memory
input cursor1_en; // enable hardware cursor1
input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
input [31:11] cursor1_ba; // cursor1 video memory base address
input cursor1_ld; // reload cursor1 from video memory
 
// video memory addresses
input [31: 2] VBAa; // video memory base address A
input [31: 2] VBAb; // video memory base address B
116,10 → 128,8
 
reg vmem_acc; // video memory access
wire nvmem_req, vmem_ack; // NOT video memory access request // video memory access acknowledge
reg dvmem_ack; // delayed video memory acknowledge
 
// wire ImDone; // Done reading image from video mem
reg ImDone; // Done reading image from video mem
wire ImDone; // Done reading image from video mem
reg dImDone; // delayed ImDone
wire ImDoneStrb; // image done (strobe signal)
reg dImDoneStrb; // delayed ImDoneStrb
126,18 → 136,20
 
wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;
wire [31:0] data_fifo_q;
wire rgb_fifo_wreq, rgb_fifo_empty, rgb_fifo_full, rgb_ffull, rgb_fifo_rreq;
reg fill_rgb_fifo;
wire [23:0] rgb_fifo_d;
wire [23:0] color_proc_q, ssel1_q, rgb_fifo_d;
wire color_proc_wreq, ssel1_wreq, rgb_fifo_wreq;
wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq;
wire ImDoneFifoQ;
reg dImDoneFifoQ;
reg [2:0] ImDoneCpQ;
reg dImDoneCpQ;
reg dImDoneFifoQ, ddImDoneFifoQ;
reg [2:0] ImDoneCursorQ;
 
reg sclr; // synchronous clear
 
wire [7:0] clut_offs; // color lookup table offset
 
reg [8:0] cursor_adr;
reg cursor0_we, cursor1_we;
 
//
// module body
//
175,18 → 187,14
 
assign stat_avmp = sel_VBA; // assign output
 
// select active clut page
 
// clut bank switch delay1; push ImDoneStrb into fifo. Account for data_fifo delay
always@(posedge clk_i)
dvmem_ack <= #1 vmem_ack;
 
// selecting active clut page / cursor data
// delay image done same amount as video-memory data
vga_fifo #(4, 1) clut_sw_fifo (
.clk(clk_i),
.aclr(1'b1),
.sclr(sclr),
.d(ImDone),
.wreq(dvmem_ack),
.wreq(vmem_ack),
.q(ImDoneFifoQ),
.rreq(data_fifo_rreq),
.empty(),
194,26 → 202,20
.full()
);
 
// clut bank switch delay2: Account for ColorProcessor DataBuffer delay
// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
always@(posedge clk_i)
if (data_fifo_rreq)
if (sclr)
dImDoneFifoQ <= #1 1'b0;
else if (data_fifo_rreq)
dImDoneFifoQ <= #1 ImDoneFifoQ;
 
// clut bank switch delay3; Account for ColorProcessor internal delay
always@(posedge clk_i)
if (sclr)
begin
ImDoneCpQ <= #1 4'h0;
dImDoneCpQ <= #1 1'b0;
end
else
begin
dImDoneCpQ <= #1 ImDoneCpQ[2];
if (rgb_fifo_wreq)
ImDoneCpQ <= #1 { ImDoneCpQ[2:0], dImDoneFifoQ };
end
ddImDoneFifoQ <= #1 1'b0;
else
ddImDoneFifoQ <= #1 dImDoneFifoQ;
 
assign clut_switch = ImDoneCpQ[2] & !dImDoneCpQ;
assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
 
always@(posedge clk_i)
if (sclr)
318,10 → 320,8
else if (hdone)
vgate_cnt <= #1 vgate_cnt_val[15:0];
 
always@(posedge clk_i)
ImDone <= #1 hdone & vdone;
assign ImDone = hdone & vdone;
 
// assign ImDone = hdone & vdone;
assign ImDoneStrb = ImDone & !dImDone;
 
always@(posedge clk_i)
375,7 → 375,7
we_o <= #1 1'b0; // read only
end
 
// pixel buffer (temporary store data read from video memory)
// video-data buffer (temporary store data read from video memory)
vga_fifo #(4, 32) data_fifo (
.clk(clk_i),
.aclr(1'b1),
391,28 → 391,21
 
assign nvmem_req = data_fifo_hfull;
 
always@(posedge clk_i)
if (sclr)
fill_rgb_fifo <= #1 1'b0;
else
fill_rgb_fifo <= #1 (rgb_fifo_empty | fill_rgb_fifo) & !rgb_fifo_full;
 
assign rgb_ffull = !(fill_rgb_fifo & !rgb_fifo_full);
 
// hookup color processor
vga_colproc color_proc (
.clk(clk_i),
.srst(sclr),
.pixel_buffer_di(data_fifo_q),
.vdat_buffer_di(data_fifo_q),
.ColorDepth(ctrl_cd),
.PseudoColor(ctrl_pc),
.pixel_buffer_empty(data_fifo_empty),
.pixel_buffer_rreq(data_fifo_rreq),
.RGB_fifo_full(rgb_ffull),
.RGB_fifo_wreq(rgb_fifo_wreq),
.R(rgb_fifo_d[23:16]),
.G(rgb_fifo_d[15:8]),
.B(rgb_fifo_d[7:0]),
.vdat_buffer_empty(data_fifo_empty),
.vdat_buffer_rreq(data_fifo_rreq),
.rgb_fifo_full(rgb_fifo_full),
.rgb_fifo_wreq(color_proc_wreq),
.r(color_proc_q[23:16]),
.g(color_proc_q[15:8]),
.b(color_proc_q[7:0]),
.clut_req(clut_req),
.clut_ack(clut_ack),
.clut_offs(clut_offs),
419,6 → 412,102
.clut_q(clut_q)
);
 
// hookup data-source-selector && hardware cursor module
`ifdef VGA_HWC1
reg scursor1_ld;
reg scursor1_en;
reg [31:0] scursor1_xy;
reg sddImDoneFifoQ, sdImDoneFifoQ;
 
always@(posedge clk_i)
if (ssel1_wreq)
begin
sdImDoneFifoQ <= #1 dImDoneFifoQ;
sddImDoneFifoQ <= #1 sdImDoneFifoQ;
end
always@(posedge clk_i)
if (sclr)
scursor1_ld <= #1 1'b0;
else
scursor1_ld <= #1 cursor1_ld | (scursor1_ld & !(ddImDoneFifoQ & !dImDoneFifoQ));
 
always@(posedge clk_i)
if (sclr)
scursor1_en <= #1 1'b0;
else if (scursor1_ld)
scursor1_en <= #1 cursor1_en;
 
always@(posedge clk_i)
if (scursor1_ld)
scursor1_xy <= #1 cursor1_xy;
 
vga_ssel ssel_and_hw_cursor1 (
.clk(clk_i),
.rst_i(sclr),
.Thgate(Thgate),
.Tvgate(Tvgate),
.idat(color_proc_q),
.idat_wreq(color_proc_wreq),
.cursor_xy(scursor1_xy),
.cursor_en(scursor1_en),
.cursor_adr(cursor_adr),
.cursor_we(cursor1_we),
.cursor_dat(dat_i),
.rgb_fifo_wreq(ssel1_wreq),
.rgb(ssel1_q)
);
`else
wire sddImDoneFifoQ, sdImDoneFifoQ;
 
assign ssel1_wreq = color_proc_wreq;
assign ssel1_q = color_proc_q;
 
assign sdImDoneFifoQ = dImDoneFifoQ;
assign sddImDoneFifoQ = ddImDoneFifoQ;
`endif
 
`ifdef VGA_HWC0
reg scursor0_ld;
reg scursor0_en;
reg [31:0] scursor0_xy;
 
always@(posedge clk_i)
if (sclr)
scursor0_ld <= #1 1'b0;
else
scursor0_ld <= #1 cursor0_ld | (scursor0_ld & !(sddImDoneFifoQ & !sdImDoneFifoQ));
 
always@(posedge clk_i)
if (sclr)
scursor0_en <= #1 1'b0;
else if (scursor0_ld)
scursor0_en <= #1 cursor0_en;
 
always@(posedge clk_i)
if (scursor0_ld)
scursor0_xy <= #1 cursor0_xy;
 
vga_ssel ssel_and_hw_cursor0 (
.clk(clk_i),
.rst_i(sclr),
.Thgate(Thgate),
.Tvgate(Tvgate),
.idat(ssel1_q),
.idat_wreq(ssel1_wreq),
.cursor_xy(scursor0_xy),
.cursor_en(scursor0_en),
.cursor_adr(cursor_adr),
.cursor_we(cursor0_we),
.cursor_dat(dat_i),
.rgb_fifo_wreq(rgb_fifo_wreq),
.rgb(rgb_fifo_d)
);
`else
assign rgb_fifo_wreq = ssel1_wreq;
assign rgb_fifo_d = ssel1_q;
`endif
 
// hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
vga_fifo #(3, 24) rgb_fifo (
.clk(clk_i),
440,3 → 529,4
 
 
 
 
/trunk/rtl/verilog/vga_enh_top.v
0,0 → 1,366
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant Enhanced VGA/LCD Core ////
//// Top Level ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001,2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: vga_enh_top.v,v 1.1 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_enh_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o,
wbm_adr_o, wbm_dat_i, wbm_cab_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i,
clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o);
 
//
// parameters
//
parameter ARST_LVL = 1'b0;
parameter LINE_FIFO_AWIDTH = 7;
 
//
// inputs & outputs
//
 
// syscon interface
input wb_clk_i; // wishbone clock input
input wb_rst_i; // synchronous active high reset
input rst_i; // asynchronous reset
output wb_inta_o; // interrupt request output
 
// slave signals
input [11:0] wbs_adr_i; // addressbus input (only 32bit databus accesses supported)
input [31:0] wbs_dat_i; // Slave databus output
output [31:0] wbs_dat_o; // Slave databus input
input [ 3:0] wbs_sel_i; // byte select inputs
input wbs_we_i; // write enabel input
input wbs_stb_i; // strobe/select input
input wbs_cyc_i; // valid bus cycle input
output wbs_ack_o; // bus cycle acknowledge output
output wbs_err_o; // bus cycle error output
// master signals
output [31:0] wbm_adr_o; // addressbus output
input [31:0] wbm_dat_i; // Master databus input
output [ 3:0] wbm_sel_o; // byte select outputs
output wbm_we_o; // write enable output
output wbm_stb_o; // strobe output
output wbm_cyc_o; // valid bus cycle output
output wbm_cab_o; // continuos address burst output
input wbm_ack_i; // bus cycle acknowledge input
input wbm_err_i; // bus cycle error input
 
// VGA signals
input clk_p_i; // pixel clock
output hsync_pad_o; // horizontal sync
reg hsync_pad_o;
output vsync_pad_o; // vertical sync
reg vsync_pad_o;
output csync_pad_o; // composite sync
reg csync_pad_o;
output blank_pad_o; // blanking signal
reg blank_pad_o;
output [ 7:0] r_pad_o, g_pad_o, b_pad_o; // RGB color signals
 
//
// variable declarations
//
 
// programable asynchronous reset
wire arst = rst_i ^ ARST_LVL;
 
// from wb_slave
wire ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven;
wire [ 1: 0] ctrl_cd, ctrl_vbl;
wire [ 7: 0] Thsync, Thgdel, Tvsync, Tvgdel;
wire [15: 0] Thgate, Thlen, Tvgate, Tvlen;
wire [31: 2] VBARa, VBARb;
wire [31: 0] cursor0_xy, cursor1_xy;
wire cursor0_en, cursor1_en;
wire [31:11] cursor0_ba, cursor1_ba;
wire cursor0_ld, cursor1_ld;
 
// to wb_slave
wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint;
reg luint;
 
// from pixel generator
wire cgate; // composite gate signal
wire ihsync, ivsync, icsync, iblank; // intermediate horizontal/vertical/composite sync, intermediate blank
 
// line fifo connections
wire line_fifo_dpm_wreq;
wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q;
 
// clut connections
wire ext_clut_req, ext_clut_ack;
wire [23:0] ext_clut_q;
wire cp_clut_req, cp_clut_ack;
wire [ 8:0] cp_clut_adr;
wire [23:0] cp_clut_q;
 
//
// Module body
//
 
// hookup wishbone slave
vga_wb_slave u1 (
// wishbone interface
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.nRESET(arst),
.ADR_I(wbs_adr_i[11:2]),
.DAT_I(wbs_dat_i),
.DAT_O(wbs_dat_o),
.SEL_I(wbs_sel_i),
.WE_I(wbs_we_i),
.STB_I(wbs_stb_i),
.CYC_I(wbs_cyc_i),
.ACK_O(wbs_ack_o),
.ERR_O(wbs_err_o),
.INTA_O(wb_inta_o),
 
// internal connections
.bl(ctrl_bl),
.csl(ctrl_csl),
.vsl(ctrl_vsl),
.hsl(ctrl_hsl),
.pc(ctrl_pc),
.cd(ctrl_cd),
.vbl(ctrl_vbl),
.cbsw(ctrl_cbsw),
.vbsw(ctrl_vbsw),
.ven(ctrl_ven),
.acmp(stat_acmp),
.avmp(stat_avmp),
.cursor0_en(cursor0_en), // cursor0 enable
.cursor0_xy(cursor0_xy), // cursor0 (x,y)
.cursor0_ba(cursor0_ba), // curso0 video memory base address
.cursor0_ld(cursor0_ld), // reload curso0 from video memory
.cursor1_en(cursor1_en), // cursor1 enable
.cursor1_xy(cursor1_xy), // cursor1 (x,y)
.cursor1_ba(cursor1_ba), // cursor1 video memory base address
.cursor1_ld(cursor1_ld), // reload cursor1 from video memory
.vbsint_in(vmem_swint), // video memory bank switch interrupt
.cbsint_in(clut_swint), // clut memory bank switch interrupt
.hint_in(hint), // horizontal interrupt
.vint_in(vint), // vertical interrupt
.luint_in(luint), // line fifo underrun interrupt
.sint_in(sint), // system-error interrupt
.Thsync(Thsync),
.Thgdel(Thgdel),
.Thgate(Thgate),
.Thlen(Thlen),
.Tvsync(Tvsync),
.Tvgdel(Tvgdel),
.Tvgate(Tvgate),
.Tvlen(Tvlen),
.VBARa(VBARa),
.VBARb(VBARb),
.clut_acc(ext_clut_req),
.clut_ack(ext_clut_ack),
.clut_q(ext_clut_q)
);
 
// hookup wishbone master
vga_wb_master u2 (
// wishbone interface
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.nrst_i(arst),
.cyc_o(wbm_cyc_o),
.stb_o(wbm_stb_o),
.cab_o(wbm_cab_o),
.we_o(wbm_we_o),
.adr_o(wbm_adr_o),
.sel_o(wbm_sel_o),
.ack_i(wbm_ack_i),
.err_i(wbm_err_i),
.dat_i(wbm_dat_i),
 
// internal connections
.sint(sint),
.ctrl_ven(ctrl_ven),
.ctrl_cd(ctrl_cd),
.ctrl_pc(ctrl_pc),
.ctrl_vbl(ctrl_vbl),
.ctrl_cbsw(ctrl_cbsw),
.ctrl_vbsw(ctrl_vbsw),
.cursor0_en(cursor0_en), // cursor0 enable
.cursor0_xy(cursor0_xy), // cursor0 (x,y)
.cursor0_ba(cursor0_ba), // curso0 video memory base address
.cursor0_ld(cursor0_ld), // reload curso0 from video memory
.cursor1_en(cursor1_en), // cursor1 enable
.cursor1_xy(cursor1_xy), // cursor1 (x,y)
.cursor1_ba(cursor1_ba), // cursor1 video memory base address
.cursor1_ld(cursor1_ld), // reload cursor1 from video memory
.VBAa(VBARa),
.VBAb(VBARb),
.Thgate(Thgate),
.Tvgate(Tvgate),
.stat_acmp(stat_acmp),
.stat_avmp(stat_avmp),
.vmem_switch(vmem_swint),
.clut_switch(clut_swint),
 
// line fifo memory signals
.line_fifo_wreq(line_fifo_dpm_wreq),
.line_fifo_d(line_fifo_dpm_d),
.line_fifo_full(line_fifo_full_wr),
 
// clut memory signals
.clut_req(cp_clut_req),
.clut_ack(cp_clut_ack),
.clut_adr(cp_clut_adr),
.clut_q(cp_clut_q)
);
 
// hookup CLUT <cycle shared memory>
vga_csm_pb #(24, 9) clut_mem(
.clk_i(wb_clk_i),
 
// color processor access
.req0_i(cp_clut_req),
.ack0_o(cp_clut_ack),
.adr0_i(cp_clut_adr),
.dat0_i(24'h0),
.dat0_o(cp_clut_q),
.we0_i(1'b0), // no writes
 
// external access
.req1_i(ext_clut_req),
.ack1_o(ext_clut_ack),
.adr1_i(wbs_adr_i[10:2]),
.dat1_i(wbs_dat_i[23:0]),
.dat1_o(ext_clut_q),
.we1_i(wbs_we_i)
);
 
// hookup pixel and video timing generator
vga_pgen u3 (
.mclk(wb_clk_i),
.pclk(clk_p_i),
.ctrl_ven(ctrl_ven),
.ctrl_HSyncL(ctrl_hsl),
.Thsync(Thsync),
.Thgdel(Thgdel),
.Thgate(Thgate),
.Thlen(Thlen),
.ctrl_VSyncL(ctrl_vsl),
.Tvsync(Tvsync),
.Tvgdel(Tvgdel),
.Tvgate(Tvgate),
.Tvlen(Tvlen),
.ctrl_CSyncL(ctrl_csl),
.ctrl_BlankL(ctrl_bl),
.eoh(hint),
.eov(vint),
.gate(cgate),
.Hsync(ihsync),
.Vsync(ivsync),
.Csync(icsync),
.Blank(iblank)
);
 
 
// delay video control signals 1 clock cycle (dual clock fifo synchronizes output)
always@(posedge clk_p_i)
begin
hsync_pad_o <= #1 ihsync;
vsync_pad_o <= #1 ivsync;
csync_pad_o <= #1 icsync;
blank_pad_o <= #1 iblank;
end
 
// hookup line-fifo
vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) u4 (
.rclk(clk_p_i),
.wclk(wb_clk_i),
.aclr(ctrl_ven),
.wreq(line_fifo_dpm_wreq),
.d(line_fifo_dpm_d),
.rreq(cgate),
.q(line_fifo_dpm_q),
.rd_empty(line_fifo_empty_rd),
.rd_full(),
.wr_empty(),
.wr_full(line_fifo_full_wr)
);
 
assign r_pad_o = line_fifo_dpm_q[23:16];
assign g_pad_o = line_fifo_dpm_q[15: 8];
assign b_pad_o = line_fifo_dpm_q[ 7: 0];
 
// generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt)
reg luint_pclk, sluint;
 
always@(posedge clk_p_i)
luint_pclk <= #1 cgate & line_fifo_empty_rd;
 
always@(posedge wb_clk_i or negedge arst)
if (!arst)
begin
sluint <= #1 1'b0;
luint <= #1 1'b0;
end
else if (wb_rst_i)
begin
sluint <= #1 1'b0;
luint <= #1 1'b0;
end
else if (!ctrl_ven)
begin
sluint <= #1 1'b0;
luint <= #1 1'b0;
end
else
begin
sluint <= #1 luint_pclk; // resample at wb_clk_i clock
luint <= #1 sluint; // sample again, reduce metastability risk
end
 
endmodule
/trunk/rtl/verilog/vga_colproc.v
1,8 → 1,8
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant VGA/LCD Core; Color Processor ////
//// WISHBONE rev.B2 compliant VGA/LCD Core ////
//// Enhanced Color Processor ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
11,8 → 11,8
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_colproc.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_colproc.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
50,9 → 50,9
 
`include "timescale.v"
 
module vga_colproc(clk, srst, pixel_buffer_di, ColorDepth, PseudoColor,
pixel_buffer_empty, pixel_buffer_rreq, RGB_fifo_full,
RGB_fifo_wreq, R, G, B,
module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor,
vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full,
rgb_fifo_wreq, r, g, b,
clut_req, clut_ack, clut_offs, clut_q);
 
//
61,27 → 61,27
input clk; // master clock
input srst; // synchronous reset
 
input [31:0] pixel_buffer_di; // Pixel Buffer data input
input [31:0] vdat_buffer_di; // video memory data input
 
input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
 
input pixel_buffer_empty;
output pixel_buffer_rreq; // pixel buffer read request
reg pixel_buffer_rreq;
input vdat_buffer_empty;
output vdat_buffer_rreq; // pixel buffer read request
reg vdat_buffer_rreq;
 
input RGB_fifo_full;
output RGB_fifo_wreq;
reg RGB_fifo_wreq;
output [7:0] R, G, B; // pixel color information
reg [7:0] R, G, B;
input rgb_fifo_full;
output rgb_fifo_wreq;
reg rgb_fifo_wreq;
output [7:0] r, g, b; // pixel color information
reg [7:0] r, g, b;
 
output clut_req; // clut request
output clut_req; // clut request
reg clut_req;
input clut_ack; // clut acknowledge
output [ 7:0] clut_offs; // clut offset
input clut_ack; // clut acknowledge
output [ 7:0] clut_offs; // clut offset
reg [7:0] clut_offs;
input [23:0] clut_q; // clut data in
input [23:0] clut_q; // clut data in
 
//
// variable declarations
98,8 → 98,8
 
// store word from pixelbuffer / wishbone input
always@(posedge clk)
if (pixel_buffer_rreq)
DataBuffer <= #1 pixel_buffer_di;
if (vdat_buffer_rreq)
DataBuffer <= #1 vdat_buffer_di;
 
//
// generate statemachine
118,7 → 118,7
reg [6:0] nxt_state; // synopsys enum_state
 
// next state decoder
always@(c_state or pixel_buffer_empty or ColorDepth or PseudoColor or RGB_fifo_full or colcnt or clut_ack)
always@(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack)
begin : nxt_state_decoder
// initial value
nxt_state = c_state;
126,7 → 126,7
case (c_state) // synopsis full_case parallel_case
// idle state
idle:
if (!pixel_buffer_empty)
if (!vdat_buffer_empty && !rgb_fifo_full)
nxt_state = fill_buf;
 
// fill data buffer
153,30 → 153,34
// 8 bits per pixel
//
bw_8bpp:
if (!RGB_fifo_full && !(|colcnt) )
if (!pixel_buffer_empty)
if (!rgb_fifo_full && !(|colcnt) )
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
 
col_8bpp:
if (!RGB_fifo_full && !(|colcnt) )
if (clut_ack)
if (!pixel_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
// do NOT check for rgb_fifo_full here, because in 8bpp_pc mode
// the color-processor always finishes the current 4pixel-block
// i.e. it runs until colcnt = '11'
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
if (!(|colcnt))
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
 
//
// 16 bits per pixel
//
col_16bpp_a:
if (!RGB_fifo_full)
if (!rgb_fifo_full)
nxt_state = col_16bpp_b;
 
col_16bpp_b:
if (!RGB_fifo_full)
if (!pixel_buffer_empty)
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
185,10 → 189,10
// 24 bits per pixel
//
col_24bpp:
if (!RGB_fifo_full)
if (!rgb_fifo_full)
if (colcnt == 2'h1) // (colcnt == 1)
nxt_state = col_24bpp; // stay in current state
else if (!pixel_buffer_empty)
else if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
197,8 → 201,8
// 32 bits per pixel
//
col_32bpp:
if (!RGB_fifo_full)
if (!pixel_buffer_empty)
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
214,15 → 218,15
 
 
reg iclut_req;
reg pixelbuf_rreq;
reg ivdat_buf_rreq;
reg [7:0] iR, iG, iB, iRa, iGa, iBa;
 
// output decoder
always@(c_state or pixel_buffer_empty or colcnt or DataBuffer or RGB_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
always@(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
begin : output_decoder
 
// initial values
pixelbuf_rreq = 1'b0;
ivdat_buf_rreq = 1'b0;
RGBbuf_wreq = 1'b0;
iclut_req = 1'b0;
235,20 → 239,40
 
case (c_state) // synopsis full_case parallel_case
idle:
if (!pixel_buffer_empty)
pixelbuf_rreq = 1'b1;
begin
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
 
// when entering from 8bpp_pseudo_color_mode
RGBbuf_wreq = clut_ack;
 
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
end
 
fill_buf:
begin
// when entering from 8bpp_pseudo_color_mode
RGBbuf_wreq = clut_ack;
 
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
end
 
//
// 8 bits per pixel
//
bw_8bpp:
begin
if (!RGB_fifo_full)
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
 
if ( (!pixel_buffer_empty) && !(|colcnt) )
pixelbuf_rreq = 1'b1;
if ( (!vdat_buffer_empty) && !(|colcnt) )
ivdat_buf_rreq = 1'b1;
end
 
case (colcnt) // synopsis full_case parallel_case
284,22 → 308,22
 
col_8bpp:
begin
if (!RGB_fifo_full & clut_ack)
begin
RGBbuf_wreq = 1'b1;
// do NOT check for rgb_fifo_full here, because in 8bpp_pc mode
// the color-processor always finishes the current 4pixel-block
// i.e. it runs until colcnt = '11'.
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
if (!(|colcnt))
if (!vdat_buffer_empty && !(|colcnt) )
ivdat_buf_rreq = 1'b1;
 
if ( (!pixel_buffer_empty) && !(|colcnt) )
pixelbuf_rreq = 1'b1;
end
RGBbuf_wreq = clut_ack;
 
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
 
iclut_req = ~RGB_fifo_full;
 
if ( !(|colcnt) && clut_ack)
iclut_req =1'b0;
iclut_req = !rgb_fifo_full || (colcnt[1] ^ colcnt[0]);
end
 
//
307,7 → 331,7
//
col_16bpp_a:
begin
if (!RGB_fifo_full)
if (!rgb_fifo_full)
RGBbuf_wreq = 1'b1;
 
iR[7:3] = DataBuffer[31:27];
317,12 → 341,12
 
col_16bpp_b:
begin
if (!RGB_fifo_full)
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
 
if (!pixel_buffer_empty)
pixelbuf_rreq = 1'b1;
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
 
iR[7:3] = DataBuffer[15:11];
335,12 → 359,12
//
col_24bpp:
begin
if (!RGB_fifo_full)
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
 
if ( (colcnt != 2'h1) && !pixel_buffer_empty)
pixelbuf_rreq = 1'b1;
if ( (colcnt != 2'h1) && !vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
 
 
386,12 → 410,12
//
col_32bpp:
begin
if (!RGB_fifo_full)
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
 
if (!pixel_buffer_empty)
pixelbuf_rreq = 1'b1;
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
 
iR[7:0] = DataBuffer[23:16];
405,9 → 429,9
// generate output registers
always@(posedge clk)
begin
R <= #1 iR;
G <= #1 iG;
B <= #1 iB;
r <= #1 iR;
g <= #1 iG;
b <= #1 iB;
 
if (RGBbuf_wreq)
begin
418,14 → 442,14
 
if (srst)
begin
pixel_buffer_rreq <= #1 1'b0;
RGB_fifo_wreq <= #1 1'b0;
vdat_buffer_rreq <= #1 1'b0;
rgb_fifo_wreq <= #1 1'b0;
clut_req <= #1 1'b0;
end
else
begin
pixel_buffer_rreq <= #1 pixelbuf_rreq;
RGB_fifo_wreq <= #1 RGBbuf_wreq;
vdat_buffer_rreq <= #1 ivdat_buf_rreq;
rgb_fifo_wreq <= #1 RGBbuf_wreq;
clut_req <= #1 iclut_req;
end
end
451,3 → 475,16
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/vga_wb_slave.v
1,6 → 1,6
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant VGA/LCD Core; Wishbone Slave ////
//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
//// Wishbone slave interface ////
//// ////
//// Author: Richard Herveille ////
11,7 → 11,7
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_slave.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_wb_slave.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
50,9 → 50,12
 
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
 
//
79,17 → 82,34
reg INTA_O;
 
// control register settings
output bl; // blanking level
output csl; // composite sync level
output vsl; // vsync level
output hsl; // hsync level
output pc; // pseudo color
output bl; // blanking level
output csl; // composite sync level
output vsl; // vsync level
output hsl; // hsync level
output pc; // pseudo color
output [1:0] cd; // color depth
output [1:0] vbl; // video memory burst length
output cbsw; // clut bank switch enable
output vbsw; // video memory bank switch enable
output ven; // vdeio system enable
output cbsw; // clut bank switch enable
output vbsw; // video memory bank switch enable
output ven; // video system enable
 
// hardware cursor settings
output cursor0_en;
output [31: 0] cursor0_xy;
output [31:11] cursor0_ba; // cursor0 base address
output cursor0_ld; // reload cursor0 from video memory
output cursor1_en;
output [31: 0] cursor1_xy;
output [31:11] cursor1_ba; // cursor1 base address
output cursor1_ld; // reload cursor1 from video memory
 
reg [31: 0] cursor0_xy;
reg [31:11] cursor0_ba;
reg cursor0_ld;
reg [31: 0] cursor1_xy;
reg [31:11] cursor1_ba;
reg cursor1_ld;
 
// status register inputs
input avmp; // active video memory page
input acmp; // active clut memory page
113,10 → 133,10
output [15:0] Tvlen;
 
// video base addresses
output [31: 2] VBARa;
reg [31: 2] VBARa;
output [31: 2] VBARb;
reg [31: 2] VBARb;
output [31:2] VBARa;
reg [31:2] VBARa;
output [31:2] VBARb;
reg [31:2] VBARb;
 
// color lookup table signals
output clut_acc;
127,18 → 147,24
//
// variable declarations
//
wire [2:0] REG_ADR = ADR_I[4:2];
wire CLUT_ADR = ADR_I[11];
parameter REG_ADR_HIBIT = 3;
 
parameter [2:0] CTRL_ADR = 3'b000;
parameter [2:0] STAT_ADR = 3'b001;
parameter [2:0] HTIM_ADR = 3'b010;
parameter [2:0] VTIM_ADR = 3'b011;
parameter [2:0] HVLEN_ADR = 3'b100;
parameter [2:0] VBARA_ADR = 3'b101;
parameter [2:0] VBARB_ADR = 3'b110;
wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];
wire CLUT_ADR = ADR_I[11];
 
parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;
parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;
parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;
parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;
parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;
parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;
parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
 
 
reg [31:0] ctrl, stat, htim, vtim, hvlen;
wire hint, vint, vbsint, cbsint, luint, sint;
wire hie, vie, vbsie, cbsie;
185,14 → 211,23
end
else if (reg_wacc)
case (ADR_I) // synopsis full_case parallel_case
HTIM_ADR : htim <= #1 DAT_I;
VTIM_ADR : vtim <= #1 DAT_I;
HVLEN_ADR : hvlen <= #1 DAT_I;
VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
HTIM_ADR : htim <= #1 DAT_I;
VTIM_ADR : vtim <= #1 DAT_I;
HVLEN_ADR : hvlen <= #1 DAT_I;
VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];
C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];
C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
endcase
end
 
always@(posedge CLK_I)
begin
cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
end
 
// generate control register
always@(posedge CLK_I or negedge nRESET)
217,8 → 252,20
stat <= #1 0;
else
begin
`ifdef VGA_HWC1
stat[21] <= #1 1'b1;
`else
stat[21] <= #1 1'b0;
`endif
`ifdef VGA_HWC0
stat[20] <= #1 1'b1;
`else
stat[20] <= #1 1'b0;
`endif
 
stat[17] <= #1 acmp;
stat[16] <= #1 avmp;
 
if (reg_wacc & (REG_ADR == STAT_ADR) )
begin
stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
241,20 → 288,22
 
 
// decode control register
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
assign cursor1_en = ctrl[21];
assign cursor0_en = ctrl[20];
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
 
// decode status register
assign cbsint = stat[7];
287,6 → 336,10
HVLEN_ADR : reg_dato = hvlen;
VBARA_ADR : reg_dato = {VBARa, 2'b0};
VBARB_ADR : reg_dato = {VBARb, 2'b0};
C0XY_ADR : reg_dato = cursor0_xy;
C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
C1XY_ADR : reg_dato = cursor1_xy;
C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
default : reg_dato = 32'h0000_0000;
endcase
 
298,3 → 351,4
INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule
 
 
/trunk/rtl/verilog/vga_csm_pb.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_csm_pb.v,v 1.5 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_csm_pb.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.5 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
141,5 → 141,3
assign ack0_o = ( (sel0 && we0_i) || ack0 );
assign ack1_o = ( (sel1 && we1_i) || ack1 );
endmodule
 
 
/trunk/rtl/verilog/vga_ssel.v
0,0 → 1,199
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
//// Video source selector / Hardware cursor block ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: vga_ssel.v,v 1.1 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
 
`include "timescale.v"
 
module vga_ssel (clk, rst_i, Thgate, Tvgate, idat, idat_wreq,
cursor_xy, cursor_en, cursor_adr, cursor_dat, cursor_we,
rgb_fifo_wreq, rgb);
 
//
// inputs & outputs
//
 
// wishbone signals
input clk; // master clock input
input rst_i; // synchronous active high reset
 
// image size
input [15:0] Thgate, Tvgate; // horizontal/vertical gate
// image data
input [23:0] idat; // image data input
input idat_wreq; // image data write request
 
// cursor data
input [31:0] cursor_xy; // cursor (x,y)
input cursor_en; // cursor enable (on/off)
input [ 8:0] cursor_adr; // cursor address
input [31:0] cursor_dat; // cursor data
input cursor_we; // write enable
 
// rgb-fifo connections
output rgb_fifo_wreq; // rgb-out write request
reg rgb_fifo_wreq;
output [23:0] rgb; // rgb data output
reg [23:0] rgb;
 
//
// variable declarations
//
reg dcursor_en;
reg [15:0] xcnt, ycnt;
wire xdone, ydone;
wire [15:0] cursor_x, cursor_y;
wire cursor_transparent;
wire [ 7:0] cursor_r, cursor_g, cursor_b;
reg inbox_x, inbox_y;
wire inbox;
reg [23:0] didat;
reg store_one;
wire [31:0] cmem_q;
reg [ 9:0] cmem_ra;
wire [ 8:0] cmem_a;
 
//
// module body
//
 
// generate x-y counters
always@(posedge clk)
if(rst_i || xdone)
xcnt <= #1 16'h0;
else if (idat_wreq)
xcnt <= #1 xcnt + 16'h1;
 
assign xdone = (xcnt == Thgate) && idat_wreq;
 
always@(posedge clk)
if(rst_i || ydone)
ycnt <= #1 16'h0;
else if (xdone)
ycnt <= #1 ycnt + 16'h1;
 
assign ydone = (ycnt == Tvgate) && idat_wreq;
 
 
// decode cursor (x,y)
assign cursor_x = cursor_xy[15: 0];
assign cursor_y = cursor_xy[31:16];
 
 
// generate inbox signals
always@(posedge clk)
begin
inbox_x <= #1 (xcnt >= cursor_x) && (xcnt < (cursor_x +16'h1f) );
inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y +16'h1f) );
end
 
assign inbox = inbox_x && inbox_y;
 
 
// hookup local cursor memory (generic synchronous single port memory)
// cursor memory should never be written to/read from at the same time
generic_spram #(9, 32) cmem(
.clk(clk),
.rst(1'b0), // no reset
.ce(1'b1), // always enable memory
.we(cursor_we),
.oe(1'b1), // always output data
.addr(cmem_a),
.di(cursor_dat),
.do(cmem_q)
);
 
assign cmem_a = cursor_we ? cursor_adr : cmem_ra[9:1];
 
 
// decode cursor data
assign cursor_transparent = cmem_ra[0] ? cmem_q[31] : cmem_q[15];
assign cursor_r = cmem_ra[0] ? {cmem_q[30:26], 3'h0} : {cmem_q[14:10], 3'h0};
assign cursor_g = cmem_ra[0] ? {cmem_q[25:21], 3'h0} : {cmem_q[ 9: 5], 3'h0};
assign cursor_b = cmem_ra[0] ? {cmem_q[20:16], 3'h0} : {cmem_q[ 4: 0], 3'h0};
 
 
// delay image data
always@(posedge clk)
if (idat_wreq)
didat <= #1 idat;
 
 
// generate selection unit
always@(posedge clk)
dcursor_en <= #1 cursor_en;
 
always@(posedge clk)
if (idat_wreq)
if (!dcursor_en || !inbox)
rgb <= #1 didat;
else if (cursor_transparent)
rgb <= #1 didat;
else
rgb <= #1 {cursor_r, cursor_g, cursor_b};
 
 
// generate write request signal
always@(posedge clk)
if (rst_i)
store_one <= #1 1'b0;
else if (idat_wreq)
store_one <= #1 1'b1;
 
always@(posedge clk)
rgb_fifo_wreq <= #1 idat_wreq & store_one;
 
 
// generate cursor address counter
always@(posedge clk)
if (!cursor_en || ydone)
cmem_ra <= #1 10'h0;
else if (inbox && idat_wreq)
cmem_ra <= #1 cmem_ra +10'h1;
 
endmodule
/trunk/rtl/verilog/vga_defines.v
1,8 → 1,8
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant VGA/LCD Core; Defines file ////
//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
//// Defines file ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
11,8 → 11,8
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_defines.v,v 1.3 2002-01-28 03:47:16 rherveille Exp $
// $Id: vga_defines.v,v 1.4 2002-02-07 05:42:10 rherveille Exp $
//
// $Date: 2002-01-28 03:47:16 $
// $Revision: 1.3 $
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
54,3 → 54,9
//
 
`define VENDOR_FPGA
 
//
// enable / disable hardware cursors
//
//`define VGA_HWC0
//`define VGA_HWC1

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