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https://opencores.org/ocsvn/eco32/eco32/trunk
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Rev 296 → Rev 297
/eco32/trunk/fpga/experiments/memdelay/memdelay.v
0,0 → 1,124
// |
// memdelay.v -- test memory delay |
// |
|
|
`timescale 1ns/10ps |
`default_nettype none |
|
|
module memdelay; |
|
reg clk; |
reg rst_in; |
reg rst; |
reg stb; |
reg we; |
wire [22:0] addr; |
wire [31:0] data_in; |
wire [31:0] data_out; |
wire ack; |
reg [5:0] state; |
reg [5:0] next_state; |
|
initial begin |
#0 $dumpfile("dump.vcd"); |
$dumpvars(0, memdelay); |
clk = 1; |
rst_in = 1; |
#25 rst_in = 0; |
#1000 $finish; |
end |
|
always begin |
#10 clk = ~ clk; |
end |
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always @(posedge clk) begin |
rst <= rst_in; |
end |
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assign addr[22:0] = 23'h123456; |
assign data_in[31:0] = 32'h12345678; |
|
ram ram_1( |
.clk(clk), |
.rst(rst), |
.stb(stb), |
.we(we), |
.addr(addr[22:0]), |
.data_in(data_in[31:0]), |
.data_out(data_out[31:0]), |
.ack(ack) |
); |
|
always @(posedge clk) begin |
if (rst) begin |
state <= 0; |
end else begin |
state <= next_state; |
end |
end |
|
always @(*) begin |
case (state[5:0]) |
6'h0: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h1; |
end |
6'h1: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h2; |
end |
6'h2: |
begin |
stb = 1; |
we = 0; |
if (ack) begin |
next_state = 6'h3; |
end else begin |
next_state = 6'h2; |
end |
end |
6'h3: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h4; |
end |
6'h4: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h5; |
end |
6'h5: |
begin |
stb = 1; |
we = 1; |
if (ack) begin |
next_state = 6'h6; |
end else begin |
next_state = 6'h5; |
end |
end |
6'h6: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h6; |
end |
default: |
begin |
stb = 0; |
we = 0; |
next_state = 6'h0; |
end |
endcase |
end |
|
endmodule |
/eco32/trunk/fpga/experiments/memdelay/ram.v
0,0 → 1,72
// |
// ram.v -- simulate external RAM |
// 8M x 32 bit = 32 MB |
// |
|
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`timescale 1ns/10ps |
`default_nettype none |
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// |
// use this set of parameters for minimal access times |
// |
//`define RD_CYCLES 4'd2 // # cycles for read, min = 2 |
//`define WR_CYCLES 4'd2 // # cycles for write, min = 2 |
|
// |
// use this set of parameters for realistic access times |
// |
`define RD_CYCLES 4'd14 // # cycles for read, min = 2 |
`define WR_CYCLES 4'd6 // # cycles for write, min = 2 |
|
|
module ram(clk, rst, |
stb, we, addr, |
data_in, data_out, ack); |
input clk; |
input rst; |
input stb; |
input we; |
input [24:2] addr; |
input [31:0] data_in; |
output reg [31:0] data_out; |
output ack; |
|
reg [31:0] mem[0:8388607]; |
reg [3:0] counter; |
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always @(posedge clk) begin |
if (stb) begin |
if (we) begin |
// write cycle |
mem[addr] <= data_in; |
end else begin |
// read cycle |
data_out <= mem[addr]; |
end |
end |
end |
|
always @(posedge clk) begin |
if (rst) begin |
counter[3:0] <= 4'h0; |
end else begin |
if (counter[3:0] == 4'h0) begin |
if (stb & ~we) begin |
// a read may need some clock cycles |
counter <= `RD_CYCLES - 1; |
end |
if (stb & we) begin |
// a write may need some clock cycles |
counter <= `WR_CYCLES - 1; |
end |
end else begin |
counter[3:0] <= counter[3:0] - 1; |
end |
end |
end |
|
assign ack = (counter[3:0] == 4'h1) ? 1 : 0; |
|
endmodule |
/eco32/trunk/fpga/experiments/memdelay/memdelay.cfg
0,0 → 1,10
[timestart] 0 |
[size] 1280 725 |
[pos] -1 -1 |
*-16.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
@28 |
memdelay.clk |
memdelay.rst |
memdelay.stb |
memdelay.we |
memdelay.ack |
/eco32/trunk/fpga/experiments/memdelay/Makefile
0,0 → 1,15
# |
# Makefile for testing the memory delay |
# |
|
all: show |
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show: memdelay |
./memdelay |
gtkwave dump.vcd memdelay.cfg |
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memdelay: memdelay.v ram.v |
iverilog -Wall -o memdelay memdelay.v ram.v |
|
clean: |
rm -f *~ memdelay dump.vcd |
/eco32/trunk/fpga/experiments/memdelay/README
0,0 → 1,3
This circuit implements a RAM simulation with adjustable |
read/write delays. The test FSM allows verifying both |
access times. |