Subversion Repositories t48

/t48/rel_1_2/COPYING File deleted

/t48/rel_1_2/sim/rtl_sim/Makefile.ghdl File deleted

/t48/rel_1_2/sim/rtl_sim/Makefile.hier File deleted

/t48/rel_1_2/sw/dump_compare.signals File deleted

/t48/rel_1_2/sw/verif/black_box/da/test.asm File deleted

t48/rel_1_2/sw/verif/black_box/da/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jmp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jmp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jmp/test.asm (nonexistent) @@ -1,11 +0,0 @@ - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jmp pass - FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/jmp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/add/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/add/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/add/rr/test.asm (nonexistent) @@ -1,106 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADD A, Rr without carry, RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - ;; fill RB0 - call fill - - ;; check RB0 - sel rb0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - - -check: mov a, #002H - add a, r0 - jnz fail_p3 - - mov a, #003H - add a, r1 - jnz fail_p3 - - mov a, #005H - add a, r2 - jnz fail_p3 - - mov a, #009H - add a, r3 - jnz fail_p3 - - mov a, #011H - add a, r4 - jnz fail_p3 - - mov a, #021H - add a, r5 - jnz fail_p3 - - mov a, #041H - add a, r6 - jnz fail_p3 - - mov a, #081H - add a, r7 - jnz fail_p3 - - ret - - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/add/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/add/a_data/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/add/a_data/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/add/a_data/test.asm (nonexistent) @@ -1,82 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADD A, data without carry. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - - add a, #055H - jz fail - ;; exact check for 055H - jb0 ok_1 - jmp fail - -ok_1: jb1 fail - - jb2 ok_2 - jmp fail - -ok_2: jb3 fail - - jb4 ok_4 - jmp fail - -ok_4: jb5 fail - - jb6 ok_6 - jmp fail - -ok_6: jb7 fail - - add a, #0AAH - jz fail - add a, #001H - jnz fail - - add a, #011111110B - jb0 fail - - add a, #011111111B - jb1 fail - jb0 ko_1 - jmp fail - -ko_1: add a, #011111110B - jb2 fail - jb1 ko_2 - jmp fail - -ko_2: add a, #011111100B - jb3 fail - jb2 ko_3 - jmp fail - -ko_3: add a, #011111000B - jb4 fail - jb3 ko_4 - jmp fail - -ko_4: add a, #011110000B - jb5 fail - jb4 ko_5 - jmp fail - -ko_5: add a, #011100000B - jb6 fail - jb5 ko_6 - jmp fail - -ko_6: add a, #011000000B - jb7 fail - jb6 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/add/a_data/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/add/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/add/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/add/ind_rr/test.asm (nonexistent) @@ -1,129 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADD A, @ Rr without carry. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - ;; - mov r0, #010H - mov r1, #020H - mov a, #002H - add a, @r0 - jnz fail - mov a, #002H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #003H - add a, @r0 - jnz fail - mov a, #003H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #005H - add a, @r0 - jnz fail - mov a, #005H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #009H - add a, @r0 - jnz fail - mov a, #009H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #011H - add a, @r0 - jnz fail - mov a, #011H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #021H - add a, @r0 - jnz fail - mov a, #021H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #041H - add a, @r0 - jnz fail - mov a, #041H - add a, @r1 - jnz fail - - inc r0 - inc r1 - mov a, #081H - add a, @r0 - jnz fail - mov a, #081H - add a, @r1 - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/add/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/tim/int/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/tim/int/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tim/int/test.asm (nonexistent) @@ -1,41 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Timer Interrupt. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - jmp start - nop - jmp fail - jmp fail - jmp timer_int - jmp fail - - ;; Start of test -start: mov a, #0F8H - mov t, a - clr a - mov r0, a - mov r1, a - - en tcnti - jtf fail - - strt t - -loop: mov a, r0 - jnz pass - djnz r1, loop - -fail: FAIL - -pass: PASS - - -timer_int: - mov r0, #0FFH - retr

t48/rel_1_2/sw/verif/black_box/tim/int/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/tim/int/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/tim/int/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tim/int/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -Modelling accuracy of interrupts is not sufficient for 1:1 dump compare. Index: t48/rel_1_2/sw/verif/black_box/tim/t/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/tim/t/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tim/t/test.asm (nonexistent) @@ -1,110 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Timer. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0F8H - mov t, a - - strt t - jtf fail - - mov r0, #000H -poll1: jtf goon1 - djnz r0, poll1 - jmp fail - -goon1: mov a, t - jnz fail - mov r0, #000H -poll2: mov a, t - add a, #0FBH - jz goon2 - djnz r0, poll2 - -goon2: stop tcnt - clr a - mov t, a - strt t - - mov a, t - jnz fail - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - mov a, t - dec a - jnz fail - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - mov a, t - dec a - dec a - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/tim/t/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jc/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jc/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jc/test.asm (nonexistent) @@ -1,20 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JC instruction. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jc fail - mov a, #0FFH - add a, #001H - jc pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/jc/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_1/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_1/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_1/test.asm (nonexistent) @@ -1,34 +0,0 @@ - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - jb0 ok_0 - jmp fail - -ok_0: jb1 ok_1 - jmp fail - -ok_1: jb2 ok_2 - jmp fail - -ok_2: jb3 ok_3 - jmp fail - -ok_3: jb4 ok_4 - jmp fail - -ok_4: jb5 ok_5 - jmp fail - -ok_5: jb6 ok_6 - jmp fail - -ok_6: jb7 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_1/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jbb/jbb_55/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jbb/jbb_55/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jbb/jbb_55/test.asm (nonexistent) @@ -1,36 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test the JBb instruction on 055H. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #055H - jb0 ok_0 - jmp fail - -ok_0: jb1 fail - - jb2 ok_2 - jmp fail - -ok_2: jb3 fail - - jb4 ok_4 - jmp fail - -ok_4: jb5 fail - - jb6 ok_6 - jmp fail - -ok_6: jb7 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/jbb/jbb_55/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jbb/jbb_aa/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jbb/jbb_aa/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jbb/jbb_aa/test.asm (nonexistent) @@ -1,35 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test the JBb instruction on 0AAH. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0AAH - jb0 fail - - jb1 ok_1 - jmp fail - -ok_1: jb2 fail - - jb3 ok_3 - jmp fail - -ok_3: jb4 fail - - jb5 ok_5 - jmp fail - -ok_5: jb6 fail - - jb7 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/jbb/jbb_aa/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_0/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_0/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_0/test.asm (nonexistent) @@ -1,20 +0,0 @@ - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - jb0 fail - jb1 fail - jb2 fail - jb3 fail - jb4 fail - jb5 fail - jb6 fail - jb7 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/jbb/jbb_all_0/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orld/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orld/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orld/test.asm (nonexistent) @@ -1,109 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORLD. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; port 4 - mov a, #000h - movd p4, a - mov a, #001h - orld p4, a - cpl a - movd a, p6 - xrl a, #001h - jnz fail - movd a, p4 - xrl a, #001h - jnz fail - - mov a, #00eh - orld p4, a - movd a, p6 - xrl a, #00fh - jnz fail - movd a, p4 - xrl a, #00fh - jnz fail - - ;; port 5 - mov a, #000h - movd p5, a - mov a, #006h - orld p5, a - cpl a - movd a, p7 - xrl a, #006h - jnz fail - movd a, p5 - xrl a, #006h - jnz fail - - mov a, #003h - orld p5, a - movd a, p7 - xrl a, #007h - jnz fail - movd a, p5 - xrl a, #007h - jnz fail - - ;; port 6 - mov a, #000h - movd p6, a - mov a, #009h - orld p6, a - cpl a - movd a, p4 - xrl a, #009h - jnz fail - movd a, p6 - xrl a, #009h - jnz fail - - mov a, #006h - orld p6, a - movd a, p4 - xrl a, #00fh - jnz fail - movd a, p6 - xrl a, #00fh - jnz fail - jmp pass - - ;; port 7 - mov a, #000h - movd p7, a - mov a, #004h - orld p7, a - cpl a - movd a, p5 - xrl a, #004h - jnz fail - movd a, p7 - xrl a, #004h - jnz fail - - mov a, #00ah - orld p7, a - movd a, p5 - xrl a, #00eh - jnz fail - movd a, p7 - xrl a, #00eh - jnz fail - - - jmp pass - - jmp fail -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/orld/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm (nonexistent) @@ -1,59 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOV Rr, A for RB0 with 2*r. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - - mov a, #000H - - mov a, r0 - jz fail - jb0 fail - - mov a, r1 - jb1 fail - - mov a, r2 - jb2 fail - - mov a, r3 - jb3 fail - - mov a, r4 - jb4 fail - - mov a, r5 - jb5 fail - - mov a, r6 - jb6 fail - - mov a, r7 - jb7 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_00/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_00/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_00/test.asm (nonexistent) @@ -1,78 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOV Rr, A for RB0 with 0x00. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #00H - mov r0, a - mov a, #0FFH - mov r1, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - - mov a, r0 - jnz fail - - mov a, #000H - mov r1, a - mov a, #0FFH - mov r0, a - mov a, r1 - jnz fail - - mov a, #000H - mov r2, a - mov a, #0FFH - mov r1, a - mov a, r2 - jnz fail - - mov a, #000H - mov r3, a - mov a, #0FFH - mov r2, a - mov a, r3 - jnz fail - - mov a, #000H - mov r4, a - mov a, #0FFH - mov r3, a - mov a, r4 - jnz fail - - mov a, #000H - mov r5, a - mov a, #0FFH - mov r4, a - mov a, r5 - jnz fail - - mov a, #000H - mov r6, a - mov a, #0FFH - mov r5, a - mov a, r6 - jnz fail - - mov a, #000H - mov r7, a - mov a, #0FFH - mov r6, a - mov a, r7 - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/mov/mov_rr_a/data_00/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mov/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mov/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mov/ind_rr/test.asm (nonexistent) @@ -1,185 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOV @ Rr for RB0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov r0, #0FFH -fill_loop: - mov a, r0 - mov @r0, a - djnz r0, fill_loop - - ;; check memory - mov a, r0 - jnz fail - mov r0, #0FFH -check_loop1: - mov a, @r1 - add a, r0 - jnz fail - dec r0 - inc r1 - mov a, r1 - jnz check_loop1 - jmp test_2 - -fail: FAIL - - ;; - ALIGN 256 - ;; - -test_2: ;; test MOV @ Rr, data - mov r0, #0C0H - mov r1, #0E0H - mov @r0, #000H - mov @r1, #020H - - inc r0 - inc r1 - mov @r0, #001H - mov @r1, #021H - inc r0 - inc r1 - mov @r0, #002H - mov @r1, #022H - inc r0 - inc r1 - mov @r0, #003H - mov @r1, #023H - inc r0 - inc r1 - mov @r0, #004H - mov @r1, #024H - inc r0 - inc r1 - mov @r0, #005H - mov @r1, #025H - inc r0 - inc r1 - mov @r0, #006H - mov @r1, #026H - inc r0 - inc r1 - mov @r0, #007H - mov @r1, #027H - inc r0 - inc r1 - mov @r0, #008H - mov @r1, #028H - inc r0 - inc r1 - mov @r0, #009H - mov @r1, #029H - inc r0 - inc r1 - mov @r0, #00AH - mov @r1, #02AH - inc r0 - inc r1 - mov @r0, #00BH - mov @r1, #02BH - inc r0 - inc r1 - mov @r0, #00CH - mov @r1, #02CH - inc r0 - inc r1 - mov @r0, #00DH - mov @r1, #02DH - inc r0 - inc r1 - mov @r0, #00EH - mov @r1, #02EH - inc r0 - inc r1 - mov @r0, #00FH - mov @r1, #02FH - ;; - inc r0 - inc r1 - mov @r0, #010H - mov @r1, #030H - inc r0 - inc r1 - mov @r0, #011H - mov @r1, #031H - inc r0 - inc r1 - mov @r0, #012H - mov @r1, #032H - inc r0 - inc r1 - mov @r0, #013H - mov @r1, #033H - inc r0 - inc r1 - mov @r0, #014H - mov @r1, #034H - inc r0 - inc r1 - mov @r0, #015H - mov @r1, #035H - inc r0 - inc r1 - mov @r0, #016H - mov @r1, #036H - inc r0 - inc r1 - mov @r0, #017H - mov @r1, #037H - inc r0 - inc r1 - mov @r0, #018H - mov @r1, #038H - inc r0 - inc r1 - mov @r0, #019H - mov @r1, #039H - inc r0 - inc r1 - mov @r0, #01AH - mov @r1, #03AH - inc r0 - inc r1 - mov @r0, #01BH - mov @r1, #03BH - inc r0 - inc r1 - mov @r0, #01CH - mov @r1, #03CH - inc r0 - inc r1 - mov @r0, #01DH - mov @r1, #03DH - inc r0 - inc r1 - mov @r0, #01EH - mov @r1, #03EH - inc r0 - inc r1 - mov @r0, #01FH - mov @r1, #03FH - - mov r0, #0FFH - mov r1, #11000001B -check_loop2: - mov a, @r0 - add a, r1 - jnz fail2 - inc r1 - dec r0 - mov a, #01000000B - add a, r0 - jnz check_loop2 - -pass2: PASS - -fail2: FAIL

t48/rel_1_2/sw/verif/black_box/mov/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_num/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_num/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_num/test.asm (nonexistent) @@ -1,50 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOV A, Rr for RB0 with 2*r. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - mov r0, #0FEH - mov r1, #0FDH - mov r2, #0FBH - mov r3, #0F7H - mov r4, #0EFH - mov r5, #0DFH - mov r6, #0BFH - mov r7, #07FH - - mov a, r0 - jz fail - jb0 fail - - mov a, r1 - jb1 fail - - mov a, r2 - jb2 fail - - mov a, r3 - jb3 fail - - mov a, r4 - jb4 fail - - mov a, r5 - jb5 fail - - mov a, r6 - jb6 fail - - mov a, r7 - jb7 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_num/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_00/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_00/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_00/test.asm (nonexistent) @@ -1,63 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOV A, Rr for RB0 with 0x00. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #055H - mov r0, #000H - mov r1, #0FFH - mov r2, #0FFH - mov r3, #0FFH - mov r4, #0FFH - mov r5, #0FFH - mov r6, #0FFH - mov r7, #0FFH - - mov a, r0 - jnz fail - - mov r1, #000H - mov r0, #0FFH - mov a, r1 - jnz fail - - mov r2, #000H - mov r1, #0FFH - mov a, r2 - jnz fail - - mov r3, #000H - mov r2, #0FFH - mov a, r3 - jnz fail - - mov r4, #000H - mov r3, #0FFH - mov a, r4 - jnz fail - - mov r5, #000H - mov r4, #0FFH - mov a, r5 - jnz fail - - mov r6, #000H - mov r5, #0FFH - mov a, r6 - jnz fail - - mov r7, #000H - mov r6, #0FFH - mov a, r7 - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/mov/a_rr/data_00/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/rb/misc/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/rb/misc/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/rb/misc/test.asm (nonexistent) @@ -1,142 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test several operations in conjunction with RB-switching. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill data memory with 0 - clr a - mov r0, a -fill_loop: - mov @r0, a - djnz r0, fill_loop - - ;; set up both register banks with indirect writes - mov r0, #01FH - mov r1, #008H -fill_rb1_loop: - mov a, r0 - mov @r0, a - dec r0 - djnz r1, fill_rb1_loop - - mov r0, #007H -fill_rb0_loop: - mov a, r0 - mov @r0, a - djnz r0, fill_rb0_loop - mov a, r0 - mov @r0, a - - ;; check RB0 - call check_rb0 - - ;; check RB1 - sel rb1 - call check_rb1 - - ;; check RB0 again - sel rb0 - call check_rb0 - - ;; check memory between RB0 and RB1 for 0 - mov r0, #00EH ; check 14 bytes - mov r1, #00AH ; starting from address A -chk_loop1: - mov a, @r1 - jnz fail - inc r1 - djnz r0, chk_loop1 - - ;; check memory above RB1 for 0 - mov r0, #0100H - 0020H ; check 256-32 bytes - mov r1, #020H ; starting from address 20H -chk_loop2: - mov a, @r1 - jnz fail - inc r1 - djnz r0, chk_loop2 - - ;; now use RB1 to indirect address register 0-7 - mov r1, #001H ; restore r1 - mov r0, #000H ; restore r0, set trap - sel rb1 - mov r0, #007H -ind_chk_loop: - mov a, @r0 - cpl a - add a, r0 - cpl a - jnz fail - djnz r0, ind_chk_loop - - -pass: PASS - -fail: FAIL - - - - ORG 0300H -check_rb0: - mov a, r0 - jnz fail_p3 - mov a,r1 - add a, #0FFH - jnz fail_p3 - mov a,r2 - add a, #0FEH - jnz fail_p3 - mov a,r3 - add a, #0FDH - jnz fail_p3 - mov a,r4 - add a, #0FCH - jnz fail_p3 - mov a,r5 - add a, #0FBH - jnz fail_p3 - mov a,r6 - add a, #0FAH - jnz fail_p3 - mov a,r7 - add a, #0F9H - jnz fail_p3 - ret - -check_rb1: - mov a, r0 - add a, #0E8H - jnz fail_p3 - mov a,r1 - add a, #0E7H - jnz fail_p3 - mov a,r2 - add a, #0E6H - jnz fail_p3 - mov a,r3 - add a, #0E5H - jnz fail_p3 - mov a,r4 - add a, #0E4H - jnz fail_p3 - mov a,r5 - add a, #0E3H - jnz fail_p3 - mov a,r6 - add a, #0E2H - jnz fail_p3 - mov a,r7 - add a, #0E1H - jnz fail_p3 - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/rb/misc/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/rb/int/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/rb/int/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/rb/int/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -Modelling accuracy of interrupts is not sufficient for 1:1 dump compare. Index: t48/rel_1_2/sw/verif/black_box/rb/int/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/rb/int/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/rb/int/test.asm (nonexistent) @@ -1,228 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test interrupts in conjunction with RB-switching. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - jmp start - nop - jmp interrupt - jmp fail - jmp fail - jmp fail - - - ;; Start of test -start: - ;; fill RB0 - clr a - call fill - - ;; fill RB1 - sel rb1 - mov a, #010H - call fill - sel rb0 - - ;; set up interrupt - clr f1 - ;; sync on next interrupt - call sync_on_int - - mov r0, #000H - en i -loop1: jf1 goon1 - djnz r0, loop1 - jmp fail - -goon1: - dis i - clr f1 - - ;; check BS implicitely - ;; r0 must not be zero - mov a, r0 - jz fail - - ;; check RB1 - sel rb1 - call check_0 - - ;; check RB0 - sel rb0 - call check_rb0 - -pass: PASS - -fail: FAIL - - - ORG 0200H -interrupt: - sel rb1 - mov r0, a - - call check_rb1 - - clr a - mov r1, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - xch a, r0 - - cpl f1 - - retr - - - ORG 0300H - -fill: add a, #0B0H - mov r0, a - inc a - mov r1, a - inc a - mov r2, a - inc a - mov r3, a - inc a - mov r4, a - inc a - mov r5, a - inc a - mov r6, a - inc a - mov r7, a - ret - -check_0: - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - ret - - ;; synchronize on interrupt - ;; use r7 for timeout detection -sync_on_int: - mov a, r7 ; save r7 - mov r7, #000H -wait_int1: - jni sync_on_int2 - djnz r7, wait_int1 - jmp fail_p3 - -sync_on_int2: - mov r7, #000H -wait_int2: - jni still_int - mov r7, a ; restore r7 - call clr_int - retr -still_int: - djnz r7, wait_int2 - jmp fail_p3 - -clr_int: - ;; clear latched interrupt request with RETR! - retr - -check_rb1: - mov a, #(~0C1H & 0FFH) - add a, r1 - cpl a - jnz fail_p3 - - mov a, #(~0C2H & 0FFH) - add a, r2 - cpl a - jnz fail_p3 - - mov a, #(~0C3H & 0FFH) - add a, r3 - cpl a - jnz fail_p3 - - mov a, #(~0C4H & 0FFH) - add a, r4 - cpl a - jnz fail_p3 - - mov a, #(~0C5H & 0FFH) - add a, r5 - cpl a - jnz fail_p3 - - mov a, #(~0C6H & 0FFH) - add a, r6 - cpl a - jnz fail_p3 - - mov a, #(~0C7H & 0FFH) - add a, r7 - cpl a - jnz fail_p3 - - ret - -check_rb0: - mov a, #(~0B1H & 0FFH) - add a, r1 - cpl a - jnz fail_p3 - - mov a, #(~0B2H & 0FFH) - add a, r2 - cpl a - jnz fail_p3 - - mov a, #(~0B3H & 0FFH) - add a, r3 - cpl a - jnz fail_p3 - - mov a, #(~0B4H & 0FFH) - add a, r4 - cpl a - jnz fail_p3 - - mov a, #(~0B5H & 0FFH) - add a, r5 - cpl a - jnz fail_p3 - - mov a, #(~0B6H & 0FFH) - add a, r6 - cpl a - jnz fail_p3 - - mov a, #(~0B7H & 0FFH) - add a, r7 - cpl a - jnz fail_p3 - - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/rb/int/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/rc/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/rc/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/rc/test.asm (nonexistent) @@ -1,107 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test RR(C) A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #080H - - rr a - jb7 fail - jb6 ok1_1 - jmp fail - -ok1_1: rr a - jb6 fail - jb5 ok1_2 - jmp fail - -ok1_2: rr a - jb5 fail - jb4 ok1_3 - jmp fail - -ok1_3: rr a - jb4 fail - jb3 ok1_4 - jmp fail - -ok1_4: rr a - jb3 fail - jb2 ok1_5 - jmp fail - -ok1_5: rr a - jb2 fail - jb1 ok1_6 - jmp fail - -ok1_6: rr a - jb1 fail - jb0 ok1_7 - jmp fail - -ok1_7: rr a - jb0 fail - jb7 ok2 - jmp fail - - -ok2: mov a, #07FH - cpl c - - rrc a - jb7 ok2_1 - jmp fail -ok2_1: jb6 fail - - rrc a - jb6 ok2_2 - jmp fail -ok2_2: jb5 fail - - rrc a - jb5 ok2_3 - jmp fail -ok2_3: jb4 fail - - rrc a - jb4 ok2_4 - jmp fail -ok2_4: jb3 fail - - rrc a - jb3 ok2_5 - jmp fail -ok2_5: jb2 fail - - rrc a - jb2 ok2_6 - jmp fail -ok2_6: jb1 fail - - rrc a - jb1 ok2_7 - jmp fail -ok2_7: jb0 fail - jnc fail - - rrc a - jb0 ok2_8 - jmp fail -ok2_8: jc fail - - rrc a - jc ok2_9 - jmp fail -ok2_9: jb7 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/rc/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/movd/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/movd/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/movd/test.asm (nonexistent) @@ -1,117 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOVD. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; - ;; read initial values - ;; - - ;; port 4 - cpl a - movd a, p4 - xrl a, #00fh - jnz fail - - ;; port 5 - cpl a - movd a, p5 - xrl a, #00fh - jnz fail - - ;; port 6 - cpl a - movd a, p6 - xrl a, #00fh - jnz fail - - ;; port 7 - cpl a - movd a, p7 - xrl a, #00fh - jnz fail - - - ;; - ;; test read/write via direct connection - ;; - - ;; port 4 => port 6 - mov a, #005h - movd p4, a - cpl a - movd a, p6 - xrl a, #005h - jnz fail - - mov a, #00ah - movd p4, a - cpl a - movd a, p6 - xrl a, #00ah - jnz fail - movd a, p4 - - ;; port 6 => port 4 - mov a, #000h - movd p6, a - cpl a - movd a, p4 - xrl a, #000h - jnz fail - - mov a, #00fh - movd p6, a - cpl a - movd a, p4 - xrl a, #00fh - jnz fail - movd p6, a - - ;; port 5 => port 7 - mov a, #005h - movd p5, a - cpl a - movd a, p7 - xrl a, #005h - jnz fail - - mov a, #00ah - movd p5, a - cpl a - movd a, p7 - xrl a, #00ah - jnz fail - movd a, p7 - - ;; port 7 => port 5 - mov a, #000h - movd p7, a - cpl a - movd a, p5 - xrl a, #000h - jnz fail - - mov a, #00fh - movd p7, a - cpl a - movd a, p5 - xrl a, #00fh - jnz fail - movd p7, a - - - jmp pass - - jmp fail -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/movd/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/expander/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/expander/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/expander/test.asm (nonexistent) @@ -1,88 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Expander port functionality. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #00AH - movd p4, a - mov a, #005H - movd p5, a - mov a, #00BH - movd p6, a - mov a, #000H - movd p7, a - - ;; check P4 - movd a, p4 - orl a, #0F5H - inc a - ;jnz fail - mov a, #0F5H - orld p4, a - movd a, p4 - inc a - ;jnz fail - mov a, #0FEH - anld p4, a - movd a, p4 - add a, #0F2H - ;jnz fail - - ;; check P5 - movd a, p5 - orl a, #0FAH - inc a - ;jnz fail - mov a, #0FAH - orld p5, a - movd a, p5 - inc a - ;jnz fail - mov a, #0FDH - anld p5, a - movd a, p5 - add a, #0F3H - ;jnz fail - - ;; check P6 - movd a, p6 - orl a, #0F4H - inc a - ;jnz fail - mov a, #0F4H - orld p6, a - movd a, p6 - inc a - ;jnz fail - mov a, #0F8H - anld p6, a - movd a, p6 - add a, #0F8H - ;jnz fail - - ;; check P7 - movd a, p7 - orl a, #0FFH - inc a - ;jnz fail - mov a, #0FFH - orld p7, a - movd a, p7 - inc a - ;jnz fail - mov a, #0F7H - anld p7, a - movd a, p7 - add a, #0F9H - ;jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/expander/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/expander/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/expander/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/expander/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail for i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/psw/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/psw/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/psw/test.asm (nonexistent) @@ -1,61 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test several commands related to PSW. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, psw - anl a, #0F7H - jnz fail - - dec a - mov psw, a - mov a, psw - inc a - jnz fail - - mov psw, a - mov a, psw - anl a, #0F7H - jnz fail - - cpl f0 - jf0 ok_1 - jmp fail -ok_1: mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~028H + 1) & 0FFH - jnz fail - - clr f0 - jnc fail - mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~088H + 1) & 0FFH - jnz fail - - clr c - jc fail - sel rb1 - mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~018H + 1) & 0FFH - jnz fail - - cpl c - jc fail - sel rb0 - mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~08H + 1) & 0FFH - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/psw/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/inc/a/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/inc/a/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/inc/a/test.asm (nonexistent) @@ -1,34 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test INC A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - inc a - add a, #0FFH - jnz fail - - inc a - jb0 ok_0 - jmp fail - -ok_0: mov a, #0FFH - inc a - jnz fail - - mov a, #010100101B - inc a - add a, #001011001B - inc a - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/inc/a/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/inc/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/inc/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/inc/rr/test.asm (nonexistent) @@ -1,243 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test INC Rr for RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - - -pass: PASS - -fail: FAIL - - - ORG 0300H -fill: mov a, #0FFH - mov r0, a - mov r1, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, #000H - inc r0 - jnz fail_p3 - mov a, r0 - jnz fail_p3 - ;; - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r1 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - ;; - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r2 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - ;; - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r3 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - ;; - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r4 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - ;; - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r5 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - ;; - mov a, r6 - jz fail_p3 - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r6 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - ;; - mov a, r7 - jz fail_p3 - - mov a, #000H - inc r7 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - ;; - mov a, r0 - jnz fail_p3 - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/inc/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/inc/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/inc/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/inc/ind_rr/test.asm (nonexistent) @@ -1,345 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test INC @ Rr for RB0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - mov r1, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - - mov r0, #001H - mov a, #000H - inc @r0 - jnz fail - mov a, r1 - jnz fail - ;; - mov a, r2 - jz fail - mov a, r3 - jz fail - mov a, r4 - jz fail - mov a, r5 - jz fail - mov a, r6 - jz fail - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r2 - jnz fail - ;; - mov a, r1 - jnz fail - ;; - mov a, r3 - jz fail - mov a, r4 - jz fail - mov a, r5 - jz fail - mov a, r6 - jz fail - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r3 - jnz fail - ;; - mov a, r1 - jnz fail - mov a, r2 - jnz fail - ;; - mov a, r4 - jz fail - mov a, r5 - jz fail - mov a, r6 - jz fail - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r4 - jnz fail - ;; - mov a, r1 - jnz fail - mov a, r2 - jnz fail - mov a, r3 - jnz fail - ;; - mov a, r5 - jz fail - mov a, r6 - jz fail - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r5 - jnz fail - ;; - mov a, r1 - jnz fail - mov a, r2 - jnz fail - mov a, r3 - jnz fail - mov a, r4 - jnz fail - ;; - mov a, r6 - jz fail - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r6 - jnz fail - ;; - mov a, r1 - jnz fail - mov a, r2 - jnz fail - mov a, r3 - jnz fail - mov a, r4 - jnz fail - mov a, r5 - jnz fail - ;; - mov a, r7 - jz fail - - mov a, #000H - inc r0 - jnz fail - inc @r0 - jnz fail - mov a, r7 - jnz fail - ;; - mov a, r1 - jnz fail - mov a, r2 - jnz fail - mov a, r3 - jnz fail - mov a, r4 - jnz fail - mov a, r5 - jnz fail - mov a, r6 - jnz fail - - jmp test_r1 - -fail: FAIL - - ;; - ALIGN 256 - ;; - -test_r1: - mov a, #0FFH - mov r0, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - - mov r1, #000H - mov a, #000H - inc @r1 - jnz fail2 - mov a, r0 - jnz fail2 - ;; - mov a, r2 - jz fail2 - mov a, r3 - jz fail2 - mov a, r4 - jz fail2 - mov a, r5 - jz fail2 - mov a, r6 - jz fail2 - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r2 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - ;; - mov a, r3 - jz fail2 - mov a, r4 - jz fail2 - mov a, r5 - jz fail2 - mov a, r6 - jz fail2 - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r3 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - mov a, r2 - jnz fail2 - ;; - mov a, r4 - jz fail2 - mov a, r5 - jz fail2 - mov a, r6 - jz fail2 - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r4 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - mov a, r2 - jnz fail2 - mov a, r3 - jnz fail2 - ;; - mov a, r5 - jz fail2 - mov a, r6 - jz fail2 - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r5 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - mov a, r2 - jnz fail2 - mov a, r3 - jnz fail2 - mov a, r4 - jnz fail2 - ;; - mov a, r6 - jz fail2 - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r6 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - mov a, r2 - jnz fail2 - mov a, r3 - jnz fail2 - mov a, r4 - jnz fail2 - mov a, r5 - jnz fail2 - ;; - mov a, r7 - jz fail2 - - mov a, #000H - inc r1 - jnz fail2 - inc @r1 - jnz fail2 - mov a, r7 - jnz fail2 - ;; - mov a, r0 - jnz fail2 - mov a, r2 - jnz fail2 - mov a, r3 - jnz fail2 - mov a, r4 - jnz fail2 - mov a, r5 - jnz fail2 - mov a, r6 - jnz fail2 - -pass: PASS - -fail2: FAIL

t48/rel_1_2/sw/verif/black_box/inc/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jnc/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jnc/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jnc/test.asm (nonexistent) @@ -1,22 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JNC instruction. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jnc ok_1 - jmp fail - -ok_1: mov a, #0FFH - add a, #001H - jnc fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/jnc/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anl/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/rr/test.asm (nonexistent) @@ -1,140 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANL A, Rr for RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, #(1 << 0) - anl a, r0 - jnz fail_p3 - mov a, #0FFH - anl a, r0 - add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 1) - anl a, r1 - jnz fail_p3 - mov a, #0FFH - anl a, r1 - add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 2) - anl a, r2 - jnz fail_p3 - mov a, #0FFH - anl a, r2 - add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 3) - anl a, r3 - jnz fail_p3 - mov a, #0FFH - anl a, r3 - add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 4) - anl a, r4 - jnz fail_p3 - mov a, #0FFH - anl a, r4 - add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 5) - anl a, r5 - jnz fail_p3 - mov a, #0FFH - anl a, r5 - add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 6) - anl a, r6 - jnz fail_p3 - mov a, #0FFH - anl a, r6 - add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 7) - anl a, r7 - jnz fail_p3 - mov a, #0FFH - anl a, r7 - add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH - jnz fail_p3 - ret - - -fail_p3: FAIL

t48/rel_1_2/sw/verif/black_box/anl/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anl/a_data/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/a_data/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/a_data/test.asm (nonexistent) @@ -1,32 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANL A, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - anl a, #000H - jnz fail - anl a, #000H - jnz fail - - mov a, #0FFH - anl a, #055H - add a, #0ABH - jnz fail - - mov a, #0FFH - anl a, #0B6H - anl a, #023H - add a, #0DEH - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/anl/a_data/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anl/bus/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/bus/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/bus/test.asm (nonexistent) @@ -1,30 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANL BUS, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - outl bus, a - - clr a - ins a, bus - inc a - jnz fail - - anl bus, #0AAH - jnz fail - - ins a, bus - add a, #056H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/anl/bus/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anl/bus/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/bus/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/bus/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail in i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/anl/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/ind_rr/test.asm (nonexistent) @@ -1,90 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANL A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testR0R1 MACRO pos - inc r0 - inc r1 - mov a, #(1 << pos) - anl a, @r0 - jnz fail - mov a, #0FFH - anl a, @r0 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - mov a, #(1 << pos) - anl a, @r1 - jnz fail - mov a, #0FFH - anl a, @r1 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - jmp goon - - ORG 256 - ;; -goon: mov r0, #00FH - mov r1, #01FH - testR0R1 0 - testR0R1 1 - testR0R1 2 - testR0R1 3 - testR0R1 4 - testR0R1 5 - testR0R1 6 - testR0R1 7 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/anl/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anl/pp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anl/pp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anl/pp/test.asm (nonexistent) @@ -1,41 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANL Pp, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - outl p1, a - outl p2, a - - clr a - in a, p1 - inc a - jnz fail - - in a, p2 - inc a - jnz fail - - anl P1, #0AAH - jnz fail - anl P2, #055H - jnz fail - - in a, p1 - add a, #056H - jnz fail - - in a, p2 - add a, #0ABH - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/anl/pp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/rl/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/rl/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/rl/test.asm (nonexistent) @@ -1,108 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test RL(C) A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #001H - - rl a - jb0 fail - jb1 ok1_1 - jmp fail - -ok1_1: rl a - jb1 fail - jb2 ok1_2 - jmp fail - -ok1_2: rl a - jb2 fail - jb3 ok1_3 - jmp fail - -ok1_3: rl a - jb3 fail - jb4 ok1_4 - jmp fail - -ok1_4: rl a - jb4 fail - jb5 ok1_5 - jmp fail - -ok1_5: rl a - jb5 fail - jb6 ok1_6 - jmp fail - -ok1_6: rl a - jb6 fail - jb7 ok1_7 - jmp fail - -ok1_7: rl a - jb7 fail - jb0 ok2 - jmp fail - - -ok2: mov a, #0FEH - cpl c - - rlc a - jb0 ok2_1 - jmp fail -ok2_1: jb1 fail - - rlc a - jb1 ok2_2 - jmp fail -ok2_2: jb2 fail - - rlc a - jb2 ok2_3 - jmp fail -ok2_3: jb3 fail - - rlc a - jb3 ok2_4 - jmp fail -ok2_4: jb4 fail - - rlc a - jb4 ok2_5 - jmp fail -ok2_5: jb5 fail - - rlc a - jb5 ok2_6 - jmp fail -ok2_6: jb6 fail - - rlc a - jb6 ok2_7 - jmp fail -ok2_7: jb7 fail - jnc fail - - rlc a - jb7 ok2_8 - jmp fail -ok2_8: jc fail - - rlc a - jc ok2_9 - jmp fail -ok2_9: jb0 fail - - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/rl/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cpl/a/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cpl/a/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cpl/a/test.asm (nonexistent) @@ -1,28 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CPL A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - cpl a - jnz fail - - cpl a - inc a - jnz fail - - mov a, #055H - cpl a - add a, #01010110B - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/cpl/a/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cpl/c/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cpl/c/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cpl/c/test.asm (nonexistent) @@ -1,31 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CPL C. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jc fail - - cpl c - jnc fail - - mov a, #0FEH - add a, #001H - jc fail - cpl c - jnc fail - - add a, #001H - jnc fail - cpl c - jc fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/cpl/c/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cpl/f0/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cpl/f0/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cpl/f0/test.asm (nonexistent) @@ -1,23 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CPL F0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jf0 fail - cpl f0 - jf0 ok_1 - jmp fail - -ok_1: cpl f0 - jf0 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/cpl/f0/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cpl/f1/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cpl/f1/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cpl/f1/test.asm (nonexistent) @@ -1,23 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CPL F1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jf1 fail - cpl f1 - jf1 ok_1 - jmp fail - -ok_1: cpl f1 - jf1 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/cpl/f1/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/clr/a/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/clr/a/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/clr/a/test.asm (nonexistent) @@ -1,33 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CLR A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FFH - jz fail - clr a - jnz fail - - inc a - jb0 ok_1 - jmp fail - -ok_1: add a, #0FFH - jnz fail - - add a, #010H - clr a - dec a - add a, #001H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/clr/a/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/clr/c/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/clr/c/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/clr/c/test.asm (nonexistent) @@ -1,29 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CLR C. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jc fail - cpl c - jnc fail - clr c - jc fail - clr c - jc fail - - mov a, #0FFH - add a, #001H - jnc fail - clr c - jc fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/clr/c/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/clr/f0/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/clr/f0/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/clr/f0/test.asm (nonexistent) @@ -1,23 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CLR F0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jf0 fail - cpl f0 - jf0 ok_1 - jmp fail - -ok_1: clr f0 - jf0 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/clr/f0/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/clr/f1/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/clr/f1/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/clr/f1/test.asm (nonexistent) @@ -1,23 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CLR F1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jf1 fail - cpl f1 - jf1 ok_1 - jmp fail - -ok_1: clr f1 - jf1 fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/clr/f1/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/movp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/movp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/movp/test.asm (nonexistent) @@ -1,67 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOVP A, @ A and MOVP3 A, @ A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -table MACRO data - DB data & 0FFH - ENDM - - ORG 0 - - ;; Start of test - mov r1, #008H - -loop: mov a, r1 - dec a - call fetch_table1 - mov r0, a - - mov a, r1 - dec a - call fetch_table3 - - add a, r0 - cpl a - jnz fail - - djnz r1, loop - - -pass: PASS - -fail: FAIL - - - ORG 0100H - - db 0AFH - db 033H - db 0C0H - db 012H - db 055H - db 061H - db 02BH - db 0F4H -fetch_table1: - movp a, @a - ret -fetch_table3: - movp3 a, @a - ret - - - ORG 0300H - - db 050H - db 0CCH - db 03FH - db 0EDH - db 0AAH - db 09EH - db 0D4H - db 00BH

t48/rel_1_2/sw/verif/black_box/movp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/outl/pp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/outl/pp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/outl/pp/test.asm (nonexistent) @@ -1,20 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test OUTL Pp, A - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #055H - outl p1, a - mov a, #0AAH - outl p2, a - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/outl/pp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/outl/bus/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/outl/bus/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/outl/bus/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail in i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/outl/bus/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/outl/bus/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/outl/bus/test.asm (nonexistent) @@ -1,20 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test OUTL BUS, A - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #055H - outl bus, a - cpl a - outl bus, a - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/outl/bus/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jz/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jz/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jz/test.asm (nonexistent) @@ -1,43 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JZ instruction. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - jz ok_0 - jmp fail - -ok_0: mov a, #001H - jz fail - - mov a, #002H - jz fail - - mov a, #004H - jz fail - - mov a, #008H - jz fail - - mov a, #010H - jz fail - - mov a, #020H - jz fail - - mov a, #040H - jz fail - - mov a, #080H - jz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/jz/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cnt/cnt/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cnt/cnt/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cnt/cnt/test.asm (nonexistent) @@ -1,82 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Counter. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #0FEH - mov t, a - - strt cnt - jtf fail - - ;; apply falling edge on T1 - anl P1, #0FDH - jtf fail - mov a, t - cpl a - add a, #0FFH - cpl a - jnz fail - - ;; apply rising edge on T1 - orl P1, #002H - jtf fail - - ;; apply falling edge on T1 - anl P1, #0FDH - jtf goon - jmp fail -goon: jtf fail - mov a, t - jnz fail - - ;; apply rising edge on T1 - orl P1, #002H - jtf fail - - ;; apply falling edge on T1 - anl P1, #0FDH - jtf fail - mov a, t - dec a - jnz fail - - ;; check inactivity of counter - stop tcnt - mov a, #0FFH - mov t, a - - ;; apply rising edge on T1 - orl P1, #002H - jtf fail - ;; apply falling edge on T1 - anl P1, #0FDH - jtf fail - ;; apply rising edge on T1 - orl P1, #002H - jtf fail - ;; apply falling edge on T1 - anl P1, #0FDH - jtf fail - - strt cnt - ;; apply rising edge on T1 - orl P1, #002H - jtf fail - ;; apply falling edge on T1 - anl P1, #0FDH - jtf goon2 - jmp fail - -goon2: - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/cnt/cnt/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/cnt/int/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/cnt/int/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cnt/int/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -Modelling accuracy of interrupts is not sufficient for 1:1 dump compare. Index: t48/rel_1_2/sw/verif/black_box/cnt/int/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/cnt/int/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/cnt/int/test.asm (nonexistent) @@ -1,113 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Counter Interrupt. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - jmp start - nop - jmp fail - jmp fail - jmp counter_int - jmp fail - - ;; Start of test -start: mov a, #0FEH - mov t, a - - mov r0, #000H - - strt cnt - en tcnti - - jtf fail - - ;; apply falling edge on T1 -> T = 0FFH - anl P1, #0FDH - call check_cnt_idle - mov a, t - inc a - jnz fail - ;; apply rising edge on T1 - orl P1, #002H - call check_cnt_idle - mov a, t - inc a - jnz fail - - ;; apply falling edge on T1 -> T = 000H - anl P1, #0FDH - jtf goon - jmp fail -goon: mov a, r0 - inc a - jnz fail - mov r0, a - jtf fail - ;; apply rising edge on T1 - orl P1, #002H - call check_cnt_idle - - ;; apply falling edge on T1 -> T = 001H - anl P1, #0FDH - call check_cnt_idle - mov a, t - dec a - jnz fail - ;; apply rising edge on T1 - orl P1, #002H - call check_cnt_idle - mov a, t - dec a - jnz fail - - ;; apply falling edge on T1 -> T = 002H - anl P1, #0FDH - call check_cnt_idle - mov a, t - dec a - dec a - jnz fail - ;; apply rising edge on T1 - orl P1, #002H - call check_cnt_idle - mov a, t - dec a - dec a - jnz fail - - ;; disable interrupt and trigger overflow - dis tcnti - mov a, #0FFH - mov t, a - call check_cnt_idle - - ;; apply falling edge on T1 -> T = 000H - anl P1, #0FDH - jtf goon2 - jmp fail -goon2: mov a, r0 - jnz fail - mov a, t - jnz fail - - -pass: PASS - -fail: FAIL - - -check_cnt_idle: - jtf fail - mov a, r0 - jnz fail - ret - - -counter_int: - mov r0, #0FFH - retr

t48/rel_1_2/sw/verif/black_box/cnt/int/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xchd/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xchd/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xchd/test.asm (nonexistent) @@ -1,121 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XCHD A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testR0R1 MACRO pos - inc r0 - inc r1 - mov a, @r0 - cpl a - add a, #((~((pos+7) # 8) << 4) & 0F0H) | (pos & 00FH) - cpl a - jnz fail - mov a, @r1 - cpl a - add a, #((~((pos+7) # 8) << 4) & 0F0H) | (pos & 00FH) - cpl a - jnz fail - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0F0H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0E1H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0D2H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0C3H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0B4H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0A5H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #096H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #087H - mov @r0, a - mov @r1, a - - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - dec r0 - xchd a, @r0 - mov r0, #017H - xchd a, @r0 - - mov a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - dec r1 - xchd a, @r1 - mov r1, #027H - xchd a, @r1 - - jmp goon - - ORG 256 - ;; -goon: mov r0, #00FH - mov r1, #01FH - testR0R1 1 - testR0R1 2 - testR0R1 3 - testR0R1 4 - testR0R1 5 - testR0R1 6 - testR0R1 7 - testR0R1 0 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/xchd/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/movx/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/movx/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/movx/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External RAM is not modelled in i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/movx/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/movx/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/movx/test.asm (nonexistent) @@ -1,60 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test MOVX A, @ Rr for RB0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov r0, #0FEH -fill_loop1: - mov a, r0 - movx @r0, a - djnz r0, fill_loop1 - - ;; check memory - mov a, r0 - jnz fail - mov r0, #0FEH - mov r1, #002H -check_loop1: - clr a - movx a, @r1 - add a, r0 - jnz fail - inc r1 - dec r0 - mov a, r0 - dec a - jnz check_loop1 - - - - mov r1, #0FEH - mov a, #002H -fill_loop2: - movx @r1, a - inc a - djnz r1, fill_loop2 - - ;; check memory - mov a, r1 - jnz fail - mov r0, #0FEH -check_loop2: - clr a - movx a, @r0 - add a, r0 - jnz fail - dec r0 - mov a, r0 - dec a - jnz check_loop2 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/movx/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/ins/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/ins/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/ins/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail in i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/ins/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/ins/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/ins/test.asm (nonexistent) @@ -1,37 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test INS A, BUS. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; deselect external memory - mov r0, #0FFH - clr a - movx @r0, a - - mov a, #055H - outl bus, a - - clr a - ins a, bus - add a, #0ABH - jnz fail - - mov a, #0AAH - outl bus, a - - clr a - ins a, bus - add a, #056H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/ins/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/int/simple_jump_to/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/int/simple_jump_to/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/int/simple_jump_to/test.asm (nonexistent) @@ -1,28 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test a simple jump to interrupt. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jmp start_user - - - ORG 3 - jmp pass - - - ORG 010H -start_user: - en i - mov r0, #080H -loop: djnz r0, loop - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/int/simple_jump_to/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -Modelling accuracy of interrupts is not sufficient for 1:1 dump compare. Index: t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/test.asm (nonexistent) @@ -1,48 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test simple interrupt/RETR requences. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jmp start_user - - - ORG 3 - cpl f1 - cpl f0 - mov r1, #060H -int_loop: - djnz r1, int_loop - jf1 int_goon - jmp fail -int_goon: - dis i - retr - - - ORG 020H -start_user: - mov r0, #080H - en i - nop -loop1: djnz r0, loop1 - jf0 fail - jf1 goon1 - jmp fail - -goon1: mov r0, #080H - cpl f1 - en i -loop2: djnz r0, loop2 - jf0 fail - jf1 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/int/simple_int_retr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/int/jni/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/int/jni/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/int/jni/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -Modelling accuracy of interrupts is not sufficient for 1:1 dump compare. Index: t48/rel_1_2/sw/verif/black_box/int/jni/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/int/jni/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/int/jni/test.asm (nonexistent) @@ -1,21 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JNI. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jni fail - - mov r0, #000H -poll: jni pass - djnz r0, poll - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/int/jni/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/tx/t0/t0/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/tx/t0/t0/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tx/t0/t0/test.asm (nonexistent) @@ -1,21 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test J(N)T0 addr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jnt0 fail - anl P1, #0FEH - jt0 fail - orl P1, #001H - jt0 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/tx/t0/t0/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/tx/t0/ent0_clk/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/tx/t0/ent0_clk/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tx/t0/ent0_clk/test.asm (nonexistent) @@ -1,15 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Execute ENT0 CLK. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - ent0 clk - -pass: PASS

t48/rel_1_2/sw/verif/black_box/tx/t0/ent0_clk/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/tx/t1/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/tx/t1/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/tx/t1/test.asm (nonexistent) @@ -1,21 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test J(N)T1 addr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jnt1 fail - anl P1, #0FDH - jt1 fail - orl P1, #002H - jt1 pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/tx/t1/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/dec/a/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/dec/a/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/dec/a/test.asm (nonexistent) @@ -1,32 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test DEC A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #001H - dec a - jnz fail - - dec a - jb0 ok_0 - jmp fail - -ok_0: inc a - jnz fail - - mov a, #10100101B - dec a - add a, #01011101B - dec a - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/dec/a/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/dec/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/dec/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/dec/rr/test.asm (nonexistent) @@ -1,244 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test DECC Rr for RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #000H - mov r0, a - mov r1, a - mov r2, a - mov r3, a - mov r4, a - mov r5, a - mov r6, a - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, #0FFH - dec r0 - jz fail_p3 - mov a, r0 - jz fail_p3 - ;; - mov a, r1 - jnz fail_p3 - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r1 - jz fail_p3 - mov a, r1 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - ;; - mov a, r2 - jnz fail_p3 - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r2 - jz fail_p3 - mov a, r2 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - ;; - mov a, r3 - jnz fail_p3 - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r3 - jz fail_p3 - mov a, r3 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - ;; - mov a, r4 - jnz fail_p3 - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r4 - jz fail_p3 - mov a, r4 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - ;; - mov a, r5 - jnz fail_p3 - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r5 - jz fail_p3 - mov a, r5 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - ;; - mov a, r6 - jnz fail_p3 - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - dec r6 - jz fail_p3 - mov a, r6 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - ;; - mov a, r7 - jnz fail_p3 - - mov a, #0FFH - inc r7 - jz fail_p3 - mov a, r7 - jz fail_p3 - ;; - mov a, r0 - jz fail_p3 - mov a, r1 - jz fail_p3 - mov a, r2 - jz fail_p3 - mov a, r3 - jz fail_p3 - mov a, r4 - jz fail_p3 - mov a, r5 - jz fail_p3 - mov a, r6 - jz fail_p3 - ret - - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/dec/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/addc/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/addc/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/addc/ind_rr/test.asm (nonexistent) @@ -1,99 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADDC A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testADDC MACRO val - jmp goon - ALIGN 040H -goon: inc r0 - inc r1 - mov a, #val - addc a, @r0 - jnz fail - jnc fail - mov a, #val - addc a, @r0 - dec a - jnz fail - jnc fail - clr c - ;; - mov a, #val - addc a, @r1 - jnz fail - jnc fail - mov a, #val - addc a, @r1 - dec a - jnz fail - jnc fail - clr c - jmp pass - ;; -fail: FAIL -pass: - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - ;; - mov r0, #00FH - mov r1, #01FH - - testADDC 002H - testADDC 003H - testADDC 005H - testADDC 009H - testADDC 011H - testADDC 021H - testADDC 041H - testADDC 081H - -pass: PASS

t48/rel_1_2/sw/verif/black_box/addc/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/addc/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/addc/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/addc/rr/test.asm (nonexistent) @@ -1,98 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADDC A, Rr with carry, RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testADDC MACRO val,reg - mov a, #val - addc a, reg - jnz fail_p3 - jnc fail_p3 - mov a, #val - addc a, reg - jz fail_p3 - jnc fail_p3 - dec a - jnz fail_p3 - clr c - jc fail_p3 - ENDM - - ORG 0 - - ;; Start of test - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - -check: testADDC 002H, r0 - testADDC 003H, r1 - testADDC 005H, r2 - testADDC 009H, r3 - testADDC 011H, r4 - testADDC 021H, r5 - testADDC 041H, r6 - testADDC 081H, r7 - ret - -clr: mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/addc/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/addc/a_data/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/addc/a_data/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/addc/a_data/test.asm (nonexistent) @@ -1,30 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ADDC A, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jc fail - mov a, #000H - - addc a, #055H - jc fail - addc a, #0ABH - jnz fail - jnc fail - - addc a, #000H - jc fail - addc a, #0FFH - jnz fail - jnc fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/addc/a_data/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orl/a_data/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/a_data/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/a_data/test.asm (nonexistent) @@ -1,32 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORL A, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - clr a - orl a, #0FFH - jz fail - orl a, #0FFH - jz fail - - clr a - orl a, #055H - add a, #0ABH - jnz fail - - clr a - orl a, #023H - orl a, #088H - add a, #055H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/orl/a_data/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orl/bus/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/bus/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/bus/test.asm (nonexistent) @@ -1,29 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORL BUS, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - outl bus, a - - cpl a - ins a, bus - jnz fail - - orl bus, #0AAH - jnz fail - - ins a, bus - add a, #056H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/orl/bus/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orl/bus/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/bus/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/bus/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail in i8039 emulator. Index: t48/rel_1_2/sw/verif/black_box/orl/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/ind_rr/test.asm (nonexistent) @@ -1,92 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORL A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testR0R1 MACRO pos - inc r0 - inc r1 - mov a, #(1 << pos) - orl a, @r0 - cpl a - jnz fail - clr a - orl a, @r0 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - mov a, #(1 << pos) - orl a, @r1 - cpl a - jnz fail - clr a - orl a, @r1 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - jmp goon - - ORG 256 - ;; -goon: mov r0, #00FH - mov r1, #01FH - testR0R1 0 - testR0R1 1 - testR0R1 2 - testR0R1 3 - testR0R1 4 - testR0R1 5 - testR0R1 6 - testR0R1 7 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/orl/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orl/pp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/pp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/pp/test.asm (nonexistent) @@ -1,40 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORL Pp, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - outl p1, a - outl p2, a - - cpl a - in a, p1 - jnz fail - - cpl a - in a, p2 - jnz fail - - orl P1, #0AAH - jnz fail - orl P2, #055H - jnz fail - - in a, p1 - add a, #056H - jnz fail - - in a, p2 - add a, #0ABH - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/orl/pp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/orl/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/orl/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/orl/rr/test.asm (nonexistent) @@ -1,149 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ORL A, Rr with RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, #(1 << 0) - orl a, r0 - cpl a - jnz fail_p3 - clr a - orl a, r0 - add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 1) - orl a, r1 - cpl a - jnz fail_p3 - clr a - orl a, r1 - add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 2) - orl a, r2 - cpl a - jnz fail_p3 - clr a - orl a, r2 - add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 3) - orl a, r3 - cpl a - jnz fail_p3 - clr a - orl a, r3 - add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 4) - orl a, r4 - cpl a - jnz fail_p3 - clr a - orl a, r4 - add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 5) - orl a, r5 - cpl a - jnz fail_p3 - clr a - orl a, r5 - add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 6) - orl a, r6 - cpl a - jnz fail_p3 - clr a - orl a, r6 - add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 7) - orl a, r7 - cpl a - jnz fail_p3 - clr a - orl a, r7 - add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH - jnz fail_p3 - - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/orl/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mb/int/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mb/int/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mb/int/test.asm (nonexistent) @@ -1,62 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Program Memory bank selector with interrupts. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - jmp start - ORG 3 - jmp interrupt & 07FFH - - ORG 7 - jmp fail - - ;; Start of test -start: - sel mb1 - mov r0, #000H - en i -poll: jf1 goon1 - djnz r0, poll - jmp fail -goon1: - - call test_mb1 & 07FFH - -pass: PASS - -fail: FAIL - - ORG 0232H - jmp fail -interrupt: - call trick_mb - cpl f1 - retr - - ORG 0250H -trick_mb: - ret - - ORG 0260H - jmp fail - - - ORG 0A32H - jmp fail_hi - jmp fail_hi - jmp fail_hi - - ORG 0A50H - jmp fail_hi - - ORG 0A60H -test_mb1: - ret - -fail_hi: - FAIL

t48/rel_1_2/sw/verif/black_box/mb/int/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/mb/call_jmp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/mb/call_jmp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/mb/call_jmp/test.asm (nonexistent) @@ -1,125 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test Program Memory bank selector with CALL and JMP. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - sel mb1 - call call1 & 07FFH - sel mb1 - jmp jmp1 & 07FFH - ;; trap - nop - jmp fail - nop - jmp fail - ;; -jmp2: sel mb1 - call call3 & 07FFH - sel mb1 - jmp jmp3 & 07FFH - ;; trap - nop - jmp fail - nop - jmp fail - ;; -jmp4: sel mb1 - call call5 & 07FFH - sel mb1 - jmp jmp5 & 07FFH - ;; trap - nop - jmp fail - nop - jmp fail -jmp6: - -pass: PASS - -fail: FAIL - - ORG 0100H - - ;; trap - jmp fail - ;; -call2: sel mb1 - ret - ;; trap - jmp fail - ;; -call4: sel mb0 - ret - ;; trap - jmp fail - ;; -call6: sel mb1 - ret - - - - ORG 0800H - - ;; trap - nop - jmp fail_hi - nop - jmp fail_hi - ;; -jmp1: sel mb0 - call call2 | 0800H - sel mb0 - jmp jmp2 | 0800H - ;; trap - nop - jmp fail_hi - nop - jmp fail_hi - ;; -jmp3: sel mb0 - call call4 | 0800H - sel mb0 - jmp jmp4 | 0800H - ;; trap - nop - jmp fail_hi - nop - jmp fail_hi - ;; -jmp5: sel mb0 - call call6 | 0800H - sel mb0 - jmp jmp6 | 0800H - ;; trap - nop - jmp fail_hi - nop - jmp fail_hi - - -fail_hi: - FAIL - - - ORG 0900H -call1: sel mb0 - ret - ;; trap - jmp fail_hi - ;; -call3: sel mb1 - ret - ;; trap - jmp fail_hi - ;; -call5: sel mb0 - ret - ;; trap - jmp fail_hi

t48/rel_1_2/sw/verif/black_box/mb/call_jmp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jnz/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jnz/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jnz/test.asm (nonexistent) @@ -1,49 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JNZ instruction. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #000H - jnz fail - - mov a, #001H - jnz ok_01 - jmp fail - -ok_01: mov a, #002H - jnz ok_02 - jmp fail - -ok_02: mov a, #004H - jnz ok_04 - jmp fail - -ok_04: mov a, #008H - jnz ok_08 - jmp fail - -ok_08: mov a, #010H - jnz ok_10 - jmp fail - -ok_10: mov a, #020H - jnz ok_20 - jmp fail - -ok_20: mov a, #040H - jnz ok_40 - jmp fail - -ok_40: mov a, #080H - jnz pass - -fail: FAIL - -pass: PASS

t48/rel_1_2/sw/verif/black_box/jnz/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xrl/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xrl/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xrl/rr/test.asm (nonexistent) @@ -1,157 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XRL A, Rr for RB0 and RB1 - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, #(1 << 0) - xrl a, r0 - cpl a - jnz fail_p3 - dec a - xrl a, r0 - cpl a - add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 1) - xrl a, r1 - cpl a - jnz fail_p3 - dec a - xrl a, r1 - cpl a - add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 2) - xrl a, r2 - cpl a - jnz fail_p3 - dec a - xrl a, r2 - cpl a - add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 3) - xrl a, r3 - cpl a - jnz fail_p3 - dec a - xrl a, r3 - cpl a - add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 4) - xrl a, r4 - cpl a - jnz fail_p3 - dec a - xrl a, r4 - cpl a - add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 5) - xrl a, r5 - cpl a - jnz fail_p3 - dec a - xrl a, r5 - cpl a - add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 6) - xrl a, r6 - cpl a - jnz fail_p3 - dec a - xrl a, r6 - cpl a - add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH - jnz fail_p3 - - mov a, #(1 << 7) - xrl a, r7 - cpl a - jnz fail_p3 - dec a - xrl a, r7 - cpl a - add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH - jnz fail_p3 - - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/xrl/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xrl/a_data/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xrl/a_data/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xrl/a_data/test.asm (nonexistent) @@ -1,32 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XRL A, data. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - clr a - xrl a, #0FFH - jz fail - xrl a, #0FFH - jnz fail - - clr a - xrl a, #055H - add a, #0ABH - jnz fail - - clr a - xrl a, #023H - xrl a, #0A9H - add a, #076H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/xrl/a_data/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xrl/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xrl/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xrl/ind_rr/test.asm (nonexistent) @@ -1,92 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XRL A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testR0R1 MACRO pos - inc r0 - inc r1 - mov a, #(1 << pos) - cpl a - xrl a, @r0 - jnz fail - clr a - xrl a, @r0 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - mov a, #(1 << pos) - cpl a - xrl a, @r1 - jnz fail - clr a - xrl a, @r1 - add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH - jnz fail - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - jmp goon - - ORG 256 - ;; -goon: mov r0, #00FH - mov r1, #01FH - testR0R1 0 - testR0R1 1 - testR0R1 2 - testR0R1 3 - testR0R1 4 - testR0R1 5 - testR0R1 6 - testR0R1 7 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/xrl/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/djnz/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/djnz/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/djnz/test.asm (nonexistent) @@ -1,54 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test DJNZ Rr, addr - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov r0, #003H - mov a, #000H - djnz r0, r0_2 - jmp fail - -r0_2: djnz r0, r0_1 - jmp fail -r0_1: mov a, #0FFH - djnz r0, fail - - - mov r1, #000H - mov r2, #000H -r1_loop: - mov a, r2 - add a, r1 - jnz fail - inc r2 - djnz r1, r1_loop - - mov a, r1 - jnz fail - - - mov a, #002H - mov r3, a - mov r4, a - mov r5, a - djnz r5, ok_r5 - jmp fail -ok_r5: djnz r4, ok_r4 - jmp fail -ok_r4: djnz r3, ok_r3 - jmp fail - -ok_r3: djnz r3, fail - djnz r4, fail - djnz r5, fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/djnz/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/jmpp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/jmpp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/jmpp/test.asm (nonexistent) @@ -1,490 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test JMPP. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -table MACRO data - DB data & 0FFH - ENDM - - ORG 0 - - ;; Start of test - mov a, #000H - jmp table1 - -fail: FAIL - -pass: PASS - - - ;; ******************************************************************* - ORG 0100H - ;; - table t1_e00 - table t1_e01 - table t1_e02 - table t1_e03 - table t1_e04 - table t1_e05 - table t1_e06 - table t1_e07 - table t1_e08 - table t1_e09 - table t1_e0a - table t1_e0b - table t1_e0c - table t1_e0d - table t1_e0e - table t1_e0f - table t1_e10 - table t1_e11 - table t1_e12 - table t1_e13 - table t1_e14 - table t1_e15 - table t1_e16 - table t1_e17 - table t1_e18 - table t1_e19 - table t1_e1a - table t1_e1b - table t1_e1c - table t1_e1d - table t1_e1e - table t1_e1f - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - ;; - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - table t1_e01 - - jmp fail -table1: jmpp @a - jmp fail - -t1_e00: mov a, #007H - jmp table2 - ;; -t1_e01: jmp fail - jmp fail - ;; -t1_e02: mov a, #005H - jmp table2 - ;; -t1_e03: jmp fail - jmp fail - ;; -t1_e04: mov a, #003H - jmp table2 - ;; -t1_e05: jmp fail - jmp fail - ;; -t1_e06: mov a, #001H - jmp table2 - ;; -t1_e07: jmp fail - jmp fail - ;; -t1_e08: jmp fail - jmp fail - ;; -t1_e09: jmp fail - jmp fail - ;; -t1_e0a: jmp fail - jmp fail - ;; -t1_e0b: jmp fail - jmp fail - ;; -t1_e0c: jmp fail - jmp fail - ;; -t1_e0d: jmp fail - jmp fail - ;; -t1_e0e: jmp fail - jmp fail - ;; -t1_e0f: jmp fail - jmp fail - ;; -t1_e10: mov a, #018H - jmp table2 - ;; -t1_e11: jmp fail - jmp fail - ;; -t1_e12: jmp fail - jmp fail - ;; -t1_e13: jmp fail - jmp fail - ;; -t1_e14: jmp fail - jmp fail - ;; -t1_e15: jmp fail - jmp fail - ;; -t1_e16: jmp fail - jmp fail - ;; -t1_e17: jmp fail - jmp fail - ;; -t1_e18: jmp fail - jmp fail - ;; -t1_e19: jmp fail - jmp fail - ;; -t1_e1a: jmp fail - jmp fail - ;; -t1_e1b: jmp fail - jmp fail - ;; -t1_e1c: jmp fail - jmp fail - ;; -t1_e1d: jmp fail - jmp fail - ;; -t1_e1e: jmp fail - jmp fail - ;; -t1_e1f: jmp pass - jmp fail - - - ;; ******************************************************************* - ORG 512 - ;; - table t2_e00 - table t2_e01 - table t2_e02 - table t2_e03 - table t2_e04 - table t2_e05 - table t2_e06 - table t2_e07 - table t2_e08 - table t2_e09 - table t2_e0a - table t2_e0b - table t2_e0c - table t2_e0d - table t2_e0e - table t2_e0f - table t2_e10 - table t2_e11 - table t2_e12 - table t2_e13 - table t2_e14 - table t2_e15 - table t2_e16 - table t2_e17 - table t2_e18 - table t2_e19 - table t2_e1a - table t2_e1b - table t2_e1c - table t2_e1d - table t2_e1e - table t2_e1f - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - ;; - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - table t2_e01 - - jmp fail -table2: jmpp @a - jmp fail - -t2_e00: jmp fail - jmp fail - ;; -t2_e01: mov a, #010H - jmp table1 - ;; -t2_e02: jmp fail - jmp fail - ;; -t2_e03: mov a, #006H - jmp table1 - ;; -t2_e04: jmp fail - jmp fail - ;; -t2_e05: mov a, #004H - jmp table1 - ;; -t2_e06: jmp fail - jmp fail - ;; -t2_e07: mov a, #002H - jmp table1 - ;; -t2_e08: jmp fail - jmp fail - ;; -t2_e09: jmp fail - jmp fail - ;; -t2_e0a: jmp fail - jmp fail - ;; -t2_e0b: jmp fail - jmp fail - ;; -t2_e0c: jmp fail - jmp fail - ;; -t2_e0d: jmp fail - jmp fail - ;; -t2_e0e: jmp fail - jmp fail - ;; -t2_e0f: jmp fail - jmp fail - ;; -t2_e10: jmp fail - jmp fail - ;; -t2_e11: jmp fail - jmp fail - ;; -t2_e12: jmp fail - jmp fail - ;; -t2_e13: jmp fail - jmp fail - ;; -t2_e14: jmp fail - jmp fail - ;; -t2_e15: jmp fail - jmp fail - ;; -t2_e16: jmp fail - jmp fail - ;; -t2_e17: jmp fail - jmp fail - ;; -t2_e18: mov a, #01FH - jmp table1 - ;; -t2_e19: jmp fail - jmp fail - ;; -t2_e1a: jmp fail - jmp fail - ;; -t2_e1b: jmp fail - jmp fail - ;; -t2_e1c: jmp fail - jmp fail - ;; -t2_e1d: jmp fail - jmp fail - ;; -t2_e1e: jmp fail - jmp fail - ;; -t2_e1f: jmp fail - jmp fail

t48/rel_1_2/sw/verif/black_box/jmpp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/in/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/in/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/in/test.asm (nonexistent) @@ -1,29 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test IN A, Pp. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #055H - outl p1, a - mov a, #0AAH - outl p2, a - - clr a - in a, p1 - add a, #0ABH - jnz fail - - in a, p2 - add a, #056H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/in/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/swap/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/swap/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/swap/test.asm (nonexistent) @@ -1,25 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test SWAP A. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, #05AH - swap a - add a, #05BH - jnz fail - - mov a, #0C8H - swap a - add a, #074H - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/swap/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/call/call_ret/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/call/call_ret/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/call/call_ret/test.asm (nonexistent) @@ -1,104 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CALL + RET(R) with simple program. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov r0, #008H - call recursive - -call1: call sub1 - jc fail - jf0 fail - jf1 ok_1 - jmp fail -ok_1: - ;; check stack contents - mov r0, #008H - mov a, @r0 - add a, #(~(call1+2 & 0FFH) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - add a, #(~((call1+2) >> 8) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - add a, #(~(call2+2 & 0FFH) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - add a, #(~((call2+2) >> 8 | 0A0H) + 1) & 0FFH - jnz fail - - - clr c - clr f0 - clr f1 - call sub3 - jc fail - jf0 fail - -pass: PASS - -fail: FAIL - - - - ORG 0156H -recursive: - dec r0 - mov a, r0 - jz rec_end - call recursive -rec_end: - ret - - - ORG 0245H - -sub1: cpl f0 - cpl f1 - cpl c -call2: call sub2 - jf0 sub1_1 - jmp fail2 -sub1_1: jnc fail2 - retr - -sub2: jf0 sub2_1 - jmp fail2 -sub2_1: clr f0 - jnc fail2 - clr c - retr - -fail2: FAIL - - - ORG 0311H - -sub3: cpl f0 - cpl c - call sub4 - jf0 fail3 - jc fail3 - ret - -sub4: jf0 sub4_1 - jmp fail3 -sub4_1: clr f0 - jnc fail3 - clr c - ret - -fail3: FAIL

t48/rel_1_2/sw/verif/black_box/call/call_ret/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/call/simple/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/call/simple/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/call/simple/test.asm (nonexistent) @@ -1,62 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test CALL addr with simple program. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - mov a, psw - - clr c -call1: call goon1 - - jmp fail - - ORG 039FH - -goon1: mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #~009H + 1 - jnz fail - -call2: call goon2 - - jmp fail - -goon2: clr c - mov a, psw - anl a, #~040H ; mask AC, tested separately with DA - add a, #~00AH + 1 - jnz fail - - ;; check stack contents - mov r0, #008H - mov a, @r0 - add a, #(~(call1+2 & 0FFH) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~((call1+2) >> 8) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - add a, #(~(call2+2 & 0FFH) + 1) & 0FFH - jnz fail - - inc r0 - mov a, @r0 - anl a, #~040H ; mask AC, tested separately with DA - add a, #(~((call2+2) >> 8 | 080H) + 1) & 0FFH - jnz fail - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/call/simple/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/anld/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/anld/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/anld/test.asm (nonexistent) @@ -1,106 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test ANLD. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; port 4 - mov a, #00fh - movd p4, a - mov a, #00ch - anld p4, a - cpl a - movd a, p6 - xrl a, #00ch - jnz fail - movd a, p4 - xrl a, #00ch - jnz fail - - mov a, #003h - anld p4, a - movd a, p6 - jnz fail - movd a, p4 - jnz fail - - ;; port 5 - mov a, #00fh - movd p5, a - mov a, #003h - anld p5, a - cpl a - movd a, p7 - xrl a, #003h - jnz fail - movd a, p5 - xrl a, #003h - jnz fail - - mov a, #009h - anld p5, a - movd a, p7 - xrl a, #001h - jnz fail - movd a, p5 - xrl a, #001h - jnz fail - - ;; port 6 - mov a, #00fh - movd p6, a - mov a, #005h - anld p6, a - cpl a - movd a, p4 - xrl a, #005h - jnz fail - movd a, p6 - xrl a, #005h - jnz fail - - mov a, #00eh - anld p6, a - movd a, p4 - xrl a, #004h - jnz fail - movd a, p6 - xrl a, #004h - jnz fail - - ;; port 7 - mov a, #00fh - movd p7, a - mov a, #00ah - anld p7, a - cpl a - movd a, p5 - xrl a, #00ah - jnz fail - movd a, p7 - xrl a, #00ah - jnz fail - - mov a, #00dh - anld p7, a - movd a, p5 - xrl a, #008h - jnz fail - movd a, p7 - xrl a, #008h - jnz fail - - - jmp pass - - jmp fail -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/anld/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xch/ind_rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xch/ind_rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xch/ind_rr/test.asm (nonexistent) @@ -1,121 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XCH A, @ Rr. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -testR0R1 MACRO pos - inc r0 - inc r1 - mov a, @r0 - cpl a - add a, #~(1 << pos) & 0FFH - cpl a - jnz fail - mov a, @r1 - cpl a - add a, #~(1 << pos) & 0FFH - cpl a - jnz fail - ENDM - - ORG 0 - - ;; Start of test - mov r0, #010H - mov r1, #020H - mov a, #0FEH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FDH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0FBH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0F7H - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0EFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0DFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #0BFH - mov @r0, a - mov @r1, a - inc r0 - inc r1 - mov a, #07FH - mov @r0, a - mov @r1, a - - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - dec r0 - xch a, @r0 - mov r0, #017H - xch a, @r0 - - mov a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - dec r1 - xch a, @r1 - mov r1, #027H - xch a, @r1 - - jmp goon - - ORG 256 - ;; -goon: mov r0, #00FH - mov r1, #01FH - testR0R1 1 - testR0R1 2 - testR0R1 3 - testR0R1 4 - testR0R1 5 - testR0R1 6 - testR0R1 7 - testR0R1 0 - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/black_box/xch/ind_rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/black_box/xch/rr/test.asm =================================================================== --- t48/rel_1_2/sw/verif/black_box/xch/rr/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/black_box/xch/rr/test.asm (nonexistent) @@ -1,119 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test XCH A, Rr for RB0 and RB1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; fill RB0 - call fill - - ;; check RB0 - call check - - ;; fill RB1 - sel rb1 - call fill - sel rb0 - - ;; clear RB0 - call clr_rb0 - - ;; check RB1 - sel rb1 - call check - - ;; check RB0 for all 0 - mov r0, #000H - mov r1, #008H -chk0_loop: - mov a, @r0 - jnz fail - inc r0 - djnz r1, chk0_loop - -pass: PASS - -fail: FAIL - - - ORG 0300H - -fill: mov a, #0FEH - mov r0, a - mov a, #0FDH - mov r1, a - mov a, #0FBH - mov r2, a - mov a, #0F7H - mov r3, a - mov a, #0EFH - mov r4, a - mov a, #0DFH - mov r5, a - mov a, #0BFH - mov r6, a - mov a, #07FH - mov r7, a - ret - -clr_rb0: - mov r0, #007H - clr a -clr_loop: - mov @r0, a - djnz r0, clr_loop - ret - -check: mov a, r7 - xch a, r6 - xch a, r5 - xch a, r4 - xch a, r3 - xch a, r2 - xch a, r1 - xch a, r0 - xch a, r7 - - mov a, r0 - add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH - jnz fail_p3 - - mov a, r1 - add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH - jnz fail_p3 - - mov a, r2 - add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH - jnz fail_p3 - - mov a, r3 - add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH - jnz fail_p3 - - mov a, r4 - add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH - jnz fail_p3 - - mov a, r5 - add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH - jnz fail_p3 - - mov a, r6 - add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH - jnz fail_p3 - - mov a, r7 - add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH - jnz fail_p3 - - ret - -fail_p3: - FAIL

t48/rel_1_2/sw/verif/black_box/xch/rr/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/int_on_jmp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/int_on_jmp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/int_on_jmp/test.asm (nonexistent) @@ -1,91 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test interrupt on JMP in Program Memory Bank 1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -test_byte: equ 020h - - ORG 0 - - ;; Start of test - jmp start - - ORG 3 - ;; check that interrupt hit JMP instruction - ;; stack must contain target of JMP instruction at - ;; location jmp_instruction - mov r0, #00ah - mov a, @r0 - ;; check low byte of program counter on stack - xrl a, #000h - jnz fail - inc r0 - mov a, @r0 - anl a, #00fh - ;; check high byte of program counter on stack - mov r0, a - xrl a, #009h ; target of PASS case? - jz int_goon - mov a, r0 - xrl a, #001h ; target of FAIL case? - jnz fail - -int_goon: - ;; interrupt hit correct instruction - mov r0, #test_byte - mov a, #0ffh - mov @r0, a - retr - -start: - ;; enable interrupt - en i - - ;; clear test byte - mov r1, #test_byte - clr a - mov @r1, a - - call program_memory_bank_1 - sel mb0 - - ;; check if interrupt was successful - mov a, @r1 - jz fail - - -pass: PASS - -fail: FAIL - - - ORG 0100H - ;; program flow continues in fail case at address 0100h - ;; after interrupt - ;; i.e. bit 11 of address is erroneously cleared. - - ;; make sure that jump to fail reaches memory bank 0 - sel mb0 - jmp fail - - - ORG 0800H -program_memory_bank_1: - ;; spend some time and wait for interrupt - mov r2, #013h - djnz r2, $ - -jmp_instruction: - ;; interrupt must hit this JMP (checked by examining stack - ;; in interrupt handler) - jmp test_jmp - ret - - ORG 0900H -test_jmp: - ;; program flow continues in pass case here after interrupt - ret

t48/rel_1_2/sw/verif/white_box/int_on_jmp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/int_on_call/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/int_on_call/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/int_on_call/test.asm (nonexistent) @@ -1,91 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test interrupt on CALL in Program Memory Bank 1. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -test_byte: equ 020h - - ORG 0 - - ;; Start of test - jmp start - - ORG 3 - ;; check that interrupt hit CALL instruction - ;; stack must contain target of CALL instruction at - ;; location call_instruction - mov r0, #00ch - mov a, @r0 - ;; check low byte of program counter on stack - xrl a, #000h - jnz fail - inc r0 - mov a, @r0 - anl a, #00fh - ;; check high byte of program counter on stack - mov r0, a - xrl a, #009h ; target of PASS case? - jz int_goon - mov a, r0 - xrl a, #001h ; target of FAIL case? - jnz fail - -int_goon: - ;; interrupt hit correct instruction - mov r0, #test_byte - mov a, #0ffh - mov @r0, a - retr - -start: - ;; enable interrupt - en i - - ;; clear test byte - mov r1, #test_byte - clr a - mov @r1, a - - call program_memory_bank_1 - sel mb0 - - ;; check if interrupt was successful - mov a, @r1 - jz fail - - -pass: PASS - -fail: FAIL - - - ORG 0100H - ;; program flow continues in fail case at address 0100h - ;; after interrupt - ;; i.e. bit 11 of address is erroneously cleared. - - ;; make sure that jump to fail reaches memory bank 0 - sel mb0 - jmp fail - - - ORG 0800H -program_memory_bank_1: - ;; spend some time and wait for interrupt - mov r2, #013h - djnz r2, $ - -call_instruction: - ;; interrupt must hit this CALL (checked by examining stack - ;; in interrupt handler) - call test_call - ret - - ORG 0900H -test_call: - ;; program flow continues in pass case here after interrupt - ret

t48/rel_1_2/sw/verif/white_box/int_on_call/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail in i8039 emulator. Index: t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/test.asm (nonexistent) @@ -1,119 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test P1 conflict for reading port or output register. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; access testbench peripherals - mov r0, #0FFH - mov a, #002H - movx @r0, a - - ;; check functionality of P1 testbench peripheral - in a, p1 - inc a - jnz fail - - mov r0, #000H - ;; extern write 00H to P1 - clr a - movx @r0, a - in a, p1 - jnz fail - ;; extern write 0AAH to P1 - mov a, #0AAH - movx @r0, a - clr a - in a, p1 - add a, #056H - jnz fail - ;; extern write 055H to P1 - mov a, #055H - movx @r0, a - clr a - in a, p1 - add a, #0ABH - jnz fail - - ;; reset extern P1 to 0FFH - dec a - movx @r0, a - - ;; - ;; Start of real test - ;; - - ;; Test ORL - - ;; set internal P1 to 0AAH - mov a, #0AAH - outl p1, a - in a, p1 - add a, #056H - jnz fail - - ;; extern write 055H to P1 - mov a, #055H - movx @r0, a - - in a, p1 - jnz fail - - ;; set internal P1 to 0ABH, setting P1[0] to 1 - orl P1, #001H - in a, p1 - dec a - jnz fail - - ;; reset extern P1 to 0FFH - dec a - movx @r0, a - - ;; compare P1 vs. 0ABH - in a, p1 - cpl a - add a, #0ABH - cpl a - jnz fail - - ;; reset intern P1 to 0FFH - dec a - outl p1, a - - ;; set internal P1 to 055H - mov a, #055H - outl p1, a - clr a - in a, p1 - add a, #0ABH - jnz fail - - ;; external write 0AAH to P1 - mov a, #0AAH - movx @r0, a - - ;; set internal P1 to 054H - anl P1, #0FEH - - ;; reset extern P1 to 0FFH - mov a, #0FFH - movx @r0, a - - ;; compare P1 vs. 054H - in a, p1 - cpl a - add a, #054H - cpl a - jnz fail - - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/white_box/p1_port_reg_conflict/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/no_dump_compare =================================================================== --- t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/no_dump_compare (revision 296) +++ t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/no_dump_compare (nonexistent) @@ -1,2 +0,0 @@ -Reason why this cell is exluded from dump compare: -External ports not modelled in detail for i8039 emulator. Index: t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/test.asm (nonexistent) @@ -1,119 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test P2 conflict for reading port or output register. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; access testbench peripherals - mov r0, #0FFH - mov a, #002H - movx @r0, a - - ;; check functionality of P2 testbench peripheral - in a, p2 - inc a - jnz fail - - mov r0, #001H - ;; extern write 00H to P2 - clr a - movx @r0, a - in a, p2 - jnz fail - ;; extern write 0AAH to P2 - mov a, #0AAH - movx @r0, a - clr a - in a, p2 - add a, #056H - jnz fail - ;; extern write 055H to P2 - mov a, #055H - movx @r0, a - clr a - in a, p2 - add a, #0ABH - jnz fail - - ;; reset extern P2 to 0FFH - dec a - movx @r0, a - - ;; - ;; Start of real test - ;; - - ;; Test ORL - - ;; set internal P2 to 0AAH - mov a, #0AAH - outl p2, a - in a, p2 - add a, #056H - jnz fail - - ;; extern write 055H to P2 - mov a, #055H - movx @r0, a - - in a, p2 - jnz fail - - ;; set internal P2 to 0ABH, setting P2[0] to 1 - orl P2, #001H - in a, p2 - dec a - jnz fail - - ;; reset extern P2 to 0FFH - dec a - movx @r0, a - - ;; compare P2 vs. 0ABH - in a, p2 - cpl a - add a, #0ABH - cpl a - jnz fail - - ;; reset intern P2 to 0FFH - dec a - outl p2, a - - ;; set internal P2 to 055H - mov a, #055H - outl p2, a - clr a - in a, p2 - add a, #0ABH - jnz fail - - ;; external write 0AAH to P2 - mov a, #0AAH - movx @r0, a - - ;; set internal P2 to 054H - anl P2, #0FEH - - ;; reset extern P2 to 0FFH - mov a, #0FFH - movx @r0, a - - ;; compare P2 vs. 054H - in a, p2 - cpl a - add a, #054H - cpl a - jnz fail - - -pass: PASS - -fail: FAIL

t48/rel_1_2/sw/verif/white_box/p2_port_reg_conflict/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/p2_io_exp/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/p2_io_exp/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/p2_io_exp/test.asm (nonexistent) @@ -1,43 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - jmp start - - -start: - call test_code - sel mb0 - - -pass: PASS - -fail: FAIL - - - - ORG 0400H -test_code: - ;; write to P2 - mov a, #089h - outl p2, a - - ;; use expander - mov a, #00ch - movd p5, a - - ;; write to P2 - mov a, #098h - outl p2, a - - ;; use expander - movd a, p6 - - ret

t48/rel_1_2/sw/verif/white_box/p2_io_exp/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/int_on_mb1/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/int_on_mb1/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/int_on_mb1/test.asm (nonexistent) @@ -1,59 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test interrupt on code in Program Memory Bank 1. - ;; => Bug report "Problem with INT and JMP" - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - -test_byte: equ 020h - - ORG 0 - - ;; Start of test - jmp start - - ;; interrupt hits djnz instruction with opcode 0EAh - ;; bus conflict results on interrupt vector address 002h - ;; -> retr instruction placed here, so test finds FAIL - retr - - ORG 3 - ;; interrupt executed - mov r0, #test_byte - mov a, #0ffh - mov @r0, a - retr - -start: - ;; enable interrupt - en i - - ;; clear test byte - mov r1, #test_byte - clr a - mov @r1, a - - call program_memory_bank_1 - sel mb0 - - ;; check if interrupt was successful - mov a, @r1 - jz fail - - -pass: PASS - -fail: FAIL - - - - ORG 0800H -program_memory_bank_1: - ;; spend some time and wait for interrupt - mov r2, #020h - djnz r2, $ - - ret

t48/rel_1_2/sw/verif/white_box/int_on_mb1/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/psen_rd_wr_timing/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/psen_rd_wr_timing/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/psen_rd_wr_timing/test.asm (nonexistent) @@ -1,59 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test overlap of PSEN and RD/WR. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; access external memory - mov r0, #0FFH - mov a, #001H - movx @r0, a - - ;; jump to external Program Memory - jmp extern_rom - -pass: PASS - -fail: FAIL - - - ORG 0800H -extern_rom: - ;; write to external memory - mov r0, #010H - mov a, #0A5H - movx @r0, a - cpl a - mov r1, a - inc r0 - movx @r0, a - - ;; read back data - movx a, @r0 - cpl a - add a, r1 - cpl a - jz read_next - jmp fail - -read_next: - mov a, r1 - cpl a - mov r1, a - dec r0 - movx a, @r0 - cpl a - add a, r1 - cpl a - jz read_ok - jmp fail - -read_ok: - jmp pass

t48/rel_1_2/sw/verif/white_box/psen_rd_wr_timing/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/white_box/pc_wrap_bit11/test.asm =================================================================== --- t48/rel_1_2/sw/verif/white_box/pc_wrap_bit11/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/white_box/pc_wrap_bit11/test.asm (nonexistent) @@ -1,45 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Test wrap-around of Program Counter on bits 10 - 0. - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - ;; Start of test - - ;; decide whether this is the first time that the test - ;; executes from address 0 - in a, P1 - jnz first_time - - ;; came here for the second time - ;; -> that's great! - jmp pass - -first_time: - clr a - outl P1, a ; tag P1 -> lock this path - ;; jump to external Program Memory - jmp end_of_first_2k - -pass: PASS - -fail: FAIL - - - ;; end of first 2k program memory - ORG 07FEH -end_of_first_2k: - nop - nop - ;; no wrap-around to address 0 - - - ORG 0800H - - jmp fail -

t48/rel_1_2/sw/verif/white_box/pc_wrap_bit11/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/gp_sw/toggle/test.asm =================================================================== --- t48/rel_1_2/sw/verif/gp_sw/toggle/test.asm (revision 296) +++ t48/rel_1_2/sw/verif/gp_sw/toggle/test.asm (nonexistent) @@ -1,23 +0,0 @@ - ;; ******************************************************************* - ;; $Id$ - ;; - ;; Toggle P1[0] - ;; ******************************************************************* - - INCLUDE "cpu.inc" - INCLUDE "pass_fail.inc" - - ORG 0 - - mov a, #0FFH - -loop: outl p1, a - xrl a, #001H - - mov r1, #000H -wait1: - mov r0, #000H -wait2: djnz r0, wait2 - djnz r1, wait1 - - jmp loop

t48/rel_1_2/sw/verif/gp_sw/toggle/test.asm Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/verif/include/cpu.inc =================================================================== --- t48/rel_1_2/sw/verif/include/cpu.inc (revision 296) +++ t48/rel_1_2/sw/verif/include/cpu.inc (nonexistent) @@ -1,2 +0,0 @@ - - CPU 8048 Index: t48/rel_1_2/sw/verif/include/Makefile.core =================================================================== --- t48/rel_1_2/sw/verif/include/Makefile.core (revision 296) +++ t48/rel_1_2/sw/verif/include/Makefile.core (nonexistent) @@ -1,36 +0,0 @@ - -.PHONY: all -all: t3x t48 t49 - -.PHONY: t3x -t3x: $(SIM_DIR)/rom_t3x.hex $(SIM_DIR)/rom_t3x_ext.hex - -.PHONY: t48 -t48: $(SIM_DIR)/rom_t48.hex $(SIM_DIR)/rom_t48_ext.hex - -.PHONY: t49 -t49: $(SIM_DIR)/rom_t49.hex $(SIM_DIR)/rom_t49_ext.hex - - -$(MODULE).p: $(MODULE).asm - asl -i $(VERIF_DIR)/include -L $< - -$(SIM_DIR)/rom_t3x.hex: $(MODULE).p - p2hex -r 0-0 $< $@ -$(SIM_DIR)/rom_t3x_ext.hex: $(MODULE).p - p2hex -r 0-4095 $< $@ - -$(SIM_DIR)/rom_t48.hex: $(MODULE).p - p2hex -r 0-1023 $< $@ -# lowest 1k of external ROM will not be used -$(SIM_DIR)/rom_t48_ext.hex: $(MODULE).p - p2hex -r 1024-4095 $< $@ - -$(SIM_DIR)/rom_t49.hex: $(MODULE).p - p2hex -r 0-2047 $< $@ -$(SIM_DIR)/rom_t49_ext.hex: $(MODULE).p - p2hex -a -r 2048-4095 $< $@ - -.PHONY: clean -clean: - rm -f *.p *~ *.hex *.lst Index: t48/rel_1_2/sw/verif/include/pass_fail.inc =================================================================== --- t48/rel_1_2/sw/verif/include/pass_fail.inc (revision 296) +++ t48/rel_1_2/sw/verif/include/pass_fail.inc (nonexistent) @@ -1,12 +0,0 @@ - -FAIL MACRO - mov a, #0AAH - mov a, #055H - mov a, #000H - ENDM - -PASS MACRO - mov a, #0AAH - mov a, #055H - mov a, #001H - ENDM Index: t48/rel_1_2/sw/verif/include/Makefile.cell =================================================================== --- t48/rel_1_2/sw/verif/include/Makefile.cell (revision 296) +++ t48/rel_1_2/sw/verif/include/Makefile.cell (nonexistent) @@ -1,4 +0,0 @@ - -MODULE=test - -include $(VERIF_DIR)/include/Makefile.core Index: t48/rel_1_2/sw/init_project.template.sh =================================================================== --- t48/rel_1_2/sw/init_project.template.sh (revision 296) +++ t48/rel_1_2/sw/init_project.template.sh (nonexistent) @@ -1,17 +0,0 @@ -############################################################################## -# -# Template script to set up all project-specific environemt variables. -# -# Copy this script to init_project.sh and fill in your local information. -# -# This script has to be sourced from the command line! -# Do not run it as a 'usual' program, as this does not set the variables -# in the current shell process. -# -############################################################################## - -export PROJECT_DIR=/t48 -export VERIF_DIR=$PROJECT_DIR/sw/verif -export SIM_DIR=$PROJECT_DIR/sim/rtl_sim - -export PATH=$PATH:$PROJECT_DIR/sw Index: t48/rel_1_2/sw/run_regression.pl =================================================================== --- t48/rel_1_2/sw/run_regression.pl (revision 296) +++ t48/rel_1_2/sw/run_regression.pl (nonexistent) @@ -1,165 +0,0 @@ -#!/usr/bin/perl -w -# -# ############################################################################ -# -# run_regression.pl -# -# $Id$ -# -# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -# -# All rights reserved -# -# ############################################################################ -# -# Purpose: -# ======== -# -# Runs regression suite over all testcells found in $VERIF_DIR. -# -# run_regression.pl [-d] -# -d : Perform a dump compare on each test with the i8039 simulator. -# -# The testcells are identified by searching for the .asm file(s). -# Each testcell is built by calling the central Makefile.cell. -# The resulting hex-file is then copied to $SIM_DIR where the VHDL simulator -# is started. -# -# Exceptions for a testcell are defined by additional files. -# no_gen : don't execute the generic/default testbench tb_behav_c0 -# no_t48 : don't execute the t8048 testbench tb_t8048_behav_c0 -# no_t39 : don't execute the t8039 testbench tb_t8039_behav_c0 -# no_dump_compare : don't include testcell when running dump compares -# io_exp : use the testbenches containing the t8243 IO expander -# tb_t8243_behav_c0 -# tb_t8048_t8243_behav_c0 -# - - -use strict; - -use Getopt::Std; - - -sub print_usage { - print < './tb_behav_c0', - 't48' => './tb_t8048_behav_c0', - 't39' => './tb_t8039_behav_c0'); -my %ghdl_io_expanders = ('gen' => './tb_t8243_behav_c0', - 't48' => './tb_t8048_t8243_behav_c0'); -my $ghdl_simulator_opt = '--assert-level=error --stop-time=20ms'; -my $ghdl_simulator_vcd = './tb_behav_c0 --assert-level=error --vcd=temp.vcd'; -# -# Choose simulator: -my %vhdl_simulators = %ghdl_simulators; -my %vhdl_io_expanders = %ghdl_io_expanders; -my $vhdl_simulator_opt = $ghdl_simulator_opt; -my $vhdl_simulator_vcd = $ghdl_simulator_vcd; -my ($vhdl_simulator_tag, $vhdl_simulator); -# -############################################################################## - - -# process command line options -if (!getopts('d', \%options)) { - print_usage(); - exit(1); -} - -if (exists($options{'d'})) { - $dump_compare = 1; -} - -$pwd = `pwd`; -chomp($pwd); - - -@asm_files = `find \$VERIF_DIR/black_box -name '*.asm'`; -push(@asm_files, `find \$VERIF_DIR/white_box -name '*.asm'`); - - -foreach $asm_file (@asm_files) { - chomp($asm_file); - # strip off assembler file names - $asm_file =~ s/\/[^\/]+\.asm//; - # strip off verification directory - $asm_file =~ s/$ENV{'VERIF_DIR'}\///; - $cells{$asm_file} = 1; -} - -while (($cell, $tag) = each(%cells)) { - $cell_dir = "$ENV{'VERIF_DIR'}/$cell"; - - if (chdir($cell_dir)) { - print("Processing $cell\n"); - - $dump_compare_cell = -e 'no_dump_compare' ? 0 : $dump_compare; - $io_exp_cell = -e 'io_exp' ? 1 : 0; - - system('rm -f $SIM_DIR/*.hex'); - system('make -f $VERIF_DIR/include/Makefile.cell clean'); - system('make -f $VERIF_DIR/include/Makefile.cell all clean'); - if ($? == 0) { - chdir($ENV{'SIM_DIR'}); - - if ($dump_compare_cell) { - system($vhdl_simulator_vcd); - system('rm -f dump sim.dump vhdl.dump'); - system('vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump'); - system('i8039 -f t48_rom.hex -x t48_ext_rom.hex -d > dump'); - system('egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump'); - system('diff -b -q sim.dump vhdl.dump'); - print("Dump Compare: "); - if ($? == 0) { - print("PASS\n"); - } else { - print("FAIL\n"); - } - system('rm -f dump sim.dump vhdl.dump temp.vcd'); - } elsif ($dump_compare) { - print("Dump Compare: Excluded\n"); - } else { - # decide which simulator set is chosen for this cell - my %cell_simulators = $io_exp_cell ? %vhdl_io_expanders : - %vhdl_simulators; - - # run all enabled simulators - while (($vhdl_simulator_tag, $vhdl_simulator) = each %cell_simulators) { - if (! -e "$cell_dir/no_$vhdl_simulator_tag") { - print("Executing simulator $vhdl_simulator_tag\n"); - system($vhdl_simulator." ".$vhdl_simulator_opt); - } - } - } - - } else { - print("Error: Cannot make cell $cell!\n"); - } - } else { - print("Error: Cannot change to directory $cell_dir!\n"); - } -} - -chdir($pwd);

t48/rel_1_2/sw/run_regression.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/vec2dump.pl =================================================================== --- t48/rel_1_2/sw/vec2dump.pl (revision 296) +++ t48/rel_1_2/sw/vec2dump.pl (nonexistent) @@ -1,167 +0,0 @@ -#!/usr/bin/perl -w -# -# ############################################################################ -# -# vec2dump.pl -# -# $Id$ -# -# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -# -# All rights reserved -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. See also the file COPYING which -# came with this application. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# ############################################################################ -# -# Purpose: -# ======== -# -# Converts a vector file into the dump format for dump_compare. -# -# A vector stream is read from STDIN and the resulting dump is written -# to STDOUT. -# - - -use strict; - - -sub bin2hex { - my $string = shift; - my ($bit, $hex); - - $hex = 0; - foreach $bit (split(//, $string)) { - $hex <<= 1; - $hex |= $bit; - } - - return(sprintf("%02X", $hex)); -} - -sub hex8 { - my $uint = shift; - - if ($uint =~ /^b(.+)$/) { - return(bin2hex($1)); - } else { - return('??'); - } -} - -sub hex16 { - my $uint = shift; - - if ($uint =~ /^b(.+)(........)$/) { - return(bin2hex($1).bin2hex($2)); - } else { - return('????'); - } -} - -sub dump_ram { - my $ram = shift; - my $elem; - - foreach $elem (@{$ram}) { - print($elem.' '); - } -} - - -my (@signals, %index, @vector); -my $i; -my $value; -my $line; -my $istrobe; -my @ram; - - -# initialize RAM -for ($i = 0; $i < 256; $i++) { - $ram[$i] = '00'; -} - - -# scan for signal names -while () { - if (/^(\S+):/) { - chomp($_); - @signals = split(/ +/); - - # remove time information - shift(@signals); - last; - } -} - -# build index -for ($i = 0; $i < scalar(@signals); $i++) { - # strip off hierarchical path - $signals[$i] =~ s/.*\.//; - $index{$signals[$i]} = $i; -} - -$istrobe = 0; -# read vectors -while () { - if (/^\d+> /) { - chop($_); - @vector = split(/ +/); - - # remove time information - shift(@vector); - - # process write operation to RAM - if ($vector[$index{'we_tmp'}] eq '1') { - $ram[hex(hex8($vector[$index{'address_tmp[7:0]'}]))] = hex8($vector[$index{'data_tmp[7:0]'}]); - } - - # find falling instruction strobe - if ($istrobe == 0) { - $istrobe = $vector[0]; - next; - } else { - $istrobe = $vector[0]; - if ($vector[0] == 0) { - # falling edge detected - } else { - next; - } - } - - # process each signal - for ($i = 1; $i < scalar(@vector); $i++) { - $_ = $signals[$i]; - $line = ''; - - SWITCH: { - if (/^program_counter/) { print(hex16($vector[$i]).' '); last; } - if (/^accumulator/) { print(hex8($vector[$i]).' '); last; } - if (/^sp/) { print(hex8($vector[$i]).' '); last; } - if (/^psw/) { print(hex8($vector[$i]).' '); last; } - if (/^bus/) { print(hex8($vector[$i]).' '); last; } - if (/^f1/) { print($vector[$i].' '); last; } - if (/^p1/) { print(hex8($vector[$i]).' '); last; } - if (/^p2/) { print(hex8($vector[$i]).' '); last; } - if (/^mb/) { print($vector[$i].' '); last; } - if (/^we_tmp/) { dump_ram(\@ram); last; } - } - } - print("\n"); - } -}

t48/rel_1_2/sw/vec2dump.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/i8039emu/i8039.c =================================================================== --- t48/rel_1_2/sw/i8039emu/i8039.c (revision 296) +++ t48/rel_1_2/sw/i8039emu/i8039.c (nonexistent) @@ -1,841 +0,0 @@ -/**************************************************************************** - * Intel 8039 Portable Emulator * - * * - * Copyright (C) 1997 by Mirko Buffoni * - * Based on the original work (C) 1997 by Dan Boris, an 8048 emulator * - * You are not allowed to distribute this software commercially * - * Please, notify me, if you make any changes to this file * - * * - * Adapted for the T48 uController project, 2004 by Arnim Laeuger * - * See http://www.opencores.org/projects.cgi/web/t48/overview * - * * - * $Id$ - * * - * **** Change Log **** * - * * - * TLP (19-Jun-2001) * - * - Changed Ports 1 and 2 to quasi bidirectional output latched ports * - * - Added the Port 1 & 2 output latch data to the debugger window * - * TLP (02-Jan-2002) * - * - External IRQs no longer go pending (sampled as a level state) * - * - Timer IRQs do not go pending if Timer interrupts are disabled * - * - Timer IRQs made pending, were incorrectly being cleared if the * - * external interrupt was being serviced * - * - External interrupts now take precedence when simultaneous * - * internal and external interrupt requests occur * - * - 'DIS TCNTI' now removes pending timer IRQs * - * - Nested IRQs of any sort are no longer allowed * - * - T_flag was not being set in the right place of execution, which * - * could have lead to it being incorrectly set after being cleared * - * - Counter overflows now also set the T_flag * - * - Added the Timer/Counter register to the debugger window * - * TLP (09-Jan-2002) * - * - Changed Interrupt system to instant servicing * - * - The Timer and Counter can no longer be 'on' simultaneously * - * - Added Save State * - * TLP (15-Feb-2002) * - * - Corrected Positive signal edge sensing (used on the T1 input) * - ****************************************************************************/ - - -#include -#include -#include - -#include "i8039.h" - - -/*** Cycle times for the jump on condition instructions, are unusual. - Condition is tested during the first cycle, so if condition is not - met, second address fetch cycle may not really be taken. For now we - just use the cycle counts as listed in the i8048 user manual. -***/ - -#if 0 -#define ADJUST_CYCLES { inst_cycles -= 1; } /* Possible real cycles setting */ -#else -#define ADJUST_CYCLES { } /* User Manual cycles setting */ -#endif - - - -/* HJB 01/05/99 changed to positive values to use pending_irq as a flag */ -#define I8039_NO_INT 0 /* No Interrupts pending or executing */ -#define I8039_EXTERNAL_INT 1 /* Execute a normal external interrupt */ -#define I8039_TIMCNT_INT 2 /* Execute a Timer/Counter interrupt */ - - -/* Layout of the registers in the debugger */ -static UINT8 i8039_reg_layout[] = { - I8039_PC, I8039_SP, I8039_PSW, I8039_A, I8039_TC, I8039_P1, I8039_P2, -1, - I8039_R0, I8039_R1, I8039_R2, I8039_R3, I8039_R4, I8039_R5, I8039_R6, I8039_R7, 0 -}; - -/* Layout of the debugger windows x,y,w,h */ -static UINT8 i8039_win_layout[] = { - 0, 0,80, 2, /* register window (top rows) */ - 0, 3,24,19, /* disassembler window (left colums) */ - 25, 3,55, 9, /* memory #1 window (right, upper middle) */ - 25,13,55, 9, /* memory #2 window (right, lower middle) */ - 0,23,80, 1, /* command line window (bottom rows) */ -}; - - -static int Ext_IRQ(void); -static int Timer_IRQ(void); - -#define M_RDMEM(A) I8039_RDMEM(A) -#define M_RDOP(A) I8039_RDOP(A) -#define M_RDOP_ARG(A) I8039_RDOP_ARG(A) -#define M_IN(A) I8039_In(A) -#define M_OUT(A,V) I8039_Out(A,V) - -#define port_r(A) I8039_In(I8039_p0 + A) -#define port_w(A,V) I8039_Out(I8039_p0 + A,V) -#define test_r(A) I8039_In(I8039_t0 + A) -#define test_w(A,V) I8039_Out(I8039_t0 + A,V) -#define bus_r() I8039_In(I8039_bus) -#define bus_w(V) I8039_Out(I8039_bus,V) - -#define C_FLAG 0x80 -#define A_FLAG 0x40 -#define F_FLAG 0x20 -#define B_FLAG 0x10 - -typedef struct -{ - PAIR PREVPC; /* previous program counter */ - PAIR PC; /* program counter */ - UINT8 A, SP, PSW; - UINT8 RAM[256]; - UINT8 bus, f1; /* Bus data, and flag1 */ - UINT8 P1, P2; /* Internal Port 1 and 2 latched outputs */ - - UINT8 pending_irq, irq_executing, masterClock, regPtr; - UINT8 t_flag, timer, timerON, countON, xirq_en, tirq_en; - UINT16 A11, A11ff; - UINT8 irq_state, irq_extra_cycles; - int (*irq_callback)(int irqline); -} I8039_Regs; - -static I8039_Regs R; -int i8039_ICount; -int inst_cycles; -static UINT8 Old_T1; - -/* The opcode table now is a combination of cycle counts and function pointers */ -typedef struct { - unsigned cycles; - void (*function) (void); -} s_opcode; - -#define POSITIVE_EDGE_T1 (( (int)(T1-Old_T1) > 0) ? 1 : 0) -#define NEGATIVE_EDGE_T1 (( (int)(Old_T1-T1) > 0) ? 1 : 0) - -#define M_Cy ((R.PSW & C_FLAG) >> 7) -#define M_Cn (!M_Cy) -#define M_Ay ((R.PSW & A_FLAG)) -#define M_An (!M_Ay) -#define M_F0y ((R.PSW & F_FLAG)) -#define M_F0n (!M_F0y) -#define M_By ((R.PSW & B_FLAG)) -#define M_Bn (!M_By) - -#define intRAM R.RAM -#define regPTR R.regPtr - -#define R0 intRAM[regPTR ] -#define R1 intRAM[regPTR+1] -#define R2 intRAM[regPTR+2] -#define R3 intRAM[regPTR+3] -#define R4 intRAM[regPTR+4] -#define R5 intRAM[regPTR+5] -#define R6 intRAM[regPTR+6] -#define R7 intRAM[regPTR+7] - - -INLINE void CLR (UINT8 flag) { R.PSW &= ~flag; } -INLINE void SET (UINT8 flag) { R.PSW |= flag; } - - -/* Get next opcode argument and increment program counter */ -INLINE unsigned M_RDMEM_OPCODE (void) -{ - unsigned retval; - retval=M_RDOP_ARG(R.PC.w.l); - R.PC.w.l++; - return retval; -} - -INLINE void push(UINT8 d) -{ - intRAM[8+R.SP++] = d; - R.SP = R.SP & 0x0f; - R.PSW = R.PSW & 0xf8; - R.PSW = R.PSW | (R.SP >> 1); -} - -INLINE UINT8 pull(void) { - R.SP = (R.SP + 15) & 0x0f; /* if (--R.SP < 0) R.SP = 15; */ - R.PSW = R.PSW & 0xf8; - R.PSW = R.PSW | (R.SP >> 1); - /* regPTR = ((M_By) ? 24 : 0); regPTR should not change */ - return intRAM[8+R.SP]; -} - -INLINE void daa_a(void) -{ - if ((R.A & 0x0f) > 0x09 || (R.PSW & A_FLAG)) - R.A += 0x06; - if ((R.A & 0xf0) > 0x90 || (R.PSW & C_FLAG)) - { - R.A += 0x60; - SET(C_FLAG); - } else CLR(C_FLAG); -} - -INLINE void M_ADD(UINT8 dat) -{ - UINT16 temp; - - CLR(C_FLAG | A_FLAG); - if ((R.A & 0xf) + (dat & 0xf) > 0xf) SET(A_FLAG); - temp = R.A + dat; - if (temp > 0xff) SET(C_FLAG); - R.A = temp & 0xff; -} - -INLINE void M_ADDC(UINT8 dat) -{ - UINT16 temp; - - CLR(A_FLAG); - if ((R.A & 0xf) + (dat & 0xf) + M_Cy > 0xf) SET(A_FLAG); - temp = R.A + dat + M_Cy; - CLR(C_FLAG); - if (temp > 0xff) SET(C_FLAG); - R.A = temp & 0xff; -} - -INLINE void M_CALL(UINT16 addr) -{ - push(R.PC.b.l); - push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); - R.PC.w.l = addr; - -} - -INLINE void M_XCHD(UINT8 addr) -{ - UINT8 dat = R.A & 0x0f; - R.A &= 0xf0; - R.A |= intRAM[addr] & 0x0f; - intRAM[addr] &= 0xf0; - intRAM[addr] |= dat; -} - - -INLINE void M_ILLEGAL(void) -{ - logerror("I8039: PC = %04x, Illegal opcode = %02x\n", R.PC.w.l-1, M_RDMEM(R.PC.w.l-1)); -} - -INLINE void M_UNDEFINED(void) -{ - logerror("I8039: PC = %04x, Unimplemented opcode = %02x\n", R.PC.w.l-1, M_RDMEM(R.PC.w.l-1)); -} - -#define INT_RAM_MASK 0xff - -static void illegal(void) { M_ILLEGAL(); } - -static void add_a_n(void) { M_ADD(M_RDMEM_OPCODE()); } -static void add_a_r0(void) { M_ADD(R0); } -static void add_a_r1(void) { M_ADD(R1); } -static void add_a_r2(void) { M_ADD(R2); } -static void add_a_r3(void) { M_ADD(R3); } -static void add_a_r4(void) { M_ADD(R4); } -static void add_a_r5(void) { M_ADD(R5); } -static void add_a_r6(void) { M_ADD(R6); } -static void add_a_r7(void) { M_ADD(R7); } -static void add_a_xr0(void) { M_ADD(intRAM[R0 & INT_RAM_MASK]); } -static void add_a_xr1(void) { M_ADD(intRAM[R1 & INT_RAM_MASK]); } -static void adc_a_n(void) { M_ADDC(M_RDMEM_OPCODE()); } -static void adc_a_r0(void) { M_ADDC(R0); } -static void adc_a_r1(void) { M_ADDC(R1); } -static void adc_a_r2(void) { M_ADDC(R2); } -static void adc_a_r3(void) { M_ADDC(R3); } -static void adc_a_r4(void) { M_ADDC(R4); } -static void adc_a_r5(void) { M_ADDC(R5); } -static void adc_a_r6(void) { M_ADDC(R6); } -static void adc_a_r7(void) { M_ADDC(R7); } -static void adc_a_xr0(void) { M_ADDC(intRAM[R0 & INT_RAM_MASK]); } -static void adc_a_xr1(void) { M_ADDC(intRAM[R1 & INT_RAM_MASK]); } -static void anl_a_n(void) { R.A &= M_RDMEM_OPCODE(); } -static void anl_a_r0(void) { R.A &= R0; } -static void anl_a_r1(void) { R.A &= R1; } -static void anl_a_r2(void) { R.A &= R2; } -static void anl_a_r3(void) { R.A &= R3; } -static void anl_a_r4(void) { R.A &= R4; } -static void anl_a_r5(void) { R.A &= R5; } -static void anl_a_r6(void) { R.A &= R6; } -static void anl_a_r7(void) { R.A &= R7; } -static void anl_a_xr0(void) { R.A &= intRAM[R0 & INT_RAM_MASK]; } -static void anl_a_xr1(void) { R.A &= intRAM[R1 & INT_RAM_MASK]; } -static void anl_bus_n(void) { bus_w( bus_r() & M_RDMEM_OPCODE() ); } -static void anl_p1_n(void) { R.P1 &= M_RDMEM_OPCODE(); port_w( 1, R.P1 ); } -static void anl_p2_n(void) { R.P2 &= M_RDMEM_OPCODE(); port_w( 2, R.P2 ); } -static void anld_p4_a(void) { port_w( 4, port_r(4) & M_RDMEM_OPCODE() ); } -static void anld_p5_a(void) { port_w( 5, port_r(5) & M_RDMEM_OPCODE() ); } -static void anld_p6_a(void) { port_w( 6, port_r(6) & M_RDMEM_OPCODE() ); } -static void anld_p7_a(void) { port_w( 7, port_r(7) & M_RDMEM_OPCODE() ); } -static void call(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | R.A11); } -static void call_1(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x100 | R.A11); } -static void call_2(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x200 | R.A11); } -static void call_3(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x300 | R.A11); } -static void call_4(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x400 | R.A11); } -static void call_5(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x500 | R.A11); } -static void call_6(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x600 | R.A11); } -static void call_7(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x700 | R.A11); } -static void clr_a(void) { R.A=0; } -static void clr_c(void) { CLR(C_FLAG); } -static void clr_f0(void) { CLR(F_FLAG); } -static void clr_f1(void) { R.f1 = 0; } -static void cpl_a(void) { R.A ^= 0xff; } -static void cpl_c(void) { R.PSW ^= C_FLAG; } -static void cpl_f0(void) { R.PSW ^= F_FLAG; } -static void cpl_f1(void) { R.f1 ^= 1; } -static void dec_a(void) { R.A--; } -static void dec_r0(void) { R0--; } -static void dec_r1(void) { R1--; } -static void dec_r2(void) { R2--; } -static void dec_r3(void) { R3--; } -static void dec_r4(void) { R4--; } -static void dec_r5(void) { R5--; } -static void dec_r6(void) { R6--; } -static void dec_r7(void) { R7--; } -static void dis_i(void) { R.xirq_en = 0; } -static void dis_tcnti(void) { R.tirq_en = 0; R.pending_irq &= ~I8039_TIMCNT_INT; } -static void djnz_r0(void) { UINT8 i=M_RDMEM_OPCODE(); R0--; if (R0 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r1(void) { UINT8 i=M_RDMEM_OPCODE(); R1--; if (R1 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r2(void) { UINT8 i=M_RDMEM_OPCODE(); R2--; if (R2 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r3(void) { UINT8 i=M_RDMEM_OPCODE(); R3--; if (R3 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r4(void) { UINT8 i=M_RDMEM_OPCODE(); R4--; if (R4 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r5(void) { UINT8 i=M_RDMEM_OPCODE(); R5--; if (R5 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r6(void) { UINT8 i=M_RDMEM_OPCODE(); R6--; if (R6 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void djnz_r7(void) { UINT8 i=M_RDMEM_OPCODE(); R7--; if (R7 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void en_i(void) { R.xirq_en = 1; if (R.irq_state == I8039_EXTERNAL_INT) { R.irq_extra_cycles += Ext_IRQ(); } } -static void en_tcnti(void) { R.tirq_en = 1; } -static void ento_clk(void) { M_UNDEFINED(); } -static void in_a_p1(void) { R.A = port_r(1) & R.P1; } -static void in_a_p2(void) { R.A = port_r(2) & R.P2; } -static void ins_a_bus(void) { R.A = bus_r(); } -static void inc_a(void) { R.A++; } -static void inc_r0(void) { R0++; } -static void inc_r1(void) { R1++; } -static void inc_r2(void) { R2++; } -static void inc_r3(void) { R3++; } -static void inc_r4(void) { R4++; } -static void inc_r5(void) { R5++; } -static void inc_r6(void) { R6++; } -static void inc_r7(void) { R7++; } -static void inc_xr0(void) { intRAM[R0 & INT_RAM_MASK]++; } -static void inc_xr1(void) { intRAM[R1 & INT_RAM_MASK]++; } - -/* static void jmp(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | R.A11; } - */ - -static void jmp(void) -{ - UINT8 i=M_RDOP(R.PC.w.l); - UINT16 oldpc,newpc; - - oldpc = R.PC.w.l-1; - R.PC.w.l = i | R.A11; - newpc = R.PC.w.l; - if (newpc == oldpc) { if (i8039_ICount > 0) i8039_ICount = 0; } /* speed up busy loop */ - else if (newpc == oldpc-1 && M_RDOP(newpc) == 0x00) /* NOP - Gyruss */ - { if (i8039_ICount > 0) i8039_ICount = 0; } -} - -static void jmp_1(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x100 | R.A11; } -static void jmp_2(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x200 | R.A11; } -static void jmp_3(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x300 | R.A11; } -static void jmp_4(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x400 | R.A11; } -static void jmp_5(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x500 | R.A11; } -static void jmp_6(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x600 | R.A11; } -static void jmp_7(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x700 | R.A11; } -static void jmpp_xa(void) { UINT16 addr = (R.PC.w.l & 0xf00) | R.A; R.PC.w.l = (R.PC.w.l & 0xf00) | M_RDMEM(addr); } -static void jb_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x01) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x02) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_2(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x04) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_3(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x08) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_4(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x10) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_5(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x20) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_6(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x40) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jb_7(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x80) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jf0(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_F0y) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jf1(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.f1) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jnc(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_Cn) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jc(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_Cy) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jni(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.irq_state == I8039_EXTERNAL_INT) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jnt_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (!test_r(0)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jt_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (test_r(0)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jnt_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (!test_r(1)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jt_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (test_r(1)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jnz(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jz(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A == 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } -static void jtf(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.t_flag) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; R.t_flag = 0; } else ADJUST_CYCLES } - -static void mov_a_n(void) { R.A = M_RDMEM_OPCODE(); } -static void mov_a_r0(void) { R.A = R0; } -static void mov_a_r1(void) { R.A = R1; } -static void mov_a_r2(void) { R.A = R2; } -static void mov_a_r3(void) { R.A = R3; } -static void mov_a_r4(void) { R.A = R4; } -static void mov_a_r5(void) { R.A = R5; } -static void mov_a_r6(void) { R.A = R6; } -static void mov_a_r7(void) { R.A = R7; } -static void mov_a_psw(void) { R.A = R.PSW | 0x08; } -static void mov_a_xr0(void) { R.A = intRAM[R0 & INT_RAM_MASK]; } -static void mov_a_xr1(void) { R.A = intRAM[R1 & INT_RAM_MASK]; } -static void mov_r0_a(void) { R0 = R.A; } -static void mov_r1_a(void) { R1 = R.A; } -static void mov_r2_a(void) { R2 = R.A; } -static void mov_r3_a(void) { R3 = R.A; } -static void mov_r4_a(void) { R4 = R.A; } -static void mov_r5_a(void) { R5 = R.A; } -static void mov_r6_a(void) { R6 = R.A; } -static void mov_r7_a(void) { R7 = R.A; } -static void mov_psw_a(void) { R.PSW = R.A | 0x08; regPTR = ((M_By) ? 24 : 0); R.SP = (R.PSW & 7) << 1; } -static void mov_r0_n(void) { R0 = M_RDMEM_OPCODE(); } -static void mov_r1_n(void) { R1 = M_RDMEM_OPCODE(); } -static void mov_r2_n(void) { R2 = M_RDMEM_OPCODE(); } -static void mov_r3_n(void) { R3 = M_RDMEM_OPCODE(); } -static void mov_r4_n(void) { R4 = M_RDMEM_OPCODE(); } -static void mov_r5_n(void) { R5 = M_RDMEM_OPCODE(); } -static void mov_r6_n(void) { R6 = M_RDMEM_OPCODE(); } -static void mov_r7_n(void) { R7 = M_RDMEM_OPCODE(); } -static void mov_a_t(void) { R.A = R.timer; } -static void mov_t_a(void) { R.timer = R.A; } -static void mov_xr0_a(void) { intRAM[R0 & INT_RAM_MASK] = R.A; } -static void mov_xr1_a(void) { intRAM[R1 & INT_RAM_MASK] = R.A; } -static void mov_xr0_n(void) { intRAM[R0 & INT_RAM_MASK] = M_RDMEM_OPCODE(); } -static void mov_xr1_n(void) { intRAM[R1 & INT_RAM_MASK] = M_RDMEM_OPCODE(); } -static void movd_a_p4(void) { R.A = port_r(4); } -static void movd_a_p5(void) { R.A = port_r(5); } -static void movd_a_p6(void) { R.A = port_r(6); } -static void movd_a_p7(void) { R.A = port_r(7); } -static void movd_p4_a(void) { port_w(4, R.A); } -static void movd_p5_a(void) { port_w(5, R.A); } -static void movd_p6_a(void) { port_w(6, R.A); } -static void movd_p7_a(void) { port_w(7, R.A); } -static void movp_a_xa(void) { R.A = M_RDMEM((R.PC.w.l & 0x0f00) | R.A); } -static void movp3_a_xa(void) { R.A = M_RDMEM(0x300 | R.A); } -static void movx_a_xr0(void) { R.A = M_IN(R0); } -static void movx_a_xr1(void) { R.A = M_IN(R1); } -static void movx_xr0_a(void) { M_OUT(R0, R.A); } -static void movx_xr1_a(void) { M_OUT(R1, R.A); } -static void nop(void) { } -static void orl_a_n(void) { R.A |= M_RDMEM_OPCODE(); } -static void orl_a_r0(void) { R.A |= R0; } -static void orl_a_r1(void) { R.A |= R1; } -static void orl_a_r2(void) { R.A |= R2; } -static void orl_a_r3(void) { R.A |= R3; } -static void orl_a_r4(void) { R.A |= R4; } -static void orl_a_r5(void) { R.A |= R5; } -static void orl_a_r6(void) { R.A |= R6; } -static void orl_a_r7(void) { R.A |= R7; } -static void orl_a_xr0(void) { R.A |= intRAM[R0 & INT_RAM_MASK]; } -static void orl_a_xr1(void) { R.A |= intRAM[R1 & INT_RAM_MASK]; } -static void orl_bus_n(void) { bus_w( bus_r() | M_RDMEM_OPCODE() ); } -static void orl_p1_n(void) { R.P1 |= M_RDMEM_OPCODE(); port_w(1, R.P1); } -static void orl_p2_n(void) { R.P2 |= M_RDMEM_OPCODE(); port_w(2, R.P2); } -static void orld_p4_a(void) { port_w(4, port_r(4) | R.A ); } -static void orld_p5_a(void) { port_w(5, port_r(5) | R.A ); } -static void orld_p6_a(void) { port_w(6, port_r(6) | R.A ); } -static void orld_p7_a(void) { port_w(7, port_r(7) | R.A ); } -static void outl_bus_a(void) { bus_w(R.A); } -static void outl_p1_a(void) { port_w(1, R.A); R.P1 = R.A; } -static void outl_p2_a(void) { port_w(2, R.A); R.P2 = R.A; } -static void ret(void) { R.PC.w.l = ((pull() & 0x0f) << 8); R.PC.w.l |= pull(); } - -static void retr(void) -{ - UINT8 i=pull(); - R.PC.w.l = ((i & 0x0f) << 8) | pull(); - R.PSW = (R.PSW & 0x0f) | (i & 0xf0); /* Stack is already changed by pull */ - regPTR = ((M_By) ? 24 : 0); - - R.irq_executing = I8039_NO_INT; - - R.A11 = R.A11ff; - - /* Take an interrupt if a request is still being made */ - if (R.irq_state == I8039_EXTERNAL_INT) { - R.irq_extra_cycles += Ext_IRQ(); /* Service External IRQ */ - } - else if (R.pending_irq == I8039_TIMCNT_INT) { - R.irq_extra_cycles += Timer_IRQ(); /* Service pending Timer/Counter IRQ */ - } -} -static void rl_a(void) { UINT8 i=R.A & 0x80; R.A <<= 1; if (i) R.A |= 0x01; else R.A &= 0xfe; } -/* NS990113 */ -static void rlc_a(void) { UINT8 i=M_Cy; if (R.A & 0x80) SET(C_FLAG); else CLR(C_FLAG); R.A <<= 1; if (i) R.A |= 0x01; else R.A &= 0xfe; } -static void rr_a(void) { UINT8 i=R.A & 1; R.A >>= 1; if (i) R.A |= 0x80; else R.A &= 0x7f; } -/* NS990113 */ -static void rrc_a(void) { UINT8 i=M_Cy; if (R.A & 1) SET(C_FLAG); else CLR(C_FLAG); R.A >>= 1; if (i) R.A |= 0x80; else R.A &= 0x7f; } -static void sel_mb0(void) { R.A11 = 0; R.A11ff = 0; } -static void sel_mb1(void) { R.A11ff = 0x800; R.A11 = 0x800; } -static void sel_rb0(void) { CLR(B_FLAG); regPTR = 0; } -static void sel_rb1(void) { SET(B_FLAG); regPTR = 24; } -static void stop_tcnt(void) { R.timerON = R.countON = 0; } -static void strt_cnt(void) { R.countON = 1; R.timerON = 0; Old_T1 = test_r(1); } /* NS990113 */ -static void strt_t(void) { R.timerON = 1; R.countON = 0; R.masterClock = 0; } /* NS990113 */ -static void swap_a(void) { UINT8 i=R.A >> 4; R.A <<= 4; R.A |= i; } -static void xch_a_r0(void) { UINT8 i=R.A; R.A=R0; R0=i; } -static void xch_a_r1(void) { UINT8 i=R.A; R.A=R1; R1=i; } -static void xch_a_r2(void) { UINT8 i=R.A; R.A=R2; R2=i; } -static void xch_a_r3(void) { UINT8 i=R.A; R.A=R3; R3=i; } -static void xch_a_r4(void) { UINT8 i=R.A; R.A=R4; R4=i; } -static void xch_a_r5(void) { UINT8 i=R.A; R.A=R5; R5=i; } -static void xch_a_r6(void) { UINT8 i=R.A; R.A=R6; R6=i; } -static void xch_a_r7(void) { UINT8 i=R.A; R.A=R7; R7=i; } -static void xch_a_xr0(void) { UINT8 i=R.A; R.A=intRAM[R0 & INT_RAM_MASK]; intRAM[R0 & INT_RAM_MASK]=i; } -static void xch_a_xr1(void) { UINT8 i=R.A; R.A=intRAM[R1 & INT_RAM_MASK]; intRAM[R1 & INT_RAM_MASK]=i; } -static void xchd_a_xr0(void) { M_XCHD(R0 & INT_RAM_MASK); } -static void xchd_a_xr1(void) { M_XCHD(R1 & INT_RAM_MASK); } -static void xrl_a_n(void) { R.A ^= M_RDMEM_OPCODE(); } -static void xrl_a_r0(void) { R.A ^= R0; } -static void xrl_a_r1(void) { R.A ^= R1; } -static void xrl_a_r2(void) { R.A ^= R2; } -static void xrl_a_r3(void) { R.A ^= R3; } -static void xrl_a_r4(void) { R.A ^= R4; } -static void xrl_a_r5(void) { R.A ^= R5; } -static void xrl_a_r6(void) { R.A ^= R6; } -static void xrl_a_r7(void) { R.A ^= R7; } -static void xrl_a_xr0(void) { R.A ^= intRAM[R0 & INT_RAM_MASK]; } -static void xrl_a_xr1(void) { R.A ^= intRAM[R1 & INT_RAM_MASK]; } - -static s_opcode opcode_main[256]= -{ - {1, nop },{0, illegal },{2, outl_bus_a },{2, add_a_n },{2, jmp },{1, en_i },{0, illegal },{1, dec_a }, - {2, ins_a_bus },{2, in_a_p1 },{2, in_a_p2 },{0, illegal },{2, movd_a_p4 },{2, movd_a_p5 },{2, movd_a_p6 },{2, movd_a_p7 }, - {1, inc_xr0 },{1, inc_xr1 },{2, jb_0 },{2, adc_a_n },{2, call },{1, dis_i },{2, jtf },{1, inc_a }, - {1, inc_r0 },{1, inc_r1 },{1, inc_r2 },{1, inc_r3 },{1, inc_r4 },{1, inc_r5 },{1, inc_r6 },{1, inc_r7 }, - {1, xch_a_xr0 },{1, xch_a_xr1 },{0, illegal },{2, mov_a_n },{2, jmp_1 },{1, en_tcnti },{2, jnt_0 },{1, clr_a }, - {1, xch_a_r0 },{1, xch_a_r1 },{1, xch_a_r2 },{1, xch_a_r3 },{1, xch_a_r4 },{1, xch_a_r5 },{1, xch_a_r6 },{1, xch_a_r7 }, - {1, xchd_a_xr0 },{1, xchd_a_xr1 },{2, jb_1 },{0, illegal },{2, call_1 },{1, dis_tcnti },{2, jt_0 },{1, cpl_a }, - {0, illegal },{2, outl_p1_a },{2, outl_p2_a },{0, illegal },{2, movd_p4_a },{2, movd_p5_a },{2, movd_p6_a },{2, movd_p7_a }, - {1, orl_a_xr0 },{1, orl_a_xr1 },{1, mov_a_t },{2, orl_a_n },{2, jmp_2 },{1, strt_cnt },{2, jnt_1 },{1, swap_a }, - {1, orl_a_r0 },{1, orl_a_r1 },{1, orl_a_r2 },{1, orl_a_r3 },{1, orl_a_r4 },{1, orl_a_r5 },{1, orl_a_r6 },{1, orl_a_r7 }, - {1, anl_a_xr0 },{1, anl_a_xr1 },{2, jb_2 },{2, anl_a_n },{2, call_2 },{1, strt_t },{2, jt_1 },{1, daa_a }, - {1, anl_a_r0 },{1, anl_a_r1 },{1, anl_a_r2 },{1, anl_a_r3 },{1, anl_a_r4 },{1, anl_a_r5 },{1, anl_a_r6 },{1, anl_a_r7 }, - {1, add_a_xr0 },{1, add_a_xr1 },{1, mov_t_a },{0, illegal },{2, jmp_3 },{1, stop_tcnt },{0, illegal },{1, rrc_a }, - {1, add_a_r0 },{1, add_a_r1 },{1, add_a_r2 },{1, add_a_r3 },{1, add_a_r4 },{1, add_a_r5 },{1, add_a_r6 },{1, add_a_r7 }, - {1, adc_a_xr0 },{1, adc_a_xr1 },{2, jb_3 },{0, illegal },{2, call_3 },{1, ento_clk },{2, jf1 },{1, rr_a }, - {1, adc_a_r0 },{1, adc_a_r1 },{1, adc_a_r2 },{1, adc_a_r3 },{1, adc_a_r4 },{1, adc_a_r5 },{1, adc_a_r6 },{1, adc_a_r7 }, - {2, movx_a_xr0 },{2, movx_a_xr1 },{0, illegal },{2, ret },{2, jmp_4 },{1, clr_f0 },{2, jni },{0, illegal }, - {2, orl_bus_n },{2, orl_p1_n },{2, orl_p2_n },{0, illegal },{2, orld_p4_a },{2, orld_p5_a },{2, orld_p6_a },{2, orld_p7_a }, - {2, movx_xr0_a },{2, movx_xr1_a },{2, jb_4 },{2, retr },{2, call_4 },{1, cpl_f0 },{2, jnz },{1, clr_c }, - {2, anl_bus_n },{2, anl_p1_n },{2, anl_p2_n },{0, illegal },{2, anld_p4_a },{2, anld_p5_a },{2, anld_p6_a },{2, anld_p7_a }, - {1, mov_xr0_a },{1, mov_xr1_a },{0, illegal },{2, movp_a_xa },{2, jmp_5 },{1, clr_f1 },{0, illegal },{1, cpl_c }, - {1, mov_r0_a },{1, mov_r1_a },{1, mov_r2_a },{1, mov_r3_a },{1, mov_r4_a },{1, mov_r5_a },{1, mov_r6_a },{1, mov_r7_a }, - {2, mov_xr0_n },{2, mov_xr1_n },{2, jb_5 },{2, jmpp_xa },{2, call_5 },{1, cpl_f1 },{2, jf0 },{0, illegal }, - {2, mov_r0_n },{2, mov_r1_n },{2, mov_r2_n },{2, mov_r3_n },{2, mov_r4_n },{2, mov_r5_n },{2, mov_r6_n },{2, mov_r7_n }, - {0, illegal },{0, illegal },{0, illegal },{0, illegal },{2, jmp_6 },{1, sel_rb0 },{2, jz },{1, mov_a_psw }, - {1, dec_r0 },{1, dec_r1 },{1, dec_r2 },{1, dec_r3 },{1, dec_r4 },{1, dec_r5 },{1, dec_r6 },{1, dec_r7 }, - {1, xrl_a_xr0 },{1, xrl_a_xr1 },{2, jb_6 },{2, xrl_a_n },{2, call_6 },{1, sel_rb1 },{0, illegal },{1, mov_psw_a }, - {1, xrl_a_r0 },{1, xrl_a_r1 },{1, xrl_a_r2 },{1, xrl_a_r3 },{1, xrl_a_r4 },{1, xrl_a_r5 },{1, xrl_a_r6 },{1, xrl_a_r7 }, - {0, illegal },{0, illegal },{0, illegal },{2, movp3_a_xa },{2, jmp_7 },{1, sel_mb0 },{2, jnc },{1, rl_a }, - {2, djnz_r0 },{2, djnz_r1 },{2, djnz_r2 },{2, djnz_r3 },{2, djnz_r4 },{2, djnz_r5 },{2, djnz_r6 },{2, djnz_r7 }, - {1, mov_a_xr0 },{1, mov_a_xr1 },{2, jb_7 },{0, illegal },{2, call_7 },{1, sel_mb1 },{2, jc },{1, rlc_a }, - {1, mov_a_r0 },{1, mov_a_r1 },{1, mov_a_r2 },{1, mov_a_r3 },{1, mov_a_r4 },{1, mov_a_r5 },{1, mov_a_r6 },{1, mov_a_r7 } -}; - - -/**************************************************************************** - * Reset registers to their initial values - ****************************************************************************/ -void i8039_reset (void *param) -{ - R.PC.w.l = 0; - R.SP = 0; - R.A = 0; - R.PSW = 0x08; /* Start with Carry SET, Bit 4 is always SET */ - memset(R.RAM, 0x0, 128); - R.P1 = 0xff; - R.P2 = 0xff; - R.bus = 0; - R.irq_executing = I8039_NO_INT; - R.pending_irq = I8039_NO_INT; - - R.A11ff = R.A11 = 0; - R.tirq_en = R.xirq_en = 0; - R.timerON = R.countON = 0; - R.timerON = 1; /* Mario Bros. doesn't work without this */ - R.irq_extra_cycles = 0; - R.masterClock = 0; - - /* print dump header */ - printf(" Addr | Instruction | PC Accu SP PSW BUS F1 P1 P2 A11 RAM\n"); - printf(" ------+--------------------+---------------------------------------\n"); -} - - -/**************************************************************************** - * Shut down CPU emulation - ****************************************************************************/ -static void i8039_exit (void) -{ - /* nothing to do ? */ -} - -/**************************************************************************** - * Issue an interrupt if necessary - ****************************************************************************/ -static int Ext_IRQ(void) -{ - int extra_cycles = 0; - - if (R.xirq_en) { - if (R.irq_executing == I8039_NO_INT) { -/* logerror("I8039: EXT INTERRUPT being serviced\n"); */ - R.irq_executing = I8039_EXTERNAL_INT; - push(R.PC.b.l); - push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); - R.PC.w.l = 0x03; - R.A11ff = R.A11; - R.A11 = 0; - - extra_cycles = 2; /* 2 clock cycles used */ - - if (R.timerON) /* NS990113 */ - R.masterClock += extra_cycles; - if (R.irq_callback) (*R.irq_callback)(0); - } - } - - return extra_cycles; -} - -static int Timer_IRQ(void) -{ - int extra_cycles = 0; - - if (R.tirq_en) { - if (R.irq_executing == I8039_NO_INT) { -/* logerror("I8039: TIMER/COUNTER INTERRUPT\n"); */ - R.irq_executing = I8039_TIMCNT_INT; - R.pending_irq &= ~I8039_TIMCNT_INT; - push(R.PC.b.l); - push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); - R.PC.w.l = 0x07; - R.A11ff = R.A11; - R.A11 = 0; - - extra_cycles = 2; /* 2 clock cycles used */ - - if (R.timerON) /* NS990113 */ - R.masterClock += extra_cycles; - } - else { - if (R.irq_executing == I8039_EXTERNAL_INT) { - R.pending_irq |= I8039_TIMCNT_INT; - } - } - } - - R.t_flag = 1; - - return extra_cycles; -} - - -static void dump_machine_state(void) -{ - int i; - - printf(" | %04X %02X %02X %02X", (UINT32)R.PC.w.l, (UINT32)R.A, (UINT32)(R.SP >> 1), (UINT32)R.PSW); - printf(" %02X %X %02X %02X", (UINT32)R.bus, (UINT32)R.f1, (UINT32)R.P1, (UINT32)R.P2); - printf(" %X ", (UINT32)(R.A11ff >> 11)); - - for (i = 0; i < 256; i++) - printf(" %02X", R.RAM[i]); - - printf("\n"); -} - - -enum {ACCU_IDLE, ACCU_HAS_AA, ACCU_HAS_55, ACCU_PASS, ACCU_FAIL}; - -/**************************************************************************** - * Execute cycles CPU cycles. Return number of cycles really executed - ****************************************************************************/ -int i8039_execute(int cycles, int dump) -{ - unsigned opcode, T1; - int count, i; - char buffer[64]; - char string[32]; - - static int accu = 0; - static int accu_state = ACCU_IDLE; - - i8039_ICount = (cycles - R.irq_extra_cycles); - R.irq_extra_cycles = 0; - - if ((accu_state == ACCU_PASS) || (accu_state == ACCU_FAIL)) { - printf("End of simulation detected\n"); - - return(accu_state == ACCU_PASS ? 0 : -1); - } - - do - { - R.PREVPC = R.PC; - - - opcode=M_RDOP(R.PC.w.l); - - buffer[0] = '\0'; - Dasm8039(buffer, R.PC.w.l); - sprintf(string, " %04X : %s", R.PC.w.l, buffer); - for (i = strlen(string); i < 26; i++) - string[i] = ' '; - string[i <= 31 ? i : 31] = '\0'; - printf("%s", string); - -/* logerror("I8039: PC = %04x, opcode = %02x\n", R.PC.w.l, opcode); */ - - R.PC.w.l++; - inst_cycles = opcode_main[opcode].cycles; - (*(opcode_main[opcode].function))(); - i8039_ICount -= inst_cycles; /*/ */ - - if (dump == 1) { - /* dump machine state information */ - dump_machine_state(); - } else - printf("\n"); - - /* end-of-simulation check */ - if (accu != R.A) { - accu = R.A; - - switch (accu_state) { - case ACCU_IDLE: - accu_state = accu == 0xaa ? ACCU_HAS_AA : ACCU_IDLE; - break; - - case ACCU_HAS_AA: - accu_state = accu == 0x55 ? ACCU_HAS_55 : ACCU_IDLE; - break; - - case ACCU_HAS_55: - switch (accu) { - case 0x01: - accu_state = ACCU_PASS; - break; - case 0x00: - accu_state = ACCU_FAIL; - break; - default: - accu_state = ACCU_IDLE; - break; - } - break; - - case ACCU_PASS: - case ACCU_FAIL: - break; - - default: - accu_state = ACCU_IDLE; - break; - } - } - - - - - if (R.countON) /* NS990113 */ - { - for ( ; inst_cycles > 0; inst_cycles-- ) - { - T1 = test_r(1); - if (NEGATIVE_EDGE_T1) - { - R.timer++; - if (R.timer == 0) { - count = Timer_IRQ(); /* Handle Counter IRQ */ - i8039_ICount -= count; - } - } - Old_T1 = T1; - } - } - - if (R.timerON) { - R.masterClock += opcode_main[opcode].cycles; - if (R.masterClock >= 32) { /* NS990113 */ - R.masterClock -= 32; - R.timer++; - if (R.timer == 0) { - count = Timer_IRQ(); /* Handle Timer IRQ */ - i8039_ICount -= count; - } - } - } - } while (i8039_ICount > 0 && accu_state != ACCU_PASS && accu_state != ACCU_FAIL); - - i8039_ICount -= R.irq_extra_cycles; - R.irq_extra_cycles = 0; - - return cycles - i8039_ICount; -} - -/**************************************************************************** - * Get all registers in given buffer - ****************************************************************************/ -static void i8039_get_context (void *dst) -{ - if( dst ) - *(I8039_Regs*)dst = R; -} - - -/**************************************************************************** - * Set all registers to given values - ****************************************************************************/ -static void i8039_set_context (void *src) -{ - if( src ) - { - R = *(I8039_Regs*)src; - regPTR = ((M_By) ? 24 : 0); - R.SP = (R.PSW << 1) & 0x0f; - } - /* Handle forced Interrupts throught the Debugger */ - if (R.irq_state != I8039_NO_INT) { - R.irq_extra_cycles += Ext_IRQ(); /* Handle External IRQ */ - } - if (R.timer == 0) { - R.irq_extra_cycles += Timer_IRQ(); /* Handle Timer IRQ */ - } -} - - -/**************************************************************************** - * Set IRQ line state - ****************************************************************************/ -void set_irq_line(int irqline, int state) -{ - if (state != CLEAR_LINE) { - R.irq_state = I8039_EXTERNAL_INT; - R.irq_extra_cycles += Ext_IRQ(); /* Handle External IRQ */ - } - else { - R.irq_state = I8039_NO_INT; - } -}

t48/rel_1_2/sw/i8039emu/i8039.c Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/i8039emu/Makefile =================================================================== --- t48/rel_1_2/sw/i8039emu/Makefile (revision 296) +++ t48/rel_1_2/sw/i8039emu/Makefile (nonexistent) @@ -1,25 +0,0 @@ - -CFLAGS = -Wall - -.PHONY: all -all: i8039 - -i8039: i8039.o memory.o main.o 8039dasm.o - gcc -s -o i8039 main.o i8039.o memory.o 8039dasm.o - -i8039.o: i8039.h i8039.c types.h memory.h - gcc $(CFLAGS) -O -c i8039.c - -8039dasm.o: 8039dasm.c - gcc $(CFLAGS) -O -c 8039dasm.c - -memory.o: memory.c memory.h types.h - gcc $(CFLAGS) -O -c memory.c - -main.o: main.c memory.h types.h i8039.h - gcc $(CFLAGS) -O -c main.c - - -.PHONY: clean -clean: - rm -f *.o *~ i8039 log Index: t48/rel_1_2/sw/i8039emu/memory.h =================================================================== --- t48/rel_1_2/sw/i8039emu/memory.h (revision 296) +++ t48/rel_1_2/sw/i8039emu/memory.h (nonexistent) @@ -1,26 +0,0 @@ -/* - * $Id: memory.h,v 1.2 2004-07-03 14:35:52 arniml Exp $ - * - */ - -#ifndef _MEMORY_H_ -#define _MEMORY_H_ - -#include "types.h" - -typedef UINT32 offs_t; - - -UINT8 program_read_byte_8(UINT16); - -UINT8 cpu_readop(UINT16); - -UINT8 cpu_readop_arg(UINT16); - -UINT8 io_read_byte_8(UINT8); - -void io_write_byte_8(UINT8, UINT8); - -int read_hex_file(char *, UINT16); - -#endif Index: t48/rel_1_2/sw/i8039emu/i8039.h =================================================================== --- t48/rel_1_2/sw/i8039emu/i8039.h (revision 296) +++ t48/rel_1_2/sw/i8039emu/i8039.h (nonexistent) @@ -1,107 +0,0 @@ -/************************************************************************** - * Intel 8039 Portable Emulator * - * * - * Copyright (C) 1997 by Mirko Buffoni * - * Based on the original work (C) 1997 by Dan Boris, an 8048 emulator * - * You are not allowed to distribute this software commercially * - * Please, notify me, if you make any changes to this file * - * * - * Adapted for the T48 uController project, 2004 by Arnim Laeuger * - * See http://www.opencores.org/projects.cgi/web/t48/overview * - * * - * $Id: i8039.h,v 1.2 2004-04-15 22:03:53 arniml Exp $ - **************************************************************************/ - -#ifndef _I8039_H -#define _I8039_H - -#ifndef INLINE -#define INLINE static inline -#endif - -#include "types.h" - - -/************************************************************************** - Internal Clock divisor - - External Clock is divided internally by 3 to produce the machine state - generator. This is then divided by 5 for the instruction cycle times. - (Each instruction cycle passes through 5 machine states). -*/ - -#define I8039_CLOCK_DIVIDER (3*5) - - - -enum { I8039_PC=1, I8039_SP, I8039_PSW, I8039_A, I8039_TC, - I8039_P1, I8039_P2, I8039_R0, I8039_R1, I8039_R2, - I8039_R3, I8039_R4, I8039_R5, I8039_R6, I8039_R7 -}; - -/* This handling of special I/O ports should be better for actual MAME - * architecture. (i.e., define access to ports { I8039_p1, I8039_p1, dkong_out_w }) - */ - -#define I8039_p0 0x100 /* Not used */ -#define I8039_p1 0x101 -#define I8039_p2 0x102 -#define I8039_p4 0x104 -#define I8039_p5 0x105 -#define I8039_p6 0x106 -#define I8039_p7 0x107 -#define I8039_t0 0x110 -#define I8039_t1 0x111 -#define I8039_bus 0x120 - - -#include "memory.h" - -/* - * Input a UINT8 from given I/O port - */ -#define I8039_In(Port) ((UINT8)io_read_byte_8((UINT8)Port)) - - -/* - * Output a UINT8 to given I/O port - */ -#define I8039_Out(Port,Value) (io_write_byte_8((UINT8)Port,(UINT8)Value)) - - -/* - * Read a UINT8 from given memory location - */ -#define I8039_RDMEM(A) ((unsigned)program_read_byte_8(A)) - - -/* - * Write a UINT8 to given memory location - */ -#define I8039_WRMEM(A,V) (program_write_byte_8(A,V)) - - -/* - * I8039_RDOP() is identical to I8039_RDMEM() except it is used for reading - * opcodes. In case of system with memory mapped I/O, this function can be - * used to greatly speed up emulation - */ -#define I8039_RDOP(A) ((unsigned)cpu_readop(A)) - - -/* - * I8039_RDOP_ARG() is identical to I8039_RDOP() except it is used for reading - * opcode arguments. This difference can be used to support systems that - * use different encoding mechanisms for opcodes and opcode arguments - */ -#define I8039_RDOP_ARG(A) ((unsigned)cpu_readop_arg(A)) - -int Dasm8039(char *dst, unsigned pc); - -void i8039_reset(void *); -int i8039_execute(int, int); -void set_irq_line(int, int); - -void logerror(char *, UINT16, UINT8); - -#endif /* _I8039_H */ Index: t48/rel_1_2/sw/i8039emu/main.c =================================================================== --- t48/rel_1_2/sw/i8039emu/main.c (revision 296) +++ t48/rel_1_2/sw/i8039emu/main.c (nonexistent) @@ -1,128 +0,0 @@ -/* - * $Id$ - * - * Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) - * - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. See also the file COPYING which - * came with this application. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include - -#include "types.h" -#include "memory.h" -#include "i8039.h" - - -void logerror(char *msg, UINT16 address, UINT8 opcode) -{ -} - - -void print_usage(void) { - printf("Usage:\n"); - printf(" i8039 -f [-x ] [-d] [-h]\n"); - printf(" -f : Name of hex file for internal ROM\n"); - printf(" -x : Name of hex file for external ROM (optional)\n"); - printf(" -d : Dump machine state\n"); - printf(" -h : Print this help\n"); -} - - -int main(int argc, char *argv[]) -{ - int do_cycles, real_cycles, total_cycles; - char *hex_file = ""; - char *ext_hex_file = ""; - int c; - int dump = 0; - - /* process options */ - while ((c = getopt(argc, argv, "df:hx:")) != -1) { - switch (c) { - case 'd': - dump = 1; - break; - - case 'f': - hex_file = optarg; - break; - - case 'x': - ext_hex_file = optarg; - break; - - case 'h': - /* fallthrough */ - - default: - print_usage(); - return(0); - break; - } - } - - /* check options */ - if (strlen(hex_file) == 0) { - print_usage(); - return(1); - } - - /* read hex file for internal ROM */ - printf("Reading %s\n", hex_file); - if (!read_hex_file(hex_file, 0)) { - printf("Error reading file!\n"); - return(1); - } - - /* read hex fiel for external ROM */ - if (strlen(ext_hex_file) > 0) { - printf("Reading %s\n", ext_hex_file); - if (!read_hex_file(ext_hex_file, 0x800)) { - printf("Error reading file!\n"); - return(1); - } - } - - printf("Resetting 8039\n"); - i8039_reset(NULL); - - do_cycles = 52; - - total_cycles = 0; - - do { - real_cycles = i8039_execute(do_cycles, dump); - - /* activate interrupt */ - set_irq_line(0, HOLD_LINE); - /* hold interrupt for 3 machine cycles */ - real_cycles += i8039_execute(3, dump); - set_irq_line(0, CLEAR_LINE); - - if (real_cycles > 0) - total_cycles += real_cycles; - } while (real_cycles > 0); - - printf("Emulated %i cycles\n", total_cycles); - printf("Simulation Result: %s\n", real_cycles == 0 ? "PASS" : "FAIL"); - - return(0); -}

t48/rel_1_2/sw/i8039emu/main.c Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/i8039emu/memory.c =================================================================== --- t48/rel_1_2/sw/i8039emu/memory.c (revision 296) +++ t48/rel_1_2/sw/i8039emu/memory.c (nonexistent) @@ -1,149 +0,0 @@ -/* - * $Id$ - * - * Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) - * - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. See also the file COPYING which - * came with this application. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -#include "memory.h" -#include "i8039.h" - - -static UINT8 code_mem[4096]; - - -static UINT8 port1 = 0xff, port2 = 0xff; - - -UINT8 program_read_byte_8(UINT16 address) -{ - return(code_mem[address]); -} - -UINT8 cpu_readop(UINT16 address) -{ - return(code_mem[address]); -} - -UINT8 cpu_readop_arg(UINT16 address) -{ - return(code_mem[address]); -} - - -UINT8 io_read_byte_8(UINT8 address) -{ - UINT8 data; - - switch (0x100 | address) { - case I8039_p1: - data = port1; - break; - - case I8039_p2: - data = port2; - break; - - case I8039_t0: - /* connect T0 to P1[0] */ - data = port1 & 0x01; - break; - - case I8039_t1: - /* connect T1 to P1[1] */ - data = (port1 & 0x02) >> 1; - break; - - default: - data = 0; - break; - } - - - return(data); -} - - -void io_write_byte_8(UINT8 address, UINT8 data) -{ - switch (0x100 | address) { - case I8039_p1: - port1 = data; - break; - - case I8039_p2: - port2 = data; - break; - - default: - break; - } -} - - -int read_hex_file(char *filename, UINT16 file_offset) -{ - FILE *hex_file; - UINT16 record_len, offset, record_type; - UINT16 byte; - char line[540]; - char *payload, *idx; - int result = 0; - - record_len = offset = record_type = 0; - hex_file = fopen(filename, "r"); - if (hex_file != NULL) { - - while (fgets(line, 539, hex_file)) { - if (sscanf(line, ":%2hx%4hx%2hx", &record_len, &offset, &record_type) == 3) { - /* strip off newline */ - idx = (char *)strchr(line, '\n'); - if (idx != NULL) - *idx = '\0'; - /* extract payload */ - payload = &(line[9]); - /* strip of checksum */ - if (strlen(payload) > 2) - payload[strlen(payload) - 2] = '\0'; - - /* read payload to array */ - if (record_type == 0) { - while (strlen(payload) >= 2) { - if (sscanf(payload, "%2hx", &byte) == 1) - code_mem[file_offset + offset++] = byte; - - payload++; - payload++; - } - } - - } - } - - result = 1; - - fclose(hex_file); - } - - return(result); -}

t48/rel_1_2/sw/i8039emu/memory.c Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/sw/i8039emu/8039dasm.c =================================================================== --- t48/rel_1_2/sw/i8039emu/8039dasm.c (revision 296) +++ t48/rel_1_2/sw/i8039emu/8039dasm.c (nonexistent) @@ -1,289 +0,0 @@ -/**************************************************************************** - * - * mcs48 disassembler - * - * This file is Copyright 1996 Michael Cuddy, Fen's Ende Sofware. - * Redistribution is allowed in source and binary form as long as both - * forms are distributed together with the file 'README'. This copyright - * notice must also accompany the files. - * - * This software should be considered a small token to all of the - * emulator authors for thier dilligence in preserving our Arcade and - * Computer history. - * - * Michael Cuddy, Fen's Ende Software. - * 11/25/1996 - * - * Adapted by Andrea Mazzoleni for use with MAME - * - ***************************************************************************/ - -#include -#include -#include -#include - -#include "memory.h" - -typedef unsigned char byte; - -#define FMT(a,b) a, b -#define PTRS_PER_FORMAT 2 - -const char *Formats[] = { - FMT("00000011dddddddd", "add a, #%X"), - FMT("01101rrr", "add a, %R"), - FMT("0110000r", "add a, @%R"), - FMT("00010011dddddddd", "adc a, #%X"), - FMT("01111rrr", "adc a, %R"), - FMT("0111000r", "adc a, @%R"), - FMT("01010011dddddddd", "anl a, #%X"), - FMT("01011rrr", "anl a, %R"), - FMT("0101000r", "anl a, @%R"), - FMT("10011000dddddddd", "anl bus, #%X"), - FMT("10011001dddddddd", "anl p1, #%X"), - FMT("10011010dddddddd", "anl p2, #%X"), - FMT("100111pp", "anld %P, a"), - FMT("aaa10100aaaaaaaa", "call %A"), - FMT("00100111", "clr a"), - FMT("10010111", "clr c"), - FMT("10100101", "clr f1"), - FMT("10000101", "clr f0"), - FMT("00110111", "cpl a"), - FMT("10100111", "cpl c"), - FMT("10010101", "cpl f0"), - FMT("10110101", "cpl f1"), - FMT("01010111", "da a"), - FMT("00000111", "dec a"), - FMT("11001rrr", "dec %R"), - FMT("00010101", "dis i"), - FMT("00110101", "dis tcnti"), - FMT("11101rrraaaaaaaa", "djnz %R, %J"), - FMT("00000101", "en i"), - FMT("00100101", "en tcnti"), - FMT("01110101", "ent0 clk"), - FMT("00001001", "in a, p1"), - FMT("00001010", "in a, p2"), - FMT("00010111", "inc a"), - FMT("00011rrr", "inc %R"), - FMT("0001000r", "inc @%R"), - FMT("00001000", "ins a,bus"), - FMT("0001 0110aaaaaaaa", "jtf %J"), - FMT("0010 0110aaaaaaaa", "jnt0 %J"), - FMT("0011 0110aaaaaaaa", "jt0 %J"), - FMT("0100 0110aaaaaaaa", "jnt1 %J"), - FMT("0101 0110aaaaaaaa", "jt1 %J"), - FMT("0111 0110aaaaaaaa", "jf1 %J"), - FMT("1000 0110aaaaaaaa", "jni %J"), - FMT("1001 0110aaaaaaaa", "jnz %J"), - FMT("1011 0110aaaaaaaa", "jf0 %J"), - FMT("1100 0110aaaaaaaa", "jz %J"), - FMT("1110 0110aaaaaaaa", "jnc %J"), - FMT("1111 0110aaaaaaaa", "jc %J"), - FMT("bbb10010aaaaaaaa", "jb%B %J"), - FMT("aaa00100aaaaaaaa", "jmp %A"), - FMT("10110011", "jmpp @a"), - FMT("00100011dddddddd", "mov a, #%X"), - FMT("11111rrr", "mov a, %R"), - FMT("1111000r", "mov a, @%R"), - FMT("11000111", "mov a, psw"), - FMT("10111rrrdddddddd", "mov %R, #%X"), - FMT("10101rrr", "mov %R, a"), - FMT("1010000r", "mov @%R, a"), - FMT("1011000rdddddddd", "mov @%R, #%X"), - FMT("11010111", "mov psw, a"), - FMT("000011pp", "movd a, %P"), - FMT("001111pp", "movd %P, a"), - FMT("01000010", "mov a, t"), - FMT("01100010", "mov t, a"), - FMT("11100011", "movp3 a, @a"), - FMT("10100011", "movp a, @a"), - FMT("1000000r", "movx a, @%R"), - FMT("1001000r", "movx @%R, a"), - FMT("0100 1rrr", "orl a, %R"), - FMT("0100 000r", "orl a, @%R"), - FMT("0100 0011dddddddd", "orl a, #%X"), - FMT("1000 1000dddddddd", "orl bus, #%X"), - FMT("1000 1001dddddddd", "orl p1, #%X"), - FMT("1000 1010dddddddd", "orl p2, #%X"), - FMT("1000 11pp", "orld %P, a"), - FMT("00000010", "outl bus, a"), - FMT("001110pp", "outl %P, a"), - FMT("10000011", "ret"), - FMT("10010011", "retr"), - FMT("11100111", "rl a"), - FMT("11110111", "rlc a"), - FMT("01110111", "rr a"), - FMT("01100111", "rrc a"), - FMT("11100101", "sel mb0"), - FMT("11110101", "sel mb1"), - FMT("11000101", "sel rb0"), - FMT("11010101", "sel rb1"), - FMT("01100101", "stop tcnt"), - FMT("01000101", "strt cnt"), - FMT("01010101", "strt t"), - FMT("01000111", "swap a"), - FMT("00101rrr", "xch a, %R"), - FMT("0010000r", "xch a, @%R"), - FMT("0011000r", "xchd a, @%R"), - FMT("1101 0011dddddddd", "xrl a, #%X"), - FMT("1101 1rrr", "xrl a, %R"), - FMT("1101 000r", "xrl a, @%R"), - FMT("00000000", "nop"), - NULL -}; - -#define MAX_OPS (((sizeof(Formats) / sizeof(Formats[0])) - 1) / PTRS_PER_FORMAT) - -typedef struct opcode { - byte mask; /* instruction mask */ - byte bits; /* constant bits */ - char extcode; /* value that gets extension code */ - const char *parse; /* how to parse bits */ - const char *fmt; /* instruction format */ -} M48Opcode; - -static M48Opcode Op[MAX_OPS+1]; -static int OpInizialized = 0; - -static void InitDasm8039(void) -{ - const char *p, **ops; - byte mask, bits; - int bit; - int i; - - ops = Formats; i = 0; - while (*ops) { - p = *ops; - mask = 0; bits = 0; bit = 7; - while (*p && bit >= 0) { - switch (*p++) { - case '1': mask |= 1<= 0) - { - /* printf("{%c/%d}",*cp,bit); */ - switch(*cp) - { - case 'a': a <<=1; a |= ((code & (1< -#include -#include -#include - -using namespace std; - -#if !(defined(max)) && _MSC_VER - // VC fix - #define max __max -#endif - -class MemBlock -{ -public: - unsigned long m_startAddress; - vector m_bytes; -}; - -class File -{ -public: - explicit File(const char *fileName, const char *mode) - { - m_file = fopen(fileName, mode); - if (m_file != NULL) - { - return; - } - string errorStr = "Error opening "; - errorStr += fileName; - errorStr += "\n"; - throw errorStr; - } - - ~File() - { - fclose(m_file); - } - - // Read binary file - void ReadBin(unsigned long limit) - { - m_top = 0; - - m_chunks.push_back(MemBlock()); - m_chunks.back().m_startAddress = 0; - - cerr << "Reading binary file\n"; - - int tmp = fgetc(m_file); - - while (!feof(m_file)) - { - m_chunks.back().m_bytes.push_back(tmp); - - if (m_chunks.back().m_bytes.size() > limit + 1) - { - m_chunks.back().m_bytes.pop_back(); - m_top = m_chunks.back().m_bytes.size() - 1; - cerr << "Ignoring data above address space!\n"; - cerr << " Limit: " << limit << "\n"; - return; - } - - tmp = fgetc(m_file); - } - - m_top = m_chunks.back().m_bytes.size() - 1; - - if (!m_chunks.back().m_bytes.size()) - { - cerr << "No data!\n"; - - m_chunks.pop_back(); - } - } - - // Read hex file - void ReadHex(unsigned long limit) - { - char szLine[1024]; - bool formatDetected = false; - bool intel; - bool endSeen = false; - bool linear = true; // Only used for intel hex - unsigned long addressBase = 0; // Only used for intel hex - unsigned long dataRecords = 0; // Only used for s-record - while (!feof(m_file)) - { - if (fgets(szLine, 1024, m_file) == 0) - { - if (ferror(m_file)) - { - throw "Error reading input!\n"; - } - continue; - } - - if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD) - { - szLine[strlen(szLine) - 1] = 0; - } - - if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD) - { - szLine[strlen(szLine) - 1] = 0; - } - - if (strlen(szLine) == 1023) - { - throw "Hex file lines to long!\n"; - } - // Ignore blank lines - if (szLine[0] == '\n') - { - continue; - } - // Detect format and warn if garbage lines are found - if (!formatDetected) - { - if (szLine[0] != ':' && szLine[0] != 'S') - { - cerr << "Ignoring garbage line!\n"; - continue; - } - if (szLine[0] == 'S') - { - intel = false; - cerr << "Detected S-Record\n"; - } - else - { - intel = true; - cerr << "Detected intel hex file\n"; - } - formatDetected = true; - } - else if ((intel && szLine[0] != ':') || - (!intel && szLine[0] != 'S')) - { - cerr << "Ignoring garbage line!\n"; - continue; - } - - if (endSeen) - { - throw "Hex line after end of file record!\n"; - } - - if (intel) - { - unsigned long dataBytes; - unsigned long startAddress; - unsigned long type; - if (sscanf(&szLine[1], "%2lx%4lx%2lx", &dataBytes, &startAddress, &type) != 3) - { - throw "Hex line beginning corrupt!\n"; - } - // Check line length - if (szLine[11 + dataBytes * 2] != '\n' && szLine[11 + dataBytes * 2] != 0) - { - throw "Hex line length incorrect!\n"; - } - // Check line checksum - unsigned char checkSum = 0; - unsigned long tmp; - for (unsigned int i = 0; i <= dataBytes + 4; ++i) - { - if (sscanf(&szLine[1 + i * 2], "%2lx", &tmp) != 1) - { - throw "Hex line data corrupt!\n"; - } - checkSum += tmp; - } - if (checkSum != 0) - { - throw "Hex line checksum error!\n"; - } - - switch (type) - { - case 0: - // Data record - if (!linear) - { - // Segmented - unsigned long test = startAddress; - test += dataBytes; - if (test > 0xffff) - { - throw "Can't handle wrapped segments!\n"; - } - } - if (!m_chunks.size() || - m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() != - addressBase + startAddress) - { - m_chunks.push_back(MemBlock()); - m_chunks.back().m_startAddress = addressBase + startAddress; - } - { - unsigned char i = 0; - for (i = 0; i < dataBytes; ++i) - { - sscanf(&szLine[9 + i * 2], "%2lx", &tmp); - if (addressBase + startAddress + i > limit) - { - cerr << "Ignoring data above address space!\n"; - cerr << "Data address: " << addressBase + startAddress + i; - cerr << " Limit: " << limit << "\n"; - if (!m_chunks.back().m_bytes.size()) - { - m_chunks.pop_back(); - } - continue; - } - m_chunks.back().m_bytes.push_back(tmp); - } - } - break; - - case 1: - // End-of-file record - if (dataBytes != 0) - { - cerr << "Warning: End of file record not zero length!\n"; - } - if (startAddress != 0) - { - cerr << "Warning: End of file record address not zero!\n"; - } - endSeen = true; - break; - - case 2: - // Extended segment address record - if (dataBytes != 2) - { - throw "Length field must be 2 in extended segment address record!\n"; - } - if (startAddress != 0) - { - throw "Address field must be zero in extended segment address record!\n"; - } - sscanf(&szLine[9], "%4lx", &startAddress); - addressBase = startAddress << 4; - linear = false; - break; - - case 3: - // Start segment address record - if (dataBytes != 4) - { - cerr << "Warning: Length field must be 4 in start segment address record!\n"; - } - if (startAddress != 0) - { - cerr << "Warning: Address field must be zero in start segment address record!\n"; - } - if (dataBytes == 4) - { - unsigned long ssa; - char ssaStr[16]; - sscanf(&szLine[9], "%8lx", &ssa); - sprintf(ssaStr, "%08X\n", ssa); - cerr << "Segment start address (CS/IP): "; - cerr << ssaStr; - } - break; - - case 4: - // Extended linear address record - if (dataBytes != 2) - { - throw "Length field must be 2 in extended linear address record!\n"; - } - if (startAddress != 0) - { - throw "Address field must be zero in extended linear address record!\n"; - } - sscanf(&szLine[9], "%4lx", &startAddress); - addressBase = ((unsigned long)startAddress) << 16; - linear = true; - break; - - case 5: - // Start linear address record - if (dataBytes != 4) - { - cerr << "Warning: Length field must be 4 in start linear address record!\n"; - } - if (startAddress != 0) - { - cerr << "Warning: Address field must be zero in start linear address record!\n"; - } - if (dataBytes == 4) - { - unsigned long lsa; - char lsaStr[16]; - sscanf(&szLine[9], "%8lx", &lsa); - sprintf(lsaStr, "%08X\n", lsa); - cerr << "Linear start address: "; - cerr << lsaStr; - } - break; - - default: - cerr << "Waring: Unknown record found!\n"; - } - } - else - { - // S-record - unsigned long count; - char type; - if (sscanf(&szLine[1], "%c%2lx", &type, &count) != 2) - { - throw "Hex line beginning corrupt!\n"; - } - // Check line length - if (szLine[4 + count * 2] != '\n' && szLine[4 + count * 2] != 0) - { - throw "Hex line length incorrect!\n"; - } - // Check line checksum - unsigned char checkSum = 0; - unsigned long tmp; - for (unsigned int i = 0; i < count + 1; ++i) - { - if (sscanf(&szLine[2 + i * 2], "%2lx", &tmp) != 1) - { - throw "Hex line data corrupt!\n"; - } - checkSum += tmp; - } - if (checkSum != 255) - { - throw "Hex line checksum error!\n"; - } - - switch (type) - { - case '0': - // Header record - { - char header[256]; - unsigned char i = 0; - for (i = 0; i + 3 < count; ++i) - { - sscanf(&szLine[8 + i * 2], "%2lx", &tmp); - header[i] = tmp; - } - header[i] = 0; - if (i > 0) - { - cerr << "Module name: " << header << "\n"; - } - } - break; - - case '1': - case '2': - case '3': - // Data record - { - dataRecords++; - unsigned long startAddress; - if (type == '1') - { - sscanf(&szLine[4], "%4lx", &startAddress); - } - else if (type == '2') - { - sscanf(&szLine[4], "%6lx", &startAddress); - } - else - { - sscanf(&szLine[4], "%8lx", &startAddress); - } - - if (!m_chunks.size() || - m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() != - startAddress) - { - m_chunks.push_back(MemBlock()); - m_chunks.back().m_startAddress = startAddress; - } - unsigned char i = 0; - for (i = (type - '1'); i + 3 < count; ++i) - { - sscanf(&szLine[8 + i * 2], "%2lx", &tmp); - if (startAddress + i > limit) - { - cerr << "Ignoring data above address space!\n"; - cerr << "Data address: " << startAddress + i; - cerr << " Limit: " << limit << "\n"; - if (!m_chunks.back().m_bytes.size()) - { - m_chunks.pop_back(); - } - continue; - } - m_chunks.back().m_bytes.push_back(tmp); - } - } - break; - - case '5': - // Count record - { - unsigned long address; - sscanf(&szLine[4], "%4lx", &address); - if (address != dataRecords) - { - throw "Wrong number of data records!\n"; - } - } - break; - - case '7': - case '8': - case '9': - // Start address record - cerr << "Ignoring start address record!\n"; - break; - - default: - cerr << "Unknown record found!\n"; - } - } - } - if (intel && !endSeen) - { - cerr << "No end of file record!\n"; - } - if (!m_chunks.size()) - { - throw "No data in file!\n"; - } - vector::iterator vi; - m_top = 0; - for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++) - { - m_top = max(m_top, vi->m_startAddress + vi->m_bytes.size() - 1); - } - } - - // Rather inefficient this one, fix sometime - bool GetByte(const unsigned long address, unsigned char &chr) - { - vector::iterator vi; - - for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++) - { - if (vi->m_startAddress + vi->m_bytes.size() > address && vi->m_startAddress <= address) - { - break; - } - } - if (vi == m_chunks.end()) - { - return false; - } - chr = vi->m_bytes[address - vi->m_startAddress]; - return true; - } - - bool BitString(const unsigned long address, const unsigned char bits, const bool lEndian, string &str) - { - bool ok = false; - long i; - unsigned char chr; - unsigned long data = 0; - unsigned long tmp; - - if (lEndian) - { - for (i = 0; i < (bits + 7) / 8; ++i) - { - ok |= GetByte(address + i, chr); - tmp = chr; - data |= tmp << (8 * i); - } - } - else - { - for (i = 0; i < (bits + 7) / 8; ++i) - { - ok |= GetByte(address + i, chr); - tmp = chr; - data |= tmp << (8 * ((bits + 7) / 8 - i - 1)); - } - } - - if (!ok) - { - return false; - } - - unsigned long mask = 1; - - str = ""; - for (i = 0; i < bits; i++) - { - if (data & mask) - { - str.insert(0,"1"); - } - else - { - str.insert(0,"0"); - } - mask <<= 1; - } - return true; - } - - FILE *Handle() { return m_file; }; - vector m_chunks; - unsigned long m_top; -private: - FILE *m_file; -}; - - -int main (int argc, char *argv[]) -{ - cerr << "Hex to VHDL ROM converter by Daniel Wallner. Version 0244\n"; - - try - { - unsigned long aWidth; - unsigned long dWidth; - char endian; - char O = 0; - - if (!(argc == 4 || argc == 5)) - { - cerr << "\nUsage: hex2rom [-b] \n"; - cerr << "\nIf the -b option is specified the file is read as a binary file\n"; - cerr << "Hex input files must be intel hex or motorola s-record\n"; - cerr << "\nThe format string has the format AEDOS where:\n"; - cerr << " A = Address bits\n"; - cerr << " E = Endianness, l or b\n"; - cerr << " D = Data bits\n"; - cerr << " O = ROM type: (one optional character)\n"; - cerr << " z for tri-state output\n"; - cerr << " a for array ROM\n"; - cerr << " s for synchronous ROM\n"; - cerr << " u for XST ucf\n"; - cerr << " l for Leonardo ucf\n"; - cerr << " S = SelectRAM usage in 1/16 parts (only used when O = u)\n"; - cerr << "\nExample:\n"; - cerr << " hex2rom test.hex Test_ROM 18b16z\n\n"; - return -1; - } - - string inFileName; - string outFileName; - - unsigned long bytes; - unsigned long select = 0; - - if (argc == 5) - { - if (strcmp(argv[1], "-b")) - { - throw "Error in arguments!\n"; - } - } - - int result; - - result = sscanf(argv[argc - 1], "%lu%c%lu%c%lu", &aWidth, &endian, &dWidth, &O, &select); - if (result < 3) - { - throw "Error in output format argument!\n"; - } - - if (aWidth > 32 || (endian != 'l' && endian != 'b') || dWidth > 32 || (result > 3 && O != 'z' && O != 'a' && O != 's' && O != 'u' && O != 'l')) - { - throw "Error in output format argument!\n"; - } - inFileName = argv[argc - 3]; - outFileName = argv[argc - 2]; - - bytes = (dWidth + 7) / 8; - - File inFile(inFileName.c_str(), "rb"); - - if (argc == 4) - { - inFile.ReadHex((1UL << aWidth) * bytes - 1); - } - else - { - inFile.ReadBin((1UL << aWidth) * bytes - 1); - } - - string line; - - unsigned long words = 1; - unsigned long i = inFile.m_top; - i /= bytes; - - while (i != 0) - { - i >>= 1; - words <<= 1; - } - - if (O != 'u' && O != 'l') - { - printf("-- This file was generated with hex2rom written by Daniel Wallner\n"); - printf("\nlibrary IEEE;"); - printf("\nuse IEEE.std_logic_1164.all;"); - printf("\nuse IEEE.numeric_std.all;"); - printf("\n\nentity %s is", outFileName.c_str()); - printf("\n\tport("); - if (O == 'z') - { - printf("\n\t\tCE_n\t: in std_logic;", dWidth - 1); - printf("\n\t\tOE_n\t: in std_logic;", dWidth - 1); - } - if (O == 's') - { - printf("\n\t\tClk\t: in std_logic;", dWidth - 1); - } - printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1); - printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1); - printf("\n\t);"); - printf("\nend %s;", outFileName.c_str()); - printf("\n\narchitecture rtl of %s is", outFileName.c_str()); - if (!O) - { - printf("\nbegin"); - printf("\n\tprocess (A)"); - printf("\n\tbegin"); - printf("\n\t\tcase to_integer(unsigned(A)) is"); - } - else if (O == 's') - { - printf("\nbegin"); - printf("\n\tprocess (Clk)"); - printf("\n\tbegin"); - printf("\n\t\tif Clk'event and Clk = '1' then"); - printf("\n\t\tcase to_integer(unsigned(A)) is"); - } - else - { - printf("\n\tsubtype ROM_WORD is std_logic_vector(%d downto 0);", dWidth - 1); - printf("\n\ttype ROM_TABLE is array(0 to %d) of ROM_WORD;", words - 1); - printf("\n\tconstant ROM: ROM_TABLE := ROM_TABLE'("); - } - - string str; - string strDC; - for (i = 0; i < dWidth; i++) - { - strDC.insert(0, "-"); - } - for (i = 0; i < words; i++) - { - if (!inFile.BitString(i * bytes, dWidth, endian == 'l', str)) - { - str = strDC; - } - if (!O || O == 's') - { - if (inFile.m_top / bytes >= i) - { - printf("\n\t\twhen %06d => D <= \"%s\";",i, str.c_str()); - printf("\t-- 0x%04X", i * bytes); - } - } - else - { - printf("\n\t\t\"%s", str.c_str()); - if (i != words - 1) - { - printf("\","); - } - else - { - printf("\");"); - } - printf("\t-- 0x%04X", i * bytes); - } - } - - if (!O || O == 's') - { - printf("\n\t\twhen others => D <= \"%s\";", strDC.c_str()); - printf("\n\t\tend case;"); - if (O == 's') - printf("\n\tend if;"); - printf("\n\tend process;"); - } - else - { - printf("\nbegin"); - if (O == 'z') - { - printf("\n\tD <= ROM(to_integer(unsigned(A))) when CE_n = '0' and OE_n = '0' else (others => 'Z');"); - } - else - { - printf("\n\tD <= ROM(to_integer(unsigned(A)));"); - } - } - printf("\nend;\n"); - } - else - { - unsigned long selectIter = 0; - unsigned long blockIter = 0; - - if (!select) - { - blockIter = ((1UL << aWidth) + 511) / 512; - } - else if (select == 16) - { - selectIter = ((1UL << aWidth) + 15) / 16; - } - else - { - blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512; - selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16; - } - - cerr << "Creating .ucf file with " << selectIter * bytes; - cerr << " LUTs and " << blockIter * bytes << " block RAMs\n"; - - unsigned long blockTotal = ((1UL << aWidth) + 511) / 512; - - printf("# This file was generated with hex2rom written by Daniel Wallner\n"); - - for (i = 0; i < selectIter; i++) - { - unsigned long base = i * 16 * bytes; - unsigned long j; - unsigned char c; - unsigned long pos; - - // Check that there is any actual data in segment - bool init = false; - for (pos = 0; pos < bytes * 16; pos++) - { - init = inFile.GetByte(base + pos, c); - if (init) - { - break; - } - } - - if (init) - { - for (j = 0; j < dWidth; j++) - { - unsigned long bitMask = 1; - unsigned long bits = 0; - - for (pos = 0; pos < 16; pos++) - { - unsigned long addr; - - if (endian = 'l') - { - addr = base + bytes * pos + j / 8; - } - else - { - addr = base + bytes * pos + bytes - j / 8 - 1; - } - - c = 0; - inFile.GetByte(addr, c); - if (c & (1 << (j % 8))) - { - bits |= bitMask; - } - bitMask <<= 1; - } - - if (O == 'u') - { - if (selectIter == 1) - { - printf("\nINST *s%s%d INIT = %04X;", outFileName.c_str(), j, bits); - } - else - { - printf("\nINST *s%s%d%d INIT = %04X;", outFileName.c_str(), i, j, bits); - } - } - else - { - if (selectIter == 1) - { - printf("\nINST *sG1_%d_S%s INIT = %04X;", j, outFileName.c_str(), bits); - } - else - { - printf("\nINST *sG1_%d_sG2_%d_S%s INIT = %04X;", i, j, outFileName.c_str(), bits); - } - } - } - } - } - - for (i = blockTotal - blockIter; i < blockTotal; i++) - { - unsigned long j; - for (j = 0; j < bytes; j++) - { - unsigned long k; - for (k = 0; k < 16; k++) - { - unsigned long base = i * 512 * bytes + k * 32 * bytes; - unsigned char c; - unsigned long pos; - - // Check that there is any actual data in segment - bool init = false; - for (pos = 0; pos < 32; pos++) - { - init = inFile.GetByte(base + bytes * pos + j, c); - if (init) - { - break; - } - } - - if (init) - { - if (O == 'u') - { - if (blockIter == 1) - { - printf("\nINST *b%s%d INIT_%02X = ", outFileName.c_str(), j, k); - } - else - { - printf("\nINST *b%s%d%d INIT_%02X = ", outFileName.c_str(), i, j, k); - } - } - else - { - if (blockIter == 1) - { - printf("\nINST *bG1_%d_B%s INIT_%02X = ", j, outFileName.c_str(), k); - } - else - { - printf("\nINST *bG1_%d_bG2_%d_B%s INIT_%02X = ", i, j, outFileName.c_str(), k); - } - } - for (pos = 0; pos < 32; pos++) - { - unsigned long addr; - - if (endian = 'l') - { - addr = base + bytes * (31 - pos) + j; - } - else - { - addr = base + bytes * (31 - pos) + bytes - j - 1; - } - - c = 0; - inFile.GetByte(addr, c); - printf("%02X", c); - } - printf(";"); - } - } - } - } - printf("\n"); - } - return 0; - } - catch (string error) - { - cerr << "Fatal: " << error; - } - catch (const char *error) - { - cerr << "Fatal: " << error; - } - return -1; -} Index: t48/rel_1_2/sw/vcd2vec.pl =================================================================== --- t48/rel_1_2/sw/vcd2vec.pl (revision 296) +++ t48/rel_1_2/sw/vcd2vec.pl (nonexistent) @@ -1,234 +0,0 @@ -#!/usr/bin/perl -w -# -# ############################################################################ -# -# vcd2vec.pl -# -# $Id$ -# -# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -# -# All rights reserved -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. See also the file COPYING which -# came with this application. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# ############################################################################ -# -# Purpose: -# ======== -# -# Converts a VCD-file to a vector file. -# -# Reads VCD from STDIN and writes the resulting vector stream to STDOUT. -# vcd2vec.pl -s [-i] [-h] -# -s : Name of the file containing the signals for vector output -# -i : Read initial state from VCD (given with $dumpvars) -# -h : Print this help -# - - -use strict; - -use Getopt::Std; - - -my $time_unit = 'ns'; - -sub print_usage { - print < [-i] [-h] - -s : Name of the file containing the signals for vector output - -i : Read initial state from VCD (given with \$dumpvars) - -h : Print this help -EOU -} - -sub print_index { - my $index = shift; - my ($tok, $desc); - - while (($tok, $desc) = each %{$index}) { - print("Token $tok:\n"); - print(" $desc->{'name'}\n"); - print(" $desc->{'pos'}\n"); - } -} - -sub dump_state { - my ($state, $time, $dump_signals) = @_; - my $signal; - - print("${time}>"); - foreach $signal (@{$dump_signals}) { - if (exists($state->{$signal})) { - print(" ".$state->{$signal}); - } else { - print(STDERR "Error: Signal '$signal' not included in VCD!\n"); - } - } - print("\n"); -} - -sub read_scope { - my $scope = shift; - my $index = shift; - my $pos = shift; - my ($token, $base, $extension); - my $ipt; - - print("Processing scope '$scope'\n"); - - while () { - last if (/^\$upscope/); - - last if (/^\$enddefinitions/); - - if (/^\$var +\S+ +\S+ +(\S+) +(\S+) +(([^\$]\S*)|\$end)/) { - $token = $1; - $base = $2; - - $extension = defined($4) ? $4 : ''; - $extension =~ s/[\[\]]//g; - - $index->{$token} = {}; - $ipt = $index->{$token}; - $ipt->{'name'} = "$scope.$base$extension"; - $ipt->{'pos'} = $$pos++; - - print("Appended ".$ipt->{'name'}."\n"); - } - - if (/^\$scope +\S+ +(\S+)/) { - read_scope("$scope.$1", $index, $pos); - } - - if (/^\$timescale/) { - $_ = ; - if (/^\s*1(\S+)/) { - $time_unit = $1; - } - } - } -} - -my %options; -my %index; -my %state; -my ($i, $time, $pos); -my $index; -my $token; -my ($ipt, $val); -my ($tok, $desc); -my $signal; -my $initial_states = 0; -local *SIGNALS_FILE; - -my @dump_signals; - -# process command line options -if (!getopts('s:ih', \%options)) { - print_usage(); - exit(1); -} - -if (exists($options{'h'})) { - print_usage(); - exit(0); -} - -if (exists($options{'i'})) { - $initial_states = 1; -} - -if (exists($options{'s'})) { -} else { - print(STDERR "File with signal names is required!\n"); - print_usage(); - exit(1); -} - - -############################################################################## -# Read signals file -# -if (!open(SIGNALS_FILE, "<$options{'s'}")) { - print(STDERR "Cannot read signals file '$options{'s'}'!\n"); - exit(1); -} - -@dump_signals = ; -close(SIGNALS_FILE); -chomp(@dump_signals); - - -# parse header -$index = {}; -$pos = 0; -read_scope("", $index, \$pos); - - -if ($initial_states) { - # read initial state - while () { last if (/^\$dumpvars/) } - while () { - last if (/^\$end/); - if (/^(.)(\S+)/) { - $val = $1; - $token = $2; - $state{$index->{$token}->{'name'}} = $val; - } - } -} - -$time = '0'; - -print("time:"); -foreach $signal (@dump_signals) { - print(" $signal"); -} -print("\n"); - -# now read all state changes -while () { - if (/^#(\d+)/) { - if ($1 != 0) { - # dump previous state - dump_state(\%state, $time, \@dump_signals); - } - $time = $1; - next; - } else { - if (/^(\S)(\S+)$/) { - $val = $1; - $token = $2; - $state{$index->{$token}->{'name'}} = $val; - } - - if (/^(\S+) (\S+)$/) { - $val = $1; - $token = $2; - $state{$index->{$token}->{'name'}} = $val; - } - } - -} - -# final dump -dump_state(\%state, $time, \@dump_signals); - -0;

t48/rel_1_2/sw/vcd2vec.pl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/syn/t8048/b5x300/t48_rom.vhd =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/t48_rom.vhd (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/t48_rom.vhd (nonexistent) @@ -1,37 +0,0 @@ --- This file was generated with hex2rom written by Daniel Wallner - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity rom_t48 is - port( - Clk : in std_logic; - A : in std_logic_vector(9 downto 0); - D : out std_logic_vector(7 downto 0) - ); -end rom_t48; - -architecture rtl of rom_t48 is - signal A_r : std_logic_vector(9 downto 0); -begin - process (Clk) - begin - if Clk'event and Clk = '1' then - A_r <= A; - end if; - end process; - process (A_r) - begin - case to_integer(unsigned(A_r)) is - when 000000 => D <= "00100011"; -- 0x0000 - when 000001 => D <= "11111111"; -- 0x0001 - when 000002 => D <= "00111001"; -- 0x0002 - when 000003 => D <= "11010011"; -- 0x0003 - when 000004 => D <= "00000001"; -- 0x0004 - when 000005 => D <= "00000100"; -- 0x0005 - when 000006 => D <= "00000010"; -- 0x0006 - when others => D <= "--------"; - end case; - end process; -end; Index: t48/rel_1_2/syn/t8048/b5x300/Makefile =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/Makefile (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/Makefile (nonexistent) @@ -1,42 +0,0 @@ -############################################################################## -# -# Generic Makefile for ISE projects -# -# $Id$ -# -# Execute with 'make ', where target is one of -# ise : build ISE project from -# - files in compile_list -# - project settings in timing.ucf and .ucf -# - project settings applied in gen_ise_project.tcl -# compile : compile ISE project by means of tcl script -# compile_project.tcl -# | all : run through all targets above -# -############################################################################## - -export MODULE := t8048 - -export COMPILE_LIST := compile_list -SOURCE_FILES := $(shell cat $(COMPILE_LIST)) -export BLD := bld - -.PHONY: all -all: $(BLD)/$(MODULE).bit - -.PHONY: ise -ise: $(BLD)/$(MODULE).ise - -.PHONY: compile -compile: $(BLD)/$(MODULE).bit - -$(BLD)/$(MODULE).ise: $(COMPILE_LIST) *.ucf gen_ise_project.tcl - xtclsh gen_ise_project.tcl - -$(BLD)/$(MODULE).bit: $(SOURCE_FILES) $(BLD)/$(MODULE).ise compile_project.tcl - xtclsh compile_project.tcl - touch $@ - -.PHONY: clean -clean: - rm -rf *~ bld

t48/rel_1_2/syn/t8048/b5x300/Makefile Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/syn/t8048/b5x300/compile_project.tcl =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/compile_project.tcl (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/compile_project.tcl (nonexistent) @@ -1,46 +0,0 @@ -############################################################################## -# -# Generic project compile script -# -# $Id$ -# -# Execute from within xtclsh. -# -# Environment variables: -# $MODULE : Name of the toplevel project -# -> mandatory <- -# $BLD : Build directory where the project and all temporary files -# are stored -# -> optional, default is "bld" <- -# -############################################################################## - -# mandatory environment variable for project name: $MODULE -if {[info exists env(MODULE)]} { - set PROJECT $env(MODULE) - puts "Info: Setting project name from \$MODULE: $PROJECT" -} else { - puts "Error: Environment variable MODULE not set." - exit 1 -} - -# optional environment variable for build directory: $BLD -# default is 'bld' -puts -nonewline "Info: " -if {[info exists env(BLD)]} { - set bld $env(BLD) - puts -nonewline "Setting build directory from \$BLD" -} else { - set bld bld - puts -nonewline "Setting build directory to default" -} -puts ": $bld" - -cd $bld - -project open $PROJECT.ise - -puts "Starting design implementation..." -process run "Generate Programming File" - -project close

t48/rel_1_2/syn/t8048/b5x300/compile_project.tcl Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/syn/t8048/b5x300/t48_rom.hex =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/t48_rom.hex (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/t48_rom.hex (nonexistent) @@ -1,2 +0,0 @@ -:0700000023FF39D3010402C4 -:00000001FF Index: t48/rel_1_2/syn/t8048/b5x300/gen_ise_project.tcl =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/gen_ise_project.tcl (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/gen_ise_project.tcl (nonexistent) @@ -1,162 +0,0 @@ -############################################################################### -# -# $Id$ -# -# Based on -# Created by Phil Hays, Xilinx -# Setup Xilinx environment, then run from Unix with "xtclsh dice.tcl" -# -# This Tcl script will implement a design and load it in the S3E FPGA on -# the Spartan 3E Starter Kit Board -# -# There are two ucf files, one for pins and one for timing -# -############################################################################### -# Contact : e-mail hotline@xilinx.com -# phone + 1 800 255 7778 -# -# Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are -# provided to you "as is". Xilinx and its licensors make and you -# receive no warranties or conditions, express, implied, -# statutory or otherwise, and Xilinx specifically disclaims any -# implied warranties of merchantability, non-infringement, or -# fitness for a particular purpose. Xilinx does not warrant that -# the functions contained in these designs will meet your -# requirements, or that the operation of these designs will be -# uninterrupted or error free, or that defects in the Designs -# will be corrected. Furthermore, Xilinx does not warrant or -# make any representations regarding use or the results of the -# use of the designs in terms of correctness, accuracy, -# reliability, or otherwise. -# -# LIMITATION OF LIABILITY. In no event will Xilinx or its -# licensors be liable for any loss of data, lost profits, cost -# or procurement of substitute goods or services, or for any -# special, incidental, consequential, or indirect damages -# arising from the use or operation of the designs or -# accompanying documentation, however caused and on any theory -# of liability. This limitation will apply even if Xilinx -# has been advised of the possibility of such damage. This -# limitation shall apply not-withstanding the failure of the -# essential purpose of any limited remedies herein. -# -# Copyright (c) 2006 Xilinx, Inc. -# All rights reserved -# -############################################################################### -# Version 1.0 - 19-Oct-2006 -# Initial version -############################################################################### - -############################################################################### -# MAIN -############################################################################### -# Modify the project settings for the specific design -# -# Make sure there are no files in the build directory that you may want to -# keep, as this TCL script cleans that directory by default! -############################################################################### - -# mandatory environment variable for project name: $MODULE -if {[info exists env(MODULE)]} { - set PROJECT $env(MODULE) - puts "Info: Setting project name from \$MODULE: $PROJECT" -} else { - puts "Error: Environment variable MODULE not set." - exit 1 -} - -# optional environment variable for build directory: $BLD -# default is 'bld' -puts -nonewline "Info: " -if {[info exists env(BLD)]} { - set bld $env(BLD) - puts -nonewline "Setting build directory from \$BLD" -} else { - set bld bld - puts -nonewline "Setting build directory to default" -} -puts ": $bld" - -# optional environment variable for source file compile list: $COMPILE_LIST -# default is 'compile_list' -puts -nonewline "Info: " -if {[info exists env(COMPILE_LIST)]} { - set compile_list $env(COMPILE_LIST) - puts -nonewline "Setting source file compile list from \$COMPILE_LIST" -} else { - set compile_list compile_list - puts -nonewline "Setting source file compile list to default" -} -puts ": $compile_list" - -if {[file exists $bld]} { - puts "Deleting all existing project files in '$bld'" - # Perhaps ask ok here?? - # Or perhaps skip project creation if project exists?? - file delete -force $bld -} -puts "Creating new project directory in '$bld'..." -file mkdir $bld - -############################################################################### -# Put two ucf file into one. -# This could be made as complex as required, however for demonstration it is -# just a simple copy. -############################################################################### - -puts "Creating new UCF file..." - -set tempucf [file join $bld temp.ucf] -set outfile [open $tempucf "w"] -set infile [open "t8048.ucf" "r"] -while {![eof $infile]} { - puts $outfile [gets $infile] -} -close $infile -close $outfile -# -puts "Creating new ISE project..." -cd $bld -project new $PROJECT.ise -project set family spartan2e -project set device xc2s300e -project set package pq208 -project set speed -6 - - -############################################################################### -# Modify the xfile add argument for the source files in the design -############################################################################### - -puts "Adding source files..." -set infile [open "../compile_list" "r"] -while {![eof $infile]} { - xfile add "../[gets $infile]" -} -xfile add temp.ucf - - -############################################################################### -# Set optional implementation options here. There is a problem with setting -# project properties that at least one source must be added to the project -# first. Therefore, the "project set" commands are after the "xfile add" -# commands. -############################################################################### - -puts "Setting project properties..." - -project set {Optimization Goal} Area -process {Synthesize - XST} -project set {Optimization Effort} Normal -process {Synthesize - XST} -project set {Use Synthesis Constraints File} 1 -process {Synthesize - XST} - -#project set "Map Effort Level" High -#project set {Perform Timing-Driven Packing and Placement} 1 -project set {Place & Route Effort Level (Overall)} Standard -#project set "Other Place & Route Command Line Options" "-intsyle xflow" -project set {Generate Post-Place & Route Static Timing Report} true -project set {Report Unconstrained Paths} 10 -process {Generate Post-Place & Route Static Timing} -project set {Report Type} {Verbose Report} -process {Generate Post-Place & Route Static Timing} -project set {Create Binary Configuration File} 1 -process {Generate Programming File} - -project close

t48/rel_1_2/syn/t8048/b5x300/gen_ise_project.tcl Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/syn/t8048/b5x300/t8048.ucf =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/t8048.ucf (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/t8048.ucf (nonexistent) @@ -1,54 +0,0 @@ -#NET "reset_n_i" LOC = "P187"; -#NET "xtal_i" LOC = "P185"; -NET "xtal_i" TNM_NET = "xtal_i"; -TIMESPEC "TS_xtal_i" = PERIOD "xtal_i" 90 ns HIGH 50 %; - -#PINLOCK_BEGIN - -#Fri Apr 30 18:23:21 2004 - -#PINLOCK_END -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -NET "ale_o" LOC = "P205" ; -NET "db_b<0>" LOC = "P133" ; -NET "db_b<1>" LOC = "P134" ; -NET "db_b<2>" LOC = "P135" ; -NET "db_b<3>" LOC = "P136" ; -NET "db_b<4>" LOC = "P138" ; -NET "db_b<5>" LOC = "P139" ; -NET "db_b<6>" LOC = "P140" ; -NET "db_b<7>" LOC = "P141" ; -NET "ea_i" LOC = "P206" ; -NET "int_n_i" LOC = "P3" ; -NET "p1_b<0>" LOC = "P82" ; -NET "p1_b<1>" LOC = "P83" ; -NET "p1_b<2>" LOC = "P84" ; -NET "p1_b<3>" LOC = "P86" ; -NET "p1_b<4>" LOC = "P87" ; -NET "p1_b<5>" LOC = "P88" ; -NET "p1_b<6>" LOC = "P89" ; -NET "p1_b<7>" LOC = "P93" ; -NET "p2_b<0>" LOC = "P94" ; -NET "p2_b<1>" LOC = "P95" ; -NET "p2_b<2>" LOC = "P96" ; -NET "p2_b<3>" LOC = "P97" ; -NET "p2_b<4>" LOC = "P98" ; -NET "p2_b<5>" LOC = "P99" ; -NET "p2_b<6>" LOC = "P100" ; -NET "p2_b<7>" LOC = "P101" ; -NET "prog_n_o" LOC = "P202" ; -NET "psen_n_o" LOC = "P204" ; -NET "rd_n_o" LOC = "P203" ; -NET "reset_n_i" LOC = "P57" ; -NET "t0_b" LOC = "P181" ; -NET "t1_i" LOC = "P200" ; -NET "wr_n_o" LOC = "P201" ; -NET "xtal_i" LOC = "P77" ; - -#PACE: Start of PACE Area Constraints - -#PACE: Start of PACE Prohibit Constraints - -#PACE: End of Constraints generated by PACE Index: t48/rel_1_2/syn/t8048/b5x300/compile_list =================================================================== --- t48/rel_1_2/syn/t8048/b5x300/compile_list (revision 296) +++ t48/rel_1_2/syn/t8048/b5x300/compile_list (nonexistent) @@ -1,30 +0,0 @@ -../../../rtl/vhdl/t48_pack-p.vhd -../../../rtl/vhdl/psw.vhd -../../../rtl/vhdl/pmem_ctrl_pack-p.vhd -../../../rtl/vhdl/pmem_ctrl.vhd -../../../rtl/vhdl/p2.vhd -../../../rtl/vhdl/p1.vhd -../../../rtl/vhdl/timer.vhd -../../../rtl/vhdl/dmem_ctrl_pack-p.vhd -../../../rtl/vhdl/dmem_ctrl.vhd -../../../rtl/vhdl/decoder_pack-p.vhd -../../../rtl/vhdl/cond_branch_pack-p.vhd -../../../rtl/vhdl/alu_pack-p.vhd -../../../rtl/vhdl/t48_comp_pack-p.vhd -../../../rtl/vhdl/int.vhd -../../../rtl/vhdl/t48_tb_pack-p.vhd -../../../rtl/vhdl/decoder.vhd -../../../rtl/vhdl/db_bus.vhd -../../../rtl/vhdl/cond_branch.vhd -../../../rtl/vhdl/clock_ctrl.vhd -../../../rtl/vhdl/bus_mux.vhd -../../../rtl/vhdl/alu.vhd -../../../rtl/vhdl/t48_core.vhd -../../../rtl/vhdl/system/generic_ram_ena.vhd -t48_rom.vhd -../../../rtl/vhdl/system/t48_rom-e.vhd -../../../rtl/vhdl/system/t48_rom-struct-a.vhd -../../../rtl/vhdl/t48_core_comp_pack-p.vhd -../../../rtl/vhdl/system/t8048_notri.vhd -../../../rtl/vhdl/system/t48_system_comp_pack-p.vhd -../../../rtl/vhdl/system/t8048.vhd Index: t48/rel_1_2/syn/t8048/jopcyc/t8048.qpf =================================================================== --- t48/rel_1_2/syn/t8048/jopcyc/t8048.qpf (revision 296) +++ t48/rel_1_2/syn/t8048/jopcyc/t8048.qpf (nonexistent) @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.1" -DATE = "22:42:11 December 02, 2004" - - -# Revisions - -PROJECT_REVISION = "t8048" Index: t48/rel_1_2/syn/t8048/jopcyc/t48_rom.vhd =================================================================== --- t48/rel_1_2/syn/t8048/jopcyc/t48_rom.vhd (revision 296) +++ t48/rel_1_2/syn/t8048/jopcyc/t48_rom.vhd (nonexistent) @@ -1,37 +0,0 @@ --- This file was generated with hex2rom written by Daniel Wallner - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity rom_t48 is - port( - Clk : in std_logic; - A : in std_logic_vector(9 downto 0); - D : out std_logic_vector(7 downto 0) - ); -end rom_t48; - -architecture rtl of rom_t48 is - signal A_r : std_logic_vector(9 downto 0); -begin - process (Clk) - begin - if Clk'event and Clk = '1' then - A_r <= A; - end if; - end process; - process (A_r) - begin - case to_integer(unsigned(A_r)) is - when 000000 => D <= "00100011"; -- 0x0000 - when 000001 => D <= "11111111"; -- 0x0001 - when 000002 => D <= "00111001"; -- 0x0002 - when 000003 => D <= "11010011"; -- 0x0003 - when 000004 => D <= "00000001"; -- 0x0004 - when 000005 => D <= "00000100"; -- 0x0005 - when 000006 => D <= "00000010"; -- 0x0006 - when others => D <= "--------"; - end case; - end process; -end; Index: t48/rel_1_2/syn/t8048/jopcyc/t8048.qsf =================================================================== --- t48/rel_1_2/syn/t8048/jopcyc/t8048.qsf (revision 296) +++ t48/rel_1_2/syn/t8048/jopcyc/t8048.qsf (nonexistent) @@ -1,71 +0,0 @@ -set_global_assignment -name TOP_LEVEL_ENTITY t8048 -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# t8048_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:20:14 MAY 08, 2004" -set_global_assignment -name LAST_QUARTUS_VERSION 7.0 -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_pack-p.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/pmem_ctrl_pack-p.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/cond_branch_pack-p.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/decoder_pack-p.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/dmem_ctrl_pack-p.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/alu_pack-p.vhd" -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/alu.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/bus_mux.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/clock_ctrl.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/cond_branch.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/db_bus.vhd -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_comp_pack-p.vhd" -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/decoder.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/dmem_ctrl.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/int.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/p1.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/p2.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/pmem_ctrl.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/psw.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/timer.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t48_core.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/generic_ram_ena.vhd -set_global_assignment -name VHDL_FILE t48_rom.vhd -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_rom-e.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_rom-struct-a.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/t48_core_comp_pack-p.vhd" -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t8048_notri.vhd -set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/system/t48_system_comp_pack-p.vhd" -set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t8048.vhd - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name VHDL_INPUT_VERSION VHDL87 - -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" -set_global_assignment -name FMAX_REQUIREMENT "11 MHz" -section_id xtal -set_instance_assignment -name CLOCK_SETTINGS xtal -to xtal_i Index: t48/rel_1_2/syn/t8048/jopcyc/t48_rom.hex =================================================================== --- t48/rel_1_2/syn/t8048/jopcyc/t48_rom.hex (revision 296) +++ t48/rel_1_2/syn/t8048/jopcyc/t48_rom.hex (nonexistent) @@ -1,2 +0,0 @@ -:0700000023FF39D3010402C4 -:00000001FF Index: t48/rel_1_2/KNOWN_BUGS =================================================================== --- t48/rel_1_2/KNOWN_BUGS (revision 296) +++ t48/rel_1_2/KNOWN_BUGS (nonexistent) @@ -1,332 +0,0 @@ - -Known bugs of the T48 uController core -====================================== -Version: $Id$ - - -Release 0.6.1 BETA ------------------- - -******************************************************************************* -Deassertion of PROG too early - -PROG is deasserted in XTAL2 cycle which might lead to read data being already -invalid (tri-stated) when the core samples P2[3:0] at the end of XTAL3. - -Fixed in: -clock_ctrl.vhd 1.12 -Fix will be included in next release. - - - -Release 0.6 BETA ----------------- - -******************************************************************************* -Deassertion of PROG too early - -See above. - -******************************************************************************* -P2 Port value restored after expander access - -After access to expander interface (ANLD Pp; MOVD A,Pp; MOVD Pp,A; ORLD Pp) -the port value of P2 is restored. This is wrong according to chapter "Port 2 -Operations" of the "Expanded MCS-48 System" manual. It states that previously -latched I/O information will be removed and not restored. - -Fixed in: -p2.vhd 1.8 -Fix will be included in next release. - -******************************************************************************* -Problem when INT and JMP - -When code is executed from Memory Bank 1, the injected CALL triggered by the -interrupt does not always vector to address 3. This happens because of a bus -collision between the decoder unit and the db_bus unit. The resulting address -can be either: -* 000h, 001h, 002h, 003h for external and timer interrupt -* 004h, 005h, 006h, 007h for timer interrupt - -The problem was introduced in release 0.6 BETA when the glitch on PCH was -fixed. - -Fixed in: -decoder.vhd 1.21 -New regression test: int_on_mb1 -Fix will be included in next release. - - - -Release 0.5 BETA ----------------- - -******************************************************************************* -Deassertion of PROG too early - -See above. - -******************************************************************************* -P2 Port value restored after expander access - -See above. - -******************************************************************************* -Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt - -An interrupt occuring during the execution of a JMP instruction, forces bit 11 -of the target address to 0. This corrupts target addresses that are located in -Program Memory Bank 1. - -Fixed in: -int.vhd 1.5 -New regression test: white_box/int_on_int -Fix will be included in next release. - -******************************************************************************* -MSB of Program Counter changed upon PC increment - -The current implementation of the Program Counter allows that the MSB (bit 11) -is modifed when the PC increments at address 07FFh linear code execution. This -is contrary to the description found in "The Expanded MCS-48 System" which -states that bit 11 is only altered by JMP and CALL/RET but not by normal -increment. - -Fixed in: -pmem_crtl.vhd 1.4 -New regression test: white_box/pc_wrap_bit11 -Fix will be included in next release. - -******************************************************************************* -Wrong clock applied to T0 - -After executing the 'ENT0 CLK' instruction, the internal clock (XTAL divided -by 3) should be applied to T0. -The t48_core applies clk_i to T0. This is equal to XTAL in the current -implementation of t8048 and others. Therefore, the clock at T0 is three times -faster than specified. - -Fixed in: -clock_ctrl.vhd 1.7 -t48_core.vhd 1.8 -Fix will be included in next release. - - - -Release 0.4 BETA ----------------- - -******************************************************************************* -P2 Port value restored after expander access - -See above. - -******************************************************************************* -Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt - -See above. - -******************************************************************************* -MSB of Program Counter changed upon PC increment - -See above. - -******************************************************************************* -Wrong clock applied to T0 - -See above. - -******************************************************************************* -RD' and WR' not asserted for INS A, BUS and OUTL BUS, A - -The control signals RD' and WR' are not asserted when the instructions INS A, -BUS and OUTL BUS, A are executed. The BUS is read or written but the control -signals are missing. - -Fixed in: -decoder.vhd 1.16 -Fix will be included in next release. - -******************************************************************************* -P1 constantly in push-pull mode in t8048 - -Port P1 is constantly driven by an active push-pull driver instead of an -open-collector driver type. This inhibits using any bit of P1 in input -direction. - -Fixed in: -t8048.vhd 1.4 -Fix will be included in next release. - - - -Release 0.3 BETA ----------------- - -******************************************************************************* -P2 Port value restored after expander access - -See above. - -******************************************************************************* -Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt - -See above. - -******************************************************************************* -MSB of Program Counter changed upon PC increment - -See above. - -******************************************************************************* -Wrong clock applied to T0 - -See above. - -******************************************************************************* -RD' and WR' not asserted for INS A, BUS and OUTL BUS, A - -See above. - -******************************************************************************* -P1 constantly in push-pull mode in t8048 - -See above. - -******************************************************************************* -PSENn Timing - -PSENn is erroneously activated during read or write from external memory when -the read and write strobe signals RDn and WRn are active. This happens when -code is executed from external Program Memory. - -The problem lies in the decoder module where the PSENn signal is generated -based on the current machine cycle. - -Fixed in decoder.vhd 1.15 -Added waveform check for PSENn in if_timing.vhd 1.3 -New regression test: white_box/psen_rd_wr_timing -Fix will be included in next release. - - - -Release 0.2 BETA ----------------- - -******************************************************************************* -P2 Port value restored after expander access - -See above. - -******************************************************************************* -MSB of Program Counter changed upon PC increment - -See above. - -******************************************************************************* -Wrong clock applied to T0 - -See above. - -******************************************************************************* -RD' and WR' not asserted for INS A, BUS and OUTL BUS, A - -See above. - -******************************************************************************* -P1 constantly in push-pull mode in t8048 - -See above. - -******************************************************************************* -PSENn Timing - -See above. - -******************************************************************************* -Program Memory bank can be switched during interrupt - -During an interrupt service routine (i.e. after vectoring to location 3 or 7 -of the Program Memory and befor executing the RETR instruction) the Program -Memory bank can be switched by executing a JMP or CALL instruction. These -instructions honour the current state of the Program Memory Bank Flag and thus -switch the Program Memory bank upon execution. - -Fixed in: -int.vhd 1.2 -decoder.vhd 1.14 -Updated regression test: -black_box/mb/int -Fix will be included in next release. - - - -Release 0.1 BETA ----------------- - -******************************************************************************* -P2 Port value restored after expander access - -See above. - -******************************************************************************* -MSB of Program Counter changed upon PC increment - -See above. - -******************************************************************************* -Wrong clock applied to T0 - -See above. - -******************************************************************************* -RD' and WR' not asserted for INS A, BUS and OUTL BUS, A - -See above. - -******************************************************************************* -PSENn Timing - -See above. - -******************************************************************************* -Program Memory bank can be switched during interrupt - -See above. - -****************************************************************************** -External Program Memory ignored when EA = 0 - -The external Program Memory is always ignored when EA = 0 with the t8048 system -toplevel. Desired behaviour is to access external Program Memory when code -has to be fetched from an address location that is outside the internal -Program Memory. - -Fixed in t8048.vhd 1.3 -Fix will be included in next release. - -****************************************************************************** -ANL and ORL to P2 read port status instead of port output register - -The ANL and ORL instructions for P2 read the port status and apply the logical -operation on this value. Instead, they should read the port output register -and operate on this value. - -Fixed in p2.vhd 1.5 -Regression test: -white_box/p2_port_reg_conflict -Fix will be included in next release. - -****************************************************************************** -Counter is not incremented - -When in counter mode, the timer/counter module does not increment upon a -falling edge of T1. Reason is a typo in the code for the edge detection signal -t1_inc_s - it will never become true. - -Fixed in timer.vhd 1.3 -Regression tests: -black_box/cnt/cnt -black_box/cnt/int -Fix will be included in next release.

t48/rel_1_2/KNOWN_BUGS Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/README =================================================================== --- t48/rel_1_2/README (revision 296) +++ t48/rel_1_2/README (nonexistent) @@ -1,295 +0,0 @@ - -README for the T48 uController project -====================================== -Version: $Id$ - - -Introduction ------------- - -The T48 µController core is an implementation of the MCS-48 microcontroller -family architecture. While being a controller core for SoC, it also aims for -code-compatability and cycle-accuracy so that it can be used as a drop-in -replacement for any MCS-48 controller. -It can be configured to better suit the requirements and characteristics of -the integrating system. On the other hand, nearly the full functionality of a -stock 8048/8049 is available. - - -Download --------- - -Download the latest stable release from the project homepage at OpenCores.org: - - http://www.opencores.org/projects.cgi/web/t48/overview/ - -You can get the latest version of the design files from CVS: - - http://www.opencores.org/pdownloads.cgi/list/t48 - -Please keep in mind that this is work in progress and might contain smaller or -bigger problems. -You should also check the Tracker for known bugs and see if they affect your -work. - - -Installation ------------- - -Once the directory structure is generated either by check-out from CVS or by -unpacking the tar-archive, the central project initialization file should be -set up. A template called init_project.template.sh is located in the sw -directory where a copy can be edited. Normally, only the definition for the -variable PROJECT_DIR has to be adjusted to the path where the directory -structure is located. -The commands for setting the necessary variables assume a bash/sh-like -shell. In case you run a different shell like csh or ksh, you should adjust -these commands as well. - -The meaning of the variables is as follows: - - * PROJECT_DIR - Points to the root of the project installation. All further references are - derived from its setting. - - * VERIF_DIR - Location of the verification suite. - - * SIM_DIR - Directory for running simulations. - -These variables must be properly set whenever scripts or makefiles of the T48 -project are executed. Otherwise, you will most likely encounter error -messages. - -NOTE: The concepts of the mentioned shells require that the init_project.sh is - run in the context of the shell. I.e. you should 'source' the script - instead of executing it like a command. This will make sure that the - variable settings are really effective in the calling shell instance. - - -Directory Structure -------------------- - -The project's directory structure follows the proposal of OpenCores.org. - -t48 - | - \--+-- rtl - | | - | \-- vhdl : VHDL code containing the RTL description - | | of the core. - | +-- system : RTL VHDL code of sample systems. - | | - | \-- t8243 : RTL VHDL code of 8243 core. - | - +-- bench - | | - | \-- vhdl : VHDL testbench code. - | - +-- sim - | | - | \-- rtl_sim : Directory for running simulations. - | - +-- syn - | | - | \-- t8048 : T8048 toplevel example synthesis. - | | - | +-- b5x300 : for SpartanIIe 300. - | | - | \-- jopcyc : for Cyclone EP1C12. - | - \-- sw : General purpose scripts and files. - | - +-- i8039emu : An MCS-48 emulator written in C. - | - \-- verif : The verification suite. - | - +-- include : Global includes and makefiles. - | - +-- black_box : Black-box verification tests. - | - +-- white_box : White-box verification tests. - | - \-- gp_sw : General purpose software. - - -Compiling the VHDL Code ------------------------ - -VHDL compilation and simulation tasks take place inside in sim/rtl_sim -directory. The project setup supports only the batch mode of certain -simulators. However, there should be no problems to integrate the testbench -and RTL code into arbitrary simulation environments. - -The main file for compilation is Makefile.hier which contains all information -regarding the dependencies of the source files and their compilation -order. There is a dedicated file for each supported simulator that maps the -generic information of Makefile.hier to object files specific to the given -simulator. - -Compilation is based on the make-utility, thus invocation looks like this: - -$ make -f Makefile. - -where denotes one of the supported simulators: - - * Makefile.ghdl - Tristan Gingold's GHDL simulator/compiler, a VHDL front-end for gcc. - http://ghdl.free.fr/ - - * Makefile.simili - DISCONTINUED - VHDL Simili, a VHDL simulator by Symphony EDA - http://www.symphonyeda.com/ - -Make will analyze all VHDL files (RTL and testbench code) and elaborate all -three testbench top-levels if appropriate for the chosen simulator: - - * tb_behav_c0 - The main testbench for regression testing. - Instantiates the plain t48_core and provides internal RAM (256 bytes) and - ROM (2k bytes) plus 2k bytes of external ROM. - - * tb_t8048_behav_c0 - The testbench for the t8048 sample system. - - * tb_t8039_behav_c0 - The testbench for the 8039 sample system. - - * tb_t8243_behav_c0 - Testbench containing the t48_core and the synchronous t8243 flavour. - - * tb_t8048_t8243_behav_c0 - Testbench containing the t8048 and the asynchronous t8243 toplevel. - -Each Makefile has a 'clean' target to delete all intermediate data: - -$ make -f Makefile. clean - -The basic simple sequence list can be found in COMPILE_LIST. This can be -useful to quickly set up the analyze stage of any compiler or -synthesizer. Especially when synthesizing the code, you want to skip the VHDL -configurations in *-c.vhd and everything below the bench/ directory. - -Preparation of the ROM Files ----------------------------- - -All testbenches listed above need two files in hex-format. They contain the -program for the T48 core and are loaded into internal and external ROM at -simulation startup. Their existance is mandatory as they are referenced in the -VHDL code of the ROM model lpm_rom.vhd. In case they are missing, the -simulation will stop immediately after elaborating the design. - -These files are: - - * rom_t49.hex - Internal ROM contents for 8x49 derivatives, - address range 000H to 7FFH. - Intel hex format, starting at address 000H. - - * rom_t49_ext.hex - External ROM contents for t8x49 derivatives, - address range 800H to FFFH. - Intel hex format, starting at address 800H. - - * rom_t48.hex - Internal ROM contents for t8x48 derivatives, - address range 000H to 3FFH. - Intel hex format, starting at address 000H. - - * rom_t48_ext.hex - External ROM contents for t8x48 derivatives, - address range 400H to FFFH. - Intel hex format, starting at address 000H. - - * rom_t3x.hex - Internal ROM contents for t803x derivatives, - empty. - - * rom_t3x_ext.hex - External ROM contents for t803x derivatives, - address range 000H to FFFH. - Intel hex format, starting at address 000H. - -The verification flow for the T48 project generates these files -automatically from the assembler source files. - -All regression tests and the general purpose software is organized in a cell -structure. Currently, this means that the software for a cell is contained in -a dedicated directory where the assembler run takes place. In the future, -there will be more aspects to a cell. - -Assembling, linking and putting the hex-files in place is under the control of -the make-mechanism. E.g. to assemble the source code of a cell, issue the -following command: - -$ make -f $VERIF_DIR/include/Makefile.cell - -This generates the linker file (test.p) and distributes its contents to the -required ROM files for internal and external program ROM. The target 'simu' -copies these files automatically to the simulation directory. So most likely, -for running a test case or any other software, you will want to issue: - -$ make -f VERIF_DIR/include/Makefile.cell all clean - -The 'all' target generates hex files for all supported testbenches. - -The only supported assembler is Alfred Arnold's macroassembler AS. See - - http://john.ccac.rwth-aachen.de:8000/as/ - - -Verification Environment ------------------------- - -The verification environment consists of a number of test programs. They are -all self-checking. I.e. after testing the targeted functionality, they emit a -pass/fail information. This information is detected by the testbench which -stops the simulation and prints out the simulation result. This is the default -mechanism for stopping the VHDL simulation. - -Pass/fail is signalled by a certain sequence of the accumulator contents: - - 1) Accumulator contains AAH - 2) Accumulator contains 55H - 3) Accumulator contains 01H -> Pass - Accumulator contains 00H -> Fail - -The detection is modelled like a state machine and in case the sequence is of -bytes inside the accumulator does not match, the detection process restarts -from the beginning. This mechanism is part of all verification tests. - -The complete regression suite can be executed with the run_regression.pl -script. For each test cell, it steps through the sequence - - 1) Assemble the source code - 2) Run the compiled VHDL design (currently only GHDL) - 3) Optionally perform a dump compare against the C-model - -It is highly recommended to redirect the output of run_regression.pl into a -file. Otherwise, analyzing the messages related to each test cell is almost -impossible. - - -FPGA Implementation -------------------- - -All of the design files contain pure RTL code. Also the RAM for the data -memory is described by generic RTL code. It should be translated automatically -by the tool chain to a technology specific RAM macro. - -There is a generic method for the program memory ROM as well, although this -project uses a flow where hex-files are loaded by lpm_rom.vhd as the default -method. Convert the ROM image to an RTL VHDL file with one of the two -following commands (either from hex or bin format): - - $ hex2rom -b [rom image file] rom_t48 10l8s > rom_t48.vhd - $ hex2rom -b [rom image file] rom_t49 11l8s > rom_t49.vhd - -The option -b specifies that [rom image file] contains binary data. Skip this -option to process a file in hex format. - -These resulting RTL representations are instantiated by t48_rom-struct-a.vhd -and t49_rom-struct-a.vhd. Altera and Xilinx design tools will detect and -extract the ROM and turn it into a memory macro.

t48/rel_1_2/README Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/if_timing-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/if_timing-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/if_timing-c.vhd (nonexistent) @@ -1,18 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Interface Timing Checker. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration if_timing_behav_c0 of if_timing is - - for behav - end for; - -end if_timing_behav_c0;

t48/rel_1_2/bench/vhdl/if_timing-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb-c.vhd (nonexistent) @@ -1,43 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t48_core. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration tb_behav_c0 of tb is - - for behav - - for rom_internal_2k : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for rom_external_2k : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for ram_256 : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for ext_ram_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for t48_core_b : t48_core - use configuration work.t48_core_struct_c0; - end for; - - for if_timing_b : if_timing - use configuration work.if_timing_behav_c0; - end for; - - end for; - -end tb_behav_c0;

t48/rel_1_2/bench/vhdl/tb-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8243-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8243-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8243-c.vhd (nonexistent) @@ -1,47 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8243 core. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration tb_t8243_behav_c0 of tb_t8243 is - - for behav - - for rom_internal_2k : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for rom_external_2k : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for ram_256 : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for ext_ram_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for t48_core_b : t48_core - use configuration work.t48_core_struct_c0; - end for; - - for t8243_sync_notri_b : t8243_sync_notri - use configuration work.t8243_sync_notri_struct_c0; - end for; - - for if_timing_b : if_timing - use configuration work.if_timing_behav_c0; - end for; - - end for; - -end tb_t8243_behav_c0;

t48/rel_1_2/bench/vhdl/tb_t8243-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8048-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8048-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8048-c.vhd (nonexistent) @@ -1,31 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8048. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration tb_t8048_behav_c0 of tb_t8048 is - - for behav - - for ext_ram_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for ext_rom_b : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for t8048_b : t8048 - use configuration work.t8048_struct_c0; - end for; - - end for; - -end tb_t8048_behav_c0;

t48/rel_1_2/bench/vhdl/tb_t8048-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8039-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8039-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8039-c.vhd (nonexistent) @@ -1,31 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8039. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration tb_t8039_behav_c0 of tb_t8039 is - - for behav - - for ext_ram_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for ext_rom_b : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for t8039_b : t8039 - use configuration work.t8039_struct_c0; - end for; - - end for; - -end tb_t8039_behav_c0;

t48/rel_1_2/bench/vhdl/tb_t8039-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8048_t8243-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8048_t8243-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8048_t8243-c.vhd (nonexistent) @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8048 driving a t8243. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration tb_t8048_t8243_behav_c0 of tb_t8048_t8243 is - - for behav - - for ext_ram_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for ext_rom_b : lpm_rom - use configuration work.lpm_rom_c0; - end for; - - for t8048_b : t8048 - use configuration work.t8048_struct_c0; - end for; - - for t8243_b : t8243 - use configuration work.t8243_struct_c0; - end for; - - end for; - -end tb_t8048_t8243_behav_c0;

t48/rel_1_2/bench/vhdl/tb_t8048_t8243-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/t48_rom-lpm-a.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/t48_rom-lpm-a.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/t48_rom-lpm-a.vhd (nonexistent) @@ -1,94 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x48 ROM --- Wrapper for ROM model from the LPM library. --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -architecture lpm of t48_rom is - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - rom_b : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 10, - LPM_NUMWORDS => 2 ** 10, - LPM_FILE => "rom_t48.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => rom_addr_i, - inclock => clk_i, - outclock => clk_i, - memenab => vdd_s, - q => rom_data_o - ); - -end lpm;

t48/rel_1_2/bench/vhdl/t48_rom-lpm-a.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/t49_rom-lpm-a.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/t49_rom-lpm-a.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/t49_rom-lpm-a.vhd (nonexistent) @@ -1,94 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x49 ROM --- Wrapper for ROM model from the LPM library. --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -architecture lpm of t49_rom is - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - rom_b : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 11, - LPM_NUMWORDS => 2 ** 11, - LPM_FILE => "rom_t49.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => rom_addr_i, - inclock => clk_i, - outclock => clk_i, - memenab => vdd_s, - q => rom_data_o - ); - -end lpm;

t48/rel_1_2/bench/vhdl/t49_rom-lpm-a.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/t48_rom-lpm-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/t48_rom-lpm-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/t48_rom-lpm-c.vhd (nonexistent) @@ -1,24 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x48 ROM --- Wrapper for ROM model from the LPM library. --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_rom_lpm_c0 of t48_rom is - - for lpm - - for rom_b: lpm_rom - use configuration work.lpm_rom_c0; - end for; - - end for; - -end t48_rom_lpm_c0;

t48/rel_1_2/bench/vhdl/t48_rom-lpm-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/t49_rom-lpm-c.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/t49_rom-lpm-c.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/t49_rom-lpm-c.vhd (nonexistent) @@ -1,24 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x49 ROM --- Wrapper for ROM model from the LPM library. --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t49_rom_lpm_c0 of t49_rom is - - for lpm - - for rom_b: lpm_rom - use configuration work.lpm_rom_c0; - end for; - - end for; - -end t49_rom_lpm_c0;

t48/rel_1_2/bench/vhdl/t49_rom-lpm-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/if_timing.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/if_timing.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/if_timing.vhd (nonexistent) @@ -1,591 +0,0 @@ -------------------------------------------------------------------------------- --- --- Interface Timing Checker. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity if_timing is - - port ( - xtal_i : in std_logic; - ale_i : in std_logic; - psen_n_i : in std_logic; - rd_n_i : in std_logic; - wr_n_i : in std_logic; - prog_n_i : in std_logic; - db_bus_i : in std_logic_vector(7 downto 0); - p2_i : in std_logic_vector(7 downto 0) - ); - -end if_timing; - - - -architecture behav of if_timing is - - signal last_xtal_rise_s : time; - signal period_s : time; - - signal last_ale_rise_s, - last_ale_fall_s : time; - - signal last_psen_n_rise_s, - last_psen_n_fall_s : time; - - signal last_rd_n_rise_s, - last_rd_n_fall_s : time; - - signal last_wr_n_rise_s, - last_wr_n_fall_s : time; - - signal last_prog_n_rise_s, - last_prog_n_fall_s : time; - - signal last_bus_change_s, - bus_change_ale_s : time; - signal last_p2_change_s : time; - - signal t_CY : time; - -begin - - t_CY <= 15 * period_s; - - ----------------------------------------------------------------------------- - -- Check RD - -- - rd_check: process (rd_n_i) - begin - case rd_n_i is - -- RD active - when '0' => - -- tLAFC1: ALE to Control RD - assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns) - report "Timing violation of tLAFC1 on RD!" - severity error; - - -- tAFC1: Addr Float to RD - assert (now - last_bus_change_s) > (t_CY * 2/15 - 40 ns) - report "Timing violation of tAFC1 on RD!" - severity error; - - -- RD inactive - when '1' => - -- tCC1: Control Pulse Width RD - assert (now - last_rd_n_fall_s) > (t_CY / 2 - 200 ns) - report "Timing violation of tCC1 on RD!" - severity error; - - when others => - null; - end case; - - end process rd_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check WR - -- - wr_check: process (wr_n_i) - begin - case wr_n_i is - -- WR active - when '0' => - -- tLAFC1: ALE to Control WR - assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns) - report "Timing violation of tLAFC1 on WR!" - severity error; - - -- tAW: Addr Setup to WR - assert (now - bus_change_ale_s) > (t_CY / 3 - 150 ns) - report "Timing violation of tAW on WR!" - severity error; - - -- WR inactive - when '1' => - -- tCC1: Control Pulse Width WR - assert (now - last_wr_n_fall_s) > (t_CY / 2 - 200 ns) - report "Timing violation of tCC1 on WR!" - severity error; - - -- tDW: Data Setup before WR - assert (now - last_bus_change_s) > (t_CY * 13/30 - 200 ns) - report "Timing violation of tDW on WR!" - severity error; - - when others => - null; - end case; - - end process wr_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check BUS - -- - bus_check: process (db_bus_i) - begin - -- RD access - -- tAD1 and tRD1 are not checked as they are constraints for the - -- external memory, not the t48! - - -- WR access - if wr_n_i = '0' then - -- tDW: Data Hold after WR - assert (now - last_wr_n_rise_s) > (t_CY / 15 - 50 ns) - report "Timing violation of tDW on BUS vs. WR!" - severity error; - - end if; - - -- Address strobe - if ale_i = '0' then - -- tLA: Addr Hold from ALE - assert (now - last_ale_fall_s) > (t_CY / 15 - 40 ns) - report "Timing violation of tLA on BUS vs. ALE!" - severity error; - end if; - - -- PSEN - if psen_n_i = '0' then - -- tRD2: PSEN to Data In - assert (now - last_psen_n_fall_s) < (t_CY * 4/15 - 170 ns) - report "Timing violation of tRD2 on BUS vs. PSEN!" - severity error; - end if; - - end process bus_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check ALE - -- - ale_check: process (ale_i) - variable t_CA1 : time; - variable t_AL : time; - begin - case ale_i is - when '0' => - t_AL := t_CY * 2/15 - 110 ns; - - -- tAL: Addr Setup to ALE - assert (now - last_bus_change_s) > t_AL - report "Timing violation of tAL on BUS vs. ALE!" - severity error; - assert (now - last_p2_change_s) > t_AL - report "Timing violation of tAL on P2 vs. ALE!" - severity error; - - when '1' => - -- tCA1: Control to ALE (RD, WR, PROG) - t_CA1 := t_CY / 15 - 40 ns; - - assert (now - last_rd_n_rise_s) > t_CA1 - report "Timing violation of tCA1 on RD vs. ALE!" - severity error; - assert (now - last_wr_n_rise_s) > t_CA1 - report "Timing violation of tCA1 on WR vs. ALE!" - severity error; - assert (now - last_prog_n_rise_s) > t_CA1 - report "Timing violation of tCA1 on PROG vs. ALE!" - severity error; - - -- tCA2: Control to ALE (PSEN) - assert (now - last_psen_n_rise_s) > (t_CY * 4/15 - 40 ns) - report "Timing violation of tCA2 on PSEN vs. ALE!" - severity error; - - -- tPL: Port 2 I/O Setup to ALE - assert (now - last_p2_change_s) > (t_CY * 4/15 - 200 ns) - report "Timing violation of tPL on P2 vs. ALE!" - severity error; - - when others => - null; - - end case; - - end process ale_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check P2 - -- - p2_check: process (p2_i) - begin - case ale_i is - when '0' => - -- tLA: Addr Hold from ALE - assert ((now - last_ale_fall_s) > (t_CY / 15 - 40 ns)) or - now = 0 ns - report "Timing violation of tLA on P2 vs. ALE!" - severity error; - - if last_ale_fall_s < last_ale_rise_s then - -- tPV: Port Output from ALE - assert (now - last_ale_fall_s) < (t_CY * 3/10 + 100 ns) - report "Timing violation of tPV on P2 vs. ALE!" - severity error; - end if; - - if prog_n_i = '1' then - -- tPD: Output Data Hold - assert ((now - last_prog_n_rise_s) > (t_CY / 10 - 50 ns)) or - now = 0 ns - report "Timing violation of tPD on P2 vs. PROG!" - severity error; - - end if; - - when '1' => - -- tLP: Port 2 I/O to ALE - assert (now - last_ale_rise_s) > (t_CY / 30 - 30 ns) - report "Timing violation of tLP on P2 vs. ALE!" - severity error; - - when others => - null; - - end case; - - end process p2_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check PROG - -- - prog_check: process (prog_n_i) - begin - case prog_n_i is - when '0' => - -- tCP: Port Control Setup to PROG' - assert (now - last_p2_change_s) > (t_CY * 2/15 - 80 ns) - report "Timing violation of tCP on P2 vs PROG'!" - severity error; - - when '1' => - -- tPP: PROG Pulse Width - assert (now - last_prog_n_fall_s) > (t_CY * 7/10 - 250 ns) - report "Timing violation of tPP!" - severity error; - - -- tDP: Output Data Setup - assert (now - last_p2_change_s) > (t_CY * 2/5 - 150 ns) - report "Timing violation of tDP on P2 vs. PROG!" - severity error; - - when others => - null; - end case; - - end process prog_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check PSEN - -- - psen_check: process (psen_n_i) - begin - case psen_n_i is - when '1' => - -- tCC2: Control Pulse Width PSEN - assert (now - last_psen_n_fall_s) > (t_CY * 2/5 - 200 ns) - report "Timing violation of tCC2 on PSEN!" - severity error; - - when '0' => - -- tLAFC2: ALE to Control PSEN - assert (now - last_ale_fall_s) > (t_CY / 10 - 75 ns) - report "Timing violation of tLAFC2 on PSEN vs. ALE!" - severity error; - - when others => - null; - - end case; - - end process psen_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Check cycle overlap - -- - cycle_overlap_check: process (psen_n_i, - rd_n_i, - wr_n_i) - variable tmp_v : std_logic_vector(2 downto 0); - begin - tmp_v := psen_n_i & rd_n_i & wr_n_i; - case tmp_v is - when "001" | - "010" | - "100" | - "000" => - assert false - report "Cycle overlap deteced on PSEN, RD and WR!" - severity error; - when others => - null; - - end case; - - end process cycle_overlap_check; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor XTAL - -- - xtal_mon: process - begin - last_xtal_rise_s <= 0 ns; - period_s <= 90 ns; - - while true loop - wait on xtal_i; - - if xtal_i = '1' then - period_s <= now - last_xtal_rise_s; - last_xtal_rise_s <= now; - end if; - - end loop; - - end process xtal_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor ALE - -- - ale_mon: process - begin - last_ale_rise_s <= 0 ns; - last_ale_fall_s <= 0 ns; - - while true loop - wait on ale_i; - - case ale_i is - when '0' => - last_ale_fall_s <= now; - when '1' => - last_ale_rise_s <= now; - when others => - null; - end case; - - end loop; - - end process ale_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor PSEN - -- - psen_mon: process - begin - last_psen_n_rise_s <= 0 ns; - last_psen_n_fall_s <= 0 ns; - - while true loop - wait on psen_n_i; - - case psen_n_i is - when '0' => - last_psen_n_fall_s <= now; - when '1' => - last_psen_n_rise_s <= now; - when others => - null; - end case; - - end loop; - - end process psen_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor RD - -- - rd_mon: process - begin - last_rd_n_rise_s <= 0 ns; - last_rd_n_fall_s <= 0 ns; - - while true loop - wait on rd_n_i; - - case rd_n_i is - when '0' => - last_rd_n_fall_s <= now; - when '1' => - last_rd_n_rise_s <= now; - when others => - null; - end case; - - end loop; - - end process rd_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor WR - -- - wr_mon: process - begin - last_wr_n_rise_s <= 0 ns; - last_wr_n_fall_s <= 0 ns; - - while true loop - wait on wr_n_i; - - case wr_n_i is - when '0' => - last_wr_n_fall_s <= now; - when '1' => - last_wr_n_rise_s <= now; - when others => - null; - end case; - - end loop; - - end process wr_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor PROG - -- - prog_mon: process - begin - last_prog_n_rise_s <= 0 ns; - last_prog_n_fall_s <= 0 ns; - - while true loop - wait on prog_n_i; - - case prog_n_i is - when '0' => - last_prog_n_fall_s <= now; - when '1' => - last_prog_n_rise_s <= now; - when others => - null; - end case; - - end loop; - - end process prog_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor BUS - -- - bus_mon: process - begin - last_bus_change_s <= 0 ns; - bus_change_ale_s <= 0 ns; - - while true loop - wait on db_bus_i; - - last_bus_change_s <= now; - - if ale_i = '1' then - bus_change_ale_s <= now; - end if; - end loop; - - end process bus_mon; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Monitor P2 - -- - p2_mon: process - begin - last_p2_change_s <= 0 ns; - - while true loop - wait on p2_i; - - last_p2_change_s <= now; - end loop; - - end process p2_mon; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/if_timing.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb.vhd (nonexistent) @@ -1,561 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t48_core. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity tb is - -end tb; - - -use work.t48_core_comp_pack.all; - -use work.t48_tb_pack.all; - -architecture behav of tb is - - -- clock period, 11 MHz - constant period_c : time := 90 ns; - - component if_timing - port( - xtal_i : in std_logic; - ale_i : in std_logic; - psen_n_i : in std_logic; - rd_n_i : in std_logic; - wr_n_i : in std_logic; - prog_n_i : in std_logic; - db_bus_i : in std_logic_vector(7 downto 0); - p2_i : in std_logic_vector(7 downto 0) - ); - end component; - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal xtal_s : std_logic; - signal xtal_n_s : std_logic; - signal res_n_s : std_logic; - signal xtal3_s : std_logic; - signal int_n_s : std_logic; - signal ale_s : std_logic; - signal rom_addr_s : std_logic_vector(11 downto 0); - signal rom_data_s : std_logic_vector( 7 downto 0); - signal ram_data_to_s : std_logic_vector( 7 downto 0); - signal ram_data_from_s : std_logic_vector( 7 downto 0); - signal ram_addr_s : std_logic_vector( 7 downto 0); - signal ram_we_s : std_logic; - - signal p1_s : std_logic_vector( 7 downto 0); - signal t48_p1_s : std_logic_vector( 7 downto 0); - signal p1_low_imp_s : std_logic; - signal p2_s : std_logic_vector( 7 downto 0); - signal t48_p2_s : std_logic_vector( 7 downto 0); - signal p2l_low_imp_s : std_logic; - signal p2h_low_imp_s : std_logic; - signal psen_n_s : std_logic; - signal prog_n_s : std_logic; - - signal bus_s : std_logic_vector( 7 downto 0); - signal t48_bus_s : std_logic_vector( 7 downto 0); - signal bus_dir_s : std_logic; - - signal ext_mem_addr_q : std_logic_vector( 7 downto 0); - signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); - signal ext_ram_we_q : std_logic; - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - - signal ext_rom_data_s : std_logic_vector( 7 downto 0); - signal ext_rom_addr_s : std_logic_vector(11 downto 0); - - signal tb_p1_q : std_logic_vector( 7 downto 0); - signal tb_p2_q : std_logic_vector( 7 downto 0); - - signal ext_mem_sel_we_q : boolean; - signal ena_ext_ram_q : boolean; - signal ena_tb_periph_q : boolean; - - signal zero_s : std_logic; - signal one_s : std_logic; - signal zero_byte_s : std_logic_vector( 7 downto 0); - -begin - - zero_s <= '0'; - one_s <= '1'; - zero_byte_s <= (others => '0'); - - ----------------------------------------------------------------------------- - -- Internal ROM, 2k bytes - -- Initialized by file rom_t49.hex. - ----------------------------------------------------------------------------- - rom_internal_2k : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 11, - LPM_NUMWORDS => 2 ** 11, - LPM_FILE => "rom_t49.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => rom_addr_s(10 downto 0), - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => rom_data_s - ); - - ----------------------------------------------------------------------------- - -- External ROM, 2k bytes - -- Initialized by file rom_t49_ext.hex. - ----------------------------------------------------------------------------- - ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0); - ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q; - rom_external_2k : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 11, - LPM_NUMWORDS => 2 ** 11, - LPM_FILE => "rom_t49_ext.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => ext_rom_addr_s(10 downto 0), - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => ext_rom_data_s - ); - - ----------------------------------------------------------------------------- - -- Internal RAM, 256 bytes - ----------------------------------------------------------------------------- - ram_256 : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ram_addr_s, - we_i => ram_we_s, - ena_i => one_s, - d_i => ram_data_to_s, - d_o => ram_data_from_s - ); - - ----------------------------------------------------------------------------- - -- External RAM, 256 bytes - ----------------------------------------------------------------------------- - ext_ram_b : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ext_mem_addr_q, - we_i => ext_ram_we_q, - ena_i => one_s, - d_i => bus_s, - d_o => ext_ram_data_from_s - ); - - t48_core_b : t48_core - generic map ( - xtal_div_3_g => 1, - register_mnemonic_g => 1, - include_port1_g => 1, - include_port2_g => 1, - include_bus_g => 1, - include_timer_g => 1, - sample_t1_state_g => 4 - ) - port map ( - xtal_i => xtal_s, - xtal_en_i => one_s, - reset_i => res_n_s, - t0_i => p1_s(0), - t0_o => open, - t0_dir_o => open, - int_n_i => int_n_s, - ea_i => rom_addr_s(11), - rd_n_o => rd_n_s, - psen_n_o => psen_n_s, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_i => bus_s, - db_o => t48_bus_s, - db_dir_o => bus_dir_s, - t1_i => p1_s(1), - p2_i => p2_s, - p2_o => t48_p2_s, - p2l_low_imp_o => p2l_low_imp_s, - p2h_low_imp_o => p2h_low_imp_s, - p1_i => p1_s, - p1_o => t48_p1_s, - p1_low_imp_o => p1_low_imp_s, - prog_n_o => prog_n_s, - clk_i => xtal_s, - en_clk_i => xtal3_s, - xtal3_o => xtal3_s, - dmem_addr_o => ram_addr_s, - dmem_we_o => ram_we_s, - dmem_data_i => ram_data_from_s, - dmem_data_o => ram_data_to_s, - pmem_addr_o => rom_addr_s, - pmem_data_i => rom_data_s - ); - - if_timing_b : if_timing - port map ( - xtal_i => xtal_s, - ale_i => ale_s, - psen_n_i => psen_n_s, - rd_n_i => rd_n_s, - wr_n_i => wr_n_s, - prog_n_i => prog_n_s, - db_bus_i => bus_s, - p2_i => t48_p2_s - ); - - - ----------------------------------------------------------------------------- - -- Port logic - -- - ports: process (t48_p1_s, - p1_low_imp_s, - t48_p2_s, - p2l_low_imp_s, - p2h_low_imp_s) - function t48_port_f(t48_p : std_logic_vector; - low_imp : std_logic) return std_logic_vector is - variable p_v : std_logic_vector(t48_p'range); - begin - if low_imp = '1' then - p_v := t48_p; - - else - for i in p_v'range loop - if t48_p(i) = '1' then - p_v(i) := 'H'; - else - p_v(i) := t48_p(i); - end if; - end loop; - - end if; - - return p_v; - end; - - begin - - p1_s <= t48_port_f(t48_p => t48_p1_s, - low_imp => p1_low_imp_s); - - p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0), - low_imp => p2l_low_imp_s); - p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4), - low_imp => p2h_low_imp_s); - - end process ports; - -- - ----------------------------------------------------------------------------- - - bus_s <= t48_bus_s - when bus_dir_s = '1' else - (others => 'Z'); - - bus_s <= ext_ram_data_from_s - when rd_n_s = '0' and ena_ext_ram_q else - (others => 'Z'); - - bus_s <= ext_rom_data_s - when psen_n_s = '0' else - (others => 'Z'); - - - ----------------------------------------------------------------------------- - -- External memory access signals - -- - ext_mem: process (wr_n_s, - ext_mem_addr_q, - ena_ext_ram_q, - ale_s, - bus_s, - xtal_s) - begin - if ale_s'event and ale_s = '0' then - if not is_X(bus_s) then - ext_mem_addr_q <= bus_s; - else - ext_mem_addr_q <= (others => '0'); - end if; - end if; - - if wr_n_s'event and wr_n_s = '1' then - -- write enable for external RAM - if ena_ext_ram_q then - ext_ram_we_q <= '1'; - end if; - - -- process external memory selector - if ext_mem_addr_q = "11111111" then - ext_mem_sel_we_q <= true; - end if; - - end if; - - if xtal_s'event and xtal_s = '1' then - ext_ram_we_q <= '0'; - ext_mem_sel_we_q <= false; - end if; - - end process ext_mem; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process ext_mem_sel - -- - -- Purpose: - -- Select external memory address space. - -- This is either - -- + external RAM - -- + testbench peripherals - -- - ext_mem_sel: process (res_n_s, xtal_s) - begin - if res_n_s = '0' then - ena_ext_ram_q <= true; - ena_tb_periph_q <= false; - - elsif xtal_s'event and xtal_s = '1' then - if ext_mem_sel_we_q then - if bus_s(0) = '1' then - ena_ext_ram_q <= true; - else - ena_ext_ram_q <= false; - end if; - - if bus_s(1) = '1' then - ena_tb_periph_q <= true; - else - ena_tb_periph_q <= false; - end if; - end if; - - end if; - - end process ext_mem_sel; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process tb_periph - -- - -- Purpose: - -- Implements the testbenc peripherals driving P1 and P2. - -- - tb_periph: process (res_n_s, wr_n_s) - - function oc_f (pX : std_logic_vector) return std_logic_vector is - variable r_v : std_logic_vector(pX'range); - begin - for i in pX'range loop - if pX(i) = '0' then - r_v(i) := '0'; - else - r_v(i) := 'H'; - end if; - end loop; - - return r_v; - end; - - begin - if res_n_s = '0' then - tb_p1_q <= (others => 'H'); - tb_p2_q <= (others => 'H'); - - elsif wr_n_s'event and wr_n_s = '1' then - if ena_tb_periph_q then - case ext_mem_addr_q is - -- P1 - when "00000000" => - tb_p1_q <= oc_f(t48_bus_s); - - -- P2 - when "00000001" => - tb_p2_q <= oc_f(t48_bus_s); - - when others => - null; - - end case; - - end if; - - end if; - - end process tb_periph; - -- - ----------------------------------------------------------------------------- - - p1_s <= tb_p1_q; - p2_s <= tb_p2_q; - - - xtal_n_s <= not xtal_s; - - ----------------------------------------------------------------------------- - -- The clock generator - -- - clk_gen: process - begin - xtal_s <= '0'; - wait for period_c/2; - xtal_s <= '1'; - wait for period_c/2; - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The reset generator - -- - res_gen: process - begin - res_n_s <= '0'; - wait for 5 * period_c; - res_n_s <= '1'; - wait; - end process res_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The interrupt generator - -- - int_gen: process - begin - int_n_s <= '1'; - wait for 750 * period_c; - int_n_s <= '0'; - wait for 45 * period_c; - end process int_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- End of simulation detection - -- - eos: process - begin - - outer: loop - wait on tb_accu_s; - if tb_accu_s = "10101010" then - wait on tb_accu_s; - if tb_accu_s = "01010101" then - wait on tb_accu_s; - if tb_accu_s = "00000001" then - -- wait for instruction strobe of this move - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - -- wait for next strobe - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - assert false - report "Simulation Result: PASS." - severity note; - else - assert false - report "Simulation Result: FAIL." - severity note; - end if; - - assert false - report "End of simulation reached." - severity failure; - - end if; - end if; - end loop; - - end process eos; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/tb.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8243.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8243.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8243.vhd (nonexistent) @@ -1,624 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8243 core. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity tb_t8243 is - -end tb_t8243; - - -use work.t48_core_comp_pack.all; -use work.t8243_comp_pack.t8243_sync_notri; - -use work.t48_tb_pack.all; - -architecture behav of tb_t8243 is - - -- clock period, 11 MHz - constant period_c : time := 90 ns; - - component if_timing - port( - xtal_i : in std_logic; - ale_i : in std_logic; - psen_n_i : in std_logic; - rd_n_i : in std_logic; - wr_n_i : in std_logic; - prog_n_i : in std_logic; - db_bus_i : in std_logic_vector(7 downto 0); - p2_i : in std_logic_vector(7 downto 0) - ); - end component; - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal xtal_s : std_logic; - signal xtal_n_s : std_logic; - signal res_n_s : std_logic; - signal xtal3_s : std_logic; - signal int_n_s : std_logic; - signal ale_s : std_logic; - signal rom_addr_s : std_logic_vector(11 downto 0); - signal rom_data_s : std_logic_vector( 7 downto 0); - signal ram_data_to_s : std_logic_vector( 7 downto 0); - signal ram_data_from_s : std_logic_vector( 7 downto 0); - signal ram_addr_s : std_logic_vector( 7 downto 0); - signal ram_we_s : std_logic; - - signal p1_s : std_logic_vector( 7 downto 0); - signal t48_p1_s : std_logic_vector( 7 downto 0); - signal p1_low_imp_s : std_logic; - signal p2_s : std_logic_vector( 7 downto 0); - signal t48_p2_s : std_logic_vector( 7 downto 0); - signal p2l_low_imp_s : std_logic; - signal p2h_low_imp_s : std_logic; - signal psen_n_s : std_logic; - signal prog_n_s : std_logic; - - signal bus_s : std_logic_vector( 7 downto 0); - signal t48_bus_s : std_logic_vector( 7 downto 0); - signal bus_dir_s : std_logic; - - signal ext_mem_addr_q : std_logic_vector( 7 downto 0); - signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); - signal ext_ram_we_q : std_logic; - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - - signal ext_rom_data_s : std_logic_vector( 7 downto 0); - signal ext_rom_addr_s : std_logic_vector(11 downto 0); - - signal tb_p1_q : std_logic_vector( 7 downto 0); - signal tb_p2_q : std_logic_vector( 7 downto 0); - - signal ext_mem_sel_we_q : boolean; - signal ena_ext_ram_q : boolean; - signal ena_tb_periph_q : boolean; - - signal t8243_p2_s : std_logic_vector(3 downto 0); - signal t8243_p2_en_s : std_logic; - signal p4_s, - p5_s, - p6_s, - p7_s : std_logic_vector(3 downto 0); - signal p4_p6_s, - p5_p7_s : std_logic_vector(3 downto 0); - signal p4_en_s, - p5_en_s, - p6_en_s, - p7_en_s : std_logic; - - signal zero_s : std_logic; - signal one_s : std_logic; - signal zero_byte_s : std_logic_vector( 7 downto 0); - -begin - - zero_s <= '0'; - one_s <= '1'; - zero_byte_s <= (others => '0'); - - ----------------------------------------------------------------------------- - -- Internal ROM, 2k bytes - -- Initialized by file rom_t49.hex. - ----------------------------------------------------------------------------- - rom_internal_2k : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 11, - LPM_NUMWORDS => 2 ** 11, - LPM_FILE => "rom_t49.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => rom_addr_s(10 downto 0), - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => rom_data_s - ); - - ----------------------------------------------------------------------------- - -- External ROM, 2k bytes - -- Initialized by file rom_t49_ext.hex. - ----------------------------------------------------------------------------- - ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0); - ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q; - rom_external_2k : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 11, - LPM_NUMWORDS => 2 ** 11, - LPM_FILE => "rom_t49_ext.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => ext_rom_addr_s(10 downto 0), - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => ext_rom_data_s - ); - - ----------------------------------------------------------------------------- - -- Internal RAM, 256 bytes - ----------------------------------------------------------------------------- - ram_256 : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ram_addr_s, - we_i => ram_we_s, - ena_i => one_s, - d_i => ram_data_to_s, - d_o => ram_data_from_s - ); - - ----------------------------------------------------------------------------- - -- External RAM, 256 bytes - ----------------------------------------------------------------------------- - ext_ram_b : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ext_mem_addr_q, - we_i => ext_ram_we_q, - ena_i => one_s, - d_i => bus_s, - d_o => ext_ram_data_from_s - ); - - t48_core_b : t48_core - generic map ( - xtal_div_3_g => 1, - register_mnemonic_g => 1, - include_port1_g => 1, - include_port2_g => 1, - include_bus_g => 1, - include_timer_g => 1, - sample_t1_state_g => 4 - ) - port map ( - xtal_i => xtal_s, - xtal_en_i => one_s, - reset_i => res_n_s, - t0_i => p1_s(0), - t0_o => open, - t0_dir_o => open, - int_n_i => int_n_s, - ea_i => rom_addr_s(11), - rd_n_o => rd_n_s, - psen_n_o => psen_n_s, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_i => bus_s, - db_o => t48_bus_s, - db_dir_o => bus_dir_s, - t1_i => p1_s(1), - p2_i => p2_s, - p2_o => t48_p2_s, - p2l_low_imp_o => p2l_low_imp_s, - p2h_low_imp_o => p2h_low_imp_s, - p1_i => p1_s, - p1_o => t48_p1_s, - p1_low_imp_o => p1_low_imp_s, - prog_n_o => prog_n_s, - clk_i => xtal_s, - en_clk_i => xtal3_s, - xtal3_o => xtal3_s, - dmem_addr_o => ram_addr_s, - dmem_we_o => ram_we_s, - dmem_data_i => ram_data_from_s, - dmem_data_o => ram_data_to_s, - pmem_addr_o => rom_addr_s, - pmem_data_i => rom_data_s - ); - - if_timing_b : if_timing - port map ( - xtal_i => xtal_s, - ale_i => ale_s, - psen_n_i => psen_n_s, - rd_n_i => rd_n_s, - wr_n_i => wr_n_s, - prog_n_i => prog_n_s, - db_bus_i => bus_s, - p2_i => t48_p2_s - ); - - - t8243_sync_notri_b : t8243_sync_notri - port map ( - clk_i => xtal_s, - clk_en_i => one_s, - reset_n_i => one_s, - cs_n_i => zero_s, - prog_n_i => prog_n_s, - p2_i => t48_p2_s(3 downto 0), - p2_o => t8243_p2_s, - p2_en_o => t8243_p2_en_s, - p4_i => p4_p6_s, - p4_o => p4_s, - p4_en_o => p4_en_s, - p5_i => p5_p7_s, - p5_o => p5_s, - p5_en_o => p5_en_s, - p6_i => p4_p6_s, - p6_o => p6_s, - p6_en_o => p6_en_s, - p7_i => p5_p7_s, - p7_o => p7_s, - p7_en_o => p7_en_s - ); - p4_p6_s <= p4_s - when p4_en_s = '1' else - (others => 'Z'); - p5_p7_s <= p5_s - when p5_en_s = '1' else - (others => 'Z'); - p4_p6_s <= p6_s - when p6_en_s = '1' else - (others => 'Z'); - p5_p7_s <= p7_s - when p7_en_s = '1' else - (others => 'Z'); - - - - ----------------------------------------------------------------------------- - -- Port logic - -- - ports: process (t48_p1_s, - p1_low_imp_s, - t48_p2_s, - p2l_low_imp_s, - p2h_low_imp_s) - function t48_port_f(t48_p : std_logic_vector; - low_imp : std_logic) return std_logic_vector is - variable p_v : std_logic_vector(t48_p'range); - begin - if low_imp = '1' then - p_v := t48_p; - - else - for i in p_v'range loop - if t48_p(i) = '1' then - p_v(i) := 'H'; - else - p_v(i) := t48_p(i); - end if; - end loop; - - end if; - - return p_v; - end; - - begin - - p1_s <= t48_port_f(t48_p => t48_p1_s, - low_imp => p1_low_imp_s); - - p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0), - low_imp => p2l_low_imp_s); - p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4), - low_imp => p2h_low_imp_s); - - end process ports; - -- - ----------------------------------------------------------------------------- - - t8243_p2: process (t8243_p2_s, - t8243_p2_en_s) - begin - p2_s <= (others => 'Z'); - - if t8243_p2_en_s = '1' then - p2_s(3 downto 0) <= t8243_p2_s; - end if; - end process t8243_p2; - - - bus_s <= t48_bus_s - when bus_dir_s = '1' else - (others => 'Z'); - - bus_s <= ext_ram_data_from_s - when rd_n_s = '0' and ena_ext_ram_q else - (others => 'Z'); - - bus_s <= ext_rom_data_s - when psen_n_s = '0' else - (others => 'Z'); - - - ----------------------------------------------------------------------------- - -- External memory access signals - -- - ext_mem: process (wr_n_s, - ext_mem_addr_q, - ena_ext_ram_q, - ale_s, - bus_s, - xtal_s) - begin - if ale_s'event and ale_s = '0' then - if not is_X(bus_s) then - ext_mem_addr_q <= bus_s; - else - ext_mem_addr_q <= (others => '0'); - end if; - end if; - - if wr_n_s'event and wr_n_s = '1' then - -- write enable for external RAM - if ena_ext_ram_q then - ext_ram_we_q <= '1'; - end if; - - -- process external memory selector - if ext_mem_addr_q = "11111111" then - ext_mem_sel_we_q <= true; - end if; - - end if; - - if xtal_s'event and xtal_s = '1' then - ext_ram_we_q <= '0'; - ext_mem_sel_we_q <= false; - end if; - - end process ext_mem; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process ext_mem_sel - -- - -- Purpose: - -- Select external memory address space. - -- This is either - -- + external RAM - -- + testbench peripherals - -- - ext_mem_sel: process (res_n_s, xtal_s) - begin - if res_n_s = '0' then - ena_ext_ram_q <= true; - ena_tb_periph_q <= false; - - elsif xtal_s'event and xtal_s = '1' then - if ext_mem_sel_we_q then - if bus_s(0) = '1' then - ena_ext_ram_q <= true; - else - ena_ext_ram_q <= false; - end if; - - if bus_s(1) = '1' then - ena_tb_periph_q <= true; - else - ena_tb_periph_q <= false; - end if; - end if; - - end if; - - end process ext_mem_sel; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process tb_periph - -- - -- Purpose: - -- Implements the testbenc peripherals driving P1 and P2. - -- - tb_periph: process (res_n_s, wr_n_s) - - function oc_f (pX : std_logic_vector) return std_logic_vector is - variable r_v : std_logic_vector(pX'range); - begin - for i in pX'range loop - if pX(i) = '0' then - r_v(i) := '0'; - else - r_v(i) := 'H'; - end if; - end loop; - - return r_v; - end; - - begin - if res_n_s = '0' then - tb_p1_q <= (others => 'H'); - tb_p2_q <= (others => 'H'); - - elsif wr_n_s'event and wr_n_s = '1' then - if ena_tb_periph_q then - case ext_mem_addr_q is - -- P1 - when "00000000" => - tb_p1_q <= oc_f(t48_bus_s); - - -- P2 - when "00000001" => - tb_p2_q <= oc_f(t48_bus_s); - - when others => - null; - - end case; - - end if; - - end if; - - end process tb_periph; - -- - ----------------------------------------------------------------------------- - - p1_s <= tb_p1_q; - p2_s <= tb_p2_q; - - - xtal_n_s <= not xtal_s; - - ----------------------------------------------------------------------------- - -- The clock generator - -- - clk_gen: process - begin - xtal_s <= '0'; - wait for period_c/2; - xtal_s <= '1'; - wait for period_c/2; - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The reset generator - -- - res_gen: process - begin - res_n_s <= '0'; - wait for 5 * period_c; - res_n_s <= '1'; - wait; - end process res_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The interrupt generator - -- - int_gen: process - begin - int_n_s <= '1'; - wait for 750 * period_c; - int_n_s <= '0'; - wait for 45 * period_c; - end process int_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- End of simulation detection - -- - eos: process - begin - - outer: loop - wait on tb_accu_s; - if tb_accu_s = "10101010" then - wait on tb_accu_s; - if tb_accu_s = "01010101" then - wait on tb_accu_s; - if tb_accu_s = "00000001" then - -- wait for instruction strobe of this move - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - -- wait for next strobe - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - assert false - report "Simulation Result: PASS." - severity note; - else - assert false - report "Simulation Result: FAIL." - severity note; - end if; - - assert false - report "End of simulation reached." - severity failure; - - end if; - end if; - end loop; - - end process eos; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/tb_t8243.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8048.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8048.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8048.vhd (nonexistent) @@ -1,296 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8048. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity tb_t8048 is - -end tb_t8048; - - -use work.t48_core_comp_pack.generic_ram_ena; -use work.t48_system_comp_pack.t8048; - -use work.t48_tb_pack.all; - -architecture behav of tb_t8048 is - - -- clock period, 11 MHz - constant period_c : time := 90 ns; - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal xtal_s : std_logic; - signal res_n_s : std_logic; - signal int_n_s : std_logic; - signal ale_s : std_logic; - signal psen_n_s : std_logic; - signal prog_n_s : std_logic; - - signal t0_b : std_logic; - - signal p1_b : std_logic_vector( 7 downto 0); - signal p2_b : std_logic_vector( 7 downto 0); - - signal db_b : std_logic_vector( 7 downto 0); - signal ext_mem_addr_s : std_logic_vector(11 downto 0); - signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); - signal ext_ram_we_s : std_logic; - signal ext_rom_data_s : std_logic_vector( 7 downto 0); - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - - signal zero_s : std_logic; - signal one_s : std_logic; - -begin - - zero_s <= '0'; - one_s <= '1'; - - p2_b <= (others => 'H'); - p1_b <= (others => 'H'); - - ----------------------------------------------------------------------------- - -- External ROM, 3k bytes - -- Initialized by file t48_ext_rom.hex. - ----------------------------------------------------------------------------- - ext_rom_b : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 12, - LPM_NUMWORDS => 3 * (2 ** 10), - LPM_FILE => "rom_t48_ext.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => ext_mem_addr_s, - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => ext_rom_data_s - ); - - ext_ram_b : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ext_mem_addr_s(7 downto 0), - we_i => ext_ram_we_s, - ena_i => one_s, - d_i => db_b, - d_o => ext_ram_data_from_s - ); - - t8048_b : t8048 - port map ( - xtal_i => xtal_s, - reset_n_i => res_n_s, - t0_b => t0_b, - int_n_i => int_n_s, - ea_i => zero_s, - rd_n_o => rd_n_s, - psen_n_o => psen_n_s, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_b => db_b, - t1_i => p1_b(1), - p2_b => p2_b, - p1_b => p1_b, - prog_n_o => prog_n_s - ); - - - ----------------------------------------------------------------------------- - -- Read from external memory - -- - db_b <= ext_rom_data_s - when psen_n_s = '0' else - (others => 'Z'); - db_b <= ext_ram_data_from_s - when rd_n_s = '0' else - (others => 'Z'); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- External RAM access signals - -- - ext_ram: process (wr_n_s, - ale_s, - p2_b, - db_b) - begin - -- lowest 1k of external ROM is not used - ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0)); - - if ale_s'event and ale_s = '0' then - if not is_X(db_b) then - ext_mem_addr_s(7 downto 0) <= db_b; - else - ext_mem_addr_s(7 downto 0) <= (others => '0'); - end if; - end if; - - if wr_n_s'event and wr_n_s = '1' then - ext_ram_we_s <= '0'; - end if; - if wr_n_s'event and wr_n_s = '0' then - ext_ram_we_s <= '1'; - end if; - - end process ext_ram; - -- - ----------------------------------------------------------------------------- - - t0_b <= p1_b(0); - - ----------------------------------------------------------------------------- - -- The clock generator - -- - clk_gen: process - begin - xtal_s <= '0'; - wait for period_c/2; - xtal_s <= '1'; - wait for period_c/2; - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The reset generator - -- - res_gen: process - begin - res_n_s <= '0'; - wait for 5 * period_c; - res_n_s <= '1'; - wait; - end process res_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The interrupt generator - -- - int_gen: process - begin - int_n_s <= '1'; - wait for 750 * period_c; - int_n_s <= '0'; - wait for 45 * period_c; - end process int_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- End of simulation detection - -- - eos: process - begin - - outer: loop - wait on tb_accu_s; - if tb_accu_s = "10101010" then - wait on tb_accu_s; - if tb_accu_s = "01010101" then - wait on tb_accu_s; - if tb_accu_s = "00000001" then - -- wait for instruction strobe of this move - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - -- wait for next strobe - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - assert false - report "Simulation Result: PASS." - severity note; - else - assert false - report "Simulation Result: FAIL." - severity note; - end if; - - assert false - report "End of simulation reached." - severity failure; - - end if; - end if; - end loop; - - end process eos; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/tb_t8048.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8039.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8039.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8039.vhd (nonexistent) @@ -1,294 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8039. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity tb_t8039 is - -end tb_t8039; - -use work.t48_core_comp_pack.generic_ram_ena; -use work.t48_system_comp_pack.t8039; - -use work.t48_tb_pack.all; - -architecture behav of tb_t8039 is - - -- clock period, 11 MHz - constant period_c : time := 90 ns; - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal xtal_s : std_logic; - signal res_n_s : std_logic; - signal int_n_s : std_logic; - signal ale_s : std_logic; - signal psen_n_s : std_logic; - signal prog_n_s : std_logic; - - signal t0_b : std_logic; - - signal p1_b : std_logic_vector( 7 downto 0); - signal p2_b : std_logic_vector( 7 downto 0); - - signal db_b : std_logic_vector( 7 downto 0); - signal ext_mem_addr_s : std_logic_vector(11 downto 0); - signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); - signal ext_ram_we_s : std_logic; - signal ext_rom_data_s : std_logic_vector( 7 downto 0); - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - - signal zero_s : std_logic; - signal one_s : std_logic; - -begin - - zero_s <= '0'; - one_s <= '1'; - - p2_b <= (others => 'H'); - p1_b <= (others => 'H'); - - ----------------------------------------------------------------------------- - -- External ROM, 4k bytes - -- Initialized by file t3x_ext_rom.hex. - ----------------------------------------------------------------------------- - ext_rom_b : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 12, - LPM_NUMWORDS => 2 ** 12, - LPM_FILE => "rom_t3x_ext.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => ext_mem_addr_s, - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => ext_rom_data_s - ); - - ext_ram_b : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ext_mem_addr_s(7 downto 0), - we_i => ext_ram_we_s, - ena_i => one_s, - d_i => db_b, - d_o => ext_ram_data_from_s - ); - - t8039_b : t8039 - port map ( - xtal_i => xtal_s, - reset_n_i => res_n_s, - t0_b => t0_b, - int_n_i => int_n_s, - ea_i => one_s, - rd_n_o => rd_n_s, - psen_n_o => psen_n_s, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_b => db_b, - t1_i => p1_b(1), - p2_b => p2_b, - p1_b => p1_b, - prog_n_o => prog_n_s - ); - - - ----------------------------------------------------------------------------- - -- Read from external memory - -- - db_b <= ext_rom_data_s - when psen_n_s = '0' else - (others => 'Z'); - db_b <= ext_ram_data_from_s - when rd_n_s = '0' else - (others => 'Z'); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- External memory access signals - -- - ext_mem: process (wr_n_s, - ale_s, - p2_b, - db_b) - begin - ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0)); - - if ale_s'event and ale_s = '0' then - if not is_X(db_b) then - ext_mem_addr_s(7 downto 0) <= db_b; - else - ext_mem_addr_s(7 downto 0) <= (others => '0'); - end if; - end if; - - if wr_n_s'event and wr_n_s = '1' then - ext_ram_we_s <= '0'; - end if; - if wr_n_s'event and wr_n_s = '0' then - ext_ram_we_s <= '1'; - end if; - - end process ext_mem; - -- - ----------------------------------------------------------------------------- - - t0_b <= p1_b(0); - - ----------------------------------------------------------------------------- - -- The clock generator - -- - clk_gen: process - begin - xtal_s <= '0'; - wait for period_c/2; - xtal_s <= '1'; - wait for period_c/2; - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The reset generator - -- - res_gen: process - begin - res_n_s <= '0'; - wait for 5 * period_c; - res_n_s <= '1'; - wait; - end process res_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The interrupt generator - -- - int_gen: process - begin - int_n_s <= '1'; - wait for 750 * period_c; - int_n_s <= '0'; - wait for 45 * period_c; - end process int_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- End of simulation detection - -- - eos: process - begin - - outer: loop - wait on tb_accu_s; - if tb_accu_s = "10101010" then - wait on tb_accu_s; - if tb_accu_s = "01010101" then - wait on tb_accu_s; - if tb_accu_s = "00000001" then - -- wait for instruction strobe of this move - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - -- wait for next strobe - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - assert false - report "Simulation Result: PASS." - severity note; - else - assert false - report "Simulation Result: FAIL." - severity note; - end if; - - assert false - report "End of simulation reached." - severity failure; - - end if; - end if; - end loop; - - end process eos; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/tb_t8039.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/bench/vhdl/tb_t8048_t8243.vhd =================================================================== --- t48/rel_1_2/bench/vhdl/tb_t8048_t8243.vhd (revision 296) +++ t48/rel_1_2/bench/vhdl/tb_t8048_t8243.vhd (nonexistent) @@ -1,310 +0,0 @@ -------------------------------------------------------------------------------- --- --- The testbench for t8048 driving a t8243. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity tb_t8048_t8243 is - -end tb_t8048_t8243; - - -use work.t48_core_comp_pack.generic_ram_ena; -use work.t48_system_comp_pack.t8048; -use work.t8243_comp_pack.t8243; - -use work.t48_tb_pack.all; - -architecture behav of tb_t8048_t8243 is - - -- clock period, 11 MHz - constant period_c : time := 90 ns; - - component lpm_rom - generic ( - LPM_WIDTH : positive; - LPM_TYPE : string := "LPM_ROM"; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_FILE : string; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_HINT : string := "UNUSED" - ); - port ( - address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - inclock : in std_logic; - outclock : in std_logic; - memenab : in std_logic; - q : out std_logic_vector(LPM_WIDTH-1 downto 0) - ); - end component; - - signal xtal_s : std_logic; - signal res_n_s : std_logic; - signal int_n_s : std_logic; - signal ale_s : std_logic; - signal psen_n_s : std_logic; - signal prog_n_s : std_logic; - - signal p1_b : std_logic_vector( 7 downto 0); - signal p2_b : std_logic_vector( 7 downto 0); - - signal p4_b : std_logic_vector( 3 downto 0); - signal p5_b : std_logic_vector( 3 downto 0); - - signal db_b : std_logic_vector( 7 downto 0); - signal ext_mem_addr_s : std_logic_vector(11 downto 0); - signal ext_ram_data_from_s : std_logic_vector( 7 downto 0); - signal ext_ram_we_s : std_logic; - signal ext_rom_data_s : std_logic_vector( 7 downto 0); - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - - signal zero_s : std_logic; - signal one_s : std_logic; - -begin - - zero_s <= '0'; - one_s <= '1'; - - p2_b <= (others => 'H'); - p1_b <= (others => 'H'); - - ----------------------------------------------------------------------------- - -- External ROM, 3k bytes - -- Initialized by file t48_ext_rom.hex. - ----------------------------------------------------------------------------- - ext_rom_b : lpm_rom - generic map ( - LPM_WIDTH => 8, - LPM_TYPE => "LPM_ROM", - LPM_WIDTHAD => 12, - LPM_NUMWORDS => 3 * (2 ** 10), - LPM_FILE => "rom_t48_ext.hex", - LPM_ADDRESS_CONTROL => "REGISTERED", - LPM_OUTDATA => "UNREGISTERED", - LPM_HINT => "UNUSED" - ) - port map ( - address => ext_mem_addr_s, - inclock => xtal_s, - outclock => zero_s, -- unused - memenab => one_s, - q => ext_rom_data_s - ); - - ext_ram_b : generic_ram_ena - generic map ( - addr_width_g => 8, - data_width_g => 8 - ) - port map ( - clk_i => xtal_s, - a_i => ext_mem_addr_s(7 downto 0), - we_i => ext_ram_we_s, - ena_i => one_s, - d_i => db_b, - d_o => ext_ram_data_from_s - ); - - t8048_b : t8048 - port map ( - xtal_i => xtal_s, - reset_n_i => res_n_s, - t0_b => p1_b(0), - int_n_i => int_n_s, - ea_i => zero_s, - rd_n_o => rd_n_s, - psen_n_o => psen_n_s, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_b => db_b, - t1_i => p1_b(1), - p2_b => p2_b, - p1_b => p1_b, - prog_n_o => prog_n_s - ); - - t8243_b : t8243 - port map ( - cs_n_i => zero_s, - prog_n_i => prog_n_s, - p2_b => p2_b(3 downto 0), - p4_b => p4_b, - p5_b => p5_b, - p6_b => p4_b, - p7_b => p5_b - ); - - p4_b <= (others => 'H'); - p5_b <= (others => 'H'); - - - ----------------------------------------------------------------------------- - -- Read from external memory - -- - db_b <= ext_rom_data_s - when psen_n_s = '0' else - (others => 'Z'); - db_b <= ext_ram_data_from_s - when rd_n_s = '0' else - (others => 'Z'); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- External RAM access signals - -- - ext_ram: process (wr_n_s, - ale_s, - p2_b, - db_b) - begin - -- lowest 1k of external ROM is not used - ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0)); - - if ale_s'event and ale_s = '0' then - if not is_X(db_b) then - ext_mem_addr_s(7 downto 0) <= db_b; - else - ext_mem_addr_s(7 downto 0) <= (others => '0'); - end if; - end if; - - if wr_n_s'event and wr_n_s = '1' then - ext_ram_we_s <= '0'; - end if; - if wr_n_s'event and wr_n_s = '0' then - ext_ram_we_s <= '1'; - end if; - - end process ext_ram; - -- - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- The clock generator - -- - clk_gen: process - begin - xtal_s <= '0'; - wait for period_c/2; - xtal_s <= '1'; - wait for period_c/2; - end process clk_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The reset generator - -- - res_gen: process - begin - res_n_s <= '0'; - wait for 5 * period_c; - res_n_s <= '1'; - wait; - end process res_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- The interrupt generator - -- - int_gen: process - begin - int_n_s <= '1'; - wait for 750 * period_c; - int_n_s <= '0'; - wait for 45 * period_c; - end process int_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- End of simulation detection - -- - eos: process - begin - - outer: loop - wait on tb_accu_s; - if tb_accu_s = "10101010" then - wait on tb_accu_s; - if tb_accu_s = "01010101" then - wait on tb_accu_s; - if tb_accu_s = "00000001" then - -- wait for instruction strobe of this move - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - -- wait for next strobe - wait until tb_istrobe_s'event and tb_istrobe_s = '1'; - assert false - report "Simulation Result: PASS." - severity note; - else - assert false - report "Simulation Result: FAIL." - severity note; - end if; - - assert false - report "End of simulation reached." - severity failure; - - end if; - end if; - end loop; - - end process eos; - -- - ----------------------------------------------------------------------------- - -end behav;

t48/rel_1_2/bench/vhdl/tb_t8048_t8243.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/cond_branch-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/cond_branch-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/cond_branch-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Conditional Branch Logic unit. --- Decisions whether to take a jump or not are made here. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_cond_branch_rtl_c0 of t48_cond_branch is - - for rtl - end for; - -end t48_cond_branch_rtl_c0;

t48/rel_1_2/rtl/vhdl/cond_branch-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/p1.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/p1.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/p1.vhd (nonexistent) @@ -1,151 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Port 1 unit. --- Implements the Port 1 logic. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -entity t48_p1 is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - write_p1_i : in boolean; - read_p1_i : in boolean; - read_reg_i : in boolean; - -- Port 1 Interface ------------------------------------------------------- - p1_i : in word_t; - p1_o : out word_t; - p1_low_imp_o : out std_logic - ); - -end t48_p1; - - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; - -architecture rtl of t48_p1 is - - -- the port output register - signal p1_q : word_t; - - -- the low impedance marker - signal low_imp_q : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Process p1_reg - -- - -- Purpose: - -- Implements the port output register. - -- - p1_reg: process (res_i, clk_i) - begin - if res_i = res_active_c then - p1_q <= (others => '1'); - low_imp_q <= '0'; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if write_p1_i then - p1_q <= data_i; - low_imp_q <= '1'; - else - low_imp_q <= '0'; - end if; - - end if; - - end if; - - end process p1_reg; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process p1_data - -- - -- Purpose: - -- Generates the T48 bus data. - -- - p1_data: process (read_p1_i, - p1_i, - read_reg_i, - p1_q) - begin - data_o <= (others => bus_idle_level_c); - - if read_p1_i then - if read_reg_i then - data_o <= p1_q; - else - data_o <= p1_i; - end if; - end if; - - end process p1_data; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - p1_o <= p1_q; - p1_low_imp_o <= low_imp_q; - -end rtl;

t48/rel_1_2/rtl/vhdl/p1.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/p2.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/p2.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/p2.vhd (nonexistent) @@ -1,238 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Port 2 unit. --- Implements the Port 2 logic. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_pack.nibble_t; - -entity t48_p2 is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - write_p2_i : in boolean; - write_exp_i : in boolean; - read_p2_i : in boolean; - read_reg_i : in boolean; - read_exp_i : in boolean; - -- Port 2 Interface ------------------------------------------------------- - output_pch_i : in boolean; - pch_i : in nibble_t; - p2_i : in word_t; - p2_o : out word_t; - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic - ); - -end t48_p2; - - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; - -architecture rtl of t48_p2 is - - -- the port output register - signal p2_q : word_t; - - -- the low impedance markers - signal l_low_imp_q, - h_low_imp_q : std_logic; - - signal en_clk_q : boolean; - signal l_low_imp_del_q, - h_low_imp_del_q : std_logic; - signal output_pch_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process p2_regs - -- - -- Purpose: - -- Implements the port output and expander registers. - -- - p2_regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - p2_q <= (others => '1'); - l_low_imp_q <= '0'; - h_low_imp_q <= '0'; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - -- default: reset low impedance marker - l_low_imp_q <= '0'; - h_low_imp_q <= '0'; - - if write_p2_i then - -- write whole P2 - p2_q <= data_i; - l_low_imp_q <= '1'; - h_low_imp_q <= '1'; - - elsif write_exp_i then - -- write lower nibble of P2 - p2_q(nibble_t'range) <= data_i(nibble_t'range); - l_low_imp_q <= '1'; - - end if; - - end if; - - end if; - - end process p2_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process p2_port - -- - -- Purpose: - -- Generates the output byte vector for Port 2. - -- It is a synchronous process clocked with XTAL. This ensures that - -- P2 data and low impedance markers are free of glitches and stabilize - -- during the same clock/machine state. - -- On the other hand, P2 is delayed by 1 XTAL cycle. - -- - p2_port: process (res_i, xtal_i) - begin - if res_i = res_active_c then - p2_o <= (others => '1'); - l_low_imp_del_q <= '0'; - h_low_imp_del_q <= '0'; - output_pch_q <= false; - en_clk_q <= false; - - elsif xtal_i'event and xtal_i = clk_active_c then - if xtal_en_i then - -- delay clock enable by one XTAL period - en_clk_q <= en_clk_i; - - p2_o <= p2_q; - output_pch_q <= output_pch_i; - - if output_pch_i then - p2_o(nibble_t'range) <= pch_i; - end if; - - -- generate low impedance trigger for one XTAL clock period after - -- global clock enable when - -- a) switching to or from PCH - -- b) l_low_imp_q is active - if en_clk_q and - ((output_pch_q xor output_pch_i) or - l_low_imp_q = '1') then - l_low_imp_del_q <= '1'; - else - l_low_imp_del_q <= '0'; - end if; - - -- generate low impedance trigger for on XTAL clock period after - -- global clock enable when - -- h_low_imp_q is active - if en_clk_q and - h_low_imp_q = '1' then - h_low_imp_del_q <= '1'; - else - h_low_imp_del_q <= '0'; - end if; - - end if; - end if; - end process p2_port; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process p2_data - -- - -- Purpose: - -- Generates the T48 bus data. - -- - p2_data: process (read_p2_i, - p2_i, - read_reg_i, - p2_q, - read_exp_i) - begin - data_o <= (others => bus_idle_level_c); - - if read_p2_i then - if read_reg_i then - data_o <= p2_q; - elsif read_exp_i then - data_o <= "0000" & p2_i(nibble_t'range); - else - data_o <= p2_i; - end if; - end if; - - end process p2_data; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - p2l_low_imp_o <= l_low_imp_del_q; - p2h_low_imp_o <= h_low_imp_del_q; - -end rtl;

t48/rel_1_2/rtl/vhdl/p2.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/alu.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/alu.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/alu.vhd (nonexistent) @@ -1,415 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Arithmetic Logic Unit (ALU). --- It contains the ALU core plus the Accumulator and the Temp Reg. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_alu_pack.alu_op_t; - -entity t48_alu is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - write_accu_i : in boolean; - write_shadow_i : in boolean; - write_temp_reg_i : in boolean; - read_alu_i : in boolean; - -- Decoder Interface ------------------------------------------------------ - carry_i : in std_logic; - carry_o : out std_logic; - aux_carry_o : out std_logic; - alu_op_i : in alu_op_t; - use_carry_i : in boolean; - da_high_i : in boolean; - da_overflow_o : out boolean; - accu_low_i : in boolean; - p06_temp_reg_i : in boolean; - p60_temp_reg_i : in boolean - ); - -end t48_alu; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.nibble_t; -use work.t48_alu_pack.all; - --- pragma translate_off -use work.t48_tb_pack.tb_accu_s; --- pragma translate_on - -architecture rtl of t48_alu is - - -- the Accumulator and Temp Reg - signal accumulator_q, - accu_shadow_q, - temp_req_q : word_t; - -- inputs to the ALU core - signal in_a_s, - in_b_s : word_t; - -- output of the ALU core - signal data_s : word_t; - - signal add_result_s : alu_operand_t; - -begin - - ----------------------------------------------------------------------------- - -- Process working_regs - -- - -- Purpose: - -- Implements the working registers: - -- + Accumulator - -- + Temp Reg - -- - working_regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - accumulator_q <= (others => '0'); - accu_shadow_q <= (others => '0'); - temp_req_q <= (others => '0'); - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if write_accu_i then - if accu_low_i then - accumulator_q(nibble_t'range) <= data_i(nibble_t'range); - else - accumulator_q <= data_i; - end if; - end if; - - if write_shadow_i then - -- write shadow directly from t48 data bus - accu_shadow_q <= data_i; - else - -- default: update shadow Accumulator from real Accumulator - accu_shadow_q <= accumulator_q; - end if; - - if p06_temp_reg_i then - -- low nibble of DA sequence - temp_req_q <= "00000110"; - elsif p60_temp_reg_i then - -- high nibble of DA sequence - temp_req_q <= "01100000"; - elsif write_temp_reg_i then - -- normal load from T48 bus - temp_req_q <= data_i; - end if; - - end if; - - end if; - - end process working_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Build the inputs to the ALU core. - -- Input A: - -- Unary operators use only Input A. - -- Is always fed from the shadow Accumulator. - -- Assumption: It never happens that the Accumulator is written and then - -- read for an ALU operation in the next cycle. - -- Its contents can thus be staged through the shadow Accu. - -- Input B: - -- Is always fed from the Temp Reg. - ----------------------------------------------------------------------------- - in_a_s <= accu_shadow_q; - in_b_s <= temp_req_q; - - - ----------------------------------------------------------------------------- - -- Process alu_core - -- - -- Purpose: - -- Implements the ALU core. - -- All operations defined in alu_op_t are handled here. - -- - alu_core: process (in_a_s, - in_b_s, - alu_op_i, - carry_i, - use_carry_i, - add_result_s) - - begin - -- default assigments - data_s <= (others => '0'); - carry_o <= '0'; - - case alu_op_i is - -- Operation: AND ------------------------------------------------------- - when ALU_AND => - data_s <= in_a_s and in_b_s; - - -- Operation: OR -------------------------------------------------------- - when ALU_OR => - data_s <= in_a_s or in_b_s; - - -- Operation: XOR ------------------------------------------------------- - when ALU_XOR => - data_s <= in_a_s xor in_b_s; - - -- Operation: Add ------------------------------------------------------- - when ALU_ADD => - data_s <= add_result_s(data_s'range); - carry_o <= add_result_s(add_result_s'high); - - -- Operation: CPL ------------------------------------------------------- - when ALU_CPL => - data_s <= not in_a_s; - - -- Operation: CLR ------------------------------------------------------- - when ALU_CLR => - data_s <= (others => '0'); - - -- Operation: RL -------------------------------------------------------- - when ALU_RL => - data_s(7 downto 1) <= in_a_s(6 downto 0); - carry_o <= in_a_s(7); - - if use_carry_i then - data_s(0) <= carry_i; - else - data_s(0) <= in_a_s(7); - end if; - - -- Operation: RR -------------------------------------------------------- - when ALU_RR => - data_s(6 downto 0) <= in_a_s(7 downto 1); - carry_o <= in_a_s(0); - - if use_carry_i then - data_s(7) <= carry_i; - else - data_s(7) <= in_a_s(0); - end if; - - -- Operation: Swap ------------------------------------------------------ - when ALU_SWAP => - data_s(3 downto 0) <= in_a_s(7 downto 4); - data_s(7 downto 4) <= in_a_s(3 downto 0); - - -- Operation: DEC ------------------------------------------------------- - when ALU_DEC => - data_s <= add_result_s(data_s'range); - - -- Operation: INC ------------------------------------------------------- - when ALU_INC => - data_s <= add_result_s(data_s'range); - - -- Operation CONCAT ----------------------------------------------------- - when ALU_CONCAT => - data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0); - - -- Operation: NOP ------------------------------------------------------- - when ALU_NOP => - data_s <= in_a_s; - - when others => - -- pragma translate_off - assert false - report "Unknown ALU operation selected!" - severity error; - -- pragma translate_on - - end case; - - end process alu_core; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process adder - -- - -- Purpose: - -- Implements the adder used by several instructions. - -- This way of modelling the adder forces resource sharing of: - -- * ADD - -- * INC - -- * DEC - -- - adder: process (in_a_s, - in_b_s, - alu_op_i, - carry_i, - use_carry_i) - - variable add_a_v, add_b_v : alu_operand_t; - variable c_v : alu_operand_t; - variable result_v : UNSIGNED(alu_operand_t'range); - variable aux_c_v : std_logic_vector(1 downto 0); - - begin - -- Carry Selection -------------------------------------------------------- - c_v := (others => '0'); - if use_carry_i and carry_i = '1' then - c_v(0) := '1'; - end if; - - -- Operand Selection ------------------------------------------------------ - -- defaults for ADD - add_a_v := '0' & in_a_s; - add_b_v := '0' & in_b_s; - - case alu_op_i is - when ALU_INC => - add_b_v := (others => '0'); - add_b_v(0) := '1'; - when ALU_DEC => - add_b_v := (others => '1'); - when others => - null; - end case; - - -- The Adder -------------------------------------------------------------- - result_v := UNSIGNED(add_a_v) + - UNSIGNED(add_b_v) + - UNSIGNED(c_v); - - add_result_s <= std_logic_vector(result_v); - - -- Auxiliary Carry -------------------------------------------------------- - aux_c_v := in_a_s(4) & in_b_s(4); - - aux_carry_o <= '0'; - case aux_c_v is - when "00" | "11" => - if result_v(4) = '1' then - aux_carry_o <= '1'; - end if; - - when "01" | "10" => - if result_v(4) = '0' then - aux_carry_o <= '1'; - end if; - - when others => - null; - - end case; - - end process adder; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process da_overflow - -- - -- Purpose: - -- Detect overflow situation during DA sequence. - -- - da_overflow: process (accu_shadow_q, - da_high_i) - - variable da_nibble_v : nibble_t; - - function da_overflow_f(data : in nibble_t) return boolean is - variable overflow_v : boolean; - begin - case data is - when "1010" | - "1011" | - "1100" | - "1101" | - "1110" | - "1111" => - overflow_v := true; - when others => - overflow_v := false; - end case; - - return(overflow_v); - end; - - begin - if da_high_i then - da_nibble_v := accu_shadow_q(7 downto 4); - else - da_nibble_v := accu_shadow_q(3 downto 0); - end if; - - da_overflow_o <= da_overflow_f(da_nibble_v); - - end process da_overflow; - -- - ----------------------------------------------------------------------------- - - - -- pragma translate_off - ----------------------------------------------------------------------------- - -- Testbench support. - ----------------------------------------------------------------------------- - tb_accu_s <= accumulator_q; - -- pragma translate_on - - ----------------------------------------------------------------------------- - -- Output Multiplexer. - ----------------------------------------------------------------------------- - data_o <= data_s - when read_alu_i else - (others => bus_idle_level_c); - -end rtl;

t48/rel_1_2/rtl/vhdl/alu.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/dmem_ctrl-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/dmem_ctrl-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/dmem_ctrl-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Data Memory control unit. --- All accesses to the Data Memory are managed here. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_dmem_ctrl_rtl_c0 of t48_dmem_ctrl is - - for rtl - end for; - -end t48_dmem_ctrl_rtl_c0;

t48/rel_1_2/rtl/vhdl/dmem_ctrl-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_comp_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_comp_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_comp_pack-p.vhd (nonexistent) @@ -1,374 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_alu_pack.alu_op_t; -use work.t48_cond_branch_pack.branch_conditions_t; -use work.t48_cond_branch_pack.comp_value_t; -use work.t48_decoder_pack.mnemonic_t; -use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; -use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; -use work.t48_pack.dmem_addr_t; -use work.t48_pack.pmem_addr_t; -use work.t48_pack.mstate_t; -use work.t48_pack.word_t; -use work.t48_pack.nibble_t; - -package t48_comp_pack is - - component t48_alu - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - data_o : out word_t; - write_accu_i : in boolean; - write_shadow_i : in boolean; - write_temp_reg_i : in boolean; - read_alu_i : in boolean; - carry_i : in std_logic; - carry_o : out std_logic; - aux_carry_o : out std_logic; - alu_op_i : in alu_op_t; - use_carry_i : in boolean; - da_high_i : in boolean; - da_overflow_o : out boolean; - accu_low_i : in boolean; - p06_temp_reg_i : in boolean; - p60_temp_reg_i : in boolean - ); - end component; - - component t48_bus_mux - port ( - alu_data_i : in word_t; - bus_data_i : in word_t; - dec_data_i : in word_t; - dm_data_i : in word_t; - pm_data_i : in word_t; - p1_data_i : in word_t; - p2_data_i : in word_t; - psw_data_i : in word_t; - tim_data_i : in word_t; - data_o : out word_t - ); - end component; - - component t48_clock_ctrl - generic ( - xtal_div_3_g : integer := 1 - ); - port ( - clk_i : in std_logic; - xtal_i : in std_logic; - xtal_en_i : in boolean; - res_i : in std_logic; - en_clk_i : in boolean; - xtal3_o : out boolean; - t0_o : out std_logic; - multi_cycle_i : in boolean; - assert_psen_i : in boolean; - assert_prog_i : in boolean; - assert_rd_i : in boolean; - assert_wr_i : in boolean; - mstate_o : out mstate_t; - second_cycle_o : out boolean; - ale_o : out boolean; - psen_o : out boolean; - prog_o : out boolean; - rd_o : out boolean; - wr_o : out boolean - ); - end component; - - component t48_cond_branch - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - compute_take_i : in boolean; - branch_cond_i : in branch_conditions_t; - take_branch_o : out boolean; - accu_i : in word_t; - t0_i : in std_logic; - t1_i : in std_logic; - int_n_i : in std_logic; - f0_i : in std_logic; - f1_i : in std_logic; - tf_i : in std_logic; - carry_i : in std_logic; - comp_value_i : in comp_value_t - ); - end component; - - component t48_db_bus - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - ea_i : in std_logic; - data_i : in word_t; - data_o : out word_t; - write_bus_i : in boolean; - read_bus_i : in boolean; - output_pcl_i : in boolean; - bidir_bus_i : in boolean; - pcl_i : in word_t; - db_i : in word_t; - db_o : out word_t; - db_dir_o : out std_logic - ); - end component; - - component t48_decoder - generic ( - register_mnemonic_g : integer := 1 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - ea_i : in std_logic; - ale_i : in boolean; - int_n_i : in std_logic; - t0_dir_o : out std_logic; - data_i : in word_t; - data_o : out word_t; - alu_write_accu_o : out boolean; - alu_write_shadow_o : out boolean; - alu_write_temp_reg_o : out boolean; - alu_read_alu_o : out boolean; - bus_write_bus_o : out boolean; - bus_read_bus_o : out boolean; - dm_write_dmem_addr_o : out boolean; - dm_write_dmem_o : out boolean; - dm_read_dmem_o : out boolean; - p1_write_p1_o : out boolean; - p1_read_p1_o : out boolean; - p2_write_p2_o : out boolean; - p2_write_exp_o : out boolean; - p2_read_p2_o : out boolean; - pm_write_pcl_o : out boolean; - pm_read_pcl_o : out boolean; - pm_write_pch_o : out boolean; - pm_read_pch_o : out boolean; - pm_read_pmem_o : out boolean; - psw_read_psw_o : out boolean; - psw_read_sp_o : out boolean; - psw_write_psw_o : out boolean; - psw_write_sp_o : out boolean; - alu_carry_i : in std_logic; - alu_op_o : out alu_op_t; - alu_da_high_o : out boolean; - alu_accu_low_o : out boolean; - alu_da_overflow_i : in boolean; - alu_p06_temp_reg_o : out boolean; - alu_p60_temp_reg_o : out boolean; - alu_use_carry_o : out boolean; - bus_output_pcl_o : out boolean; - bus_bidir_bus_o : out boolean; - clk_multi_cycle_o : out boolean; - clk_assert_psen_o : out boolean; - clk_assert_prog_o : out boolean; - clk_assert_rd_o : out boolean; - clk_assert_wr_o : out boolean; - clk_mstate_i : in mstate_t; - clk_second_cycle_i : in boolean; - cnd_compute_take_o : out boolean; - cnd_branch_cond_o : out branch_conditions_t; - cnd_take_branch_i : in boolean; - cnd_comp_value_o : out comp_value_t; - cnd_f1_o : out std_logic; - cnd_tf_o : out std_logic; - dm_addr_type_o : out dmem_addr_ident_t; - tim_read_timer_o : out boolean; - tim_write_timer_o : out boolean; - tim_start_t_o : out boolean; - tim_start_cnt_o : out boolean; - tim_stop_tcnt_o : out boolean; - p1_read_reg_o : out boolean; - p2_read_reg_o : out boolean; - p2_read_exp_o : out boolean; - p2_output_pch_o : out boolean; - pm_inc_pc_o : out boolean; - pm_write_pmem_addr_o : out boolean; - pm_addr_type_o : out pmem_addr_ident_t; - psw_special_data_o : out std_logic; - psw_carry_i : in std_logic; - psw_aux_carry_i : in std_logic; - psw_f0_i : in std_logic; - psw_inc_stackp_o : out boolean; - psw_dec_stackp_o : out boolean; - psw_write_carry_o : out boolean; - psw_write_aux_carry_o : out boolean; - psw_write_f0_o : out boolean; - psw_write_bs_o : out boolean; - tim_overflow_i : in boolean - ); - end component; - - component t48_dmem_ctrl - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - write_dmem_addr_i : in boolean; - write_dmem_i : in boolean; - read_dmem_i : in boolean; - addr_type_i : in dmem_addr_ident_t; - bank_select_i : in std_logic; - data_o : out word_t; - dmem_data_i : in word_t; - dmem_addr_o : out dmem_addr_t; - dmem_we_o : out std_logic; - dmem_data_o : out word_t - ); - end component; - - component t48_int - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - clk_mstate_i : in mstate_t; - jtf_executed_i : in boolean; - tim_overflow_i : in boolean; - tf_o : out std_logic; - en_tcnti_i : in boolean; - dis_tcnti_i : in boolean; - int_n_i : in std_logic; - ale_i : in boolean; - last_cycle_i : in boolean; - en_i_i : in boolean; - dis_i_i : in boolean; - ext_int_o : out boolean; - tim_int_o : out boolean; - retr_executed_i : in boolean; - int_executed_i : in boolean; - int_pending_o : out boolean; - int_in_progress_o : out boolean - ); - end component; - - component t48_timer - generic ( - sample_t1_state_g : integer := 4 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - t1_i : in std_logic; - clk_mstate_i : in mstate_t; - data_i : in word_t; - data_o : out word_t; - read_timer_i : in boolean; - write_timer_i : in boolean; - start_t_i : in boolean; - start_cnt_i : in boolean; - stop_tcnt_i : in boolean; - overflow_o : out std_logic - ); - end component; - - component t48_p1 - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - data_o : out word_t; - write_p1_i : in boolean; - read_p1_i : in boolean; - read_reg_i : in boolean; - p1_i : in word_t; - p1_o : out word_t; - p1_low_imp_o : out std_logic - ); - end component; - - component t48_p2 - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - data_i : in word_t; - data_o : out word_t; - write_p2_i : in boolean; - write_exp_i : in boolean; - read_p2_i : in boolean; - read_reg_i : in boolean; - read_exp_i : in boolean; - output_pch_i : in boolean; - pch_i : in nibble_t; - p2_i : in word_t; - p2_o : out word_t; - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic - ); - end component; - - component t48_pmem_ctrl - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - data_o : out word_t; - write_pcl_i : in boolean; - read_pcl_i : in boolean; - write_pch_i : in boolean; - read_pch_i : in boolean; - inc_pc_i : in boolean; - write_pmem_addr_i : in boolean; - addr_type_i : in pmem_addr_ident_t; - read_pmem_i : in boolean; - pmem_addr_o : out pmem_addr_t; - pmem_data_i : in word_t - ); - end component; - - component t48_psw - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - data_o : out word_t; - read_psw_i : in boolean; - read_sp_i : in boolean; - write_psw_i : in boolean; - write_sp_i : in boolean; - special_data_i : in std_logic; - inc_stackp_i : in boolean; - dec_stackp_i : in boolean; - write_carry_i : in boolean; - write_aux_carry_i : in boolean; - write_f0_i : in boolean; - write_bs_i : in boolean; - carry_o : out std_logic; - aux_carry_i : in std_logic; - aux_carry_o : out std_logic; - f0_o : out std_logic; - bs_o : out std_logic - ); - end component; - -end t48_comp_pack;

t48/rel_1_2/rtl/vhdl/t48_comp_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/int.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/int.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/int.vhd (nonexistent) @@ -1,253 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Interrupt Controller. --- It collects the interrupt sources and notifies the decoder. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.mstate_t; - -entity t48_int is - - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - clk_mstate_i : in mstate_t; - jtf_executed_i : in boolean; - tim_overflow_i : in boolean; - tf_o : out std_logic; - en_tcnti_i : in boolean; - dis_tcnti_i : in boolean; - int_n_i : in std_logic; - ale_i : in boolean; - last_cycle_i : in boolean; - en_i_i : in boolean; - dis_i_i : in boolean; - ext_int_o : out boolean; - tim_int_o : out boolean; - retr_executed_i : in boolean; - int_executed_i : in boolean; - int_pending_o : out boolean; - int_in_progress_o : out boolean - ); - -end t48_int; - - -use work.t48_pack.all; - -architecture rtl of t48_int is - - constant tim_int_c : std_logic := '0'; - constant ext_int_c : std_logic := '1'; - - type int_state_t is (IDLE, PENDING, INT); - - signal int_state_s, - int_state_q : int_state_t; - - signal timer_flag_q : boolean; - signal timer_overflow_q : boolean; - signal timer_int_enable_q : boolean; - signal int_q : boolean; - signal int_enable_q : boolean; - signal ale_q : boolean; - signal int_type_q : std_logic; - signal int_in_progress_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process nstate - -- - -- Purpose: - -- Determines the next state of the Interrupt controller FSM. - -- - nstate: process (int_state_q, - int_type_q, - int_in_progress_q, - int_executed_i, - retr_executed_i, - clk_mstate_i, - last_cycle_i) - begin - int_state_s <= int_state_q; - - case int_state_q is - when IDLE => - if int_in_progress_q and - last_cycle_i and clk_mstate_i = MSTATE5 then - int_state_s <= PENDING; - end if; - - when PENDING => - if int_executed_i then - int_state_s <= INT; - end if; - - when INT => - if retr_executed_i then - int_state_s <= IDLE; - end if; - - when others => - int_state_s <= IDLE; - - end case; - - end process nstate; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process regs - -- - -- Purpose: - -- Implement the various registers. - -- They are designed according Figure "Interrupt Logic" of - -- "The Single Component MCS-48 System". - -- - regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - timer_flag_q <= false; - timer_overflow_q <= false; - timer_int_enable_q <= false; - int_enable_q <= false; - int_type_q <= '0'; - int_state_q <= IDLE; - int_in_progress_q <= false; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - int_state_q <= int_state_s; - - if jtf_executed_i then - timer_flag_q <= false; - elsif tim_overflow_i then - timer_flag_q <= true; - end if; - - if (int_type_q = tim_int_c and int_executed_i) or - not timer_int_enable_q then - timer_overflow_q <= false; - elsif tim_overflow_i then - timer_overflow_q <= true; - end if; - - if dis_tcnti_i then - timer_int_enable_q <= false; - elsif en_tcnti_i then - timer_int_enable_q <= true; - end if; - - if dis_i_i then - int_enable_q <= false; - elsif en_i_i then - int_enable_q <= true; - end if; - - if retr_executed_i then - int_in_progress_q <= false; - elsif (int_q and int_enable_q) or - timer_overflow_q then - int_in_progress_q <= true; - if not int_in_progress_q then - int_type_q <= to_stdLogic(int_q and int_enable_q); - end if; - end if; - - end if; - - end if; - - end process regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process xtal_regs - -- - -- Purpose: - -- Implements the sequential registers clocked with XTAL. - -- - xtal_regs: process (res_i, xtal_i) - begin - if res_i = res_active_c then - int_q <= false; - ale_q <= false; - - elsif xtal_i'event and xtal_i = clk_active_c then - if xtal_en_i then - ale_q <= ale_i; - - if last_cycle_i and - ale_q and not ale_i then - int_q <= not to_boolean(int_n_i); - end if; - - end if; - end if; - end process xtal_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - tf_o <= to_stdLogic(timer_flag_q); - ext_int_o <= int_type_q = ext_int_c; - tim_int_o <= int_type_q = tim_int_c; - int_pending_o <= int_state_q = PENDING; - int_in_progress_o <= int_in_progress_q and int_state_q /= IDLE; - -end rtl;

t48/rel_1_2/rtl/vhdl/int.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/db_bus.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/db_bus.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/db_bus.vhd (nonexistent) @@ -1,146 +0,0 @@ -------------------------------------------------------------------------------- --- --- The BUS unit. --- Implements the BUS port logic. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -entity t48_db_bus is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - ea_i : in std_logic; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - write_bus_i : in boolean; - read_bus_i : in boolean; - -- BUS Interface ---------------------------------------------------------- - output_pcl_i : in boolean; - bidir_bus_i : in boolean; - pcl_i : in word_t; - db_i : in word_t; - db_o : out word_t; - db_dir_o : out std_logic - ); - -end t48_db_bus; - - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.to_stdLogic; - -architecture rtl of t48_db_bus is - - -- the BUS output register - signal bus_q : word_t; - - -- BUS direction marker - signal db_dir_q, - db_dir_qq : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Process bus_regs - -- - -- Purpose: - -- Implements the BUS output register. - -- - bus_regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - bus_q <= (others => '0'); - db_dir_q <= '0'; - db_dir_qq <= '0'; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - if write_bus_i then - db_dir_qq <= '1'; - else - -- extend bus direction by one machine cycle - db_dir_qq <= db_dir_q; - end if; - - if write_bus_i then - bus_q <= data_i; - - db_dir_q <= '1'; - - elsif ea_i = '1' or bidir_bus_i then - db_dir_q <= '0'; - - end if; - - end if; - - end if; - - end process bus_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - db_o <= pcl_i - when output_pcl_i else - bus_q; - db_dir_o <= db_dir_qq or - to_stdLogic(output_pcl_i); - data_o <= (others => bus_idle_level_c) - when not read_bus_i else - db_i; - -end rtl;

t48/rel_1_2/rtl/vhdl/db_bus.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_tb_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_tb_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_tb_pack-p.vhd (nonexistent) @@ -1,22 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t48_tb_pack is - - -- Instruction strobe visibility - signal tb_istrobe_s : std_logic; - - -- Accumulator visibilty - signal tb_accu_s : std_logic_vector(7 downto 0); - -end t48_tb_pack;

t48/rel_1_2/rtl/vhdl/t48_tb_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/timer-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/timer-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/timer-c.vhd (nonexistent) @@ -1,16 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Timer/Counter unit. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_timer_rtl_c0 of t48_timer is - - for rtl - end for; - -end t48_timer_rtl_c0;

t48/rel_1_2/rtl/vhdl/timer-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/cond_branch.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/cond_branch.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/cond_branch.vhd (nonexistent) @@ -1,201 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Conditional Branch Logic unit. --- Decisions whether to take a jump or not are made here. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -use work.t48_cond_branch_pack.all; - -entity t48_cond_branch is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- Decoder Interface ------------------------------------------------------ - compute_take_i : in boolean; - branch_cond_i : in branch_conditions_t; - take_branch_o : out boolean; - accu_i : in word_t; - t0_i : in std_logic; - t1_i : in std_logic; - int_n_i : in std_logic; - f0_i : in std_logic; - f1_i : in std_logic; - tf_i : in std_logic; - carry_i : in std_logic; - comp_value_i : in comp_value_t - ); - -end t48_cond_branch; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pack.res_active_c; -use work.t48_pack.clk_active_c; - -architecture rtl of t48_cond_branch is - - -- marker for branch taken - signal take_branch_s, - take_branch_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process decide_take - -- - -- Purpose: - -- Decides whether a branch has to be taken or not. - -- - decide_take: process (accu_i, - branch_cond_i, - t0_i, t1_i, - int_n_i, - f0_i, f1_i, - tf_i, - carry_i, - comp_value_i) - variable or_v : std_logic; - begin - -- default assignment - take_branch_s <= false; - or_v := '0'; - - case branch_cond_i is - -- Branch On: Accumulator Bit ------------------------------------------- - when COND_ON_BIT => - if accu_i(TO_INTEGER(UNSIGNED(comp_value_i))) = '1' then - take_branch_s <= true; - end if; - - -- Branch On: Accumulator Zero ------------------------------------------ - when COND_Z => - for i in accu_i'range loop - or_v := or_v or accu_i(i); - end loop; - take_branch_s <= or_v = not comp_value_i(0); - - -- Branch On: Carry ----------------------------------------------------- - when COND_C => - take_branch_s <= carry_i = comp_value_i(0); - - -- Branch On: Flag 0 ---------------------------------------------------- - when COND_F0 => - take_branch_s <= f0_i = '1'; - - -- Branch On: Flag 1 ---------------------------------------------------- - when COND_F1 => - take_branch_s <= f1_i = '1'; - - -- Branch On: Interrupt ------------------------------------------------- - when COND_INT => - take_branch_s <= int_n_i = '0'; - - -- Branch On: Test 0 ---------------------------------------------------- - when COND_T0 => - take_branch_s <= t0_i = comp_value_i(0); - - -- Branch On: Test 1 ---------------------------------------------------- - when COND_T1 => - take_branch_s <= t1_i = comp_value_i(0); - - -- Branch On: Timer Flag ------------------------------------------------ - when COND_TF => - take_branch_s <= tf_i = '1'; - - when others => - -- pragma translate_off - assert false - report "Unknown branch condition specified!" - severity error; - -- pragma translate_on - - end case; - - end process decide_take; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process reg - -- - -- Purpose: - -- Implement the marker register. - -- - reg: process (res_i, clk_i) - begin - if res_i = res_active_c then - take_branch_q <= false; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if compute_take_i then - take_branch_q <= take_branch_s; - end if; - - end if; - - end if; - - end process reg; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - take_branch_o <= take_branch_q; - -end rtl;

t48/rel_1_2/rtl/vhdl/cond_branch.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_core_comp_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_core_comp_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_core_comp_pack-p.vhd (nonexistent) @@ -1,95 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t48_core_comp_pack is - - component t48_core - generic ( - xtal_div_3_g : integer := 1; - register_mnemonic_g : integer := 1; - include_port1_g : integer := 1; - include_port2_g : integer := 1; - include_bus_g : integer := 1; - include_timer_g : integer := 1; - sample_t1_state_g : integer := 4 - ); - - port ( - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic; - clk_i : in std_logic; - en_clk_i : in std_logic; - xtal3_o : out std_logic; - dmem_addr_o : out std_logic_vector( 7 downto 0); - dmem_we_o : out std_logic; - dmem_data_i : in std_logic_vector( 7 downto 0); - dmem_data_o : out std_logic_vector( 7 downto 0); - pmem_addr_o : out std_logic_vector(11 downto 0); - pmem_data_i : in std_logic_vector( 7 downto 0) - ); - end component; - - component generic_ram_ena - generic ( - addr_width_g : integer := 10; - data_width_g : integer := 8 - ); - port ( - clk_i : in std_logic; - a_i : in std_logic_vector(addr_width_g-1 downto 0); - we_i : in std_logic; - ena_i : in std_logic; - d_i : in std_logic_vector(data_width_g-1 downto 0); - d_o : out std_logic_vector(data_width_g-1 downto 0) - ); - end component; - - component t48_rom - port ( - clk_i : in std_logic; - rom_addr_i : in std_logic_vector(9 downto 0); - rom_data_o : out std_logic_vector(7 downto 0) - ); - end component; - - component t49_rom - port ( - clk_i : in std_logic; - rom_addr_i : in std_logic_vector(10 downto 0); - rom_data_o : out std_logic_vector( 7 downto 0) - ); - end component; - -end t48_core_comp_pack;

t48/rel_1_2/rtl/vhdl/t48_core_comp_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/pmem_ctrl-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/pmem_ctrl-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/pmem_ctrl-c.vhd (nonexistent) @@ -1,17 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Program Memory control unit. --- All operations related to the Program Memory are managed here. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_pmem_ctrl_rtl_c0 of t48_pmem_ctrl is - - for rtl - end for; - -end t48_pmem_ctrl_rtl_c0;

t48/rel_1_2/rtl/vhdl/pmem_ctrl-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/bus_mux-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/bus_mux-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/bus_mux-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T48 Bus Connector. --- Multiplexes all drivers of the T48 bus. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_bus_mux_rtl_c0 of t48_bus_mux is - - for rtl - end for; - -end t48_bus_mux_rtl_c0;

t48/rel_1_2/rtl/vhdl/bus_mux-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8243 Core --- --- $Id$ --- -------------------------------------------------------------------------------- - -configuration t8243_struct_c0 of t8243 is - - for struct - - for t8243_async_notri_b: t8243_async_notri - use configuration work.t8243_async_notri_struct_c0; - end for; - - end for; - -end t8243_struct_c0;

t48/rel_1_2/rtl/vhdl/t8243/t8243-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243.vhd (nonexistent) @@ -1,137 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T8243 asynchronous toplevel --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8243 is - - port ( - -- Control Interface ------------------------------------------------------ - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ------------------------------------------------------- - p2_b : inout std_logic_vector(3 downto 0); - -- Port 4 Interface ------------------------------------------------------- - p4_b : inout std_logic_vector(3 downto 0); - -- Port 5 Interface ------------------------------------------------------- - p5_b : inout std_logic_vector(3 downto 0); - -- Port 6 Interface ------------------------------------------------------- - p6_b : inout std_logic_vector(3 downto 0); - -- Port 7 Interface ------------------------------------------------------- - p7_b : inout std_logic_vector(3 downto 0) - ); - -end t8243; - - -use work.t8243_comp_pack.t8243_async_notri; - -architecture struct of t8243 is - - signal p2_s, - p4_s, - p5_s, - p6_s, - p7_s : std_logic_vector(3 downto 0); - signal p2_en_s, - p4_en_s, - p5_en_s, - p6_en_s, - p7_en_s : std_logic; - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - - ----------------------------------------------------------------------------- - -- The asynchronous T8243 - ----------------------------------------------------------------------------- - t8243_async_notri_b : t8243_async_notri - port map ( - reset_n_i => vdd_s, -- or generate power-on reset - cs_n_i => cs_n_i, - prog_n_i => prog_n_i, - p2_i => p2_b, - p2_o => p2_s, - p2_en_o => p2_en_s, - p4_i => p4_b, - p4_o => p4_s, - p4_en_o => p4_en_s, - p5_i => p5_b, - p5_o => p5_s, - p5_en_o => p5_en_s, - p6_i => p6_b, - p6_o => p6_s, - p6_en_o => p6_en_s, - p7_i => p7_b, - p7_o => p7_s, - p7_en_o => p7_en_s - ); - - - ----------------------------------------------------------------------------- - -- Bidirectional pad structures - ----------------------------------------------------------------------------- - p2_b <= p2_s - when p2_en_s = '1' else - (others => 'Z'); - p4_b <= p4_s - when p4_en_s = '1' else - (others => 'Z'); - p5_b <= p5_s - when p5_en_s = '1' else - (others => 'Z'); - p6_b <= p6_s - when p6_en_s = '1' else - (others => 'Z'); - p7_b <= p7_s - when p7_en_s = '1' else - (others => 'Z'); - -end struct;

t48/rel_1_2/rtl/vhdl/t8243/t8243.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri.vhd (nonexistent) @@ -1,153 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T8243 synchronous toplevel without tri-state signals --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8243_sync_notri is - - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - clk_en_i : in std_logic; - reset_n_i : in std_logic; - -- Control Interface ------------------------------------------------------ - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ------------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ------------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ------------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ------------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ------------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - -end t8243_sync_notri; - - -use work.t8243_comp_pack.t8243_core; - -architecture struct of t8243_sync_notri is - - signal prog_n_q : std_logic; - signal clk_rise_en_s, - clk_fall_en_s : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Process edge_detect - -- - -- Purpose: - -- Implements the sequential element required for edge detection - -- on the PROG input. - -- - edge_detect: process (clk_i, reset_n_i) - begin - if reset_n_i = '0' then - prog_n_q <= '1'; - elsif rising_edge(clk_i) then - if clk_en_i = '1' then - prog_n_q <= prog_n_i; - end if; - end if; - end process edge_detect; - -- - ----------------------------------------------------------------------------- - - - -- clock enables to detect rising and falling edges of PROG - clk_rise_en_s <= clk_en_i and - not prog_n_q and prog_n_i; - clk_fall_en_s <= clk_en_i and - prog_n_q and not prog_n_i; - - - ----------------------------------------------------------------------------- - -- The T8243 Core - ----------------------------------------------------------------------------- - t8243_core_b : t8243_core - generic map ( - clk_fall_level_g => 1 - ) - port map ( - clk_i => clk_i, - clk_rise_en_i => clk_rise_en_s, - clk_fall_en_i => clk_fall_en_s, - reset_n_i => reset_n_i, - cs_n_i => cs_n_i, - prog_n_i => prog_n_i, - p2_i => p2_i, - p2_o => p2_o, - p2_en_o => p2_en_o, - p4_i => p4_i, - p4_o => p4_o, - p4_en_o => p4_en_o, - p5_i => p5_i, - p5_o => p5_o, - p5_en_o => p5_en_o, - p6_i => p6_i, - p6_o => p6_o, - p6_en_o => p6_en_o, - p7_i => p7_i, - p7_o => p7_o, - p7_en_o => p7_en_o - ); - -end struct;

t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8243 Core --- --- $Id$ --- -------------------------------------------------------------------------------- - -configuration t8243_sync_notri_struct_c0 of t8243_sync_notri is - - for struct - - for t8243_core_b: t8243_core - use configuration work.t8243_core_rtl_c0; - end for; - - end for; - -end t8243_sync_notri_struct_c0;

t48/rel_1_2/rtl/vhdl/t8243/t8243_sync_notri-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_core.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_core.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_core.vhd (nonexistent) @@ -1,291 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T8243 Core --- This is the core module implementing all functionality of the --- original 8243 chip. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee. std_logic_1164.all; - -entity t8243_core is - - generic ( - clk_fall_level_g : integer := 0 - ); - port ( - -- System Interface ------------------------------------------------------- - clk_i : in std_logic; - clk_rise_en_i : in std_logic; - clk_fall_en_i : in std_logic; - reset_n_i : in std_logic; - -- Control Interface ------------------------------------------------------ - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ------------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ------------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ------------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ------------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ------------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - -end t8243_core; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of t8243_core is - - function int2stdlogic_f(level_i : in integer) return std_logic is - begin - if level_i = 0 then - return '0'; - else - return '1'; - end if; - end; - - constant clk_fall_level_c : std_logic := int2stdlogic_f(clk_fall_level_g); - - type instr_t is (INSTR_READ, INSTR_WRITE, INSTR_ORLD, INSTR_ANLD); - signal instr_q : instr_t; - - constant port_4_c : integer := 4; - constant port_5_c : integer := 5; - constant port_6_c : integer := 6; - constant port_7_c : integer := 7; - - subtype port_range_t is natural range port_7_c downto port_4_c; - signal px_sel_q : std_logic_vector(port_range_t); - - signal px_en_q : std_logic_vector(port_range_t); - signal p2_en_q : std_logic; - - subtype port_vector_t is std_logic_vector(3 downto 0); - type four_ports_t is array (port_range_t) of port_vector_t; - signal px_latch_q : four_ports_t; - - signal data_s : port_vector_t; - - signal p2_s, - p4_s, - p5_s, - p6_s, - p7_s : port_vector_t; - -begin - - -- get rid of H and L - p2_s <= to_X01(p2_i); - p4_s <= to_X01(p4_i); - p5_s <= to_X01(p5_i); - p6_s <= to_X01(p6_i); - p7_s <= to_X01(p7_i); - - ----------------------------------------------------------------------------- - -- Process ctrl_seq - -- - -- Purpose: - -- Implements the sequential elements that control the T8243 core. - -- * latch port number - -- * latch instruction - -- - ctrl_seq: process (clk_i, cs_n_i) - begin - if cs_n_i = '1' then - px_sel_q <= (others => '0'); - p2_en_q <= '0'; - instr_q <= INSTR_WRITE; - - elsif clk_i'event and clk_i = clk_fall_level_c then - if cs_n_i = '0' and clk_fall_en_i = '1' then - -- enable addressed port ---------------------------------------------- - px_sel_q <= (others => '0'); - px_sel_q(to_integer(unsigned(p2_s(1 downto 0))) + - port_range_t'low) <= '1'; - - p2_en_q <= '0'; - - -- decode instruction ------------------------------------------------- - case p2_s(3 downto 2) is - when "00" => - instr_q <= INSTR_READ; - p2_en_q <= '1'; - when "01" => - instr_q <= INSTR_WRITE; - when "10" => - instr_q <= INSTR_ORLD; - when "11" => - instr_q <= INSTR_ANLD; - when others => - null; - end case; - - end if; - - end if; - end process ctrl_seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process port_seq - -- - -- Purpose: - -- Implements the sequential elements of the four ports. - -- - port_seq: process (clk_i, reset_n_i) - begin - if reset_n_i = '0' then - px_en_q <= (others => '0'); - px_latch_q <= (others => (others => '0')); - - elsif rising_edge(clk_i) then - if cs_n_i = '0' and clk_rise_en_i = '1' then - for idx in port_range_t loop - if px_sel_q(idx) = '1' then - if instr_q = INSTR_READ then - -- port is being read from, switch off output enable - px_en_q(idx) <= '0'; - - else - -- port is being written to, enable output - px_en_q(idx) <= '1'; - -- and latch value - px_latch_q(idx) <= data_s; - end if; - end if; - end loop; - end if; - - end if; - end process port_seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process data_gen - -- - -- Purpose: - -- Generates the data for the four port latches. - -- * determines data inputs - -- * calculates result of instruction - -- - -- Multiplexes the read value for P2. - -- - data_gen: process (px_sel_q, - instr_q, - p2_s, - px_latch_q, - p4_s, p5_s, p6_s, p7_s) - variable port_v : port_vector_t; - begin - -- select addressed port - case px_sel_q is - when "0001" => - port_v := px_latch_q(port_4_c); - p2_o <= p4_s; - when "0010" => - port_v := px_latch_q(port_5_c); - p2_o <= p5_s; - when "0100" => - port_v := px_latch_q(port_6_c); - p2_o <= p6_s; - when "1000" => - port_v := px_latch_q(port_7_c); - p2_o <= p7_s; - when others => - port_v := (others => '-'); - p2_o <= (others => '-'); - end case; - - case instr_q is - when INSTR_WRITE => - data_s <= p2_s; - when INSTR_ORLD => - data_s <= p2_s or port_v; - when INSTR_ANLD => - data_s <= p2_s and port_v; - when others => - data_s <= (others => '-'); - end case; - - end process; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - p2_en_o <= '1' - when cs_n_i = '0' and prog_n_i = '0' and p2_en_q = '1' else - '0'; - p4_o <= px_latch_q(port_4_c); - p4_en_o <= px_en_q(port_4_c); - p5_o <= px_latch_q(port_5_c); - p5_en_o <= px_en_q(port_5_c); - p6_o <= px_latch_q(port_6_c); - p6_en_o <= px_en_q(port_6_c); - p7_o <= px_latch_q(port_7_c); - p7_en_o <= px_en_q(port_7_c); - -end rtl;

t48/rel_1_2/rtl/vhdl/t8243/t8243_core.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri.vhd (nonexistent) @@ -1,124 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T8243 asynchronous toplevel without tri-state signals --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8243_async_notri is - - port ( - -- System Interface ------------------------------------------------------- - reset_n_i : in std_logic; - -- Control Interface ------------------------------------------------------ - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ------------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ------------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ------------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ------------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ------------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - -end t8243_async_notri; - - -use work.t8243_comp_pack.t8243_core; - -architecture struct of t8243_async_notri is - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - - ----------------------------------------------------------------------------- - -- The T8243 Core - ----------------------------------------------------------------------------- - t8243_core_b : t8243_core - generic map ( - clk_fall_level_g => 0 - ) - port map ( - clk_i => prog_n_i, - clk_rise_en_i => vdd_s, - clk_fall_en_i => vdd_s, - reset_n_i => reset_n_i, - cs_n_i => cs_n_i, - prog_n_i => prog_n_i, - p2_i => p2_i, - p2_o => p2_o, - p2_en_o => p2_en_o, - p4_i => p4_i, - p4_o => p4_o, - p4_en_o => p4_en_o, - p5_i => p5_i, - p5_o => p5_o, - p5_en_o => p5_en_o, - p6_i => p6_i, - p6_o => p6_o, - p6_en_o => p6_en_o, - p7_i => p7_i, - p7_o => p7_o, - p7_en_o => p7_en_o - ); - -end struct;

t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_core-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_core-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_core-c.vhd (nonexistent) @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8243 Core --- --- $Id$ --- -------------------------------------------------------------------------------- - -configuration t8243_core_rtl_c0 of t8243_core is - - for rtl - end for; - -end t8243_core_rtl_c0;

t48/rel_1_2/rtl/vhdl/t8243/t8243_core-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8243 Core --- --- $Id$ --- -------------------------------------------------------------------------------- - -configuration t8243_async_notri_struct_c0 of t8243_async_notri is - - for struct - - for t8243_core_b: t8243_core - use configuration work.t8243_core_rtl_c0; - end for; - - end for; - -end t8243_async_notri_struct_c0;

t48/rel_1_2/rtl/vhdl/t8243/t8243_async_notri-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t8243/t8243_comp_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t8243/t8243_comp_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t8243/t8243_comp_pack-p.vhd (nonexistent) @@ -1,132 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t8243_comp_pack is - - component t8243_core - generic ( - clk_fall_level_g : integer := 0 - ); - port ( - -- System Interface ----------------------------------------------------- - clk_i : in std_logic; - clk_rise_en_i : in std_logic; - clk_fall_en_i : in std_logic; - reset_n_i : in std_logic; - -- Control Interface ---------------------------------------------------- - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ----------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ----------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ----------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ----------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ----------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - end component; - - component t8243_sync_notri - port ( - -- System Interface ----------------------------------------------------- - clk_i : in std_logic; - clk_en_i : in std_logic; - reset_n_i : in std_logic; - -- Control Interface ---------------------------------------------------- - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ----------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ----------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ----------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ----------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ----------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - end component; - - component t8243_async_notri - port ( - -- System Interface ----------------------------------------------------- - reset_n_i : in std_logic; - -- Control Interface ---------------------------------------------------- - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ----------------------------------------------------- - p2_i : in std_logic_vector(3 downto 0); - p2_o : out std_logic_vector(3 downto 0); - p2_en_o : out std_logic; - -- Port 4 Interface ----------------------------------------------------- - p4_i : in std_logic_vector(3 downto 0); - p4_o : out std_logic_vector(3 downto 0); - p4_en_o : out std_logic; - -- Port 5 Interface ----------------------------------------------------- - p5_i : in std_logic_vector(3 downto 0); - p5_o : out std_logic_vector(3 downto 0); - p5_en_o : out std_logic; - -- Port 6 Interface ----------------------------------------------------- - p6_i : in std_logic_vector(3 downto 0); - p6_o : out std_logic_vector(3 downto 0); - p6_en_o : out std_logic; - -- Port 7 Interface ----------------------------------------------------- - p7_i : in std_logic_vector(3 downto 0); - p7_o : out std_logic_vector(3 downto 0); - p7_en_o : out std_logic - ); - end component; - - component t8243 - port ( - -- Control Interface ---------------------------------------------------- - cs_n_i : in std_logic; - prog_n_i : in std_logic; - -- Port 2 Interface ----------------------------------------------------- - p2_b : inout std_logic_vector(3 downto 0); - -- Port 4 Interface ----------------------------------------------------- - p4_b : inout std_logic_vector(3 downto 0); - -- Port 5 Interface ----------------------------------------------------- - p5_b : inout std_logic_vector(3 downto 0); - -- Port 6 Interface ----------------------------------------------------- - p6_b : inout std_logic_vector(3 downto 0); - -- Port 7 Interface ----------------------------------------------------- - p7_b : inout std_logic_vector(3 downto 0) - ); - end component; - -end;

t48/rel_1_2/rtl/vhdl/t8243/t8243_comp_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/dmem_ctrl.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/dmem_ctrl.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/dmem_ctrl.vhd (nonexistent) @@ -1,202 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Data Memory control unit. --- All accesses to the Data Memory are managed here. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.dmem_addr_t; -use work.t48_pack.word_t; -use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; - -entity t48_dmem_ctrl is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- Control Interface ------------------------------------------------------ - data_i : in word_t; - write_dmem_addr_i : in boolean; - write_dmem_i : in boolean; - read_dmem_i : in boolean; - addr_type_i : in dmem_addr_ident_t; - bank_select_i : in std_logic; - data_o : out word_t; - -- Data Memory Interface -------------------------------------------------- - dmem_data_i : in word_t; - dmem_addr_o : out dmem_addr_t; - dmem_we_o : out std_logic; - dmem_data_o : out word_t - ); - -end t48_dmem_ctrl; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.to_stdLogic; - -use work.t48_dmem_ctrl_pack.all; - -architecture rtl of t48_dmem_ctrl is - - signal dmem_addr_s, - dmem_addr_q : dmem_addr_t; -begin - - ----------------------------------------------------------------------------- - -- Process addr_decode - -- - -- Purpose: - -- Decode/multiplex the address information for the Data Memory. - -- - addr_decode: process (data_i, - addr_type_i, - bank_select_i, - dmem_addr_q) - variable stack_addr_v : unsigned(5 downto 0); - begin - -- default assignment - dmem_addr_s <= dmem_addr_q; - stack_addr_v := (others => '0'); - - case addr_type_i is - when DM_PLAIN => - dmem_addr_s <= data_i; - - when DM_REG => - dmem_addr_s <= (others => '0'); - dmem_addr_s(2 downto 0) <= data_i(2 downto 0); - -- implement bank switching - if bank_select_i = '1' then - -- dmem address 24 - 31: access proper set - dmem_addr_s(4 downto 3) <= "11"; - end if; - - when DM_STACK => - -- build address from stack pointer - stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0)); - -- dmem address 8 - 23 - stack_addr_v := stack_addr_v + 8; - - dmem_addr_s <= (others => '0'); - dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v); - - when DM_STACK_HIGH => - dmem_addr_s(0) <= '1'; - - when others => - -- do nothing - - -- pragma translate_off - assert false - report "Unknown address type identification for Data Memory controller!" - severity error; - -- pragma translate_on - - end case; - - end process addr_decode; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process dmem_addr_reg - -- - -- Purpose: - -- Implements the Data Memory Address Register. - -- This register is required to hold the address during a write operation - -- as we cannot hold the address in the input register of the - -- synchronous RAM (no clock suppression/gating). - -- - -- NOTE: May be obsoleted by clock enable feature of generic RTL RAM. - -- - dmem_addr_reg: process (res_i, clk_i) - begin - if res_i = res_active_c then - dmem_addr_q <= (others => '0'); - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if write_dmem_addr_i then - dmem_addr_q <= dmem_addr_s; - end if; - - end if; - - end if; - - end process dmem_addr_reg; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output mapping. - ----------------------------------------------------------------------------- - dmem_addr_o <= dmem_addr_s - when write_dmem_addr_i and en_clk_i else - dmem_addr_q; - - -- data from bus is fed through - dmem_data_o <= data_i; - - -- data to bus is enabled upon read request - data_o <= dmem_data_i - when read_dmem_i else - (others => bus_idle_level_c); - - -- write enable to Data Memory is fed through - dmem_we_o <= to_stdLogic(write_dmem_i); - -end rtl;

t48/rel_1_2/rtl/vhdl/dmem_ctrl.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_core-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_core-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_core-c.vhd (nonexistent) @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- T48 Microcontroller Core --- --- $Id$ --- -------------------------------------------------------------------------------- - -configuration t48_core_struct_c0 of t48_core is - - for struct - - for alu_b : t48_alu - use configuration work.t48_alu_rtl_c0; - end for; - - for bus_mux_b : t48_bus_mux - use configuration work.t48_bus_mux_rtl_c0; - end for; - - for clock_ctrl_b : t48_clock_ctrl - use configuration work.t48_clock_ctrl_rtl_c0; - end for; - - for cond_branch_b : t48_cond_branch - use configuration work.t48_cond_branch_rtl_c0; - end for; - - for use_db_bus - for db_bus_b : t48_db_bus - use configuration work.t48_db_bus_rtl_c0; - end for; - end for; - - for decoder_b : t48_decoder - use configuration work.t48_decoder_rtl_c0; - end for; - - for dmem_ctrl_b : t48_dmem_ctrl - use configuration work.t48_dmem_ctrl_rtl_c0; - end for; - - for use_timer - for timer_b : t48_timer - use configuration work.t48_timer_rtl_c0; - end for; - end for; - - for use_p1 - for p1_b : t48_p1 - use configuration work.t48_p1_rtl_c0; - end for; - end for; - - for use_p2 - for p2_b : t48_p2 - use configuration work.t48_p2_rtl_c0; - end for; - end for; - - for pmem_ctrl_b : t48_pmem_ctrl - use configuration work.t48_pmem_ctrl_rtl_c0; - end for; - - for psw_b : t48_psw - use configuration work.t48_psw_rtl_c0; - end for; - - end for; - -end t48_core_struct_c0;

t48/rel_1_2/rtl/vhdl/t48_core-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_pack-p.vhd (nonexistent) @@ -1,82 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t48_pack is - - ----------------------------------------------------------------------------- - -- Global constants - ----------------------------------------------------------------------------- - - -- clock active level - constant clk_active_c : std_logic := '1'; - -- reset active level - constant res_active_c : std_logic := '0'; - -- idle level on internal data bus - constant bus_idle_level_c : std_logic := '1'; - - -- global data word width - constant word_width_c : natural := 8; - - -- data memory address width - constant dmem_addr_width_c : natural := 8; - -- program memory address width - constant pmem_addr_width_c : natural := 12; - - - ----------------------------------------------------------------------------- - -- Global data types - ----------------------------------------------------------------------------- - - -- the global data word width type - subtype word_t is std_logic_vector(word_width_c-1 downto 0); - subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0); - -- the global data memory address type - subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0); - -- the global program memory address type - subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0); - subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c); - - -- the machine states - type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5); - - - ----------------------------------------------------------------------------- - -- Global functions - ----------------------------------------------------------------------------- - - function to_stdLogic(input: boolean) return std_logic; - function to_boolean(input: std_logic) return boolean; - -end t48_pack; - -package body t48_pack is - - function to_stdLogic(input: boolean) return std_logic is - begin - if input then - return '1'; - else - return '0'; - end if; - end to_stdLogic; - - function to_boolean(input: std_logic) return boolean is - begin - if input = '1' then - return true; - else - return false; - end if; - end to_boolean; - -end t48_pack;

t48/rel_1_2/rtl/vhdl/t48_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/timer.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/timer.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/timer.vhd (nonexistent) @@ -1,252 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Timer/Counter unit. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_pack.mstate_t; - -entity t48_timer is - - generic ( - -- state in which T1 is sampled (3 or 4) - sample_t1_state_g : integer := 4 - ); - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - t1_i : in std_logic; - clk_mstate_i : in mstate_t; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - read_timer_i : in boolean; - write_timer_i : in boolean; - -- Decoder Interface ------------------------------------------------------ - start_t_i : in boolean; - start_cnt_i : in boolean; - stop_tcnt_i : in boolean; - overflow_o : out std_logic - ); - -end t48_timer; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pack.all; - -architecture rtl of t48_timer is - - -- the 8 bit counter core - signal counter_q : unsigned(word_t'range); - signal overflow_q : boolean; - - -- increment signal for the counter core - type inc_type_t is (NONE, TIMER, COUNTER); - signal increment_s : boolean; - signal inc_sel_q : inc_type_t; - - -- T1 edge detector - signal t1_q : std_logic; - signal t1_inc_s : boolean; - - -- timer prescaler - signal prescaler_q : unsigned(4 downto 0); - signal pre_inc_s : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Verify the generics - ----------------------------------------------------------------------------- - - -- pragma translate_off - assert (sample_t1_state_g = 3) or (sample_t1_state_g = 4) - report "sample_t1_state_g must be either 3 or 4!" - severity failure; - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Process t1_edge - -- - -- Purpose: - -- Implements the edge detector for T1. - -- - t1_edge: process (t1_i, - t1_q, - clk_mstate_i) - begin - t1_inc_s <= false; - - -- sample in state according to generic - -- Old devices: sample at the beginning of state 3 - -- New devices: sample in state 4 - if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or - (sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then - -- detect falling edge - if t1_q = '1' and t1_i = '0' then - t1_inc_s <= true; - end if; - end if; - - end process t1_edge; - -- - ----------------------------------------------------------------------------- - - - pre_inc_s <= clk_mstate_i = MSTATE4 and prescaler_q = 31; - - - ----------------------------------------------------------------------------- - -- Process inc_sel - -- - -- Purpose: - -- Select increment source (timer, counter or none). - -- - inc_sel: process (inc_sel_q, - pre_inc_s, - t1_inc_s) - begin - -- default assignment - increment_s <= false; - - case inc_sel_q is - when NONE => - increment_s <= false; - when TIMER => - increment_s <= pre_inc_s; - when COUNTER => - increment_s <= t1_inc_s; - when others => - null; - end case; - - end process inc_sel; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process regs - -- - -- Purpose: - -- Implements the counter, the prescaler and other registers. - -- - regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - overflow_q <= false; - t1_q <= '0'; - prescaler_q <= (others => '0'); - inc_sel_q <= NONE; - counter_q <= (others => '0'); - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - -- Counter Core and overflow ------------------------------------------ - overflow_q <= false; - - if write_timer_i then - counter_q <= unsigned(data_i); - - elsif increment_s then - counter_q <= counter_q + 1; - - if counter_q = 255 then - overflow_q <= true; - end if; - - end if; - - -- T1 edge detector --------------------------------------------------- - if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or - (sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then - t1_q <= t1_i; - end if; - - -- Prescaler ---------------------------------------------------------- - if start_t_i then - prescaler_q <= (others => '0'); - - elsif clk_mstate_i = MSTATE3 then - prescaler_q <= prescaler_q + 1; - - end if; - - -- Increment Selector ------------------------------------------------- - if start_t_i then - inc_sel_q <= TIMER; - elsif start_cnt_i then - inc_sel_q <= COUNTER; - elsif stop_tcnt_i then - inc_sel_q <= NONE; - end if; - - end if; - - end if; - - end process regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - data_o <= std_logic_vector(counter_q) - when read_timer_i else - (others => bus_idle_level_c); - overflow_o <= to_stdLogic(overflow_q); - -end rtl;

t48/rel_1_2/rtl/vhdl/timer.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/pmem_ctrl.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/pmem_ctrl.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/pmem_ctrl.vhd (nonexistent) @@ -1,222 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Program Memory control unit. --- All operations related to the Program Memory are managed here. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.pmem_addr_t; -use work.t48_pack.word_t; -use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; - -entity t48_pmem_ctrl is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - write_pcl_i : in boolean; - read_pcl_i : in boolean; - write_pch_i : in boolean; - read_pch_i : in boolean; - inc_pc_i : in boolean; - write_pmem_addr_i : in boolean; - addr_type_i : in pmem_addr_ident_t; - read_pmem_i : in boolean; - -- Porgram Memroy Interface ----------------------------------------------- - pmem_addr_o : out pmem_addr_t; - pmem_data_i : in word_t - ); - -end t48_pmem_ctrl; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pmem_ctrl_pack.all; -use work.t48_pack.res_active_c; -use work.t48_pack.clk_active_c; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.pmem_addr_width_c; -use work.t48_pack.dmem_addr_width_c; -use work.t48_pack.page_t; - -architecture rtl of t48_pmem_ctrl is - - -- implemented counter width of Program Counter - -- the upper bit is only altered by JMP, CALL and RET(R) - subtype pc_count_range_t is natural range pmem_addr_width_c-2 downto 0; - - -- the Program Counter - signal program_counter_q : unsigned(pmem_addr_t'range); - - - -- the Program Memory address - signal pmem_addr_s, - pmem_addr_q : std_logic_vector(pmem_addr_t'range); - -begin - - ----------------------------------------------------------------------------- - -- Process program_counter - -- - -- Purpose: - -- Implements the Program Counter. - -- - program_counter: process (res_i, clk_i) - begin - if res_i = res_active_c then - program_counter_q <= (others => '0'); - pmem_addr_q <= (others => '0'); - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - -- parallel load mode - if write_pcl_i then - program_counter_q(data_i'range) <= UNSIGNED(data_i); - elsif write_pch_i then - program_counter_q(pmem_addr_width_c-1 downto data_i'high+1) <= - UNSIGNED(data_i(pmem_addr_width_c - dmem_addr_width_c - 1 downto 0)); - elsif inc_pc_i then - -- increment mode - -- the MSB is not modified by linear increments - -- it can only be altered by JMP, CALL or RET(R) - program_counter_q(pc_count_range_t) <= - program_counter_q(pc_count_range_t) + 1; - end if; - - -- set pmem address - if write_pmem_addr_i then - pmem_addr_q <= pmem_addr_s; - end if; - - end if; - - end if; - - end process program_counter; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process pmem_addr - -- - -- Purpose: - -- Multiplex the Program Memory address. - -- - pmem_addr: process (program_counter_q, - addr_type_i, - pmem_addr_q, - data_i) - begin - -- default assignment - pmem_addr_s <= STD_LOGIC_VECTOR(program_counter_q); - - case addr_type_i is - when PM_PC => - -- default is ok - null; - - when PM_PAGE => - pmem_addr_s(word_t'range) <= data_i; - -- take page address from program counter - -- => important for JMPP, MOVP! - -- they must wrap to next page when at FF! - - when PM_PAGE3 => - pmem_addr_s(word_t'range) <= data_i; - -- page address is explicitely specified - pmem_addr_s(page_t'range) <= "0011"; - - when others => - null; - - end case; - - end process pmem_addr; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process data_output - -- - -- Purpose: - -- Multiplex the data bus output. - -- - data_output: process (read_pmem_i, - read_pcl_i, - read_pch_i, - pmem_data_i, - program_counter_q) - begin - data_o <= (others => bus_idle_level_c); - - if read_pmem_i then - data_o <= pmem_data_i; - elsif read_pcl_i then - data_o <= STD_LOGIC_VECTOR(program_counter_q(data_o'range)); - elsif read_pch_i then - data_o(3 downto 0) <= STD_LOGIC_VECTOR(program_counter_q(pmem_addr_width_c-1 downto data_o'high+1)); - end if; - - end process data_output; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - pmem_addr_o <= pmem_addr_q; - -end rtl;

t48/rel_1_2/rtl/vhdl/pmem_ctrl.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/bus_mux.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/bus_mux.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/bus_mux.vhd (nonexistent) @@ -1,100 +0,0 @@ -------------------------------------------------------------------------------- --- --- The T48 Bus Connector. --- Multiplexes all drivers of the T48 bus. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -entity t48_bus_mux is - - port ( - alu_data_i : in word_t; - bus_data_i : in word_t; - dec_data_i : in word_t; - dm_data_i : in word_t; - pm_data_i : in word_t; - p1_data_i : in word_t; - p2_data_i : in word_t; - psw_data_i : in word_t; - tim_data_i : in word_t; - data_o : out word_t - ); - -end t48_bus_mux; - - -use work.t48_pack.bus_idle_level_c; - -architecture rtl of t48_bus_mux is - -begin - - or_tree: if bus_idle_level_c = '0' generate - data_o <= alu_data_i or - bus_data_i or - dec_data_i or - dm_data_i or - pm_data_i or - p1_data_i or - p2_data_i or - psw_data_i or - tim_data_i; - end generate; - - and_tree: if bus_idle_level_c = '1' generate - data_o <= alu_data_i and - bus_data_i and - dec_data_i and - dm_data_i and - pm_data_i and - p1_data_i and - p2_data_i and - psw_data_i and - tim_data_i; - end generate; - -end rtl;

t48/rel_1_2/rtl/vhdl/bus_mux.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/decoder-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/decoder-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/decoder-c.vhd (nonexistent) @@ -1,24 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Decoder unit. --- It decodes the instruction opcodes and executes them. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_decoder_rtl_c0 of t48_decoder is - - for rtl - - for int_b: t48_int - use configuration work.t48_int_rtl_c0; - end for; - - end for; - -end t48_decoder_rtl_c0;

t48/rel_1_2/rtl/vhdl/decoder-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/t48_core.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/t48_core.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/t48_core.vhd (nonexistent) @@ -1,632 +0,0 @@ -------------------------------------------------------------------------------- --- --- T48 Microcontroller Core --- --- $Id$ --- --- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- --- Limitations : --- ============= --- --- Compared to the original MCS-48 architecture, the following limitations --- apply: --- --- * Single-step mode not implemented. --- Not selected for future implementation. --- --- * Reading of internal Program Memory not implemented. --- Not selected for future implementation. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t48_core is - - generic ( - -- divide XTAL1 by 3 to derive Clock States - xtal_div_3_g : integer := 1; - -- store mnemonic in flip-flops (registered-out) - register_mnemonic_g : integer := 1; - -- include the port 1 module - include_port1_g : integer := 1; - -- include the port 2 module - include_port2_g : integer := 1; - -- include the BUS module - include_bus_g : integer := 1; - -- include the timer module - include_timer_g : integer := 1; - -- state in which T1 is sampled (3 or 4) - sample_t1_state_g : integer := 4 - ); - - port ( - -- T48 Interface ---------------------------------------------------------- - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic; - -- Core Interface --------------------------------------------------------- - clk_i : in std_logic; - en_clk_i : in std_logic; - xtal3_o : out std_logic; - dmem_addr_o : out std_logic_vector( 7 downto 0); - dmem_we_o : out std_logic; - dmem_data_i : in std_logic_vector( 7 downto 0); - dmem_data_o : out std_logic_vector( 7 downto 0); - pmem_addr_o : out std_logic_vector(11 downto 0); - pmem_data_i : in std_logic_vector( 7 downto 0) - ); - -end t48_core; - - -use work.t48_alu_pack.alu_op_t; -use work.t48_cond_branch_pack.branch_conditions_t; -use work.t48_cond_branch_pack.comp_value_t; -use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; -use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; -use work.t48_comp_pack.all; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.word_t; -use work.t48_pack.pmem_addr_t; -use work.t48_pack.mstate_t; -use work.t48_pack.to_stdLogic; -use work.t48_pack.to_boolean; - -architecture struct of t48_core is - - signal t48_data_s : word_t; - - signal xtal_en_s : boolean; - signal en_clk_s : boolean; - - -- ALU signals - signal alu_data_s : word_t; - signal alu_write_accu_s : boolean; - signal alu_write_shadow_s : boolean; - signal alu_write_temp_reg_s : boolean; - signal alu_read_alu_s : boolean; - signal alu_carry_s : std_logic; - signal alu_aux_carry_s : std_logic; - signal alu_op_s : alu_op_t; - signal alu_use_carry_s : boolean; - signal alu_da_high_s : boolean; - signal alu_da_overflow_s : boolean; - signal alu_accu_low_s : boolean; - signal alu_p06_temp_reg_s : boolean; - signal alu_p60_temp_reg_s : boolean; - - -- BUS signals - signal bus_write_bus_s : boolean; - signal bus_read_bus_s : boolean; - signal bus_output_pcl_s : boolean; - signal bus_bidir_bus_s : boolean; - signal bus_data_s : word_t; - - -- Clock Controller signals - signal clk_multi_cycle_s : boolean; - signal clk_assert_psen_s : boolean; - signal clk_assert_prog_s : boolean; - signal clk_assert_rd_s : boolean; - signal clk_assert_wr_s : boolean; - signal clk_mstate_s : mstate_t; - signal clk_second_cycle_s : boolean; - signal psen_s : boolean; - signal prog_s : boolean; - signal rd_s : boolean; - signal wr_s : boolean; - signal ale_s : boolean; - signal xtal3_s : boolean; - - -- Conditional Branch Logic signals - signal cnd_compute_take_s : boolean; - signal cnd_branch_cond_s : branch_conditions_t; - signal cnd_take_branch_s : boolean; - signal cnd_comp_value_s : comp_value_t; - signal cnd_f1_s : std_logic; - signal cnd_tf_s : std_logic; - - -- Data Memory Controller signals - signal dm_write_dmem_addr_s : boolean; - signal dm_write_dmem_s : boolean; - signal dm_read_dmem_s : boolean; - signal dm_addr_type_s : dmem_addr_ident_t; - signal dm_data_s : word_t; - - -- Decoder signals - signal dec_data_s : word_t; - - -- Port 1 signals - signal p1_write_p1_s : boolean; - signal p1_read_p1_s : boolean; - signal p1_read_reg_s : boolean; - signal p1_data_s : word_t; - - -- Port 2 signals - signal p2_write_p2_s : boolean; - signal p2_write_exp_s : boolean; - signal p2_read_p2_s : boolean; - signal p2_read_reg_s : boolean; - signal p2_read_exp_s : boolean; - signal p2_output_pch_s : boolean; - signal p2_data_s : word_t; - - -- Program Memory Controller signals - signal pm_write_pcl_s : boolean; - signal pm_read_pcl_s : boolean; - signal pm_write_pch_s : boolean; - signal pm_read_pch_s : boolean; - signal pm_read_pmem_s : boolean; - signal pm_inc_pc_s : boolean; - signal pm_write_pmem_addr_s : boolean; - signal pm_data_s : word_t; - signal pm_addr_type_s : pmem_addr_ident_t; - signal pmem_addr_s : pmem_addr_t; - - -- PSW signals - signal psw_read_psw_s : boolean; - signal psw_read_sp_s : boolean; - signal psw_write_psw_s : boolean; - signal psw_write_sp_s : boolean; - signal psw_carry_s : std_logic; - signal psw_aux_carry_s : std_logic; - signal psw_f0_s : std_logic; - signal psw_bs_s : std_logic; - signal psw_special_data_s : std_logic; - signal psw_inc_stackp_s : boolean; - signal psw_dec_stackp_s : boolean; - signal psw_write_carry_s : boolean; - signal psw_write_aux_carry_s : boolean; - signal psw_write_f0_s : boolean; - signal psw_write_bs_s : boolean; - signal psw_data_s : word_t; - - -- Timer signals - signal tim_overflow_s : boolean; - signal tim_of_s : std_logic; - signal tim_read_timer_s : boolean; - signal tim_write_timer_s : boolean; - signal tim_start_t_s : boolean; - signal tim_start_cnt_s : boolean; - signal tim_stop_tcnt_s : boolean; - signal tim_data_s : word_t; - -begin - - ----------------------------------------------------------------------------- - -- Check generics for valid values. - ----------------------------------------------------------------------------- - -- pragma translate_off - assert include_timer_g = 0 or include_timer_g = 1 - report "include_timer_g must be either 1 or 0!" - severity failure; - - assert include_port1_g = 0 or include_port1_g = 1 - report "include_port1_g must be either 1 or 0!" - severity failure; - - assert include_port2_g = 0 or include_port2_g = 1 - report "include_port2_g must be either 1 or 0!" - severity failure; - - assert include_bus_g = 0 or include_bus_g = 1 - report "include_bus_g must be either 1 or 0!" - severity failure; - -- pragma translate_on - - - xtal_en_s <= to_boolean(xtal_en_i); - en_clk_s <= to_boolean(en_clk_i); - - alu_b : t48_alu - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - data_i => t48_data_s, - data_o => alu_data_s, - write_accu_i => alu_write_accu_s, - write_shadow_i => alu_write_shadow_s, - write_temp_reg_i => alu_write_temp_reg_s, - read_alu_i => alu_read_alu_s, - carry_i => psw_carry_s, - carry_o => alu_carry_s, - aux_carry_o => alu_aux_carry_s, - alu_op_i => alu_op_s, - use_carry_i => alu_use_carry_s, - da_high_i => alu_da_high_s, - da_overflow_o => alu_da_overflow_s, - accu_low_i => alu_accu_low_s, - p06_temp_reg_i => alu_p06_temp_reg_s, - p60_temp_reg_i => alu_p60_temp_reg_s - ); - - bus_mux_b : t48_bus_mux - port map ( - alu_data_i => alu_data_s, - bus_data_i => bus_data_s, - dec_data_i => dec_data_s, - dm_data_i => dm_data_s, - pm_data_i => pm_data_s, - p1_data_i => p1_data_s, - p2_data_i => p2_data_s, - psw_data_i => psw_data_s, - tim_data_i => tim_data_s, - data_o => t48_data_s - ); - - clock_ctrl_b : t48_clock_ctrl - generic map ( - xtal_div_3_g => xtal_div_3_g - ) - port map ( - clk_i => clk_i, - xtal_i => xtal_i, - xtal_en_i => xtal_en_s, - res_i => reset_i, - en_clk_i => en_clk_s, - xtal3_o => xtal3_s, - t0_o => t0_o, - multi_cycle_i => clk_multi_cycle_s, - assert_psen_i => clk_assert_psen_s, - assert_prog_i => clk_assert_prog_s, - assert_rd_i => clk_assert_rd_s, - assert_wr_i => clk_assert_wr_s, - mstate_o => clk_mstate_s, - second_cycle_o => clk_second_cycle_s, - ale_o => ale_s, - psen_o => psen_s, - prog_o => prog_s, - rd_o => rd_s, - wr_o => wr_s - ); - - cond_branch_b : t48_cond_branch - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - compute_take_i => cnd_compute_take_s, - branch_cond_i => cnd_branch_cond_s, - take_branch_o => cnd_take_branch_s, - accu_i => alu_data_s, - t0_i => To_X01Z(t0_i), - t1_i => To_X01Z(t1_i), - int_n_i => int_n_i, - f0_i => psw_f0_s, - f1_i => cnd_f1_s, - tf_i => cnd_tf_s, - carry_i => psw_carry_s, - comp_value_i => cnd_comp_value_s - ); - - use_db_bus: if include_bus_g = 1 generate - db_bus_b : t48_db_bus - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - ea_i => ea_i, - data_i => t48_data_s, - data_o => bus_data_s, - write_bus_i => bus_write_bus_s, - read_bus_i => bus_read_bus_s, - output_pcl_i => bus_output_pcl_s, - bidir_bus_i => bus_bidir_bus_s, - pcl_i => pmem_addr_s(word_t'range), - db_i => db_i, - db_o => db_o, - db_dir_o => db_dir_o - ); - end generate; - - skip_db_bus: if include_bus_g = 0 generate - bus_data_s <= (others => bus_idle_level_c); - db_o <= (others => '0'); - db_dir_o <= '0'; - end generate; - - decoder_b : t48_decoder - generic map ( - register_mnemonic_g => register_mnemonic_g - ) - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - xtal_i => xtal_i, - xtal_en_i => xtal_en_s, - ea_i => ea_i, - ale_i => ale_s, - int_n_i => int_n_i, - t0_dir_o => t0_dir_o, - data_i => t48_data_s, - data_o => dec_data_s, - alu_write_accu_o => alu_write_accu_s, - alu_write_shadow_o => alu_write_shadow_s, - alu_write_temp_reg_o => alu_write_temp_reg_s, - alu_read_alu_o => alu_read_alu_s, - bus_write_bus_o => bus_write_bus_s, - bus_read_bus_o => bus_read_bus_s, - dm_write_dmem_addr_o => dm_write_dmem_addr_s, - dm_write_dmem_o => dm_write_dmem_s, - dm_read_dmem_o => dm_read_dmem_s, - p1_write_p1_o => p1_write_p1_s, - p1_read_p1_o => p1_read_p1_s, - pm_write_pcl_o => pm_write_pcl_s, - p2_write_p2_o => p2_write_p2_s, - p2_write_exp_o => p2_write_exp_s, - p2_read_p2_o => p2_read_p2_s, - pm_read_pcl_o => pm_read_pcl_s, - pm_write_pch_o => pm_write_pch_s, - pm_read_pch_o => pm_read_pch_s, - pm_read_pmem_o => pm_read_pmem_s, - psw_read_psw_o => psw_read_psw_s, - psw_read_sp_o => psw_read_sp_s, - psw_write_psw_o => psw_write_psw_s, - psw_write_sp_o => psw_write_sp_s, - alu_carry_i => alu_carry_s, - alu_op_o => alu_op_s, - alu_use_carry_o => alu_use_carry_s, - alu_da_high_o => alu_da_high_s, - alu_da_overflow_i => alu_da_overflow_s, - alu_accu_low_o => alu_accu_low_s, - alu_p06_temp_reg_o => alu_p06_temp_reg_s, - alu_p60_temp_reg_o => alu_p60_temp_reg_s, - bus_output_pcl_o => bus_output_pcl_s, - bus_bidir_bus_o => bus_bidir_bus_s, - clk_multi_cycle_o => clk_multi_cycle_s, - clk_assert_psen_o => clk_assert_psen_s, - clk_assert_prog_o => clk_assert_prog_s, - clk_assert_rd_o => clk_assert_rd_s, - clk_assert_wr_o => clk_assert_wr_s, - clk_mstate_i => clk_mstate_s, - clk_second_cycle_i => clk_second_cycle_s, - cnd_compute_take_o => cnd_compute_take_s, - cnd_branch_cond_o => cnd_branch_cond_s, - cnd_take_branch_i => cnd_take_branch_s, - cnd_comp_value_o => cnd_comp_value_s, - cnd_f1_o => cnd_f1_s, - cnd_tf_o => cnd_tf_s, - dm_addr_type_o => dm_addr_type_s, - tim_read_timer_o => tim_read_timer_s, - tim_write_timer_o => tim_write_timer_s, - tim_start_t_o => tim_start_t_s, - tim_start_cnt_o => tim_start_cnt_s, - tim_stop_tcnt_o => tim_stop_tcnt_s, - p1_read_reg_o => p1_read_reg_s, - p2_read_reg_o => p2_read_reg_s, - p2_read_exp_o => p2_read_exp_s, - p2_output_pch_o => p2_output_pch_s, - pm_inc_pc_o => pm_inc_pc_s, - pm_write_pmem_addr_o => pm_write_pmem_addr_s, - pm_addr_type_o => pm_addr_type_s, - psw_special_data_o => psw_special_data_s, - psw_carry_i => psw_carry_s, - psw_aux_carry_i => psw_aux_carry_s, - psw_f0_i => psw_f0_s, - psw_inc_stackp_o => psw_inc_stackp_s, - psw_dec_stackp_o => psw_dec_stackp_s, - psw_write_carry_o => psw_write_carry_s, - psw_write_aux_carry_o => psw_write_aux_carry_s, - psw_write_f0_o => psw_write_f0_s, - psw_write_bs_o => psw_write_bs_s, - tim_overflow_i => tim_overflow_s - ); - - dmem_ctrl_b : t48_dmem_ctrl - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - data_i => t48_data_s, - write_dmem_addr_i => dm_write_dmem_addr_s, - write_dmem_i => dm_write_dmem_s, - read_dmem_i => dm_read_dmem_s, - addr_type_i => dm_addr_type_s, - bank_select_i => psw_bs_s, - data_o => dm_data_s, - dmem_data_i => dmem_data_i, - dmem_addr_o => dmem_addr_o, - dmem_we_o => dmem_we_o, - dmem_data_o => dmem_data_o - ); - - use_timer: if include_timer_g = 1 generate - timer_b : t48_timer - generic map ( - sample_t1_state_g => sample_t1_state_g - ) - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - t1_i => To_X01Z(t1_i), - clk_mstate_i => clk_mstate_s, - data_i => t48_data_s, - data_o => tim_data_s, - read_timer_i => tim_read_timer_s, - write_timer_i => tim_write_timer_s, - start_t_i => tim_start_t_s, - start_cnt_i => tim_start_cnt_s, - stop_tcnt_i => tim_stop_tcnt_s, - overflow_o => tim_of_s - ); - end generate; - - skip_timer: if include_timer_g = 0 generate - tim_data_s <= (others => bus_idle_level_c); - tim_of_s <= '0'; - end generate; - - tim_overflow_s <= to_boolean(tim_of_s); - - use_p1: if include_port1_g = 1 generate - p1_b : t48_p1 - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - data_i => t48_data_s, - data_o => p1_data_s, - write_p1_i => p1_write_p1_s, - read_p1_i => p1_read_p1_s, - read_reg_i => p1_read_reg_s, - p1_i => p1_i, - p1_o => p1_o, - p1_low_imp_o => p1_low_imp_o - ); - end generate; - - skip_p1: if include_port1_g = 0 generate - p1_data_s <= (others => bus_idle_level_c); - p1_o <= (others => '0'); - p1_low_imp_o <= '0'; - end generate; - - use_p2: if include_port2_g = 1 generate - p2_b : t48_p2 - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - xtal_i => xtal_i, - xtal_en_i => xtal_en_s, - data_i => t48_data_s, - data_o => p2_data_s, - write_p2_i => p2_write_p2_s, - write_exp_i => p2_write_exp_s, - read_p2_i => p2_read_p2_s, - read_reg_i => p2_read_reg_s, - read_exp_i => p2_read_exp_s, - output_pch_i => p2_output_pch_s, - pch_i => pmem_addr_s(11 downto 8), - p2_i => p2_i, - p2_o => p2_o, - p2l_low_imp_o => p2l_low_imp_o, - p2h_low_imp_o => p2h_low_imp_o - ); - end generate; - - skip_p2: if include_port2_g = 0 generate - p2_data_s <= (others => bus_idle_level_c); - p2_o <= (others => '0'); - p2l_low_imp_o <= '0'; - p2h_low_imp_o <= '0'; - end generate; - - pmem_ctrl_b : t48_pmem_ctrl - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - data_i => t48_data_s, - data_o => pm_data_s, - write_pcl_i => pm_write_pcl_s, - read_pcl_i => pm_read_pcl_s, - write_pch_i => pm_write_pch_s, - read_pch_i => pm_read_pch_s, - inc_pc_i => pm_inc_pc_s, - write_pmem_addr_i => pm_write_pmem_addr_s, - addr_type_i => pm_addr_type_s, - read_pmem_i => pm_read_pmem_s, - pmem_addr_o => pmem_addr_s, - pmem_data_i => pmem_data_i - ); - - psw_b : t48_psw - port map ( - clk_i => clk_i, - res_i => reset_i, - en_clk_i => en_clk_s, - data_i => t48_data_s, - data_o => psw_data_s, - read_psw_i => psw_read_psw_s, - read_sp_i => psw_read_sp_s, - write_psw_i => psw_write_psw_s, - write_sp_i => psw_write_sp_s, - special_data_i => psw_special_data_s, - inc_stackp_i => psw_inc_stackp_s, - dec_stackp_i => psw_dec_stackp_s, - write_carry_i => psw_write_carry_s, - write_aux_carry_i => psw_write_aux_carry_s, - write_f0_i => psw_write_f0_s, - write_bs_i => psw_write_bs_s, - carry_o => psw_carry_s, - aux_carry_i => alu_aux_carry_s, - aux_carry_o => psw_aux_carry_s, - f0_o => psw_f0_s, - bs_o => psw_bs_s - ); - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - ale_o <= to_stdLogic(ale_s); - psen_n_o <= to_stdLogic(not psen_s); - prog_n_o <= to_stdLogic(not prog_s); - rd_n_o <= to_stdLogic(not rd_s); - wr_n_o <= to_stdLogic(not wr_s); - xtal3_o <= to_stdLogic(xtal3_s); - pmem_addr_o <= pmem_addr_s; - -end struct;

t48/rel_1_2/rtl/vhdl/t48_core.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/psw-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/psw-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/psw-c.vhd (nonexistent) @@ -1,17 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Program Status Word (PSW). --- Implements the PSW with its special bits. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_psw_rtl_c0 of t48_psw is - - for rtl - end for; - -end t48_psw_rtl_c0;

t48/rel_1_2/rtl/vhdl/psw-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/cond_branch_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/cond_branch_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/cond_branch_pack-p.vhd (nonexistent) @@ -1,28 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t48_cond_branch_pack is - - ----------------------------------------------------------------------------- - -- The branch conditions. - ----------------------------------------------------------------------------- - type branch_conditions_t is (COND_ON_BIT, COND_Z, - COND_C, - COND_F0, COND_F1, - COND_INT, - COND_T0, COND_T1, - COND_TF); - - subtype comp_value_t is std_logic_vector(2 downto 0); - -end t48_cond_branch_pack;

t48/rel_1_2/rtl/vhdl/cond_branch_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/clock_ctrl-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/clock_ctrl-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/clock_ctrl-c.vhd (nonexistent) @@ -1,14 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- The clock control unit. --- -------------------------------------------------------------------------------- - -configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is - - for rtl - end for; - -end t48_clock_ctrl_rtl_c0;

t48/rel_1_2/rtl/vhdl/clock_ctrl-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/p1-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/p1-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/p1-c.vhd (nonexistent) @@ -1,17 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Port 1 unit. --- Implements the Port 1 logic. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_p1_rtl_c0 of t48_p1 is - - for rtl - end for; - -end t48_p1_rtl_c0;

t48/rel_1_2/rtl/vhdl/p1-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/decoder_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/decoder_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/decoder_pack-p.vhd (nonexistent) @@ -1,428 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -package t48_decoder_pack is - - ----------------------------------------------------------------------------- - -- The Mnemonics. - ----------------------------------------------------------------------------- - type mnemonic_t is (MN_ADD, - MN_ADD_A_DATA, - MN_ANL, - MN_ANL_A_DATA, - MN_ANL_EXT, - MN_CALL, - MN_CLR_A, - MN_CLR_C, - MN_CLR_F, - MN_CPL_A, - MN_CPL_C, - MN_CPL_F, - MN_DA, - MN_DEC, - MN_DIS_EN_I, - MN_DIS_EN_TCNTI, - MN_DJNZ, - MN_ENT0_CLK, - MN_IN, - MN_INC, - MN_INS, - MN_JBB, - MN_JC, - MN_JF, - MN_JMP, - MN_JMPP, - MN_JNI, - MN_JT, - MN_JTF, - MN_JZ, - MN_MOV_A_DATA, - MN_MOV_A_PSW, - MN_MOV_A_RR, - MN_MOV_PSW_A, - MN_MOV_RR, - MN_MOV_RR_DATA, - MN_MOV_T, - MN_MOVD_A_PP, - MN_MOVP, - MN_MOVX, - MN_NOP, - MN_ORL, - MN_ORL_A_DATA, - MN_ORL_EXT, - MN_OUTD_PP_A, - MN_OUTL_EXT, - MN_RET, - MN_RL, - MN_RR, - MN_SEL_MB, - MN_SEL_RB, - MN_STOP_TCNT, - MN_STRT, - MN_SWAP, - MN_XCH, - MN_XRL, - MN_XRL_A_DATA); - - type mnemonic_rec_t is - record - mnemonic : mnemonic_t; - multi_cycle : boolean; - end record; - - function decode_opcode_f(opcode : in word_t) return - mnemonic_rec_t; - -end t48_decoder_pack; - - -package body t48_decoder_pack is - - function decode_opcode_f(opcode : in word_t) return - mnemonic_rec_t is - variable mnemonic_v : mnemonic_t; - variable multi_cycle_v : boolean; - variable result_v : mnemonic_rec_t; - begin - -- default assignment - mnemonic_v := MN_NOP; - multi_cycle_v := false; - - case opcode is - -- Mnemonic ADD --------------------------------------------------------- - when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr - "01101100" | "01101101" | "01101110" | "01101111" | -- - "01100000" | "01100001" | -- ADD A, @ Rr - "01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr - "01111100" | "01111101" | "01111110" | "01111111" | -- - "01110000" | "01110001" => -- ADDC A, @ Rr - mnemonic_v := MN_ADD; - - -- Mnemonic ADD_A_DATA -------------------------------------------------- - when "00000011" | -- ADD A, data - "00010011" => -- ADDC A, data - mnemonic_v := MN_ADD_A_DATA; - multi_cycle_v := true; - - -- Mnemonic ANL --------------------------------------------------------- - when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr - "01011100" | "01011101" | "01011110" | "01011111" | -- - "01010000" | "01010001" => -- ANL A, @ Rr - mnemonic_v := MN_ANL; - - -- Mnemonic ANL_A_DATA -------------------------------------------------- - when "01010011" => -- ANL A, data - mnemonic_v := MN_ANL_A_DATA; - multi_cycle_v := true; - - -- Mnemonic ANL_EXT ----------------------------------------------------- - when "10011000" | -- ANL BUS, data - "10011001" | "10011010" => -- ANL PP, data - mnemonic_v := MN_ANL_EXT; - multi_cycle_v := true; - - -- Mnemonic CALL -------------------------------------------------------- - when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr - "10010100" | "10110100" | "11010100" | "11110100" => -- - mnemonic_v := MN_CALL; - multi_cycle_v := true; - - -- Mnemonic CLR_A ------------------------------------------------------- - when "00100111" => -- CLR A - mnemonic_v := MN_CLR_A; - - -- Mnemonic CLR_C ------------------------------------------------------- - when "10010111" => -- CLR C - mnemonic_v := MN_CLR_C; - - -- Mnemonic CLR_F ------------------------------------------------------- - when "10000101" | -- CLR F0 - "10100101" => - mnemonic_v := MN_CLR_F; - - -- Mnemonic CPL_A ------------------------------------------------------- - when "00110111" => -- CPL A - mnemonic_v := MN_CPL_A; - - -- Mnemonic CPL_C ------------------------------------------------------- - when "10100111" => -- CPL C - mnemonic_v := MN_CPL_C; - - -- Mnemonic CPL_F ------------------------------------------------------- - when "10010101" | -- CPL F0 - "10110101" => -- CPL F1 - mnemonic_v := MN_CPL_F; - - -- Mnemonic DA ---------------------------------------------------------- - when "01010111" => -- DA D - mnemonic_v := MN_DA; - - -- Mnemonic DEC --------------------------------------------------------- - when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr - "11001100" | "11001101" | "11001110" | "11001111" | -- - "00000111" => -- DEC A - mnemonic_v := MN_DEC; - - -- Mnemonic DIS_EN_I ---------------------------------------------------- - when "00010101" | -- DIS I - "00000101" => -- EN I - mnemonic_v := MN_DIS_EN_I; - - -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ - when "00110101" | -- DIS TCNTI - "00100101" => -- EN TCNTI - mnemonic_v := MN_DIS_EN_TCNTI; - - -- Mnemonic DJNZ -------------------------------------------------------- - when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr - "11101100" | "11101101" | "11101110" | "11101111" => -- - mnemonic_v := MN_DJNZ; - multi_cycle_v := true; - - -- Mnemonic ENT0_CLK ---------------------------------------------------- - when "01110101" => -- ENT0 CLK - mnemonic_v := MN_ENT0_CLK; - - -- Mnemonic IN ---------------------------------------------------------- - when "00001001" | "00001010" => -- IN A, Pp - mnemonic_v := MN_IN; - multi_cycle_v := true; - - -- Mnemonic INC --------------------------------------------------------- - when "00010111" | -- INC A - "00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr - "00011100" | "00011101" | "00011110" | "00011111" | -- - "00010000" | "00010001" => -- INC @ Rr - mnemonic_v := MN_INC; - - -- Mnemonic INS --------------------------------------------------------- - when "00001000" => -- INS A, BUS - mnemonic_v := MN_INS; - multi_cycle_v := true; - - -- Mnemonic JBB --------------------------------------------------------- - when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr - "10010010" | "10110010" | "11010010" | "11110010" => -- - mnemonic_v := MN_JBB; - multi_cycle_v := true; - - -- Mnemonic JC ---------------------------------------------------------- - when "11110110" | -- JC addr - "11100110" => -- JNC addr - mnemonic_v := MN_JC; - multi_cycle_v := true; - - -- Mnemonic JF ---------------------------------------------------------- - when "10110110" | -- JF0 addr - "01110110" => -- JF1 addr - mnemonic_v := MN_JF; - multi_cycle_v := true; - - -- Mnemonic JMP --------------------------------------------------------- - when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr - "10000100" | "10100100" | "11000100" | "11100100" => -- - mnemonic_v := MN_JMP; - multi_cycle_v := true; - - -- Mnemonic JMPP -------------------------------------------------------- - when "10110011" => -- JMPP @ A - mnemonic_v := MN_JMPP; - multi_cycle_v := true; - - -- Mnemonic JNI --------------------------------------------------------- - when "10000110" => -- JNI addr - mnemonic_v := MN_JNI; - multi_cycle_v := true; - - -- Mnemonic JT ---------------------------------------------------------- - when "00100110" | -- JNT0 addr - "01000110" | -- JNT1 addr - "00110110" | -- JT0 addr - "01010110" => -- JT1 addr - mnemonic_v := MN_JT; - multi_cycle_v := true; - - -- Mnemonic JTF --------------------------------------------------------- - when "00010110" => -- JTF addr - mnemonic_v := MN_JTF; - multi_cycle_v := true; - - -- Mnemonic JZ ---------------------------------------------------------- - when "10010110" | -- JNZ addr - "11000110" => -- JZ addr - mnemonic_v := MN_JZ; - multi_cycle_v := true; - - -- Mnemonic MOV_A_DATA -------------------------------------------------- - when "00100011" => -- MOV A, data - mnemonic_v := MN_MOV_A_DATA; - multi_cycle_v := true; - - -- Mnemonic MOV_A_PSW --------------------------------------------------- - when "11000111" => -- MOV A, PSW - mnemonic_v := MN_MOV_A_PSW; - - -- Mnemonic MOV_A_RR ---------------------------------------------------- - when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr - "11111100" | "11111101" | "11111110" | "11111111" | -- - "11110000" | "11110001" => -- MOV A, @ Rr - mnemonic_v := MN_MOV_A_RR; - - -- Mnemonic MOV_PSW_A --------------------------------------------------- - when "11010111" => -- MOV PSW, A - mnemonic_v := MN_MOV_PSW_A; - - -- Mnemonic MOV_RR ------------------------------------------------------ - when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A - "10101100" | "10101101" | "10101110" | "10101111" | -- - "10100000" | "10100001" => -- MOV @ Rr, A - mnemonic_v := MN_MOV_RR; - - -- Mnemonic MOV_RR_DATA ------------------------------------------------- - when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data - "10111100" | "10111101" | "10111110" | "10111111" | -- - "10110000" | "10110001" => -- MOV @ Rr, data - mnemonic_v := MN_MOV_RR_DATA; - multi_cycle_v := true; - - -- Mnemonic MOV_T ------------------------------------------------------- - when "01100010" | -- MOV T, A - "01000010" => -- MOV A, T - mnemonic_v := MN_MOV_T; - - -- Mnemonic MOVD_A_PP --------------------------------------------------- - when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp - mnemonic_v := MN_MOVD_A_PP; - multi_cycle_v := true; - - -- Mnemonic MOVP -------------------------------------------------------- - when "10100011" | -- MOVP A, @ A - "11100011" => -- MOVP3 A, @ A - mnemonic_v := MN_MOVP; - multi_cycle_v := true; - - -- Mnemonic MOVX -------------------------------------------------------- - when "10000000" | "10000001" | -- MOVX A, @ Rr - "10010000" | "10010001" => -- MOVX @ Rr, A - mnemonic_v := MN_MOVX; - multi_cycle_v := true; - - -- Mnemonic NOP --------------------------------------------------------- - when "00000000" => -- NOP - mnemonic_v := MN_NOP; - - -- Mnemonic ORL --------------------------------------------------------- - when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr - "01001100" | "01001101" | "01001110" | "01001111" | -- - "01000000" | "01000001" => -- ORL A, @ Rr - mnemonic_v := MN_ORL; - - -- Mnemonic ORL_A_DATA -------------------------------------------------- - when "01000011" => -- ORL A, data - mnemonic_v := MN_ORL_A_DATA; - multi_cycle_v := true; - - -- Mnemonic ORL_EXT ----------------------------------------------------- - when "10001000" | -- ORL BUS, data - "10001001" | "10001010" => -- ORL Pp, data - mnemonic_v := MN_ORL_EXT; - multi_cycle_v := true; - - -- Mnemonic OUTD_PP_A --------------------------------------------------- - when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A - "10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A - "10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A - mnemonic_v := MN_OUTD_PP_A; - multi_cycle_v := true; - - -- Mnemonic OUTL_EXT ---------------------------------------------------- - when "00111001" | "00111010" | -- OUTL Pp, A - "00000010" => -- OUTL BUS, A - mnemonic_v := MN_OUTL_EXT; - multi_cycle_v := true; - - -- Mnemonic RET --------------------------------------------------------- - when "10000011" | -- RET - "10010011" => -- RETR - mnemonic_v := MN_RET; - multi_cycle_v := true; - - -- Mnemonic RL ---------------------------------------------------------- - when "11100111" | -- RL A - "11110111" => -- RLC A - mnemonic_v := MN_RL; - - -- Mnemonic RR ---------------------------------------------------------- - when "01110111" | -- RR A - "01100111" => -- RRC A - mnemonic_v := MN_RR; - - -- Mnemonic SEL_MB ------------------------------------------------------ - when "11100101" | -- SEL MB0 - "11110101" => -- SEL MB1 - mnemonic_v := MN_SEL_MB; - - -- Mnemonic SEL_RB ------------------------------------------------------ - when "11000101" | -- SEL RB0 - "11010101" => -- SEL RB1 - mnemonic_v := MN_SEL_RB; - - -- Mnemonic STOP_TCNT --------------------------------------------------- - when "01100101" => -- STOP TCNT - mnemonic_v := MN_STOP_TCNT; - - -- Mnemonic START ------------------------------------------------------- - when "01000101" | -- STRT CNT - "01010101" => -- STRT T - mnemonic_v := MN_STRT; - - -- Mnemonic SWAP -------------------------------------------------------- - when "01000111" => -- SWAP A - mnemonic_v := MN_SWAP; - - -- Mnemonic XCH --------------------------------------------------------- - when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr - "00101100" | "00101101" | "00101110" | "00101111" | -- - "00100000" | "00100001" | -- XCH A, @ Rr - "00110000" | "00110001" => -- XCHD A, @ Rr - mnemonic_v := MN_XCH; - - -- Mnemonic XRL --------------------------------------------------------- - when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr - "11011100" | "11011101" | "11011110" | "11011111" | -- - "11010000" | "11010001" => -- XRL A, @ Rr - mnemonic_v := MN_XRL; - - -- Mnemonic XRL_A_DATA -------------------------------------------------- - when "11010011" => -- XRL A, data - mnemonic_v := MN_XRL_A_DATA; - multi_cycle_v := true; - - when others => - -- pragma translate_off - assert now = 0 ns - report "Unknown opcode." - severity warning; - -- pragma translate_on - - end case; - - result_v.mnemonic := mnemonic_v; - result_v.multi_cycle := multi_cycle_v; - - return result_v; - end; - -end t48_decoder_pack;

t48/rel_1_2/rtl/vhdl/decoder_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/dmem_ctrl_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/dmem_ctrl_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/dmem_ctrl_pack-p.vhd (nonexistent) @@ -1,21 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -package t48_dmem_ctrl_pack is - - ----------------------------------------------------------------------------- - -- Address Type Identifier - ----------------------------------------------------------------------------- - type dmem_addr_ident_t is (DM_PLAIN, - DM_REG, - DM_STACK, - DM_STACK_HIGH); - -end t48_dmem_ctrl_pack;

t48/rel_1_2/rtl/vhdl/dmem_ctrl_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/p2-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/p2-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/p2-c.vhd (nonexistent) @@ -1,17 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Port 2 unit. --- Implements the Port 2 logic. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_p2_rtl_c0 of t48_p2 is - - for rtl - end for; - -end t48_p2_rtl_c0;

t48/rel_1_2/rtl/vhdl/p2-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/alu-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/alu-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/alu-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Arithmetic Logic Unit (ALU). --- It contains the ALU core plus the Accumulator and the Temp Reg. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_alu_rtl_c0 of t48_alu is - - for rtl - end for; - -end t48_alu_rtl_c0;

t48/rel_1_2/rtl/vhdl/alu-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t48_system_comp_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t48_system_comp_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t48_system_comp_pack-p.vhd (nonexistent) @@ -1,177 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package t48_system_comp_pack is - - component t48_wb_master - port ( - xtal_i : in std_logic; - res_i : in std_logic; - en_clk_o : out std_logic; - ale_i : in std_logic; - rd_n_i : in std_logic; - wr_n_i : in std_logic; - adr_i : in std_logic; - db_bus_i : in std_logic_vector( 7 downto 0); - db_bus_o : out std_logic_vector( 7 downto 0); - wb_cyc_o : out std_logic; - wb_stb_o : out std_logic; - wb_we_o : out std_logic; - wb_adr_o : out std_logic_vector(23 downto 0); - wb_ack_i : in std_logic; - wb_dat_i : in std_logic_vector( 7 downto 0); - wb_dat_o : out std_logic_vector( 7 downto 0) - ); - end component; - - component t8048_notri - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic - ); - end component; - - component t8039_notri - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic - ); - end component; - - component t8050_wb - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic; - wb_cyc_o : out std_logic; - wb_stb_o : out std_logic; - wb_we_o : out std_logic; - wb_adr_o : out std_logic_vector(23 downto 0); - wb_ack_i : in std_logic; - wb_dat_i : in std_logic_vector( 7 downto 0); - wb_dat_o : out std_logic_vector( 7 downto 0) - ); - end component; - - component t8048 - port ( - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_b : inout std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_b : inout std_logic_vector( 7 downto 0); - t1_i : in std_logic; - p2_b : inout std_logic_vector( 7 downto 0); - p1_b : inout std_logic_vector( 7 downto 0); - prog_n_o : out std_logic - ); - end component; - - component t8039 - port ( - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_b : inout std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_b : inout std_logic_vector( 7 downto 0); - t1_i : in std_logic; - p2_b : inout std_logic_vector( 7 downto 0); - p1_b : inout std_logic_vector( 7 downto 0); - prog_n_o : out std_logic - ); - end component; - -end t48_system_comp_pack;

t48/rel_1_2/rtl/vhdl/system/t48_system_comp_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-a.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-a.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-a.vhd (nonexistent) @@ -1,65 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x48 ROM --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -architecture struct of t48_rom is - - component rom_t48 - port( - Clk : in std_logic; - A : in std_logic_vector(9 downto 0); - D : out std_logic_vector(7 downto 0) - ); - end component; - -begin - - rom_b : rom_t48 - port map ( - Clk => clk_i, - A => rom_addr_i, - D => rom_data_o - ); - -end struct;

t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-a.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-a.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-a.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-a.vhd (nonexistent) @@ -1,65 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x49 ROM --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -architecture struct of t49_rom is - - component rom_t49 - port( - Clk : in std_logic; - A : in std_logic_vector(10 downto 0); - D : out std_logic_vector( 7 downto 0) - ); - end component; - -begin - - rom_b : rom_t49 - port map ( - Clk => clk_i, - A => rom_addr_i, - D => rom_data_o - ); - -end struct;

t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-a.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/generic_ram_ena.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/generic_ram_ena.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/generic_ram_ena.vhd (nonexistent) @@ -1,100 +0,0 @@ -------------------------------------------------------------------------------- --- --- Parametrizable, generic RAM with enable. --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity generic_ram_ena is - - generic ( - addr_width_g : integer := 10; - data_width_g : integer := 8 - ); - port ( - clk_i : in std_logic; - a_i : in std_logic_vector(addr_width_g-1 downto 0); - we_i : in std_logic; - ena_i : in std_logic; - d_i : in std_logic_vector(data_width_g-1 downto 0); - d_o : out std_logic_vector(data_width_g-1 downto 0) - ); - -end generic_ram_ena; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of generic_ram_ena is - - type mem_t is array (natural range 0 to 2**addr_width_g-1) of - std_logic_vector(d_i'range); - signal mem_q : mem_t - -- pragma translate_off - := (others => (others => '0')) - -- pragma translate_on - ; - signal a_q : std_logic_vector(a_i'range); - -begin - - mem: process (clk_i) - begin - - if clk_i'event and clk_i = '1' then - if ena_i = '1' then - if we_i = '1' then - mem_q(to_integer(unsigned(a_i))) <= d_i; - end if; - - a_q <= a_i; - end if; - - end if; - end process mem; - - d_o <= mem_q(to_integer(unsigned(a_q))); - -end rtl;

t48/rel_1_2/rtl/vhdl/system/generic_ram_ena.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-c.vhd (nonexistent) @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x48 ROM --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_rom_struct_c0 of t48_rom is - - for struct - - for rom_b: rom_t48 - use configuration work.rom_t48_rtl_c0; - end for; - - end for; - -end t48_rom_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t48_rom-struct-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-c.vhd (nonexistent) @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x49 ROM --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t49_rom_struct_c0 of t49_rom is - - for struct - - for rom_b: rom_t49 - use configuration work.rom_t49_rtl_c0; - end for; - - end for; - -end t49_rom_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t49_rom-struct-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8039_notri.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8039_notri.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8039_notri.vhd (nonexistent) @@ -1,204 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8039 Microcontroller System --- 8039 toplevel without tri-states --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8039_notri is - - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic - ); - -end t8039_notri; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_core_comp_pack.t48_core; -use work.t48_core_comp_pack.generic_ram_ena; - -architecture struct of t8039_notri is - - signal xtal3_s : std_logic; - signal dmem_addr_s : std_logic_vector( 7 downto 0); - signal dmem_we_s : std_logic; - signal dmem_data_from_s : std_logic_vector( 7 downto 0); - signal dmem_data_to_s : std_logic_vector( 7 downto 0); - signal pmem_data_s : std_logic_vector( 7 downto 0); - - signal p1_in_s, - p1_out_s : std_logic_vector( 7 downto 0); - signal p2_in_s, - p2_out_s : std_logic_vector( 7 downto 0); - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - ----------------------------------------------------------------------------- - -- Check generics for valid values. - ----------------------------------------------------------------------------- - -- pragma translate_off - assert gate_port_input_g = 0 or gate_port_input_g = 1 - report "gate_port_input_g must be either 1 or 0!" - severity failure; - -- pragma translate_on - - - -- no Program memory available - pmem_data_s <= (others => '0'); - - - t48_core_b : t48_core - generic map ( - xtal_div_3_g => 1, - register_mnemonic_g => 1, - include_port1_g => 1, - include_port2_g => 1, - include_bus_g => 1, - include_timer_g => 1, - sample_t1_state_g => 4 - ) - port map ( - xtal_i => xtal_i, - xtal_en_i => xtal_en_i, - reset_i => reset_n_i, - t0_i => t0_i, - t0_o => t0_o, - t0_dir_o => t0_dir_o, - int_n_i => int_n_i, - ea_i => ea_i, - rd_n_o => rd_n_o, - psen_n_o => psen_n_o, - wr_n_o => wr_n_o, - ale_o => ale_o, - db_i => db_i, - db_o => db_o, - db_dir_o => db_dir_o, - t1_i => t1_i, - p2_i => p2_in_s, - p2_o => p2_out_s, - p2l_low_imp_o => p2l_low_imp_o, - p2h_low_imp_o => p2h_low_imp_o, - p1_i => p1_in_s, - p1_o => p1_out_s, - p1_low_imp_o => p1_low_imp_o, - prog_n_o => prog_n_o, - clk_i => xtal_i, - en_clk_i => xtal3_s, - xtal3_o => xtal3_s, - dmem_addr_o => dmem_addr_s, - dmem_we_o => dmem_we_s, - dmem_data_i => dmem_data_from_s, - dmem_data_o => dmem_data_to_s, - pmem_addr_o => open, - pmem_data_i => pmem_data_s - ); - - - ----------------------------------------------------------------------------- - -- Gate port 1 and 2 input bus with respetive output value - ----------------------------------------------------------------------------- - gate_ports: if gate_port_input_g = 1 generate - p1_in_s <= p1_i and p1_out_s; - p2_in_s <= p2_i and p2_out_s; - end generate; - - pass_ports: if gate_port_input_g = 0 generate - p1_in_s <= p1_i; - p2_in_s <= p2_i; - end generate; - - p1_o <= p1_out_s; - p2_o <= p2_out_s; - - - ram_128_b : generic_ram_ena - generic map ( - addr_width_g => 7, - data_width_g => 8 - ) - port map ( - clk_i => xtal_i, - a_i => dmem_addr_s(6 downto 0), - we_i => dmem_we_s, - ena_i => vdd_s, - d_i => dmem_data_to_s, - d_o => dmem_data_from_s - ); - -end struct;

t48/rel_1_2/rtl/vhdl/system/t8039_notri.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8048_notri.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8048_notri.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8048_notri.vhd (nonexistent) @@ -1,244 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- 8048 toplevel without tri-states --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8048_notri is - - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - xtal_i : in std_logic; - xtal_en_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_i : in std_logic_vector( 7 downto 0); - db_o : out std_logic_vector( 7 downto 0); - db_dir_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic - ); - -end t8048_notri; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_core_comp_pack.t48_core; -use work.t48_core_comp_pack.t48_rom; -use work.t48_core_comp_pack.generic_ram_ena; - -architecture struct of t8048_notri is - - -- Address width of internal ROM - constant rom_addr_width_c : natural := 10; - - signal xtal3_s : std_logic; - signal dmem_addr_s : std_logic_vector( 7 downto 0); - signal dmem_we_s : std_logic; - signal dmem_data_from_s : std_logic_vector( 7 downto 0); - signal dmem_data_to_s : std_logic_vector( 7 downto 0); - signal pmem_addr_s : std_logic_vector(11 downto 0); - signal pmem_data_s : std_logic_vector( 7 downto 0); - - signal ea_s : std_logic; - - signal p1_in_s, - p1_out_s : std_logic_vector( 7 downto 0); - signal p2_in_s, - p2_out_s : std_logic_vector( 7 downto 0); - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - ----------------------------------------------------------------------------- - -- Check generics for valid values. - ----------------------------------------------------------------------------- - -- pragma translate_off - assert gate_port_input_g = 0 or gate_port_input_g = 1 - report "gate_port_input_g must be either 1 or 0!" - severity failure; - -- pragma translate_on - - - t48_core_b : t48_core - generic map ( - xtal_div_3_g => 1, - register_mnemonic_g => 1, - include_port1_g => 1, - include_port2_g => 1, - include_bus_g => 1, - include_timer_g => 1, - sample_t1_state_g => 4 - ) - port map ( - xtal_i => xtal_i, - xtal_en_i => xtal_en_i, - reset_i => reset_n_i, - t0_i => t0_i, - t0_o => t0_o, - t0_dir_o => t0_dir_o, - int_n_i => int_n_i, - ea_i => ea_s, - rd_n_o => rd_n_o, - psen_n_o => psen_n_o, - wr_n_o => wr_n_o, - ale_o => ale_o, - db_i => db_i, - db_o => db_o, - db_dir_o => db_dir_o, - t1_i => t1_i, - p2_i => p2_in_s, - p2_o => p2_out_s, - p2l_low_imp_o => p2l_low_imp_o, - p2h_low_imp_o => p2h_low_imp_o, - p1_i => p1_in_s, - p1_o => p1_out_s, - p1_low_imp_o => p1_low_imp_o, - prog_n_o => prog_n_o, - clk_i => xtal_i, - en_clk_i => xtal3_s, - xtal3_o => xtal3_s, - dmem_addr_o => dmem_addr_s, - dmem_we_o => dmem_we_s, - dmem_data_i => dmem_data_from_s, - dmem_data_o => dmem_data_to_s, - pmem_addr_o => pmem_addr_s, - pmem_data_i => pmem_data_s - ); - - - ----------------------------------------------------------------------------- - -- Gate port 1 and 2 input bus with respetive output value - ----------------------------------------------------------------------------- - gate_ports: if gate_port_input_g = 1 generate - p1_in_s <= p1_i and p1_out_s; - p2_in_s <= p2_i and p2_out_s; - end generate; - - pass_ports: if gate_port_input_g = 0 generate - p1_in_s <= p1_i; - p2_in_s <= p2_i; - end generate; - - p1_o <= p1_out_s; - p2_o <= p2_out_s; - - - ----------------------------------------------------------------------------- - -- Process ea - -- - -- Purpose: - -- Detects access to external program memory. - -- Either by ea_i = '1' or when program memory address leaves address - -- range of internal ROM. - -- - ea: process (ea_i, - pmem_addr_s) - begin - if ea_i = '1' then - -- Forced external access - ea_s <= '1'; - - elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then - -- Internal access - ea_s <= '0'; - - else - -- Access to program memory out of internal range - ea_s <= '1'; - - end if; - - end process ea; - -- - ----------------------------------------------------------------------------- - - - rom_1k_b : t48_rom - port map ( - clk_i => xtal_i, - rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), - rom_data_o => pmem_data_s - ); - - ram_64_b : generic_ram_ena - generic map ( - addr_width_g => 6, - data_width_g => 8 - ) - port map ( - clk_i => xtal_i, - a_i => dmem_addr_s(5 downto 0), - we_i => dmem_we_s, - ena_i => vdd_s, - d_i => dmem_data_to_s, - d_o => dmem_data_from_s - ); - -end struct;

t48/rel_1_2/rtl/vhdl/system/t8048_notri.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/wb_master-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/wb_master-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/wb_master-c.vhd (nonexistent) @@ -1,18 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Wishbone master module. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_wb_master_rtl_c0 of t48_wb_master is - - for rtl - end for; - -end t48_wb_master_rtl_c0;

t48/rel_1_2/rtl/vhdl/system/wb_master-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/lpm_rom.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/lpm_rom.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/lpm_rom.vhd (nonexistent) @@ -1,437 +0,0 @@ --------------------------------------------------------------------------- --- This VHDL file was developed by Altera Corporation. It may be --- freely copied and/or distributed at no cost. Any persons using this --- file for any purpose do so at their own risk, and are responsible for --- the results of such use. Altera Corporation does not guarantee that --- this file is complete, correct, or fit for any particular purpose. --- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must --- accompany any copy of this file. --- --------------------------------------------------------------------------- --- LPM Synthesizable Models (Support string type generic) --------------------------------------------------------------------------- --- Version 2.0 (lpm 220) Date 01/04/00 --- --- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly --- read in values from LPM_FILE (*.hex) when the DATA width is greater --- than 16 bits. --- 2. Explicit sign conversions are added to standard logic vector --- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and --- LPM_COMPARE. --- 3. LPM_FIFO_DC is rewritten to have correct outputs. --- 4. LPM_FIFO outputs zeros when nothing has been read from it, and --- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full. --- 5. Fixed LPM_DIVIDE to divide correctly. --------------------------------------------------------------------------- --- Version 1.9 (lpm 220) Date 11/30/99 --- --- 1. Fixed UNUSED file not found problem and initialization problem --- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO. --- 2. Fixed LPM_MULT when SUM port is not used. --- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise --- at the same time. --- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded --- and counter is incrementing. --- 5. Got rid of "Illegal Character" error message at time = 0 ns when --- simulating LPM_COUNTER. --------------------------------------------------------------------------- --- Version 1.8 (lpm 220) Date 10/25/99 --- --- 1. Some LPM_PVALUE implementations were missing, and now implemented. --- 2. Fixed LPM_COUNTER to count correctly without conversion overflow, --- that is, when LPM_MODULUS = 2 ** LPM_WIDTH. --- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress --- changes. --------------------------------------------------------------------------- --- Version 1.7 (lpm 220) Date 07/13/99 --- --- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and --- Quartus behaviour and LPM220-compliant behaviour. --------------------------------------------------------------------------- --- Version 1.6 (lpm 220) Date 06/15/99 --- --- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug. --- 2. Fixed LPM_COUNTER to use LPM_MODULUS value. --- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to --- comply with the specfication. --- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and --- LPM_FIFO_DC; they are all initialized to 0's. --------------------------------------------------------------------------- --- Version 1.5 (lpm 220) Date 05/10/99 --- --- Changed LPM_MODULUS from string type to integer. --------------------------------------------------------------------------- --- Version 1.4 (lpm 220) Date 02/05/99 --- --- 1. Added LPM_DIVIDE module. --- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT --- and LPM_COMPARE --- 3. Replaced the constants holding string with the actual string. --------------------------------------------------------------------------- --- Version 1.3 Date 07/30/96 --- --- Modification History --- --- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE, --- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION, --- and LPM_PVALUE --- --- 2. Added the two dimentional port components (AND, OR, XOR, and MUX). --------------------------------------------------------------------------- --- Excluded Functions: --- --- LPM_FSM and LPM_TTABLE --- --------------------------------------------------------------------------- --- Assumptions: --- --- 1. All ports and signal types are std_logic or std_logic_vector --- from IEEE 1164 package. --- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed --- package are assumed to be accessible from IEEE library. --- 3. lpm_component_package must be accessible from library work. --- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT, --- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is --- string "UNUSED". --------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; ---use work.LPM_COMPONENTS.all; -use std.textio.all; - -entity LPM_ROM is - generic (LPM_WIDTH : positive; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_ADDRESS_CONTROL : string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_FILE : string; - LPM_TYPE : string := "LPM_ROM"; - LPM_HINT : string := "UNUSED"); - port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); - INCLOCK : in STD_LOGIC := '0'; - OUTCLOCK : in STD_LOGIC := '0'; - MEMENAB : in STD_LOGIC := '1'; - Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)); - - function int_to_str( value : integer ) return string is - variable ivalue,index : integer; - variable digit : integer; - variable line_no: string(8 downto 1) := " "; - begin - ivalue := value; - index := 1; - while (ivalue > 0 ) loop - digit := ivalue MOD 10; - ivalue := ivalue/10; - case digit is - when 0 => - line_no(index) := '0'; - when 1 => - line_no(index) := '1'; - when 2 => - line_no(index) := '2'; - when 3 => - line_no(index) := '3'; - when 4 => - line_no(index) := '4'; - when 5 => - line_no(index) := '5'; - when 6 => - line_no(index) := '6'; - when 7 => - line_no(index) := '7'; - when 8 => - line_no(index) := '8'; - when 9 => - line_no(index) := '9'; - when others => - ASSERT FALSE - REPORT "Illegal number!" - SEVERITY ERROR; - end case; - index := index + 1; - end loop; - return line_no; - end; - - function hex_str_to_int( str : string ) return integer is - variable len : integer := str'length; - variable ivalue : integer := 0; - variable digit : integer; - begin - for i in len downto 1 loop - case str(i) is - when '0' => - digit := 0; - when '1' => - digit := 1; - when '2' => - digit := 2; - when '3' => - digit := 3; - when '4' => - digit := 4; - when '5' => - digit := 5; - when '6' => - digit := 6; - when '7' => - digit := 7; - when '8' => - digit := 8; - when '9' => - digit := 9; - when 'A' => - digit := 10; - when 'a' => - digit := 10; - when 'B' => - digit := 11; - when 'b' => - digit := 11; - when 'C' => - digit := 12; - when 'c' => - digit := 12; - when 'D' => - digit := 13; - when 'd' => - digit := 13; - when 'E' => - digit := 14; - when 'e' => - digit := 14; - when 'F' => - digit := 15; - when 'f' => - digit := 15; - when others => - ASSERT FALSE - REPORT "Illegal character "& str(i) & "in Intel Hex File! " - SEVERITY ERROR; - end case; - ivalue := ivalue * 16 + digit; - end loop; - return ivalue; - end; - - procedure Shrink_line(L : inout LINE; pos : in integer) is - subtype nstring is string(1 to pos); - variable stmp : nstring; - begin - if pos >= 1 then - read(l, stmp); - end if; - end; - -end LPM_ROM; - -architecture LPM_SYN of lpm_rom is - ---type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); -type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); - -signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0); -signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0); - -begin - - enable_mem: process(memenab, q2) - begin - if (memenab = '1') then - q <= q2; - else - q <= (OTHERS => 'Z'); - end if; - end process; - - sync: process(address, address_reg, q_tmp, q_reg) - begin - if (lpm_address_control = "REGISTERED") then - address_tmp <= address_reg; - else - address_tmp <= address; - end if; - if (lpm_outdata = "REGISTERED") then - q2 <= q_reg; - else - q2 <= q_tmp; - end if; - end process; - - input_reg: process (inclock) - begin - if inclock'event and inclock = '1' then - address_reg <= address; - end if; - end process; - - output_reg: process (outclock) - begin - if outclock'event and outclock = '1' then - q_reg <= q_tmp; - end if; - end process; - - memory: process(memenab, address_tmp) - variable mem_data : lpm_memory; - variable mem_data_tmp : integer := 0; - variable mem_init: boolean := false; - variable i, j, k, lineno : integer := 0; - variable buf: line ; - variable booval: boolean ; - FILE mem_data_file: TEXT IS IN LPM_FILE; - variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1); - variable startadd: string(4 downto 1); - variable ibase: integer := 0; - variable ibyte: integer := 0; - variable istartadd: integer := 0; - variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0); - begin - -- INITIALIZE -- - if NOT(mem_init) then - -- INITIALIZE TO 0 -- - for i in mem_data'LOW to mem_data'HIGH loop - mem_data(i) := (OTHERS => '0'); - end loop; - - if (LPM_FILE = "UNUSED") then - ASSERT FALSE - REPORT "Initialization file not found!" - SEVERITY ERROR; - else - WHILE NOT ENDFILE(mem_data_file) loop - booval := true; - READLINE(mem_data_file, buf); - lineno := lineno + 1; - check_sum_vec := (OTHERS => '0'); - if (buf(buf'LOW) = ':') then - i := 1; - shrink_line(buf, i); - READ(L=>buf, VALUE=>byte, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!" - SEVERITY ERROR; - end if; - ibyte := hex_str_to_int(byte); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, 8); - READ(L=>buf, VALUE=>startadd, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - istartadd := hex_str_to_int(startadd); - addr(2) := startadd(4); - addr(1) := startadd(3); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); - addr(2) := startadd(2); - addr(1) := startadd(1); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); - READ(L=>buf, VALUE=>rec_type, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length); - else - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - case rec_type is - when "00"=> -- Data record - i := 0; - k := lpm_width / 8; - if ((lpm_width MOD 8) /= 0) then - k := k + 1; - end if; - -- k = no. of bytes per CAM entry. - while (i < ibyte) loop - mem_data_tmp := 0; - for j in 1 to k loop - READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time. - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length); - mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain); - end loop; - i := i + k; - mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width)); - istartadd := istartadd + 1; - end loop; - when "01"=> - exit; - when "02"=> - ibase := 0; - if (ibyte /= 2) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! " - SEVERITY ERROR; - end if; - for i in 0 to (ibyte-1) loop - READ(L=>buf, VALUE=>base,good=>booval); - ibase := ibase * 256 + hex_str_to_int(base); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length); - end loop; - ibase := ibase * 16; - when OTHERS => - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! " - SEVERITY ERROR; - end case; - READ(L=>buf, VALUE=>checksum,good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! " - SEVERITY ERROR; - end if; - - check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; - check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum),8); - - if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!" - SEVERITY ERROR; - end if; - end loop; - end if; - mem_init := TRUE; - end if; - - -- MEMORY FUNCTION -- - --if memenab = '1' then - q_tmp <= mem_data(to_integer(UNSIGNED(address_tmp))); - --else - -- q_tmp <= (OTHERS => 'Z'); - --end if; - end process; - -end LPM_SYN; - - ---------------------------------------------------------------------------- - - --- pragma translate_off -configuration lpm_rom_c0 of lpm_rom is - - for lpm_syn - end for; - -end lpm_rom_c0; --- pragma translate_on

t48/rel_1_2/rtl/vhdl/system/lpm_rom.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8039-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8039-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8039-c.vhd (nonexistent) @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8039 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t8039_struct_c0 of t8039 is - - for struct - - for t8039_notri_b : t8039_notri - use configuration work.t8039_notri_struct_c0; - end for; - - end for; - -end t8039_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t8039-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8048-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8048-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8048-c.vhd (nonexistent) @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t8048_struct_c0 of t8048 is - - for struct - - for t8048_notri_b : t8048_notri - use configuration work.t8048_notri_struct_c0; - end for; - - end for; - -end t8048_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t8048-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8050_wb.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8050_wb.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8050_wb.vhd (nonexistent) @@ -1,290 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- 8050 toplevel with Wishbone interface --- --- $Id$ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8050_wb is - - generic ( - gate_port_input_g : integer := 1 - ); - - port ( - -- T48 Interface ---------------------------------------------------------- - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_i : in std_logic; - t0_o : out std_logic; - t0_dir_o : out std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - t1_i : in std_logic; - p2_i : in std_logic_vector( 7 downto 0); - p2_o : out std_logic_vector( 7 downto 0); - p2l_low_imp_o : out std_logic; - p2h_low_imp_o : out std_logic; - p1_i : in std_logic_vector( 7 downto 0); - p1_o : out std_logic_vector( 7 downto 0); - p1_low_imp_o : out std_logic; - prog_n_o : out std_logic; - -- Wishbone Interface ----------------------------------------------------- - wb_cyc_o : out std_logic; - wb_stb_o : out std_logic; - wb_we_o : out std_logic; - wb_adr_o : out std_logic_vector(23 downto 0); - wb_ack_i : in std_logic; - wb_dat_i : in std_logic_vector( 7 downto 0); - wb_dat_o : out std_logic_vector( 7 downto 0) - - ); - -end t8050_wb; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_core_comp_pack.t48_core; -use work.t48_core_comp_pack.syn_rom; -use work.t48_core_comp_pack.syn_ram; -use work.t48_system_comp_pack.t48_wb_master; - -architecture struct of t8050_wb is - - -- Address width of internal ROM - constant rom_addr_width_c : natural := 12; - - signal xtal3_s : std_logic; - signal dmem_addr_s : std_logic_vector( 7 downto 0); - signal dmem_we_s : std_logic; - signal dmem_data_from_s : std_logic_vector( 7 downto 0); - signal dmem_data_to_s : std_logic_vector( 7 downto 0); - signal pmem_addr_s : std_logic_vector(11 downto 0); - signal pmem_data_s : std_logic_vector( 7 downto 0); - - signal ea_s : std_logic; - - signal ale_s : std_logic; - signal wr_n_s : std_logic; - signal rd_n_s : std_logic; - signal db_bus_to_t48, - db_bus_from_t48 : std_logic_vector( 7 downto 0); - - signal wb_en_clk_s : std_logic; - signal xtal_en_s : std_logic; - - signal p1_in_s, - p1_out_s : std_logic_vector( 7 downto 0); - signal p2_in_s, - p2_out_s : std_logic_vector( 7 downto 0); - -begin - - ----------------------------------------------------------------------------- - -- Check generics for valid values. - ----------------------------------------------------------------------------- - -- pragma translate_off - assert gate_port_input_g = 0 or gate_port_input_g = 1 - report "gate_port_input_g must be either 1 or 0!" - severity failure; - -- pragma translate_on - - - t48_core_b : t48_core - generic map ( - xtal_div_3_g => 1, - register_mnemonic_g => 1, - include_port1_g => 1, - include_port2_g => 1, - include_bus_g => 1, - include_timer_g => 1, - sample_t1_state_g => 4 - ) - port map ( - xtal_i => xtal_i, - xtal_en_i => xtal_en_s, - reset_i => reset_n_i, - t0_i => t0_i, - t0_o => t0_o, - t0_dir_o => t0_dir_o, - int_n_i => int_n_i, - ea_i => ea_s, - rd_n_o => rd_n_s, - psen_n_o => psen_n_o, - wr_n_o => wr_n_s, - ale_o => ale_s, - db_i => db_bus_to_t48, - db_o => db_bus_from_t48, - db_dir_o => open, - t1_i => t1_i, - p2_i => p2_in_s, - p2_o => p2_out_s, - p2l_low_imp_o => p2l_low_imp_o, - p2h_low_imp_o => p2h_low_imp_o, - p1_i => p1_in_s, - p1_o => p1_out_s, - p1_low_imp_o => p1_low_imp_o, - prog_n_o => prog_n_o, - clk_i => xtal_i, - en_clk_i => xtal3_s, - xtal3_o => xtal3_s, - dmem_addr_o => dmem_addr_s, - dmem_we_o => dmem_we_s, - dmem_data_i => dmem_data_from_s, - dmem_data_o => dmem_data_to_s, - pmem_addr_o => pmem_addr_s, - pmem_data_i => pmem_data_s - ); - - - ----------------------------------------------------------------------------- - -- Gate port 1 and 2 input bus with respetive output value - ----------------------------------------------------------------------------- - gate_ports: if gate_port_input_g = 1 generate - p1_in_s <= p1_i and p1_out_s; - p2_in_s <= p2_i and p2_out_s; - end generate; - - pass_ports: if gate_port_input_g = 0 generate - p1_in_s <= p1_i; - p2_in_s <= p2_i; - end generate; - - p1_o <= p1_out_s; - p2_o <= p2_out_s; - - ale_o <= ale_s; - wr_n_o <= wr_n_s; - rd_n_o <= rd_n_s; - - - ----------------------------------------------------------------------------- - -- Generate clock enable - ----------------------------------------------------------------------------- - xtal_en_s <= wb_en_clk_s; - - - ----------------------------------------------------------------------------- - -- Process ea - -- - -- Purpose: - -- Detects access to external program memory. - -- Either by ea_i = '1' or when program memory address leaves address - -- range of internal ROM. - -- - ea: process (ea_i, - pmem_addr_s) - begin - if ea_i = '1' then - -- Forced external access - ea_s <= '1'; - --- elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then - else - -- Internal access - ea_s <= '0'; - --- else --- -- Access to program memory out of internal range --- ea_s <= '1'; - - end if; - - end process ea; - -- - ----------------------------------------------------------------------------- - - - wb_master_b : t48_wb_master - port map ( - xtal_i => xtal_i, - res_i => reset_n_i, - en_clk_o => wb_en_clk_s, - ale_i => ale_s, - rd_n_i => rd_n_s, - wr_n_i => wr_n_s, - adr_i => p2_out_s(4), - db_bus_i => db_bus_from_t48, - db_bus_o => db_bus_to_t48, - wb_cyc_o => wb_cyc_o, - wb_stb_o => wb_stb_o, - wb_we_o => wb_we_o, - wb_adr_o => wb_adr_o, - wb_ack_i => wb_ack_i, - wb_dat_i => wb_dat_i, - wb_dat_o => wb_dat_o - ); - - - rom_4k_b : syn_rom - generic map ( - address_width_g => rom_addr_width_c - ) - port map ( - clk_i => xtal_i, - rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), - rom_data_o => pmem_data_s - ); - - ram_256_b : syn_ram - generic map ( - address_width_g => 8 - ) - port map ( - clk_i => xtal_i, - res_i => reset_n_i, - ram_addr_i => dmem_addr_s(7 downto 0), - ram_data_i => dmem_data_to_s, - ram_we_i => dmem_we_s, - ram_data_o => dmem_data_from_s - ); - -end struct;

t48/rel_1_2/rtl/vhdl/system/t8050_wb.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/lpm_ram_dq.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/lpm_ram_dq.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/lpm_ram_dq.vhd (nonexistent) @@ -1,439 +0,0 @@ --------------------------------------------------------------------------- --- This VHDL file was developed by Altera Corporation. It may be --- freely copied and/or distributed at no cost. Any persons using this --- file for any purpose do so at their own risk, and are responsible for --- the results of such use. Altera Corporation does not guarantee that --- this file is complete, correct, or fit for any particular purpose. --- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must --- accompany any copy of this file. --- --------------------------------------------------------------------------- --- LPM Synthesizable Models (Support string type generic) --------------------------------------------------------------------------- --- Version 2.0 (lpm 220) Date 01/04/00 --- --- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly --- read in values from LPM_FILE (*.hex) when the DATA width is greater --- than 16 bits. --- 2. Explicit sign conversions are added to standard logic vector --- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and --- LPM_COMPARE. --- 3. LPM_FIFO_DC is rewritten to have correct outputs. --- 4. LPM_FIFO outputs zeros when nothing has been read from it, and --- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full. --- 5. Fixed LPM_DIVIDE to divide correctly. --------------------------------------------------------------------------- --- Version 1.9 (lpm 220) Date 11/30/99 --- --- 1. Fixed UNUSED file not found problem and initialization problem --- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO. --- 2. Fixed LPM_MULT when SUM port is not used. --- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise --- at the same time. --- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded --- and counter is incrementing. --- 5. Got rid of "Illegal Character" error message at time = 0 ns when --- simulating LPM_COUNTER. --------------------------------------------------------------------------- --- Version 1.8 (lpm 220) Date 10/25/99 --- --- 1. Some LPM_PVALUE implementations were missing, and now implemented. --- 2. Fixed LPM_COUNTER to count correctly without conversion overflow, --- that is, when LPM_MODULUS = 2 ** LPM_WIDTH. --- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress --- changes. --------------------------------------------------------------------------- --- Version 1.7 (lpm 220) Date 07/13/99 --- --- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and --- Quartus behaviour and LPM220-compliant behaviour. --------------------------------------------------------------------------- --- Version 1.6 (lpm 220) Date 06/15/99 --- --- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug. --- 2. Fixed LPM_COUNTER to use LPM_MODULUS value. --- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to --- comply with the specfication. --- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and --- LPM_FIFO_DC; they are all initialized to 0's. --------------------------------------------------------------------------- --- Version 1.5 (lpm 220) Date 05/10/99 --- --- Changed LPM_MODULUS from string type to integer. --------------------------------------------------------------------------- --- Version 1.4 (lpm 220) Date 02/05/99 --- --- 1. Added LPM_DIVIDE module. --- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT --- and LPM_COMPARE --- 3. Replaced the constants holding string with the actual string. --------------------------------------------------------------------------- --- Version 1.3 Date 07/30/96 --- --- Modification History --- --- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE, --- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION, --- and LPM_PVALUE --- --- 2. Added the two dimentional port components (AND, OR, XOR, and MUX). --------------------------------------------------------------------------- --- Excluded Functions: --- --- LPM_FSM and LPM_TTABLE --- --------------------------------------------------------------------------- --- Assumptions: --- --- 1. All ports and signal types are std_logic or std_logic_vector --- from IEEE 1164 package. --- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed --- package are assumed to be accessible from IEEE library. --- 3. lpm_component_package must be accessible from library work. --- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT, --- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is --- string "UNUSED". --------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; ---use IEEE.std_logic_unsigned.all; -use std.textio.all; - -entity LPM_RAM_DQ is - generic (LPM_WIDTH : positive; - LPM_WIDTHAD : positive; - LPM_NUMWORDS : natural := 0; - LPM_INDATA : string := "REGISTERED"; - LPM_ADDRESS_CONTROL: string := "REGISTERED"; - LPM_OUTDATA : string := "REGISTERED"; - LPM_FILE : string := "UNUSED"; - LPM_TYPE : string := "LPM_RAM_DQ"; - LPM_HINT : string := "UNUSED"); - port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); - ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); - INCLOCK : in std_logic := '0'; - OUTCLOCK : in std_logic := '0'; - WE : in std_logic; - Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); - - function int_to_str( value : integer ) return string is - variable ivalue,index : integer; - variable digit : integer; - variable line_no: string(8 downto 1) := " "; - begin - ivalue := value; - index := 1; - while (ivalue > 0) loop - digit := ivalue MOD 10; - ivalue := ivalue/10; - case digit is - when 0 => - line_no(index) := '0'; - when 1 => - line_no(index) := '1'; - when 2 => - line_no(index) := '2'; - when 3 => - line_no(index) := '3'; - when 4 => - line_no(index) := '4'; - when 5 => - line_no(index) := '5'; - when 6 => - line_no(index) := '6'; - when 7 => - line_no(index) := '7'; - when 8 => - line_no(index) := '8'; - when 9 => - line_no(index) := '9'; - when others => - ASSERT FALSE - REPORT "Illegal number!" - SEVERITY ERROR; - end case; - index := index + 1; - end loop; - return line_no; - end; - - function hex_str_to_int( str : string ) return integer is - variable len : integer := str'length; - variable ivalue : integer := 0; - variable digit : integer; - begin - for i in len downto 1 loop - case str(i) is - when '0' => - digit := 0; - when '1' => - digit := 1; - when '2' => - digit := 2; - when '3' => - digit := 3; - when '4' => - digit := 4; - when '5' => - digit := 5; - when '6' => - digit := 6; - when '7' => - digit := 7; - when '8' => - digit := 8; - when '9' => - digit := 9; - when 'A' => - digit := 10; - when 'a' => - digit := 10; - when 'B' => - digit := 11; - when 'b' => - digit := 11; - when 'C' => - digit := 12; - when 'c' => - digit := 12; - when 'D' => - digit := 13; - when 'd' => - digit := 13; - when 'E' => - digit := 14; - when 'e' => - digit := 14; - when 'F' => - digit := 15; - when 'f' => - digit := 15; - when others => - ASSERT FALSE - REPORT "Illegal character "& str(i) & "in Intel Hex File! " - SEVERITY ERROR; - end case; - ivalue := ivalue * 16 + digit; - end loop; - return ivalue; - end; - - procedure Shrink_line(L : inout LINE; pos : in integer) is - subtype nstring is string(1 to pos); - variable stmp : nstring; - begin - if pos >= 1 then - read(l, stmp); - end if; - end; - -end LPM_RAM_DQ; - -architecture LPM_SYN of lpm_ram_dq is - ---type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); -type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); - -signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0); -signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0'); -signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0); -signal we_tmp, we_reg : std_logic; - -begin - - sync: process(data, data_reg, address, address_reg, - we, we_reg, q_tmp, q_reg) - begin - if (lpm_address_control = "REGISTERED") then - address_tmp <= address_reg; - we_tmp <= we_reg; - else - address_tmp <= address; - we_tmp <= we; - end if; - if (lpm_indata = "REGISTERED") then - data_tmp <= data_reg; - else - data_tmp <= data; - end if; - if (lpm_outdata = "REGISTERED") then - q <= q_reg; - else - q <= q_tmp; - end if; - end process; - - input_reg: process (inclock) - begin - if inclock'event and inclock = '1' then - data_reg <= data; - address_reg <= address; - we_reg <= we; - end if; - end process; - - output_reg: process (outclock) - begin - if outclock'event and outclock = '1' then - q_reg <= q_tmp; - end if; - end process; - - memory: process(data_tmp, we_tmp, address_tmp) - variable mem_data : lpm_memory; - variable mem_data_tmp : integer := 0; - variable mem_init: boolean := false; - variable i,j,k,lineno: integer := 0; - variable buf: line ; - variable booval: boolean ; - FILE unused_file: TEXT IS OUT "UNUSED"; - FILE mem_data_file: TEXT IS IN LPM_FILE; - variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1); - variable startadd: string(4 downto 1); - variable ibase: integer := 0; - variable ibyte: integer := 0; - variable istartadd: integer := 0; - variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0); - begin - -- INITIALIZE -- - if NOT(mem_init) then - -- INITIALIZE TO 0 -- - for i in mem_data'LOW to mem_data'HIGH loop - mem_data(i) := (OTHERS => '0'); - end loop; - - if (LPM_FILE = "UNUSED") then - ASSERT FALSE - REPORT "Initialization file not found!" - SEVERITY WARNING; - else - WHILE NOT ENDFILE(mem_data_file) loop - booval := true; - READLINE(mem_data_file, buf); - lineno := lineno + 1; - check_sum_vec := (OTHERS => '0'); - if (buf(buf'LOW) = ':') then - i := 1; - shrink_line(buf, i); - READ(L=>buf, VALUE=>byte, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!" - SEVERITY ERROR; - end if; - ibyte := hex_str_to_int(byte); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length); - READ(L=>buf, VALUE=>startadd, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - istartadd := hex_str_to_int(startadd); - addr(2) := startadd(4); - addr(1) := startadd(3); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); - addr(2) := startadd(2); - addr(1) := startadd(1); - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length); - READ(L=>buf, VALUE=>rec_type, good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length); - else - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - case rec_type is - when "00"=> -- Data record - i := 0; - k := lpm_width / 8; - if ((lpm_width MOD 8) /= 0) then - k := k + 1; - end if; - -- k = no. of bytes per CAM entry. - while (i < ibyte) loop - mem_data_tmp := 0; - for j in 1 to k loop - READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time. - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length); - mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain); - end loop; - i := i + k; - mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width)); - istartadd := istartadd + 1; - end loop; - when "01"=> - exit; - when "02"=> - ibase := 0; - if (ibyte /= 2) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! " - SEVERITY ERROR; - end if; - for i in 0 to (ibyte-1) loop - READ(L=>buf, VALUE=>base,good=>booval); - ibase := ibase * 256 + hex_str_to_int(base); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! " - SEVERITY ERROR; - end if; - check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length); - end loop; - ibase := ibase * 16; - when OTHERS => - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! " - SEVERITY ERROR; - end case; - READ(L=>buf, VALUE=>checksum,good=>booval); - if not (booval) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! " - SEVERITY ERROR; - end if; - - check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; - check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length); - - if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then - ASSERT FALSE - REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!" - SEVERITY ERROR; - end if; - end loop; - end if; - mem_init := TRUE; - end if; - - -- MEMORY FUNCTION -- - if we_tmp = '1' then - mem_data (to_integer(unsigned(address_tmp))) := data_tmp; - end if; - q_tmp <= mem_data(to_integer(unsigned(address_tmp))); - end process; - -end LPM_SYN; - - --- pragma translate_off -configuration lpm_ram_dq_c0 of lpm_ram_dq is - - for lpm_syn - end for; - -end lpm_ram_dq_c0; --- pragma translate_on

t48/rel_1_2/rtl/vhdl/system/lpm_ram_dq.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/generic_ram_ena-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/generic_ram_ena-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/generic_ram_ena-c.vhd (nonexistent) @@ -1,18 +0,0 @@ -------------------------------------------------------------------------------- --- --- Parametrizable, generic RAM with enable. --- --- $Id$ --- --- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration generic_ram_ena_rtl_c0 of generic_ram_ena is - - for rtl - end for; - -end generic_ram_ena_rtl_c0;

t48/rel_1_2/rtl/vhdl/system/generic_ram_ena-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t48_rom-e.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t48_rom-e.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t48_rom-e.vhd (nonexistent) @@ -1,57 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x48 ROM --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t48_rom is - - port ( - clk_i : in std_logic; - rom_addr_i : in std_logic_vector(9 downto 0); - rom_data_o : out std_logic_vector(7 downto 0) - ); - -end t48_rom;

t48/rel_1_2/rtl/vhdl/system/t48_rom-e.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t49_rom-e.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t49_rom-e.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t49_rom-e.vhd (nonexistent) @@ -1,57 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8x49 ROM --- --- $Id$ --- --- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t49_rom is - - port ( - clk_i : in std_logic; - rom_addr_i : in std_logic_vector(10 downto 0); - rom_data_o : out std_logic_vector( 7 downto 0) - ); - -end t49_rom;

t48/rel_1_2/rtl/vhdl/system/t49_rom-e.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8039_notri-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8039_notri-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8039_notri-c.vhd (nonexistent) @@ -1,28 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8039 Microcontroller System --- 8039 toplevel without tri-states --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t8039_notri_struct_c0 of t8039_notri is - - for struct - - for ram_128_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for t48_core_b : t48_core - use configuration work.t48_core_struct_c0; - end for; - - end for; - -end t8039_notri_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t8039_notri-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8048_notri-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8048_notri-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8048_notri-c.vhd (nonexistent) @@ -1,31 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t8048_notri_struct_c0 of t8048_notri is - - for struct - - for rom_1k_b : t48_rom - use configuration work.t48_rom_lpm_c0; - end for; - - for ram_64_b : generic_ram_ena - use configuration work.generic_ram_ena_rtl_c0; - end for; - - for t48_core_b : t48_core - use configuration work.t48_core_struct_c0; - end for; - - end for; - -end t8048_notri_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t8048_notri-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/wb_master.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/wb_master.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/wb_master.vhd (nonexistent) @@ -1,249 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Wishbone master module. --- --- $Id$ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- --- --- Short description: --- This design implements a simple Wishbone bus master. It connects to the --- BUS interface of the T48 uController core. --- --- The CPU clock is suppressed with en_clk_o to stall the CPU until the --- acknowledge signal from the peripheral is detected. --- --- The adr_i input selects between configuration and Wishbone address range: --- 1 - configuration range --- 0 - Wishbone range --- --- When configuration range is selected, two address register are accessible. --- 000h -> adr1 --- 001h -> adr2 --- These registers can be read and written with movx to their addresses. --- --- When Wishbone range is selected, all movx generate Wishbone bus cycles --- (either read or write) at following address: --- Wishbone address = adr2 & adr1 & address of movx --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.all; - -entity t48_wb_master is - - port ( - xtal_i : in std_logic; - res_i : in std_logic; - en_clk_o : out std_logic; - -- T48 Interface ---------------------------------------------------------- - ale_i : in std_logic; - rd_n_i : in std_logic; - wr_n_i : in std_logic; - adr_i : in std_logic; - db_bus_i : in std_logic_vector( 7 downto 0); - db_bus_o : out std_logic_vector( 7 downto 0); - -- Wishbone Interface ----------------------------------------------------- - wb_cyc_o : out std_logic; - wb_stb_o : out std_logic; - wb_we_o : out std_logic; - wb_adr_o : out std_logic_vector(23 downto 0); - wb_ack_i : in std_logic; - wb_dat_i : in std_logic_vector( 7 downto 0); - wb_dat_o : out std_logic_vector( 7 downto 0) - ); - -end t48_wb_master; - - -architecture rtl of t48_wb_master is - - ----------------------------------------------------------------------------- - -- Controller FSM - ----------------------------------------------------------------------------- - type state_t is (IDLE, CYC, WAIT_INACT); - signal state_s, - state_q : state_t; - - ----------------------------------------------------------------------------- - -- Select signals for each range - ----------------------------------------------------------------------------- - signal sel_adr1_s, - sel_adr2_s, - sel_wb_s : boolean; - - signal wr_s, - rd_s : boolean; - - signal adr_q : std_logic_vector(23 downto 0); - signal wb_dat_q : std_logic_vector( 7 downto 0); - -begin - - ----------------------------------------------------------------------------- - -- Select signal generation - ----------------------------------------------------------------------------- - sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000"; - sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001"; - sel_wb_s <= adr_i = '0'; - - wr_s <= wr_n_i = '0'; - rd_s <= rd_n_i = '0'; - - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements. - -- - seq: process (res_i, xtal_i) - begin - if res_i = res_active_c then - adr_q <= (others => '0'); - wb_dat_q <= (others => '0'); - state_q <= IDLE; - - elsif xtal_i'event and xtal_i = clk_active_c then - -- Address register ----------------------------------------------------- - -- update lowest address byte - if ale_i = '1' then - adr_q(word_t'range) <= db_bus_i; - end if; - -- set adr1 part - if wr_s and sel_adr1_s then - adr_q(word_t'length*2 - 1 downto word_t'length) <= db_bus_i; - end if; - -- set adr2 part - if wr_s and sel_adr2_s then - adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i; - end if; - - -- Data from peripheral has to be saved --------------------------------- - if wb_ack_i = '1' then - wb_dat_q <= wb_dat_i; - end if; - - -- FSM state ------------------------------------------------------------ - state_q <= state_s; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process fsm - -- - -- Purpose: - -- Implements the state transitions of the controller FSM. - -- - fsm: process (state_q, - wr_s, - rd_s, - sel_wb_s, - wb_ack_i) - begin - -- default assignments - wb_cyc_o <= '0'; - wb_stb_o <= '0'; - en_clk_o <= '1'; - state_s <= IDLE; - - case state_q is - -- Idle State: Wait for read or write access ---------------------------- - when IDLE => - if sel_wb_s and (wr_s or rd_s) then - state_s <= CYC; - end if; - - -- WB Cycle State: Start Wishbone cycle and wait for ack ---------------- - when CYC => - wb_cyc_o <= '1'; - wb_stb_o <= '1'; - en_clk_o <= '0'; - - if wb_ack_i = '1' then - state_s <= WAIT_INACT; - else - state_s <= CYC; - end if; - - -- Wait inact State: Wait for end of T48 access ------------------------- - when WAIT_INACT => - if not wr_s and not rd_s then - state_s <= IDLE; - else - state_s <= WAIT_INACT; - end if; - - when others => - null; - - end case; - - end process fsm; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output multiplexer - ----------------------------------------------------------------------------- - db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length) - when sel_adr1_s else - adr_q(word_t'length*3 - 1 downto word_t'length*2) - when sel_adr2_s else - wb_dat_q; - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - wb_adr_o <= adr_q; - wb_dat_o <= db_bus_i; - wb_we_o <= '1' - when wr_s and sel_wb_s else - '0'; - -end rtl;

t48/rel_1_2/rtl/vhdl/system/wb_master.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8039.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8039.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8039.vhd (nonexistent) @@ -1,182 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8039 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8039 is - - port ( - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_b : inout std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_b : inout std_logic_vector( 7 downto 0); - t1_i : in std_logic; - p2_b : inout std_logic_vector( 7 downto 0); - p1_b : inout std_logic_vector( 7 downto 0); - prog_n_o : out std_logic - ); - -end t8039; - - -use work.t48_system_comp_pack.t8039_notri; - -architecture struct of t8039 is - - signal t0_s : std_logic; - signal t0_dir_s : std_logic; - signal db_s : std_logic_vector( 7 downto 0); - signal db_dir_s : std_logic; - signal p2_s : std_logic_vector( 7 downto 0); - signal p2l_low_imp_s : std_logic; - signal p2h_low_imp_s : std_logic; - signal p1_s : std_logic_vector( 7 downto 0); - signal p1_low_imp_s : std_logic; - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - t8039_notri_b : t8039_notri - generic map ( - -- we don't need explicit gating of input ports - -- this is done implicitely by the bidirectional pads - gate_port_input_g => 0 - ) - - port map ( - xtal_i => xtal_i, - xtal_en_i => vdd_s, - reset_n_i => reset_n_i, - t0_i => t0_b, - t0_o => t0_s, - t0_dir_o => t0_dir_s, - int_n_i => int_n_i, - ea_i => ea_i, - rd_n_o => rd_n_o, - psen_n_o => psen_n_o, - wr_n_o => wr_n_o, - ale_o => ale_o, - db_i => db_b, - db_o => db_s, - db_dir_o => db_dir_s, - t1_i => t1_i, - p2_i => p2_b, - p2_o => p2_s, - p2l_low_imp_o => p2l_low_imp_s, - p2h_low_imp_o => p2h_low_imp_s, - p1_i => p1_b, - p1_o => p1_s, - p1_low_imp_o => p1_low_imp_s, - prog_n_o => prog_n_o - ); - - ----------------------------------------------------------------------------- - -- Process bidirs - -- - -- Purpose: - -- Assign bidirectional signals. - -- - bidirs: process (t0_b, t0_s, t0_dir_s, - db_b, db_s, db_dir_s, - p1_b, p1_s, p1_low_imp_s, - p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) - - function port_bidir_f(port_value : in std_logic_vector; - low_imp : in std_logic) return std_logic_vector is - variable result_v : std_logic_vector(port_value'range); - begin - for idx in port_value'high downto port_value'low loop - if low_imp = '1' then - result_v(idx) := port_value(idx); - elsif port_value(idx) = '0' then - result_v(idx) := '0'; - else - result_v(idx) := 'Z'; - end if; - end loop; - - return result_v; - end; - - begin - -- Test 0 ----------------------------------------------------------------- - if t0_dir_s = '1' then - t0_b <= t0_s; - else - t0_b <= 'Z'; - end if; - - -- Data Bus --------------------------------------------------------------- - if db_dir_s = '1' then - db_b <= db_s; - else - db_b <= (others => 'Z'); - end if; - - -- Port 1 ----------------------------------------------------------------- - p1_b <= port_bidir_f(port_value => p1_s, - low_imp => p1_low_imp_s); - - -- Port 2 ----------------------------------------------------------------- - p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), - low_imp => p2l_low_imp_s); - p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), - low_imp => p2h_low_imp_s); - - end process bidirs; - -- - ----------------------------------------------------------------------------- - -end struct;

t48/rel_1_2/rtl/vhdl/system/t8039.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8048.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8048.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8048.vhd (nonexistent) @@ -1,186 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity t8048 is - - port ( - xtal_i : in std_logic; - reset_n_i : in std_logic; - t0_b : inout std_logic; - int_n_i : in std_logic; - ea_i : in std_logic; - rd_n_o : out std_logic; - psen_n_o : out std_logic; - wr_n_o : out std_logic; - ale_o : out std_logic; - db_b : inout std_logic_vector( 7 downto 0); - t1_i : in std_logic; - p2_b : inout std_logic_vector( 7 downto 0); - p1_b : inout std_logic_vector( 7 downto 0); - prog_n_o : out std_logic - ); - -end t8048; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_system_comp_pack.t8048_notri; - -architecture struct of t8048 is - - signal t0_s : std_logic; - signal t0_dir_s : std_logic; - signal db_s : std_logic_vector( 7 downto 0); - signal db_dir_s : std_logic; - signal p2_s : std_logic_vector( 7 downto 0); - signal p2l_low_imp_s : std_logic; - signal p2h_low_imp_s : std_logic; - signal p1_s : std_logic_vector( 7 downto 0); - signal p1_low_imp_s : std_logic; - - signal vdd_s : std_logic; - -begin - - vdd_s <= '1'; - - t8048_notri_b : t8048_notri - generic map ( - -- we don't need explicit gating of input ports - -- this is done implicitely by the bidirectional pads - gate_port_input_g => 0 - ) - - port map ( - xtal_i => xtal_i, - xtal_en_i => vdd_s, - reset_n_i => reset_n_i, - t0_i => t0_b, - t0_o => t0_s, - t0_dir_o => t0_dir_s, - int_n_i => int_n_i, - ea_i => ea_i, - rd_n_o => rd_n_o, - psen_n_o => psen_n_o, - wr_n_o => wr_n_o, - ale_o => ale_o, - db_i => db_b, - db_o => db_s, - db_dir_o => db_dir_s, - t1_i => t1_i, - p2_i => p2_b, - p2_o => p2_s, - p2l_low_imp_o => p2l_low_imp_s, - p2h_low_imp_o => p2h_low_imp_s, - p1_i => p1_b, - p1_o => p1_s, - p1_low_imp_o => p1_low_imp_s, - prog_n_o => prog_n_o - ); - - ----------------------------------------------------------------------------- - -- Process bidirs - -- - -- Purpose: - -- Assign bidirectional signals. - -- - bidirs: process (t0_b, t0_s, t0_dir_s, - db_b, db_s, db_dir_s, - p1_b, p1_s, p1_low_imp_s, - p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s) - - function port_bidir_f(port_value : in std_logic_vector; - low_imp : in std_logic) return std_logic_vector is - variable result_v : std_logic_vector(port_value'range); - begin - for idx in port_value'high downto port_value'low loop - if low_imp = '1' then - result_v(idx) := port_value(idx); - elsif port_value(idx) = '0' then - result_v(idx) := '0'; - else - result_v(idx) := 'Z'; - end if; - end loop; - - return result_v; - end; - - begin - -- Test 0 ----------------------------------------------------------------- - if t0_dir_s = '1' then - t0_b <= t0_s; - else - t0_b <= 'Z'; - end if; - - -- Data Bus --------------------------------------------------------------- - if db_dir_s = '1' then - db_b <= db_s; - else - db_b <= (others => 'Z'); - end if; - - -- Port 1 ----------------------------------------------------------------- - p1_b <= port_bidir_f(port_value => p1_s, - low_imp => p1_low_imp_s); - - -- Port 2 ----------------------------------------------------------------- - p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0), - low_imp => p2l_low_imp_s); - p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4), - low_imp => p2h_low_imp_s); - - end process bidirs; - -- - ----------------------------------------------------------------------------- - - -end struct;

t48/rel_1_2/rtl/vhdl/system/t8048.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/system/t8050_wb-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/system/t8050_wb-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/system/t8050_wb-c.vhd (nonexistent) @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- --- --- T8048 Microcontroller System --- --- $Id$ --- --- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t8050_wb_struct_c0 of t8050_wb is - - for struct - - for rom_4k_b : syn_rom - use configuration work.syn_rom_lpm_c0; - end for; - - for ram_256_b : syn_ram - use configuration work.syn_ram_lpm_c0; - end for; - - for wb_master_b : t48_wb_master - use configuration work.t48_wb_master_rtl_c0; - end for; - - for t48_core_b : t48_core - use configuration work.t48_core_struct_c0; - end for; - - end for; - -end t8050_wb_struct_c0;

t48/rel_1_2/rtl/vhdl/system/t8050_wb-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/decoder.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/decoder.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/decoder.vhd (nonexistent) @@ -1,2008 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Decoder unit. --- It decodes the instruction opcodes and executes them. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_pack.mstate_t; -use work.t48_alu_pack.alu_op_t; -use work.t48_cond_branch_pack.all; -use work.t48_dmem_ctrl_pack.all; -use work.t48_pmem_ctrl_pack.all; - -entity t48_decoder is - - generic ( - -- store mnemonic in flip-flops (registered-out) - register_mnemonic_g : integer := 1 - ); - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - xtal_i : in std_logic; - xtal_en_i : in boolean; - ea_i : in std_logic; - ale_i : in boolean; - int_n_i : in std_logic; - t0_dir_o : out std_logic; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - alu_write_accu_o : out boolean; - alu_write_shadow_o : out boolean; - alu_write_temp_reg_o : out boolean; - alu_read_alu_o : out boolean; - bus_write_bus_o : out boolean; - bus_read_bus_o : out boolean; - dm_write_dmem_addr_o : out boolean; - dm_write_dmem_o : out boolean; - dm_read_dmem_o : out boolean; - p1_write_p1_o : out boolean; - p1_read_p1_o : out boolean; - p2_write_p2_o : out boolean; - p2_write_exp_o : out boolean; - p2_read_p2_o : out boolean; - p2_read_exp_o : out boolean; - pm_write_pcl_o : out boolean; - pm_read_pcl_o : out boolean; - pm_write_pch_o : out boolean; - pm_read_pch_o : out boolean; - pm_read_pmem_o : out boolean; - psw_read_psw_o : out boolean; - psw_read_sp_o : out boolean; - psw_write_psw_o : out boolean; - psw_write_sp_o : out boolean; - -- ALU Interface ---------------------------------------------------------- - alu_carry_i : in std_logic; - alu_op_o : out alu_op_t; - alu_use_carry_o : out boolean; - alu_da_high_o : out boolean; - alu_accu_low_o : out boolean; - alu_p06_temp_reg_o : out boolean; - alu_p60_temp_reg_o : out boolean; - alu_da_overflow_i : in boolean; - -- BUS Interface ---------------------------------------------------------- - bus_output_pcl_o : out boolean; - bus_bidir_bus_o : out boolean; - -- Clock Controller Interface --------------------------------------------- - clk_multi_cycle_o : out boolean; - clk_assert_psen_o : out boolean; - clk_assert_prog_o : out boolean; - clk_assert_rd_o : out boolean; - clk_assert_wr_o : out boolean; - clk_mstate_i : in mstate_t; - clk_second_cycle_i : in boolean; - -- Conditional Branch Logic Interface ------------------------------------- - cnd_compute_take_o : out boolean; - cnd_branch_cond_o : out branch_conditions_t; - cnd_take_branch_i : in boolean; - cnd_comp_value_o : out comp_value_t; - cnd_f1_o : out std_logic; - cnd_tf_o : out std_logic; - -- Data Memory Controller Interface --------------------------------------- - dm_addr_type_o : out dmem_addr_ident_t; - -- Port 1 Interface ------------------------------------------------------- - p1_read_reg_o : out boolean; - -- Port 2 Interface ------------------------------------------------------- - p2_read_reg_o : out boolean; - p2_output_pch_o : out boolean; - -- Program Memory Controller Interface ------------------------------------ - pm_inc_pc_o : out boolean; - pm_write_pmem_addr_o : out boolean; - pm_addr_type_o : out pmem_addr_ident_t; - -- Program Status Word Interface ------------------------------------------ - psw_special_data_o : out std_logic; - psw_carry_i : in std_logic; - psw_aux_carry_i : in std_logic; - psw_f0_i : in std_logic; - psw_inc_stackp_o : out boolean; - psw_dec_stackp_o : out boolean; - psw_write_carry_o : out boolean; - psw_write_aux_carry_o : out boolean; - psw_write_f0_o : out boolean; - psw_write_bs_o : out boolean; - -- Timer Interface -------------------------------------------------------- - tim_read_timer_o : out boolean; - tim_write_timer_o : out boolean; - tim_start_t_o : out boolean; - tim_start_cnt_o : out boolean; - tim_stop_tcnt_o : out boolean; - tim_overflow_i : in boolean - ); - -end t48_decoder; - - -use work.t48_pack.all; -use work.t48_alu_pack.all; -use work.t48_decoder_pack.all; - -use work.t48_comp_pack.t48_int; - --- pragma translate_off -use work.t48_tb_pack.tb_istrobe_s; --- pragma translate_on - -architecture rtl of t48_decoder is - - -- Enable fixing a bug of Quartus II 4.0 - constant enable_quartus_bugfix_c : boolean := true; - - -- Opcode Decoder - signal opc_multi_cycle_s : boolean; - signal opc_read_bus_s : boolean; - signal opc_inj_int_s : boolean; - signal opc_opcode_q : word_t; - signal opc_mnemonic_s : mnemonic_t; - signal last_cycle_s : boolean; - - -- state translators - signal assert_psen_s : boolean; - - -- branch taken handshake - signal branch_taken_s, - branch_taken_q : boolean; - signal pm_inc_pc_s : boolean; - signal pm_write_pmem_addr_s : boolean; - -- additional signal to increment PC during CALL - signal add_inc_pc_s : boolean; - -- addtional signal to set PC during RET(R) - signal add_write_pmem_addr_s : boolean; - - -- Flag 1 - signal clear_f1_s, - cpl_f1_s : boolean; - signal f1_q : std_logic; - -- memory bank select - signal clear_mb_s, - set_mb_s : boolean; - signal mb_q : std_logic; - - -- T0 direction selection - signal ent0_clk_s : boolean; - signal t0_dir_q : std_logic; - - signal data_s : word_t; - signal read_dec_s : boolean; - - signal tf_s : std_logic; - - signal bus_read_bus_s : boolean; - signal add_read_bus_s : boolean; - - signal dm_write_dmem_s : boolean; - - signal p2_output_exp_s : boolean; - - signal movx_first_cycle_s : boolean; - - -- interrupt handling - signal jtf_executed_s : boolean; - signal en_tcnti_s : boolean; - signal dis_tcnti_s : boolean; - signal en_i_s : boolean; - signal dis_i_s : boolean; - signal tim_int_s : boolean; - signal retr_executed_s : boolean; - signal int_executed_s : boolean; - signal int_pending_s : boolean; - signal int_in_progress_s : boolean; - - -- the mnemonic - signal mnemonic_rec_s : mnemonic_rec_t; - signal mnemonic_q : mnemonic_t; - - -- pragma translate_off - signal istrobe_res_q : std_logic; - signal istrobe_q : std_logic; - signal injected_int_q : std_logic; - -- pragma translate_on - -begin - - -- pragma translate_off - - -- Register Mnemonic -------------------------------------------------------- - assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0) - report "register_mnemonic_g must be either 1 or 0!" - severity failure; - - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Opcode Decoder - -- - mnemonic_rec_s <= decode_opcode_f(opcode => opc_opcode_q); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process opc_regs - -- - -- Purpose: - -- Implements the opcode and mnemonic registers. - -- - opc_regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - opc_opcode_q <= (others => '0'); -- NOP - mnemonic_q <= MN_NOP; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if opc_read_bus_s then - opc_opcode_q <= data_i; - elsif opc_inj_int_s then - opc_opcode_q <= "00010100"; - else - mnemonic_q <= mnemonic_rec_s.mnemonic; - end if; - - end if; - - end if; - - end process opc_regs; - -- - opc_multi_cycle_s <= mnemonic_rec_s.multi_cycle; - opc_mnemonic_s <= mnemonic_q - when register_mnemonic_g = 1 else - mnemonic_rec_s.mnemonic; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Interrupt Controller. - ----------------------------------------------------------------------------- - int_b : t48_int - port map ( - clk_i => clk_i, - res_i => res_i, - en_clk_i => en_clk_i, - xtal_i => xtal_i, - xtal_en_i => xtal_en_i, - clk_mstate_i => clk_mstate_i, - jtf_executed_i => jtf_executed_s, - tim_overflow_i => tim_overflow_i, - tf_o => tf_s, - en_tcnti_i => en_tcnti_s, - dis_tcnti_i => dis_tcnti_s, - int_n_i => int_n_i, - ale_i => ale_i, - last_cycle_i => last_cycle_s, - en_i_i => en_i_s, - dis_i_i => dis_i_s, - ext_int_o => open, - tim_int_o => tim_int_s, - retr_executed_i => retr_executed_s, - int_executed_i => int_executed_s, - int_pending_o => int_pending_s, - int_in_progress_o => int_in_progress_s - ); - - last_cycle_s <= not opc_multi_cycle_s or - (opc_multi_cycle_s and clk_second_cycle_i); - - ----------------------------------------------------------------------------- - -- Process machine_cycle - -- - -- Purpose: - -- Generates the control signals that are basically needed for the - -- handling of a machine cycle. - -- - machine_cycle: process (clk_mstate_i, - clk_second_cycle_i, - last_cycle_s, - ea_i, - assert_psen_s, - branch_taken_q, - int_pending_s, - p2_output_exp_s, - movx_first_cycle_s) - - variable need_address_v : boolean; - - begin - -- default assignments - clk_assert_psen_o <= false; - pm_inc_pc_s <= false; - pm_write_pmem_addr_s <= false; - pm_read_pmem_o <= false; - bus_output_pcl_o <= false; - p2_output_pch_o <= false; - opc_read_bus_s <= false; - opc_inj_int_s <= false; - bus_read_bus_s <= false; - - need_address_v := not clk_second_cycle_i or - (clk_second_cycle_i and assert_psen_s); - - case clk_mstate_i is - when MSTATE1 => - if need_address_v then - if ea_i = '0' then - if not int_pending_s then - pm_read_pmem_o <= true; - end if; - - else - if not int_pending_s then - bus_read_bus_s <= true; - end if; - p2_output_pch_o <= true; - end if; - - end if; - - if not clk_second_cycle_i then - if not int_pending_s then - opc_read_bus_s <= true; - else - opc_inj_int_s <= true; -- inject interrupt call - end if; - end if; - - when MSTATE2 => - if need_address_v and not branch_taken_q and - not int_pending_s then - pm_inc_pc_s <= true; - end if; - - when MSTATE3 => - if need_address_v then - -- Theory of operation: - -- Program Memory address is updated at end of State 3 (or end of - -- State 2 in case of a RET). Address information is thus available - -- latest with State 4. - -- This is the time where we need information about access target - -- (internal or external = EA). EA information needs to be stable - -- until end of State 1. - pm_write_pmem_addr_s <= true; - end if; - - when MSTATE4 => - if ea_i = '1' and - ((not clk_second_cycle_i and assert_psen_s) - or last_cycle_s) then - clk_assert_psen_o <= true; - p2_output_pch_o <= true; - bus_output_pcl_o <= true; - end if; - - when MSTATE5 => - if ea_i = '1' and - (need_address_v or last_cycle_s) and - -- Suppress output of PCH when either - -- a) expander port is driven on P2, has priority - not p2_output_exp_s and - -- b) first cycle of MOVX, don't disturb external access - not movx_first_cycle_s then - p2_output_pch_o <= true; - end if; - - when others => - -- pragma translate_off - assert false - report "Unkown machine state!" - severity error; - -- pragma translate_on - - end case; - - end process machine_cycle; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process decode - -- - -- Purpose: - -- Indentifies each single instruction and steps through the related - -- execution sequence. - -- - decode: process (alu_carry_i, - psw_aux_carry_i, - alu_da_overflow_i, - clk_mstate_i, - clk_second_cycle_i, - cnd_take_branch_i, - opc_opcode_q, - opc_mnemonic_s, - psw_carry_i, - psw_f0_i, - f1_q, - mb_q, - tim_int_s, - int_pending_s, - int_in_progress_s) - - procedure address_indirect_3_f is - begin - -- apply dmem address from selected register for indirect mode - if opc_opcode_q(3) = '0' or enable_quartus_bugfix_c then - dm_read_dmem_o <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_PLAIN; - end if; - end; - - procedure and_or_xor_add_4_f is - begin - -- write dmem contents to Temp Reg - dm_read_dmem_o <= true; - alu_write_temp_reg_o <= true; - end; - - procedure and_or_xor_add_5_f (alu_op : alu_op_t) is - begin - -- perform ALU operation and store in Accumulator - alu_op_o <= alu_op; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - end; - - procedure cond_jump_c2_m1_f is - begin - -- store address in Program Counter low byte if branch has to - -- be taken --- if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - pm_write_pcl_o <= true; - branch_taken_s <= true; --- end if; - end; - - -- intermediate value of the Program Memory Bank Flag - variable mb_v : std_logic; - - begin - -- default assignments - data_s <= (others => '-'); - read_dec_s <= false; - branch_taken_s <= false; - clear_f1_s <= false; - cpl_f1_s <= false; - clear_mb_s <= false; - set_mb_s <= false; - add_inc_pc_s <= false; - assert_psen_s <= false; - alu_write_accu_o <= false; - alu_write_shadow_o <= false; - alu_write_temp_reg_o <= false; - alu_p06_temp_reg_o <= false; - alu_p60_temp_reg_o <= false; - alu_read_alu_o <= false; - bus_write_bus_o <= false; - bus_bidir_bus_o <= false; - dm_write_dmem_addr_o <= false; - dm_write_dmem_s <= false; - dm_read_dmem_o <= false; - pm_write_pcl_o <= false; - pm_read_pcl_o <= false; - pm_write_pch_o <= false; - pm_read_pch_o <= false; - pm_addr_type_o <= PM_PC; - psw_read_psw_o <= false; - psw_read_sp_o <= false; - psw_write_psw_o <= false; - psw_write_sp_o <= false; - alu_op_o <= ALU_NOP; - alu_use_carry_o <= false; - alu_da_high_o <= false; - alu_accu_low_o <= false; - clk_assert_prog_o <= false; - clk_assert_rd_o <= false; - clk_assert_wr_o <= false; - cnd_branch_cond_o <= COND_ON_BIT; - cnd_compute_take_o <= false; - cnd_comp_value_o <= opc_opcode_q(7 downto 5); - dm_addr_type_o <= DM_REG; - tim_read_timer_o <= false; - tim_write_timer_o <= false; - tim_start_t_o <= false; - tim_start_cnt_o <= false; - tim_stop_tcnt_o <= false; - p1_write_p1_o <= false; - p1_read_p1_o <= false; - p1_read_reg_o <= false; - p2_write_p2_o <= false; - p2_write_exp_o <= false; - p2_read_p2_o <= false; - p2_read_reg_o <= false; - p2_read_exp_o <= false; - p2_output_exp_s <= false; - psw_special_data_o <= '0'; - psw_inc_stackp_o <= false; - psw_dec_stackp_o <= false; - psw_write_carry_o <= false; - psw_write_aux_carry_o <= false; - psw_write_f0_o <= false; - psw_write_bs_o <= false; - jtf_executed_s <= false; - en_tcnti_s <= false; - dis_tcnti_s <= false; - en_i_s <= false; - dis_i_s <= false; - retr_executed_s <= false; - int_executed_s <= false; - add_write_pmem_addr_s <= false; - ent0_clk_s <= false; - add_read_bus_s <= false; - movx_first_cycle_s <= false; - - -- the Program Memory Bank Flag is held low when interrupts are in progress - -- according to the MCS-48 User's Manual - if int_in_progress_s then - mb_v := '0'; - else - mb_v := mb_q; - end if; - - -- prepare potential register indirect address mode - if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then - data_s <= (others => '0'); - if opc_opcode_q(3) = '1' then - data_s(2 downto 0) <= opc_opcode_q(2 downto 0); - else - data_s(2 downto 0) <= "00" & opc_opcode_q(0); - end if; - - read_dec_s <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_REG; - end if; - - case opc_mnemonic_s is - - -- Mnemonic ADD --------------------------------------------------------- - when MN_ADD => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- store data from RAM to Temp Reg - when MSTATE4 => - and_or_xor_add_4_f; - - -- perform ADD and store in Accumulator - when MSTATE5 => - and_or_xor_add_5_f(alu_op => ALU_ADD); - - if opc_opcode_q(4) = '1' then - alu_use_carry_o <= true; - end if; - - psw_special_data_o <= alu_carry_i; - psw_write_carry_o <= true; - psw_write_aux_carry_o <= true; - - when others => - null; - - end case; - - -- Mnemonic ADD_A_DATA -------------------------------------------------- - when MN_ADD_A_DATA => - assert_psen_s <= true; - - if clk_second_cycle_i then - case clk_mstate_i is - -- write Temp Reg when contents of Program Memory is on bus - when MSTATE1 => - alu_write_temp_reg_o <= true; - - -- perform ADD and store in Accumulator - when MSTATE3 => - and_or_xor_add_5_f(alu_op => ALU_ADD); - - if opc_opcode_q(4) = '1' then - alu_use_carry_o <= true; - end if; - - psw_special_data_o <= alu_carry_i; - psw_write_carry_o <= true; - psw_write_aux_carry_o <= true; - - when others => - null; - - end case; - - end if; - - -- Mnemonic ANL --------------------------------------------------------- - when MN_ANL => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- store data from RAM to Temp Reg - when MSTATE4 => - and_or_xor_add_4_f; - - -- perform AND and store in Accumulator - when MSTATE5 => - and_or_xor_add_5_f(alu_op => ALU_AND); - - when others => - null; - - end case; - - -- Mnemonic ANL_A_DATA -------------------------------------------------- - when MN_ANL_A_DATA => - assert_psen_s <= true; - - if clk_second_cycle_i then - case clk_mstate_i is - -- write Temp Reg when contents of Program Memory is on bus - when MSTATE1 => - alu_write_temp_reg_o <= true; - - -- perform AND and store in Accumulator - when MSTATE3 => - and_or_xor_add_5_f(alu_op => ALU_AND); - - when others => - null; - - end case; - - end if; - - -- Mnemonic ANL_EXT ----------------------------------------------------- - when MN_ANL_EXT => - assert_psen_s <= true; - - if not clk_second_cycle_i then - -- read port to Temp Reg - if clk_mstate_i = MSTATE5 then - if opc_opcode_q(1 downto 0) = "00" then - add_read_bus_s <= true; - elsif opc_opcode_q(1) = '0' then - p1_read_p1_o <= true; - p1_read_reg_o <= true; - else - p2_read_p2_o <= true; - p2_read_reg_o <= true; - end if; - - alu_write_temp_reg_o <= true; - end if; - - else - case clk_mstate_i is - -- write shadow Accumulator when contents of Program Memory is - -- on bus - when MSTATE1 => - alu_write_shadow_o <= true; - - -- loop shadow Accumulator through ALU to prevent update from - -- real Accumulator - when MSTATE2 => - alu_read_alu_o <= true; - alu_write_shadow_o <= true; - - -- write result of AND operation back to port - when MSTATE3 => - alu_op_o <= ALU_AND; - alu_read_alu_o <= true; - - if opc_opcode_q(1 downto 0) = "00" then - bus_write_bus_o <= true; - elsif opc_opcode_q(1) = '0' then - p1_write_p1_o <= true; - else - p2_write_p2_o <= true; - end if; - - when others => - null; - - end case; - - end if; - - -- Mnemonic CALL -------------------------------------------------------- - when MN_CALL => - assert_psen_s <= true; - - if not clk_second_cycle_i then - case clk_mstate_i is - -- read Stack Pointer and address Data Memory for low byte - -- also increment Program Counter to point to next instruction - when MSTATE3 => - psw_read_sp_o <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_STACK; - - -- only increment PC if this is not an injected CALL - -- injected CALLS are not located in Program Memory, - -- the PC points already to the instruction to be executed - -- after the interrupt - if not int_pending_s then - add_inc_pc_s <= true; - end if; - - -- store Program Counter low byte on stack - when MSTATE4 => - pm_read_pcl_o <= true; - dm_write_dmem_s <= true; - - -- store Program Counter high byte and PSW on stack - -- increment Stack pointer - when MSTATE5 => - psw_read_psw_o <= true; - pm_read_pch_o <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_STACK_HIGH; - dm_write_dmem_s <= true; - psw_inc_stackp_o <= true; - - when others => - null; - - end case; - - else - case clk_mstate_i is - -- store address in Program Counter low byte - when MSTATE1 => - pm_write_pcl_o <= true; - branch_taken_s <= true; - if int_pending_s then - -- apply low part of vector address manually - data_s <= (others => '0'); - data_s(1 downto 0) <= "11"; - if tim_int_s then - data_s(2) <= '1'; - end if; - read_dec_s <= true; - end if; - - when MSTATE2 => - pm_write_pch_o <= true; - read_dec_s <= true; - if not int_pending_s then - -- store high part of target address in Program Counter - data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); - else - -- apply high part of vector address manually - data_s <= (others => '0'); - int_executed_s <= true; - end if; - - when others => - null; - - end case; - - end if; - - -- Mnemonic CLR_A ------------------------------------------------------- - when MN_CLR_A => - -- write CLR output of ALU to Accumulator - if clk_mstate_i = MSTATE3 then - alu_op_o <= ALU_CLR; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - end if; - - -- Mnemonic CLR_C ------------------------------------------------------- - when MN_CLR_C => - -- store 0 to Carry - if clk_mstate_i = MSTATE3 then - psw_special_data_o <= '0'; - psw_write_carry_o <= true; - end if; - - -- Mnemonic CLR_F ------------------------------------------------------- - when MN_CLR_F => - -- store 0 to selected flag - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(5) = '0' then - psw_special_data_o <= '0'; - psw_write_f0_o <= true; - else - clear_f1_s <= true; - end if; - - end if; - - -- Mnemonic CPL_A ------------------------------------------------------- - when MN_CPL_A => - -- write CPL output of ALU to Accumulator - if clk_mstate_i = MSTATE3 then - alu_op_o <= ALU_CPL; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - end if; - - -- Mnemnonic CPL_C ------------------------------------------------------ - when MN_CPL_C => - -- write inverse of Carry to PSW - if clk_mstate_i = MSTATE3 then - psw_special_data_o <= not psw_carry_i; - psw_write_carry_o <= true; - end if; - - -- Mnemonic CPL_F ------------------------------------------------------- - when MN_CPL_f => - -- write inverse of selected flag back to flag - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(5) = '0' then - psw_special_data_o <= not psw_f0_i; - psw_write_f0_o <= true; - else - cpl_f1_s <= true; - end if; - - end if; - - -- Mnemonic DA ---------------------------------------------------------- - when MN_DA => - alu_op_o <= ALU_ADD; - - case clk_mstate_i is - -- Step 1: Preload Temp Reg with 0x06 - when MSTATE3 => - alu_p06_temp_reg_o <= true; - - -- Step 2: Check Auxiliary Carry and overflow on low nibble - -- Add 0x06 to shadow Accumulator if one is true - when MSTATE4 => - if psw_aux_carry_i = '1' or alu_da_overflow_i then - alu_read_alu_o <= true; - alu_write_shadow_o <= true; - end if; - - -- preload Temp Reg with 0x60 - alu_p60_temp_reg_o <= true; - - -- Step 3: Check overflow on high nibble - -- Add 0x60 to shadow Accumulator if true and store result - -- in Accumulator and PSW (only Carry) - when MSTATE5 => - alu_da_high_o <= true; - - if alu_da_overflow_i then - psw_special_data_o <= alu_carry_i; - else - alu_op_o <= ALU_NOP; - psw_special_data_o <= '0'; - end if; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - psw_write_carry_o <= true; - - when others => - null; - - end case; - - -- Mnemonic DEC --------------------------------------------------------- - when MN_DEC => - case clk_mstate_i is - when MSTATE4 => - -- DEC Rr: store data from RAM to shadow Accumulator - if opc_opcode_q(6) = '1' then - dm_read_dmem_o <= true; - alu_write_shadow_o <= true; - end if; - - when MSTATE5 => - alu_op_o <= ALU_DEC; - alu_read_alu_o <= true; - - if opc_opcode_q(6) = '0' then - -- write DEC of Accumulator to Accumulator - alu_write_accu_o <= true; - else - -- store DEC of shadow Accumulator back to dmem - dm_write_dmem_s <= true; - end if; - - when others => - null; - - end case; - - -- Mnemonic DIS_EN_I ---------------------------------------------------- - when MN_DIS_EN_I => - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(4) = '1' then - dis_i_s <= true; - else - en_i_s <= true; - end if; - end if; - - -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ - when MN_DIS_EN_TCNTI => - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(4) = '1' then - dis_tcnti_s <= true; - else - en_tcnti_s <= true; - end if; - end if; - - -- Mnemonic DJNZ -------------------------------------------------------- - when MN_DJNZ => - assert_psen_s <= true; - - if not clk_second_cycle_i then - case clk_mstate_i is - -- store data from RAM to shadow Accumulator - when MSTATE4 => - dm_read_dmem_o <= true; - alu_write_shadow_o <= true; - - -- write DEC result of shadow Accumulator back to dmem and - -- conditional branch logic - when MSTATE5 => - alu_op_o <= ALU_DEC; - alu_read_alu_o <= true; - dm_write_dmem_s <= true; - - cnd_compute_take_o <= true; - cnd_branch_cond_o <= COND_Z; - cnd_comp_value_o(0) <= '0'; - - when others => - null; - - end case; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic ENT0_CLK ---------------------------------------------------- - when MN_ENT0_CLK => - if clk_mstate_i = MSTATE3 then - ent0_clk_s <= true; - end if; - - -- Mnemonic IN ---------------------------------------------------------- - when MN_IN => - -- read Port and store in Accumulator - if clk_second_cycle_i and clk_mstate_i = MSTATE2 then - alu_write_accu_o <= true; - - if opc_opcode_q(1) = '0' then - p1_read_p1_o <= true; - else - p2_read_p2_o <= true; - end if; - end if; - - -- Mnemonic INS --------------------------------------------------------- - when MN_INS => - clk_assert_rd_o <= true; - - -- read BUS and store in Accumulator - if clk_second_cycle_i and clk_mstate_i = MSTATE2 then - alu_write_accu_o <= true; - - add_read_bus_s <= true; - end if; - - -- Mnemonic INC --------------------------------------------------------- - when MN_INC => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - when MSTATE4 => - -- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator - if opc_opcode_q(3 downto 2) /= "01" then - dm_read_dmem_o <= true; - alu_write_shadow_o <= true; - end if; - - when MSTATE5 => - alu_op_o <= ALU_INC; - alu_read_alu_o <= true; - - if opc_opcode_q(3 downto 2) = "01" then - -- write INC output of ALU to Accumulator - alu_write_accu_o <= true; - else - -- store INC of shadow Accumulator back to dmem - dm_write_dmem_s <= true; - end if; - - when others => - null; - - end case; - - -- Mnemonic JBB --------------------------------------------------------- - when MN_JBB => - assert_psen_s <= true; - cnd_branch_cond_o <= COND_ON_BIT; - - if not clk_second_cycle_i then - -- read Accumulator and start branch calculation - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - cnd_compute_take_o <= true; - -- cnd_comp_value_o is ok by default assignment - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic JC ---------------------------------------------------------- - when MN_JC => - assert_psen_s <= true; - cnd_branch_cond_o <= COND_C; - - if not clk_second_cycle_i then - -- start branch calculation - if clk_mstate_i = MSTATE3 then - cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_q(4); - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic JF ---------------------------------------------------------- - when MN_JF => - assert_psen_s <= true; - - if not clk_second_cycle_i then - -- start branch calculation - if clk_mstate_i = MSTATE3 then - cnd_compute_take_o <= true; - if opc_opcode_q(7) = '1' then - -- JF0 - cnd_branch_cond_o <= COND_F0; - else - -- JF1 - cnd_branch_cond_o <= COND_F1; - end if; - - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - - -- Mnemonic JMP --------------------------------------------------------- - when MN_JMP => - assert_psen_s <= true; - - if clk_second_cycle_i then - case clk_mstate_i is - -- store address in Program Counter low byte - when MSTATE1 => - pm_write_pcl_o <= true; - branch_taken_s <= true; - - -- store high part of target address in Program Counter - when MSTATE2 => - data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); - read_dec_s <= true; - pm_write_pch_o <= true; - - when others => - null; - - end case; - - end if; - - -- Mnemonic JMPP -------------------------------------------------------- - when MN_JMPP => - assert_psen_s <= true; - - if not clk_second_cycle_i then - -- write Accumulator to Program Memory address - -- (skip page offset update from Program Counter) - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - pm_addr_type_o <= PM_PAGE; - end if; - - else - if clk_mstate_i = MSTATE1 then - -- store address in Program Counter low byte - pm_write_pcl_o <= true; - branch_taken_s <= true; - end if; - - end if; - - -- Mnemonic JNI --------------------------------------------------------- - when MN_JNI => - assert_psen_s <= true; - cnd_branch_cond_o <= COND_INT; - - if not clk_second_cycle_i then - -- start branch calculation - if clk_mstate_i = MSTATE3 then - cnd_compute_take_o <= true; - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic JT ---------------------------------------------------------- - when MN_JT => - assert_psen_s <= true; - if opc_opcode_q(6) = '0' then - cnd_branch_cond_o <= COND_T0; - else - cnd_branch_cond_o <= COND_T1; - end if; - - if not clk_second_cycle_i then - -- start branch calculation - if clk_mstate_i = MSTATE3 then - cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_q(4); - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic JTF --------------------------------------------------------- - when MN_JTF => - assert_psen_s <= true; - cnd_branch_cond_o <= COND_TF; - - if not clk_second_cycle_i then - -- start branch calculation - if clk_mstate_i = MSTATE3 then - cnd_compute_take_o <= true; - jtf_executed_s <= true; - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic JZ ---------------------------------------------------------- - when MN_JZ => - assert_psen_s <= true; - cnd_branch_cond_o <= COND_Z; - - if not clk_second_cycle_i then - -- read Accumulator and start branch calculation - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_q(6); - end if; - - else - -- store address in Program Counter low byte if branch has to - -- be taken - if clk_mstate_i = MSTATE1 and cnd_take_branch_i then - cond_jump_c2_m1_f; - end if; - - end if; - - -- Mnemonic MOV_A_DATA -------------------------------------------------- - when MN_MOV_A_DATA => - assert_psen_s <= true; - - -- Write Accumulator when contents of Program Memory is on bus - -- during machine state 1 of second cycle. - if clk_second_cycle_i and clk_mstate_i = MSTATE1 then - alu_write_accu_o <= true; - end if; - - -- Mnemonic MOV_A_RR ---------------------------------------------------- - when MN_MOV_A_RR => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- read data from RAM and store in Accumulator - when MSTATE4 => - and_or_xor_add_4_f; - alu_write_accu_o <= true; - - when others => - null; - - end case; - - -- Mnemonic MOV_A_PSW --------------------------------------------------- - when MN_MOV_A_PSW => - if clk_mstate_i = MSTATE3 then - psw_read_psw_o <= true; - psw_read_sp_o <= true; - alu_write_accu_o <= true; - end if; - - -- Mnemoniv MOV_PSW_A --------------------------------------------------- - when MN_MOV_PSW_A => - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - psw_write_psw_o <= true; - psw_write_sp_o <= true; - end if; - - -- Mnemonic MOV_RR ------------------------------------------------------ - when MN_MOV_RR => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- write Accumulator to dmem - when MSTATE5 => - alu_read_alu_o <= true; - dm_write_dmem_s <= true; - - when others => - null; - - end case; - - -- Mnemonic MOV_RR_DATA ------------------------------------------------- - when MN_MOV_RR_DATA => - assert_psen_s <= true; - - -- read RAM once for indirect address mode - if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - end if; - - -- Write Data Memory when contents of Program Memory is on bus - -- during machine state 1 of second cycle. - if clk_second_cycle_i and clk_mstate_i = MSTATE1 then - dm_write_dmem_s <= true; - end if; - - -- Mnemonic MOV_T ------------------------------------------------------- - when MN_MOV_T => - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(5) = '1' then - alu_read_alu_o <= true; -- MOV T, A - tim_write_timer_o <= true; - else - tim_read_timer_o <= true; -- MOV A, T - alu_write_accu_o <= true; - end if; - end if; - - -- Mnemonic OUTD_PP_A --------------------------------------------------- - when MN_OUTD_PP_A => - clk_assert_prog_o <= true; - - if not clk_second_cycle_i then - case clk_mstate_i is - -- propagate expander port number to Port 2 - when MSTATE3 => - - data_s(7 downto 4) <= (others => '0'); - data_s(1 downto 0) <= opc_opcode_q(1 downto 0); - -- decide which 8243 command to use - case opc_opcode_q(7 downto 4) is - when "1001" => - data_s(3 downto 2) <= "11"; -- ANLD command - when "1000" => - data_s(3 downto 2) <= "10"; -- ORLD command - when "0011" => - data_s(3 downto 2) <= "01"; -- MOVD command - when others => - null; - end case; - - read_dec_s <= true; - p2_write_exp_o <= true; - - -- output expander port number on Port 2 while active edge of PROG - -- write Accumulator to expander port - when MSTATE4 => - p2_output_exp_s <= true; - - alu_read_alu_o <= true; - p2_write_exp_o <= true; - - when MSTATE5 => - p2_output_exp_s <= true; - - when others => - null; - - end case; - - else - -- hold expander port until inactive edge of PROG - if clk_mstate_i = MSTATE1 or clk_mstate_i = MSTATE2 then - p2_output_exp_s <= true; - end if; - - end if; - - -- Mnemonic MOVD_A_PP --------------------------------------------------- - when MN_MOVD_A_PP => - clk_assert_prog_o <= true; - - if not clk_second_cycle_i then - case clk_mstate_i is - -- propagate expander port number to Port 2 - when MSTATE3 => - data_s <= "0000" & - "00" & -- 8243 command: read - opc_opcode_q(1 downto 0); - read_dec_s <= true; - p2_write_exp_o <= true; - - -- output expander port number on Port 2 while active edge of PROG - -- write 1's to expander port to set lower nibble of Port 2 to input - when MSTATE4 => - p2_output_exp_s <= true; - - data_s(nibble_t'range) <= (others => '1'); - read_dec_s <= true; - p2_write_exp_o <= true; - - when MSTATE5 => - p2_output_exp_s <= true; - - when others => - null; - - end case; - - else - case clk_mstate_i is - -- hold expander port until inactive edge of PROG - when MSTATE1 => - p2_output_exp_s <= true; - - -- hold expander port until inactive edge of PROG - -- write Accumulator with nibble of expander port - when MSTATE2 => - p2_read_p2_o <= true; - p2_output_exp_s <= true; - p2_read_exp_o <= true; - alu_write_accu_o <= true; - - when others => - null; - - end case; - - end if; - - -- Mnemonic MOVP -------------------------------------------------------- - when MN_MOVP => - assert_psen_s <= true; - - if not clk_second_cycle_i then - -- write Accumulator to Program Memory address - -- (skip page offset update from Program Counter) - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - if opc_opcode_q(6) = '0' then - pm_addr_type_o <= PM_PAGE; - else - pm_addr_type_o <= PM_PAGE3; - end if; - end if; - - else - if clk_mstate_i = MSTATE1 then - -- store data from Program Memory in Accumulator - alu_write_accu_o <= true; - -- trick & treat to prevent additional PC increment - -- our branch target is the previously incremented PC! - branch_taken_s <= true; - end if; - - end if; - - -- Mnemonic MOVX -------------------------------------------------------- - when MN_MOVX => - bus_bidir_bus_o <= true; - - if opc_opcode_q(4) = '0' then - clk_assert_rd_o <= true; - else - clk_assert_wr_o <= true; - end if; - - if not clk_second_cycle_i then - movx_first_cycle_s <= true; - case clk_mstate_i is - -- read dmem and put contents on BUS as external address - when MSTATE3 => - dm_read_dmem_o <= true; - bus_write_bus_o <= true; - - -- store contents of Accumulator to BUS - when MSTATE5 => - if opc_opcode_q(4) = '1' then - alu_read_alu_o <= true; - bus_write_bus_o <= true; - end if; - - when others => - null; - end case; - - else - if clk_mstate_i = MSTATE2 then - if opc_opcode_q(4) = '0' then - -- store contents of BUS in Accumulator - add_read_bus_s <= true; - alu_write_accu_o <= true; - else - -- store contents of Accumulator to BUS - -- to this to keep bus in output direction - alu_read_alu_o <= true; - bus_write_bus_o <= true; - end if; - end if; - - end if; - - -- Mnemonic NOP --------------------------------------------------------- - when MN_NOP => - -- nothing to do - - -- Mnemonic ORL --------------------------------------------------------- - when MN_ORL => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- store data from RAM to Temp Reg - when MSTATE4 => - and_or_xor_add_4_f; - - -- perform OR and store in Accumulator - when MSTATE5 => - and_or_xor_add_5_f(alu_op => ALU_OR); - - when others => - null; - - end case; - - -- Mnemonic ORL_A_DATA -------------------------------------------------- - when MN_ORL_A_DATA => - assert_psen_s <= true; - - if clk_second_cycle_i then - case clk_mstate_i is - -- write Temp Reg when contents of Program Memory is on bus - when MSTATE1 => - alu_write_temp_reg_o <= true; - - -- perform OR and store in Accumulator - when MSTATE3 => - and_or_xor_add_5_f(alu_op => ALU_OR); - - when others => - null; - - end case; - - end if; - - -- Mnemonic ORL_EXT ----------------------------------------------------- - when MN_ORL_EXT => - assert_psen_s <= true; - - if not clk_second_cycle_i then - -- read port to Temp Reg - if clk_mstate_i = MSTATE5 then - if opc_opcode_q(1 downto 0) = "00" then - add_read_bus_s <= true; - elsif opc_opcode_q(1) = '0' then - p1_read_p1_o <= true; - p1_read_reg_o <= true; - else - p2_read_p2_o <= true; - p2_read_reg_o <= true; - end if; - - alu_write_temp_reg_o <= true; - end if; - - else - case clk_mstate_i is - -- write shadow Accumulator when contents of Program Memory is - -- on bus - when MSTATE1 => - alu_write_shadow_o <= true; - - -- loop shadow Accumulator through ALU to prevent update from - -- real Accumulator - when MSTATE2 => - alu_read_alu_o <= true; - alu_write_shadow_o <= true; - - -- write result of OR operation back to port - when MSTATE3 => - alu_op_o <= ALU_OR; - alu_read_alu_o <= true; - - if opc_opcode_q(1 downto 0) = "00" then - bus_write_bus_o <= true; - elsif opc_opcode_q(1) = '0' then - p1_write_p1_o <= true; - else - p2_write_p2_o <= true; - end if; - - when others => - null; - - end case; - - end if; - - -- Mnemonic OUTL_EXT ---------------------------------------------------- - when MN_OUTL_EXT => - if opc_opcode_q(4) = '0' then - clk_assert_wr_o <= true; - end if; - - -- read Accumulator and store in Port/BUS output register - if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then - alu_read_alu_o <= true; - - if opc_opcode_q(4) = '1' then - if opc_opcode_q(1) = '0' then - p1_write_p1_o <= true; - else - p2_write_p2_o <= true; - end if; - - else - bus_write_bus_o <= true; - - end if; - - end if; - - -- Mnemonic RET --------------------------------------------------------- - when MN_RET => - if not clk_second_cycle_i then - case clk_mstate_i is - -- decrement Stack Pointer - when MSTATE3 => - psw_dec_stackp_o <= true; - - -- read Stack Pointer and address Data Memory for low byte - when MSTATE4 => - psw_read_sp_o <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_STACK; - - -- read Data Memory and store to Program Counter low - -- prepare address to Data memory for high byte - when MSTATE5 => - dm_read_dmem_o <= true; - pm_write_pcl_o <= true; - dm_write_dmem_addr_o <= true; - dm_addr_type_o <= DM_STACK_HIGH; - - when others => - null; - - end case; - - else - case clk_mstate_i is - -- read Data Memory and store to Program Counter high and PSW - when MSTATE1 => - dm_read_dmem_o <= true; - pm_write_pch_o <= true; - if opc_opcode_q(4) = '1' then - psw_write_psw_o <= true; - retr_executed_s <= true; - end if; - - when MSTATE2 => - add_write_pmem_addr_s <= true; - - when others => - null; - - end case; - - end if; - - -- Mnemonic RL ---------------------------------------------------------- - when MN_RL => - if clk_mstate_i = MSTATE3 then - alu_op_o <= ALU_RL; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - - if opc_opcode_q(4) = '1' then - psw_special_data_o <= alu_carry_i; - psw_write_carry_o <= true; - alu_use_carry_o <= true; - end if; - end if; - - -- Mnemonic RR ---------------------------------------------------------- - when MN_RR => - if clk_mstate_i = MSTATE3 then - alu_op_o <= ALU_RR; - alu_read_alu_o <= true; - alu_write_accu_o <= true; - - if opc_opcode_q(4) = '0' then - psw_special_data_o <= alu_carry_i; - psw_write_carry_o <= true; - alu_use_carry_o <= true; - end if; - end if; - - -- Mnemonic SEL_MB ------------------------------------------------------ - when MN_SEL_MB => - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(4) = '1' then - set_mb_s <= true; - else - clear_mb_s <= true; - end if; - end if; - - -- Mnemonic SEL_RB ------------------------------------------------------ - when MN_SEL_RB => - if clk_mstate_i = MSTATE3 then - psw_special_data_o <= opc_opcode_q(4); - psw_write_bs_o <= true; - end if; - - -- Mnemonic STOP_TCNT --------------------------------------------------- - when MN_STOP_TCNT => - if clk_mstate_i = MSTATE3 then - tim_stop_tcnt_o <= true; - end if; - - -- Mnemonic STRT -------------------------------------------------------- - when MN_STRT => - if clk_mstate_i = MSTATE3 then - if opc_opcode_q(4) = '1' then - tim_start_t_o <= true; - else - tim_start_cnt_o <= true; - end if; - end if; - - -- Mnemonic SWAP -------------------------------------------------------- - when MN_SWAP => - alu_op_o <= ALU_SWAP; - - if clk_mstate_i = MSTATE3 then - alu_read_alu_o <= true; - alu_write_accu_o <= true; - end if; - - -- Mnemonic XCH --------------------------------------------------------- - when MN_XCH => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- store data from RAM in Accumulator and Temp Reg - -- Accumulator is already shadowed! - when MSTATE4 => - dm_read_dmem_o <= true; - alu_write_accu_o <= true; - alu_write_temp_reg_o <= true; - if opc_opcode_q(4) = '1' then - -- XCHD - -- only write lower nibble of Accumulator - alu_accu_low_o <= true; - end if; - - -- store data from shadow (previous) Accumulator to dmem - when MSTATE5 => - dm_write_dmem_s <= true; - alu_read_alu_o <= true; - if opc_opcode_q(4) = '1' then - -- XCHD - -- concatenate shadow Accumulator and Temp Reg - alu_op_o <= ALU_CONCAT; - end if; - - when others => - null; - - end case; - - -- Mnemonic XRL --------------------------------------------------------- - when MN_XRL => - case clk_mstate_i is - -- read RAM once for indirect address mode - when MSTATE3 => - if not enable_quartus_bugfix_c or - opc_opcode_q(3) = '0' then - address_indirect_3_f; - end if; - - -- store data from RAM to Temp Reg - when MSTATE4 => - and_or_xor_add_4_f; - - -- perform XOR and store in Accumulator - when MSTATE5 => - and_or_xor_add_5_f(alu_op => ALU_XOR); - - when others => - null; - - end case; - - -- Mnemonic XRL_A_DATA -------------------------------------------------- - when MN_XRL_A_DATA => - assert_psen_s <= true; - - if clk_second_cycle_i then - case clk_mstate_i is - -- write Temp Reg when contents of Program Memory is on bus - when MSTATE1 => - alu_write_temp_reg_o <= true; - - -- perform XOR and store in Accumulator - when MSTATE3 => - and_or_xor_add_5_f(alu_op => ALU_XOR); - - when others => - null; - - end case; - - end if; - - -- Unimplemented mnemonic ----------------------------------------------- - when others => - -- this will behave like a NOP - - -- pragma translate_off - assert false - report "Mnemonic not yet implemented." - severity warning; - -- pragma translate_on - - end case; - - end process decode; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process regs - -- - -- Purpose: - -- Implements the various registes. - -- - regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - branch_taken_q <= false; - f1_q <= '0'; - mb_q <= '0'; - t0_dir_q <= '0'; - -- pragma translate_off - istrobe_res_q <= '1'; - istrobe_q <= '0'; - injected_int_q <= '0'; - -- pragma translate_on - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - -- branch taken flag - if branch_taken_s then - branch_taken_q <= true; - elsif clk_mstate_i = MSTATE5 then - -- release flag when new instruction starts - branch_taken_q <= false; - end if; - - -- Flag 1 - if clear_f1_s then - f1_q <= '0'; - elsif cpl_f1_s then - f1_q <= not f1_q; - end if; - - -- Memory Bank select - if clear_mb_s then - mb_q <= '0'; - elsif set_mb_s then - mb_q <= '1'; - end if; - - -- T0 direction selection - if ent0_clk_s then - t0_dir_q <= '1'; - end if; - - -- pragma translate_off - -- Marker for injected instruction ------------------------------------ - if opc_inj_int_s then - injected_int_q <= '1'; - elsif clk_mstate_i = MSTATE5 and last_cycle_s then - injected_int_q <= '0'; - end if; - - -- Remove istrobe after reset suppression ----------------------------- - if clk_mstate_i = MSTATE5 and last_cycle_s then - istrobe_res_q <= '0'; - end if; - -- pragma translate_on - - end if; - - -- pragma translate_off - -- Instruction Strobe --------------------------------------------------- - if clk_mstate_i = MSTATE5 and last_cycle_s and - injected_int_q = '0' then - if istrobe_res_q = '0' then - istrobe_q <= '1'; - end if; - else - istrobe_q <= '0'; - end if; - -- pragma translate_on - - end if; - - end process regs; - -- - ----------------------------------------------------------------------------- - - -- pragma translate_off - -- assign to global signal for testbench - tb_istrobe_s <= istrobe_q; - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - clk_multi_cycle_o <= opc_multi_cycle_s; - cnd_f1_o <= f1_q; - cnd_tf_o <= tf_s; - data_o <= data_s - when read_dec_s else - (others => bus_idle_level_c); - dm_write_dmem_o <= dm_write_dmem_s and en_clk_i; - pm_inc_pc_o <= pm_inc_pc_s or add_inc_pc_s; - pm_write_pmem_addr_o <= pm_write_pmem_addr_s or add_write_pmem_addr_s; - t0_dir_o <= t0_dir_q; - bus_read_bus_o <= bus_read_bus_s or add_read_bus_s; - -end rtl;

t48/rel_1_2/rtl/vhdl/decoder.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/psw.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/psw.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/psw.vhd (nonexistent) @@ -1,212 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Program Status Word (PSW). --- Implements the PSW with its special bits. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; - -entity t48_psw is - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - data_o : out word_t; - read_psw_i : in boolean; - read_sp_i : in boolean; - write_psw_i : in boolean; - write_sp_i : in boolean; - -- Decoder Interface ------------------------------------------------------ - special_data_i : in std_logic; - inc_stackp_i : in boolean; - dec_stackp_i : in boolean; - write_carry_i : in boolean; - write_aux_carry_i : in boolean; - write_f0_i : in boolean; - write_bs_i : in boolean; - carry_o : out std_logic; - aux_carry_i : in std_logic; - aux_carry_o : out std_logic; - f0_o : out std_logic; - bs_o : out std_logic - ); - -end t48_psw; - - -library ieee; -use ieee.numeric_std.all; - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.bus_idle_level_c; -use work.t48_pack.nibble_t; - -architecture rtl of t48_psw is - - -- special bit positions in PSW - constant carry_c : natural := 3; - constant aux_carry_c : natural := 2; - constant f0_c : natural := 1; - constant bs_c : natural := 0; - - -- the PSW register - signal psw_q : nibble_t; - -- the Stack Pointer - signal sp_q : unsigned(2 downto 0); - - -- pragma translate_off - signal psw_s : word_t; - -- pragma translate_on - -begin - - ----------------------------------------------------------------------------- - -- Process psw_reg - -- - -- Purpose: - -- Implements the PSW register. - -- - psw_reg: process (res_i, clk_i) - begin - if res_i = res_active_c then - psw_q <= (others => '0'); - sp_q <= (others => '0'); - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - -- T48 bus access - if write_psw_i then - psw_q <= data_i(7 downto 4); - end if; - if write_sp_i then - sp_q <= unsigned(data_i(2 downto 0)); - end if; - - -- increment Stack Pointer - if inc_stackp_i then - sp_q <= sp_q + 1; - end if; - -- decrement Stack Pointer - if dec_stackp_i then - sp_q <= sp_q - 1; - end if; - - -- access to special bits - if write_carry_i then - psw_q(carry_c) <= special_data_i; - end if; - -- - if write_aux_carry_i then - psw_q(aux_carry_c) <= aux_carry_i; - end if; - -- - if write_f0_i then - psw_q(f0_c) <= special_data_i; - end if; - -- - if write_bs_i then - psw_q(bs_c) <= special_data_i; - end if; - - end if; - - end if; - - end process psw_reg; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process data_out - -- - -- Purpose: - -- Output multiplexer for T48 Data Bus. - -- - data_out: process (read_psw_i, - read_sp_i, - psw_q, - sp_q) - begin - data_o <= (others => bus_idle_level_c); - - if read_psw_i then - data_o(7 downto 4) <= psw_q; - end if; - - if read_sp_i then - data_o(3 downto 0) <= '1' & std_logic_vector(sp_q); - end if; - - end process data_out; - -- - ----------------------------------------------------------------------------- - - - -- pragma translate_off - tb: process (psw_q, sp_q) - begin - psw_s(7 downto 4) <= psw_q; - psw_s(3) <= '1'; - psw_s(2 downto 0) <= std_logic_vector(sp_q); - end process tb; - -- pragma translate_on - - ----------------------------------------------------------------------------- - -- Output mapping. - ----------------------------------------------------------------------------- - carry_o <= psw_q(carry_c); - aux_carry_o <= psw_q(aux_carry_c); - f0_o <= psw_q(f0_c); - bs_o <= psw_q(bs_c); - -end rtl;

t48/rel_1_2/rtl/vhdl/psw.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/int-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/int-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/int-c.vhd (nonexistent) @@ -1,17 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Interrupt Controller. --- It collects the interrupt sources and notifies the decoder. --- --- $Id$ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_int_rtl_c0 of t48_int is - - for rtl - end for; - -end t48_int_rtl_c0;

t48/rel_1_2/rtl/vhdl/int-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/alu_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/alu_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/alu_pack-p.vhd (nonexistent) @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_width_c; - -package t48_alu_pack is - - ----------------------------------------------------------------------------- - -- The ALU operations - ----------------------------------------------------------------------------- - type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR, - ALU_CPL, ALU_CLR, - ALU_RL, ALU_RR, - ALU_SWAP, - ALU_DEC, ALU_INC, - ALU_ADD, - ALU_CONCAT, - ALU_NOP); - - ----------------------------------------------------------------------------- - -- The dedicated ALU arithmetic types. - ----------------------------------------------------------------------------- - subtype alu_operand_t is std_logic_vector(word_width_c downto 0); - -end t48_alu_pack;

t48/rel_1_2/rtl/vhdl/alu_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/pmem_ctrl_pack-p.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/pmem_ctrl_pack-p.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/pmem_ctrl_pack-p.vhd (nonexistent) @@ -1,20 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -package t48_pmem_ctrl_pack is - - ----------------------------------------------------------------------------- - -- Address Type Identifier - ----------------------------------------------------------------------------- - type pmem_addr_ident_t is (PM_PC, - PM_PAGE, - PM_PAGE3); - -end t48_pmem_ctrl_pack;

t48/rel_1_2/rtl/vhdl/pmem_ctrl_pack-p.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/db_bus-c.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/db_bus-c.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/db_bus-c.vhd (nonexistent) @@ -1,19 +0,0 @@ -------------------------------------------------------------------------------- --- --- The BUS unit. --- Implements the BUS port logic. --- --- $Id$ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_db_bus_rtl_c0 of t48_db_bus is - - for rtl - end for; - -end t48_db_bus_rtl_c0;

t48/rel_1_2/rtl/vhdl/db_bus-c.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/rtl/vhdl/clock_ctrl.vhd =================================================================== --- t48/rel_1_2/rtl/vhdl/clock_ctrl.vhd (revision 296) +++ t48/rel_1_2/rtl/vhdl/clock_ctrl.vhd (nonexistent) @@ -1,397 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Clock Control unit. --- Clock States and Machine Cycles are generated here. --- --- $Id$ --- --- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.all; - -entity t48_clock_ctrl is - - generic ( - -- divide XTAL1 by 3 to derive Clock States - xtal_div_3_g : integer := 1 - ); - - port ( - clk_i : in std_logic; - xtal_i : in std_logic; - xtal_en_i : in boolean; - res_i : in std_logic; - en_clk_i : in boolean; - xtal3_o : out boolean; - t0_o : out std_logic; - multi_cycle_i : in boolean; - assert_psen_i : in boolean; - assert_prog_i : in boolean; - assert_rd_i : in boolean; - assert_wr_i : in boolean; - mstate_o : out mstate_t; - second_cycle_o : out boolean; - ale_o : out boolean; - psen_o : out boolean; - prog_o : out boolean; - rd_o : out boolean; - wr_o : out boolean - ); - -end t48_clock_ctrl; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of t48_clock_ctrl is - - -- The three XTAL1 cycles. - signal xtal_q : unsigned(1 downto 0); - signal xtal1_s, - xtal2_s, - xtal3_s : boolean; - signal x1_s, - x2_s, - x3_s : std_logic; - - signal t0_q : std_logic; - - - -- The five clock states. - signal mstate_q : mstate_t; - - signal ale_q : boolean; - signal psen_q : boolean; - signal prog_q : boolean; - signal rd_q : boolean; - signal wr_q : boolean; - - - -- The Machine Cycle marker. - signal second_cycle_q : boolean; - signal multi_cycle_q : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Verify the generics - ----------------------------------------------------------------------------- - - -- pragma translate_off - - -- XTAL1 divide by 3 -------------------------------------------------------- - assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0) - report "xtal_div_3_g must be either 1 or 0!" - severity failure; - - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Divide XTAL1 by 3 to derive Clock States. - ----------------------------------------------------------------------------- - use_xtal_div: if xtal_div_3_g = 1 generate - xtal: process (res_i, xtal_i) - begin - if res_i = res_active_c then - xtal_q <= TO_UNSIGNED(0, 2); - t0_q <= '0'; - - elsif xtal_i'event and xtal_i = clk_active_c then - if xtal_en_i then - if xtal_q < 2 then - xtal_q <= xtal_q + 1; - else - xtal_q <= TO_UNSIGNED(0, 2); - end if; - - if xtal3_s then - t0_q <= '1'; - else - t0_q <= '0'; - end if; - - end if; - - end if; - end process xtal; - - x1_s <= '1' - when xtal_q = 0 and xtal_en_i else - '0'; - x2_s <= '1' - when xtal_q = 1 and xtal_en_i else - '0'; - x3_s <= '1' - when xtal_q = 2 and xtal_en_i else - '0'; - t0_o <= t0_q; - - end generate; - - ----------------------------------------------------------------------------- - -- XTAL1 is used directly for Clock States. - ----------------------------------------------------------------------------- - no_xtal_div: if xtal_div_3_g = 0 generate - xtal_q <= TO_UNSIGNED(0, 2); - - x1_s <= '1' - when xtal_en_i else - '0'; - x2_s <= '1' - when xtal_en_i else - '0'; - x3_s <= '1' - when xtal_en_i else - '0'; - t0_o <= xtal_i; - - end generate; - - -- And finally the boolean flags -------------------------------------------- - xtal1_s <= to_boolean(x1_s); - xtal2_s <= to_boolean(x2_s); - xtal3_s <= to_boolean(x3_s); - - - ----------------------------------------------------------------------------- - -- Process external_signal - -- - -- Purpose: - -- Control signals ALE, PSEN, PROG and RD/WR are generated here. - -- - external_signals: process (res_i, xtal_i) - begin - if res_i = res_active_c then - ale_q <= false; - psen_q <= false; - prog_q <= false; - rd_q <= false; - wr_q <= false; - - elsif xtal_i'event and xtal_i = clk_active_c then - - case mstate_q is - when MSTATE5 => - -- RD, WR are set at the end of XTAL2 of first machine cycle - if xtal2_s and not second_cycle_q then - if assert_rd_i then - rd_q <= true; - end if; - if assert_wr_i then - wr_q <= true; - end if; - end if; - - when MSTATE1 => - if xtal3_s then - psen_q <= false; - end if; - - when MSTATE2 => - if xtal3_s then - -- RD, WR are removed at the end of XTAL3 of second machine cycle - rd_q <= false; - wr_q <= false; - -- so is PROG - prog_q <= false; - end if; - - when MSTATE3 => - -- ALE is set at the end of XTAL3 of every machine cycle - if xtal3_s then - ale_q <= true; - end if; - - when MSTATE4 => - if xtal3_s then - -- PSEN is set at the end of XTAL3 - if assert_psen_i then - psen_q <= true; - end if; - - end if; - - -- PROG is set at the end of XTAL3 - if xtal3_s and - multi_cycle_q and not second_cycle_q and assert_prog_i then - prog_q <= true; - end if; - - -- ALE is removed at the end of XTAL2 of every machine cycle - if xtal2_s then - ale_q <= false; - end if; - - when others => - -- recover when states are out of sync - ale_q <= false; - psen_q <= false; - prog_q <= false; - rd_q <= false; - wr_q <= false; - - end case; - - end if; - - end process external_signals; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process states - -- - -- Purpose: - -- The Clock State controller. - -- - states: process (res_i, clk_i) - begin - if res_i = res_active_c then - -- Reset machine state to MSTATE3 - -- This allows a proper instruction fetch for the first real instruction - -- after reset. - -- The MSTATE3 is part of a virtual NOP that has no MSTATE1 and MSTATE2. - mstate_q <= MSTATE3; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - case mstate_q is - when MSTATE5 => - mstate_q <= MSTATE1; - - when MSTATE1 => - mstate_q <= MSTATE2; - - when MSTATE2 => - mstate_q <= MSTATE3; - - when MSTATE3 => - mstate_q <= MSTATE4; - - when MSTATE4 => - mstate_q <= MSTATE5; - - when others => - -- recover when states are out of sync - mstate_q <= MSTATE1; - - -- pragma translate_off - assert false - report "Encoding of Clock States failed!" - severity error; - -- pragma translate_on - - end case; - - end if; - - end if; - - end process states; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process machine_cycle - -- - -- Purpose: - -- Keep track of machine cycles. - -- Basically, this means to differ between first and second cycle. - -- - machine_cycle: process (res_i, clk_i) - variable state2_v, state5_v : boolean; - begin - if res_i = res_active_c then - multi_cycle_q <= false; - second_cycle_q <= false; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - state2_v := mstate_q = MSTATE2; - state5_v := mstate_q = MSTATE5; - - -- multi cycle information is delivered in State 2 from the decoder - if state2_v and multi_cycle_i then - multi_cycle_q <= true; - end if; - - -- mark second machine cycle - if multi_cycle_q and state5_v then - second_cycle_q <= true; - end if; - - -- reset at end of second machine cycle - if state5_v and - (multi_cycle_q and second_cycle_q) then - multi_cycle_q <= false; - second_cycle_q <= false; - end if; - - end if; - - end if; - - end process machine_cycle; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output assignments - ----------------------------------------------------------------------------- - xtal3_o <= xtal3_s; - mstate_o <= mstate_q; - second_cycle_o <= second_cycle_q; - ale_o <= ale_q; - psen_o <= psen_q; - prog_o <= prog_q; - rd_o <= rd_q; - wr_o <= wr_q; - -end rtl;

t48/rel_1_2/rtl/vhdl/clock_ctrl.vhd Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/COMPILE_LIST =================================================================== --- t48/rel_1_2/COMPILE_LIST (revision 296) +++ t48/rel_1_2/COMPILE_LIST (nonexistent) @@ -1,87 +0,0 @@ - -Compile list for the T48 uController project -============================================ -Version: $Id$ - -bench/vhdl/if_timing.vhd -bench/vhdl/if_timing-c.vhd -rtl/vhdl/t48_pack-p.vhd -rtl/vhdl/psw.vhd -rtl/vhdl/psw-c.vhd -rtl/vhdl/pmem_ctrl_pack-p.vhd -rtl/vhdl/pmem_ctrl.vhd -rtl/vhdl/pmem_ctrl-c.vhd -rtl/vhdl/p2.vhd -rtl/vhdl/p2-c.vhd -rtl/vhdl/p1.vhd -rtl/vhdl/p1-c.vhd -rtl/vhdl/timer.vhd -rtl/vhdl/timer-c.vhd -rtl/vhdl/dmem_ctrl_pack-p.vhd -rtl/vhdl/dmem_ctrl.vhd -rtl/vhdl/dmem_ctrl-c.vhd -rtl/vhdl/decoder_pack-p.vhd -rtl/vhdl/cond_branch_pack-p.vhd -rtl/vhdl/alu_pack-p.vhd -rtl/vhdl/t48_comp_pack-p.vhd -rtl/vhdl/int.vhd -rtl/vhdl/int-c.vhd -rtl/vhdl/t48_tb_pack-p.vhd -rtl/vhdl/decoder.vhd -rtl/vhdl/decoder-c.vhd -rtl/vhdl/db_bus.vhd -rtl/vhdl/db_bus-c.vhd -rtl/vhdl/cond_branch.vhd -rtl/vhdl/cond_branch-c.vhd -rtl/vhdl/clock_ctrl.vhd -rtl/vhdl/clock_ctrl-c.vhd -rtl/vhdl/bus_mux.vhd -rtl/vhdl/bus_mux-c.vhd -rtl/vhdl/alu.vhd -rtl/vhdl/alu-c.vhd -rtl/vhdl/t48_core.vhd -rtl/vhdl/t48_core-c.vhd -rtl/vhdl/system/generic_ram_ena.vhd -rtl/vhdl/system/generic_ram_ena-c.vhd -rtl/vhdl/system/lpm_rom.vhd -rtl/vhdl/t48_core_comp_pack-p.vhd -bench/vhdl/tb.vhd -bench/vhdl/tb-c.vhd -Elaborate tb_behav_c0 - -rtl/vhdl/system/t48_rom-e.vhd -bench/vhdl/t48_rom-lpm-a.vhd -bench/vhdl/t48_rom-lpm-c.vhd -rtl/vhdl/system/t8048_notri.vhd -rtl/vhdl/system/t8048_notri-c.vhd -rtl/vhdl/system/t48_system_comp_pack-p.vhd -rtl/vhdl/system/t8048.vhd -rtl/vhdl/system/t8048-c.vhd -bench/vhdl/tb_t8048.vhd -bench/vhdl/tb_t8048-c.vhd -Elaborate tb_t8048_behav_c0 - -rtl/vhdl/system/t8039_notri.vhd -rtl/vhdl/system/t8039_notri-c.vhd -rtl/vhdl/system/t8039.vhd -rtl/vhdl/system/t8039-c.vhd -bench/vhdl/tb_t8039.vhd -bench/vhdl/tb_t8039-c.vhd -Elaborate tb_t8039_behav_c0 - -rtl/vhdl/t8243/t8243_core.vhd -rtl/vhdl/t8243/t8243_core-c.vhd -rtl/vhdl/t8243/t8243_comp_pack-p.vhd -rtl/vhdl/t8243/t8243_async_notri.vhd -rtl/vhdl/t8243/t8243_async_notri-c.vhd -rtl/vhdl/t8243/t8243.vhd -rtl/vhdl/t8243/t8243-c.vhd -bench/vhdl/tb_t8048_t8243.vhd -bench/vhdl/tb_t8048_t8243-c.vhd -Elaborate tb_t8048_t8243_behav_c0 - -rtl/vhdl/t8243/t8243_sync_notri.vhd -rtl/vhdl/t8243/t8243_sync_notri-c.vhd -bench/vhdl/tb_t8243.vhd -bench/vhdl/tb_t8243-c.vhd -Elaborate tb_t8243_behav_c0

t48/rel_1_2/COMPILE_LIST Property changes : Deleted: svn:keywords ## -1 +0,0 ## -Id \ No newline at end of property Index: t48/rel_1_2/doc/src/block_detail.fig =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: t48/rel_1_2/doc/src/block_detail.fig =================================================================== --- t48/rel_1_2/doc/src/block_detail.fig (revision 296) +++ t48/rel_1_2/doc/src/block_detail.fig (nonexistent)

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t48/rel_1_2/doc/T48 Integration Manual.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: t48/rel_1_2/CHANGELOG =================================================================== --- t48/rel_1_2/CHANGELOG (revision 296) +++ t48/rel_1_2/CHANGELOG (nonexistent) @@ -1,127 +0,0 @@ - -Change log for the T48 uController core -======================================= -Version: $Id$ - - -Release 1.1 ------------ - -* code optimizations in the decoder to reduce LUT usage with - Xilinx ISE/XST. - -* fix tb_t8048 and tb_t8049 with respect to P1[0]->T0 signalling. - -* synthesis templates for QuartusII and ISE. - -* added dedicated version of hex2rom utility for RTL ROM generation - (keeps compatibility with QuartusII 7.2). - -* better describe RTL ROM and RAM macros. - - -Release 1.0 ------------ - -* T8243 I/O expander added to project - -* Bugfix for "Deassertion of PROG too early" - PROG is deasserted at end of XTAL3 now. - Applied in clock_ctrl.vhd 1.12 - -* new input xtal_en_i gates xtal_i base clock - -* counter_q in timer module has asynchronous reset - -* replaced syn_rom and syn_ram with t48_rom and generic_ram_ena - -* verification environment updated for new testbenches - - -Release 0.6.1 BETA ------------------- - -* Bugfix for "PROBLEM WHEN INT AND JMP" - Suppress assertion of bus_read_bus_s when interrupt is pending. - Applied in decoder.vhd 1.21 - -* Bugfix for "P2 Port value restored after expander access" - Applied in p2.vhd 1.8 - -* change low impedance markers for P2 - separate marker for low and high part - -* shift assertion of ALE and PROG to xtal3 - -* properly drive P1 and P2 with low impedance markers - -* suppress p2_output_pch_o when MOVX operation is accessing the - external memory - -* suppress p2_output_pch_o when p2_output_exp is active - -* operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 - - -Release 0.6 BETA ----------------- - -* Bugfix for "Wrong clock applied to T0" - Applied in clock_ctrl.vhd 1.7 - t48_core.vhd 1.8 - -* Introduced "notri" hierarchy for t8048 and t8039 system. - This allows the usage of such a system without tri-state signals. - -* Fixed lpm_memory type definition in lpm_rom.vhd and lpm_ram.vhd. - -* New Wishbone master module: wb_master.vhd - -* New system toplevel: t8050_wb.vhd - Contains the Wishbone master. - -* Prefixed all design units with 't48_'. - -* Updates for running the core with full xtal clock. Should work now. - -* Move latching of BUS to MSTATE2 in decoder.vhd - -> sample BUS at the end of RD' - -* Fix a glitch on PCH when an interrupt occurs during external - program memory fetch in decoder.vhd - -* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted - by interrupt" - and "Return address of CALL to Program Memory Bank 1 corrupted - by interrupt" - Applied in int.vhd 1.5 - -* Bugfix for "MSB of Program Counter changed upon PC increment" - Applied in pmem_ctrl.vhd 1.4 - -* Preliminary Integration Manual added. - - -Release 0.5 BETA ----------------- - -* Bugfix for "P1 constantly in push-pull mode in t8048" - Applied in t8048.vhd 1.3 - -* Bugfix for "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" - Applied in decoder.vhd 1.16 - db_bus.vhd 1.3 - Updated testcase black_box/ins. - -* P1, P2 and BUS are written during the first instruction cycle of the - OUTL instruction. This matches the descirption in the User Manual. - The previous implementation updated these ports at the end of the - second instruction cycle. - Applied in decoder.vhd 1.16 - -* Shifted deassertion of RD and WR to end of XTAL3 of machine state 2. - The previous deassertion at the end of XTAL2 was not according to the - User Manual. Their rising edge can now be used as a read/write strobe. - On the other hand, PROG is still deasserted at the end of XTAL3. This - is needed to for the rising edge of PROG within valid P2 expander data. - Applied in clock_ctrl.vhd 1.6

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