URL
https://opencores.org/ocsvn/usb11_sim_model/usb11_sim_model/trunk
Subversion Repositories usb11_sim_model
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- from Rev 3 to Rev 4
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Rev 3 → Rev 4
/usb11_sim_model/trunk/usb_FS_monitor.vhd
7,7 → 7,7
-- the associated disclaimer. -- |
-- -- |
-- This software is provided ''as is'' and without any express or implied warranties, including, but not -- |
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event -- |
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. In no event -- |
-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or -- |
-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss -- |
-- of use, data, or profits; or business interruption) however caused and on any theory of liability, -- |
27,19 → 27,19
-- Version / date Description -- |
-- -- |
-- 01 05 Mar 2011 MN Initial version -- |
-- 02 01 Nov 2011 MN clk_60MHz now internally generated; next_state corrected -- |
-- 03 30 Jan 2012 MN fixed problems at transfer end, modified for protocol checking -- |
-- -- |
-- End change history -- |
--==========================================================================================================-- |
|
LIBRARY IEEE; |
LIBRARY work, IEEE; |
USE work.usb_commands.ALL; |
USE IEEE.std_logic_1164.all; |
USE IEEE.std_logic_textio.all; |
USE std.textio.all; |
LIBRARY work; |
USE work.usb_commands.all; |
|
ENTITY usb_fs_monitor IS PORT( |
clk_60MHz : IN STD_LOGIC; |
master_oe : IN STD_LOGIC; |
usb_Dp : IN STD_LOGIC; |
usb_Dn : IN STD_LOGIC); |
46,17 → 46,18
END usb_fs_monitor; |
|
ARCHITECTURE SIM OF usb_fs_monitor IS |
TYPE state_mode IS(idle, pid, addr, frame, data, spec, eop); |
TYPE state_mode IS(idle, pid, token1, token2, frame1, frame2, data, eop, err); |
SIGNAL clk_en : STD_LOGIC; |
SIGNAL clk_60MHz : STD_LOGIC; |
SIGNAL usb_state : state_mode; |
SIGNAL byte_valid : STD_LOGIC; |
SIGNAL usb_dp_sync : STD_LOGIC; |
SIGNAL usb_dn_sync : STD_LOGIC; |
SIGNAL clk_en : STD_LOGIC; |
SIGNAL usb_bit : STD_LOGIC; |
SIGNAL usb_byte : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL byte_valid : STD_LOGIC; |
SIGNAL xfer_busy : STD_LOGIC; |
SIGNAL bit_cntr : NATURAL; |
SIGNAL dll_cntr : NATURAL; |
SIGNAL next_state : state_mode; |
SIGNAL stuffing_det : STD_LOGIC; |
SIGNAL edge_detect : STD_LOGIC; |
SIGNAL usb_dp_s0 : STD_LOGIC; |
SIGNAL usb_dp_s1 : STD_LOGIC; |
63,6 → 64,7
SIGNAL usb_dn_s0 : STD_LOGIC; |
SIGNAL usb_dn_s1 : STD_LOGIC; |
SIGNAL usb_dp_last : STD_LOGIC; |
SIGNAL se0 : BOOLEAN; |
|
BEGIN |
|
70,6 → 72,17
-- Synchronize Inputs -- |
--==========================================================================================================-- |
|
p_clk_60MHz : PROCESS |
BEGIN |
clk_60MHz <= '0'; |
While true loop |
clk_60MHz <= '0'; |
WAIT FOR 8333 ps; |
clk_60MHz <= '1'; |
WAIT FOR 8334 ps; -- 60 MHz |
end loop; |
END PROCESS; |
|
p_usb_dp_sync: process (clk_60MHz) |
begin |
if rising_edge(clk_60MHz) then |
96,6 → 109,8
end if; |
end process; |
|
usb_bit <= usb_dp_sync AND NOT usb_dn_sync; |
|
p_usb_d_last: process (clk_60MHz) |
begin |
if rising_edge(clk_60MHz) THEN |
105,22 → 120,22
|
edge_detect <= usb_dp_last XOR usb_dp_sync; |
|
p_dll_cntr: process (clk_60MHz) |
begin |
if rising_edge(clk_60MHz) then |
if edge_detect ='1' then |
if dll_cntr >= 8 then |
dll_cntr <= 2; -- clk_en detected, now centered in following cycle |
else |
dll_cntr <= 7; -- adjust clk_en to center cycle |
end if; |
elsif dll_cntr >= 8 then -- normal count sequence is 8->4->5->6->7->8->4... |
p_dll_cntr: PROCESS (clk_60MHz) |
BEGIN |
IF rising_edge(clk_60MHz) THEN |
IF edge_detect ='1' THEN |
IF dll_cntr >= 8 THEN |
dll_cntr <= 2; -- clk_en to be centered in next count sequence |
ELSE |
dll_cntr <= 7; -- clk_en is now centered |
END IF; |
ELSIF dll_cntr >= 8 THEN -- normal count sequence is 8->4->5->6->7->8->4... |
dll_cntr <= 4; |
else |
ELSE |
dll_cntr <= dll_cntr +1; |
end if; |
end if; |
end process; |
END IF; |
END IF; |
END PROCESS; |
|
clk_en <= '1' WHEN dll_cntr >= 8 ELSE '0'; |
|
128,197 → 143,224
-- Analyse USB Inputs -- |
--==========================================================================================================-- |
|
--se0 <= usb_Dp_sync='0' AND usb_Dn_sync='0'; |
|
p_xfer_busy : PROCESS |
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0); |
p_se0 : PROCESS(clk_60MHz) |
BEGIN |
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1'; |
sync_pattern := sync_pattern(6 DOWNTO 0) & usb_Dp_sync; |
IF sync_pattern = "01010100" THEN |
xfer_busy <= '1'; |
WAIT UNTIL rising_edge(clk_60MHz) AND usb_Dp_sync ='0' AND usb_Dn_sync ='0' AND clk_en ='1'; |
IF rising_edge(clk_60MHz) THEN |
IF clk_en ='1' THEN |
se0 <= usb_Dp_sync='0' AND usb_Dn_sync='0'; |
END IF; |
END IF; |
xfer_busy <= '0'; |
END PROCESS; |
|
p_se0_det : PROCESS |
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0); |
p_reset_det : PROCESS(clk_60MHz) |
VARIABLE se0_lev : BOOLEAN; |
VARIABLE se0_time : Time := 0 ns; |
VARIABLE v_LineWr : line := NULL; |
BEGIN |
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1'; |
IF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN |
IF NOT se0_lev THEN |
se0_lev := TRUE; |
se0_time := now; |
END IF; |
ELSE |
IF se0_lev THEN |
se0_time := now - se0_time; |
IF se0_time >= 200 ns THEN |
write (v_LineWr, now, right,15); |
IF se0_time >= 2500 ns THEN |
write (v_LineWr, STRING'(" USB Reset detected for ")); |
ELSE |
write (v_LineWr, STRING'(" USB lines at SE0 for ")); |
IF rising_edge(clk_60MHz) THEN |
IF clk_en ='1' THEN |
IF se0 THEN |
IF NOT se0_lev THEN |
se0_lev := TRUE; |
se0_time := now; |
END IF; |
write (v_LineWr, se0_time, right,15); |
PrintLine(v_LineWr); |
ELSE |
IF se0_lev THEN |
se0_time := now - se0_time; |
IF se0_time >= 200 ns THEN |
write (v_LineWr, now, right,15); |
IF se0_time >= 2500 ns THEN |
write (v_LineWr, STRING'(" USB Reset detected for ")); |
ELSE |
write (v_LineWr, STRING'(" USB lines at SE0 for ")); |
END IF; |
write (v_LineWr, se0_time, right,15); |
PrintLine(v_LineWr); |
END IF; |
END IF; |
se0_lev := FALSE; |
END IF; |
END IF; |
se0_lev := FALSE; |
END IF; |
END PROCESS; |
|
p_usb_byte : PROCESS(xfer_busy, clk_60MHz, clk_en) |
p_usb_byte : PROCESS(usb_state, clk_60MHz) |
VARIABLE hold, usb_last : STD_LOGIC; |
VARIABLE ones_cnt : NATURAL; |
BEGIN |
IF xfer_busy ='0' THEN |
usb_last := usb_Dp_sync; |
bit_cntr <= 0; |
ones_cnt := 0; |
byte_valid <= '0'; |
usb_byte <= (OTHERS => 'H'); |
ELSIF rising_edge(clk_60MHz) AND clk_en ='1' THEN |
IF usb_Dp_sync = usb_last THEN |
usb_byte <= '1' & usb_byte(7 DOWNTO 1); |
bit_cntr <= (bit_cntr +1) MOD 8; |
ones_cnt := (ones_cnt +1); |
IF ones_cnt > 6 THEN |
ASSERT FALSE REPORT"Stuffing error" SEVERITY ERROR; |
END IF; |
hold := '0'; |
ELSE |
IF ones_cnt /= 6 THEN |
usb_byte <= '0' & usb_byte(7 DOWNTO 1); |
IF rising_edge(clk_60MHz) THEN |
IF usb_state = idle OR usb_state = eop THEN |
usb_last := usb_bit; |
bit_cntr <= 0; |
ones_cnt := 0; |
byte_valid <= '0'; |
usb_byte <= (OTHERS => 'H'); |
ELSIF clk_en ='1' THEN |
IF usb_bit = usb_last THEN |
usb_byte <= '1' & usb_byte(7 DOWNTO 1); |
bit_cntr <= (bit_cntr +1) MOD 8; |
ones_cnt := (ones_cnt +1); |
IF ones_cnt > 6 THEN |
ASSERT FALSE REPORT"Stuffing error" SEVERITY ERROR; |
END IF; |
hold := '0'; |
ELSE |
hold := '1'; |
IF ones_cnt /= 6 THEN |
usb_byte <= '0' & usb_byte(7 DOWNTO 1); |
bit_cntr <= (bit_cntr +1) MOD 8; |
hold := '0'; |
ELSE |
hold := '1'; |
END IF; |
ones_cnt := 0; |
END IF; |
ones_cnt := 0; |
IF bit_cntr=7 THEN |
byte_valid <= NOT hold; |
ELSE |
byte_valid <= '0'; |
END IF; |
usb_last := usb_bit; |
END IF; |
IF bit_cntr=7 THEN |
byte_valid <= NOT hold; |
ELSE |
byte_valid <= '0'; |
END IF; |
usb_last := usb_Dp_sync; |
stuffing_det <= hold; |
END IF; |
END PROCESS; |
|
p_usb_state : PROCESS |
BEGIN |
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1'; |
IF xfer_busy ='0' THEN |
usb_state <= idle; |
ELSIF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN |
usb_state <= eop; |
ELSE |
usb_state <= next_state; |
END IF; |
END PROCESS; |
|
p_next_state : PROCESS |
p_usb_state : PROCESS(clk_60MHz) |
VARIABLE address : STD_LOGIC_VECTOR(6 DOWNTO 0); |
VARIABLE endpoint : STD_LOGIC_VECTOR(3 DOWNTO 0); |
VARIABLE frame_no : STD_LOGIC_VECTOR(10 DOWNTO 0); |
VARIABLE byte_cnt : NATURAL; |
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0); |
VARIABLE v_LineWr : line := NULL; |
BEGIN |
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1'; |
CASE usb_state IS |
WHEN idle => next_state <= pid; |
WHEN pid => IF byte_valid ='1' THEN |
IF usb_byte(3 DOWNTO 0) /= NOT usb_byte(7 DOWNTO 4) THEN |
ASSERT FALSE REPORT"PID error" SEVERITY ERROR; |
END IF; |
write (v_LineWr, now, right,15); |
IF master_oe ='1' THEN |
write (v_LineWr, STRING'(" Send ")); |
ELSE |
write (v_LineWr, STRING'(" Recv ")); |
END IF; |
byte_cnt := 0; |
CASE usb_byte(3 DOWNTO 0) IS |
WHEN x"1" => next_state <= addr; |
write (v_LineWr, STRING'("OUT-Token")); |
WHEN x"9" => next_state <= addr; |
write (v_LineWr, STRING'("IN-Token")); |
WHEN x"5" => next_state <= frame; |
write (v_LineWr, STRING'("SOF-Token")); |
WHEN x"D" => next_state <= addr; |
write (v_LineWr, STRING'("Setup")); |
WHEN x"3" => next_state <= data; |
write (v_LineWr, STRING'("Data0")); |
WHEN x"B" => next_state <= data; |
write (v_LineWr, STRING'("Data1")); |
WHEN x"7" => next_state <= data; |
write (v_LineWr, STRING'("Data2")); |
WHEN x"F" => next_state <= data; |
write (v_LineWr, STRING'("MData")); |
WHEN x"2" => next_state <= idle; |
write (v_LineWr, STRING'("ACK")); |
WHEN x"A" => next_state <= idle; |
write (v_LineWr, STRING'("NAK")); |
WHEN x"E" => next_state <= idle; |
write (v_LineWr, STRING'("STALL")); |
WHEN x"6" => next_state <= idle; |
write (v_LineWr, STRING'("NYET")); |
-- WHEN x"C" => next_state <= spec; |
-- write (v_LineWr, STRING'("Preamble")); |
WHEN x"C" => next_state <= spec; |
write (v_LineWr, STRING'("ERR")); |
WHEN x"8" => next_state <= spec; |
write (v_LineWr, STRING'("Split")); |
WHEN x"4" => next_state <= spec; |
write (v_LineWr, STRING'("Ping")); |
WHEN OTHERS => next_state <= idle; |
ASSERT FALSE REPORT"PID is zero" SEVERITY ERROR; |
END CASE; |
END IF; |
WHEN addr => IF byte_valid ='1' THEN |
address := usb_byte(6 DOWNTO 0); |
endpoint(0) := usb_byte(7); |
WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1'; |
endpoint(3 DOWNTO 1) := usb_byte(2 DOWNTO 0); |
write (v_LineWr, STRING'(": Address 0x")); |
HexWrite (v_LineWr, address); |
write (v_LineWr, STRING'(", Endpoint 0x")); |
HexWrite (v_LineWr, endpoint); |
write (v_LineWr, STRING'(", CRC5 0x")); |
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3)); |
next_state <= idle; |
END IF; |
WHEN frame =>IF byte_valid ='1' THEN |
frame_no(7 DOWNTO 0) := usb_byte; |
WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1'; |
frame_no(10 DOWNTO 8) := usb_byte(2 DOWNTO 0); |
write (v_LineWr, STRING'(": Frame No 0x")); |
HexWrite (v_LineWr, frame_no); |
write (v_LineWr, STRING'(", CRC5 0x")); |
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3)); |
next_state <= idle; |
END IF; |
WHEN data => WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1'; |
byte_cnt := byte_cnt +1; |
IF byte_cnt = 17 THEN |
PrintLine(v_LineWr); |
write (v_LineWr, now, right,15); |
write (v_LineWr, STRING'(" .....")); |
byte_cnt := 1; |
END IF; |
write (v_LineWr, STRING'(" 0x")); |
HexWrite (v_LineWr, usb_byte); |
WHEN eop => next_state <= idle; |
PrintLine(v_LineWr); |
WHEN OTHERS => next_state <= idle; |
END CASE; |
IF rising_edge(clk_60MHz) THEN |
IF clk_en ='1' THEN |
IF se0 THEN |
sync_pattern := (OTHERS => '0'); |
ELSE |
sync_pattern := sync_pattern(6 DOWNTO 0) & usb_bit; |
END IF; |
CASE usb_state IS |
WHEN idle => IF sync_pattern = "01010100" THEN |
usb_state <= pid; |
ELSE |
usb_state <= idle; |
END IF; |
WHEN pid => IF byte_valid ='1' THEN |
IF usb_byte(3 DOWNTO 0) /= NOT usb_byte(7 DOWNTO 4) THEN --+------+------+-------------+ |
ASSERT FALSE REPORT"PID error" SEVERITY ERROR; --| PID | usb- | String | |
END IF; --|Bit3:0|state | | |
write (v_LineWr, now, right,15); --|------|------|-------------| |
IF master_oe ='1' THEN --| x"1" | token| "OUT-Token" | |
write (v_LineWr, STRING'(" Send ")); --| x"2" | idle | "ACK" | |
ELSE --| x"3" | data | "Data0" | |
write (v_LineWr, STRING'(" Recv ")); --| x"4" | N/A | "Ping" | |
END IF; --| x"5" | frame| "SOF-Token" | |
byte_cnt := 0; --| x"6" | idle | "NYET" | |
ASSERT usb_byte(3 DOWNTO 0) = NOT usb_byte(7 DOWNTO 4) --| x"7" | data | "Data2" | |
REPORT"PID error detected" SEVERITY ERROR; --| x"8" | N/A | "Split" | |
CASE usb_byte(3 DOWNTO 0) IS --| x"9" | token| "IN-Token" | |
WHEN x"1" => write (v_LineWr, STRING'("OUT-Token")); --| x"A" | idle | "NAK" | |
WHEN x"9" => write (v_LineWr, STRING'("IN-Token")); --| x"B" | data | "Data1" | |
WHEN x"5" => write (v_LineWr, STRING'("SOF-Token")); --| x"C" | N/A | "Preamble" | |
WHEN x"D" => write (v_LineWr, STRING'("Setup")); --| x"D" | token| "Setup" | |
WHEN x"3" => write (v_LineWr, STRING'("Data0")); --| x"E" | idle | "STALL" | |
WHEN x"B" => write (v_LineWr, STRING'("Data1")); --| x"F" | data | "MData" | |
WHEN x"7" => write (v_LineWr, STRING'("Data2")); --| x"0" | idle | "Error" | |
WHEN x"F" => write (v_LineWr, STRING'("MData")); --+------+------+-------------+ |
WHEN x"2" => write (v_LineWr, STRING'("ACK")); |
WHEN x"A" => write (v_LineWr, STRING'("NAK")); |
WHEN x"E" => write (v_LineWr, STRING'("STALL")); |
WHEN x"6" => write (v_LineWr, STRING'("NYET")); |
WHEN x"C" => write (v_LineWr, STRING'("Preamble")); |
-- WHEN x"C" => write (v_LineWr, STRING'("SPLIT-ERR")); |
WHEN x"8" => write (v_LineWr, STRING'("Split")); |
WHEN x"4" => write (v_LineWr, STRING'("Ping")); |
WHEN OTHERS => ASSERT FALSE REPORT"PID is zero" SEVERITY ERROR; |
END CASE; |
CASE usb_byte(3 DOWNTO 0) IS |
WHEN x"1" | x"9" | x"D" => usb_state <= token1; |
WHEN x"5" => usb_state <= frame1; |
WHEN x"3" | x"B" | x"7" | x"F" => usb_state <= data; |
WHEN x"2" | x"A" | x"E" | x"6" => usb_state <= eop; |
PrintLine(v_LineWr); -- print as soon as possible |
WHEN others => usb_state <= idle; |
ASSERT FALSE REPORT "FS-Monitor: This PID is not impemented" SEVERITY WARNING; |
END CASE; |
END IF; |
IF se0 THEN |
usb_state <= err; |
END IF; |
WHEN token1 => IF byte_valid ='1' THEN |
address := usb_byte(6 DOWNTO 0); |
endpoint(0) := usb_byte(7); |
usb_state <= token2; |
END IF; |
IF se0 THEN |
usb_state <= err; |
END IF; |
WHEN token2 => IF byte_valid ='1' THEN |
endpoint(3 DOWNTO 1) := usb_byte(2 DOWNTO 0); |
write (v_LineWr, STRING'(": Address 0x")); |
HexWrite (v_LineWr, address); |
write (v_LineWr, STRING'(", Endpoint 0x")); |
HexWrite (v_LineWr, endpoint); |
write (v_LineWr, STRING'(", CRC5 0x")); |
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3)); |
usb_state <= eop; |
PrintLine(v_LineWr); |
END IF; |
WHEN frame1 => IF byte_valid ='1' THEN |
frame_no(7 DOWNTO 0) := usb_byte; |
usb_state <= frame2; |
END IF; |
IF se0 THEN |
usb_state <= err; |
END IF; |
WHEN frame2 => IF byte_valid ='1' THEN |
frame_no(10 DOWNTO 8) := usb_byte(2 DOWNTO 0); |
write (v_LineWr, STRING'(": Frame No 0x")); |
HexWrite (v_LineWr, frame_no); |
write (v_LineWr, STRING'(", CRC5 0x")); |
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3)); |
usb_state <= err; |
usb_state <= eop; |
PrintLine(v_LineWr); |
END IF; |
WHEN data => IF byte_valid ='1' THEN |
byte_cnt := byte_cnt +1; |
IF byte_cnt = 17 THEN |
PrintLine(v_LineWr); |
write (v_LineWr, now, right,15); |
write (v_LineWr, STRING'(" .....")); |
byte_cnt := 1; |
END IF; |
write (v_LineWr, STRING'(" 0x")); |
HexWrite (v_LineWr, usb_byte); |
ELSIF se0 THEN |
PrintLine(v_LineWr); |
IF bit_cntr <= 1 THEN |
usb_state <= idle; |
ELSE |
usb_state <= err; |
END IF; |
END IF; |
WHEN eop => IF se0 THEN |
usb_state <= idle; |
ELSIF stuffing_det = '0' THEN |
usb_state <= err; |
END IF; |
WHEN OTHERS => PrintLine(v_LineWr); -- CASE err |
ASSERT FALSE REPORT "FS monitor: protocol error" SEVERITY ERROR; |
usb_state <= idle; |
END CASE; |
END IF; |
END IF; |
END PROCESS; |
|
usb_busy <= usb_state /= idle; -- global signal, used in usb_commands -- |
usb_busy <= NOT(usb_state = idle OR usb_state = eop); -- global signal, defiened and used in usb_commands -- |
|
END SIM; |
|