URL
https://opencores.org/ocsvn/wbicapetwo/wbicapetwo/trunk
Subversion Repositories wbicapetwo
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/wbicapetwo/trunk/rtl/wbicape6.v
0,0 → 1,304
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbicape6.v |
// |
// Project: Wishbone to ICAPE_SPARTAN6 interface conversion |
// |
// Purpose: This is a companion project to the ICAPE2 conversion, instead |
// involving a conversion from a 32-bit WISHBONE bus to read |
// and write the ICAPE_SPARTAN6 program. This is the 'non-simple' |
// portion of the interface, sporting all of the smarts necessary to run |
// the simple interface and make working with ICAPE as simple as |
// reading and writing from a wishbone bus. For example, register ID's |
// are given by bus addresses, even though they take extra cycles to |
// set and clear within the interface. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Following instructions on page 116-117 of the configuration guide ... |
// |
// W FFFF |
// W FFFF |
// W AA99 |
// W 5566 |
// W 2000 NOOP |
// W 2901 Write Type-1 packet header to read register 901?? |
// W 2000 NOOP |
// W 2000 NOOP |
// W 2000 NOOP |
// W 2000 NOOP |
// R vvvv Read register from previous packet header command |
// W 30A1 Write word to CMD register |
// W 000D DESYNC command |
// W 2000 NOOP |
// W 2000 NOOP |
// |
// Bits need to be bit-reversed within a byte |
// |
// |
// IPROG example |
// |
// W FFFF |
// W AA99 |
// W 5566 |
// W 3261 Write 1 words to GENERAL_1 |
// W xxxx write Multiboot start address [15:0] |
// W 3281 Write 1 words to GENERAL_2 |
// W xxxx write Opcode and multiboot start address [23:16] |
// W 32A1 Write 1 words to GENERAL_3 |
// W xxxx write Fallback start address |
// W 32C1 Write 1 words to GENERAL_4 |
// W xxxx write Opcode dne Fallback start address [23:16] |
// W 30A1 Write 1 word to CMD |
// W 000E IPGROG Cmd |
// W 2000 NOOP |
// |
// |
// |
// This fails when using wgregs on the XuLA2 board because the ICAPE port and |
// the JTAG port cannot both be active at the same time. |
// |
// |
`define ICAP_IDLE 5'h0 |
`define ICAP_START 5'h1 |
`define ICAP_CLOSE 5'hf |
module wbicape6(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, dbg_data); |
input i_clk; |
// Wishbone slave inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [5:0] i_wb_addr; |
input [31:0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output reg o_wb_stall; |
output wire [31:0] o_wb_data; |
output wire [31:0] dbg_data; |
|
// Interface to the lower level ICAPE port |
reg icap_cyc, icap_stb, icap_we; |
reg [15:0] icap_data_i; |
wire icap_ack, icap_stall; |
wire [15:0] icap_data_o; |
|
reg [4:0] state; |
reg r_we; |
reg [15:0] r_data; |
|
wire [25:0] icap_dbg; |
assign dbg_data = { i_wb_stb, state[3:0], r_we, icap_dbg }; |
|
reg stalled_state; |
reg [7:0] r_cmd_word; |
wire [15:0] w_cmd_word; |
assign w_cmd_word = { 3'b001, r_cmd_word, 5'h00 }; // Type-1 packet hdr |
initial icap_stb = 1'b0; |
initial icap_cyc = 1'b0; |
initial state = `ICAP_IDLE; |
always @(posedge i_clk) |
begin |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b0; |
if (stalled_state) |
state <= `ICAP_IDLE; |
else if ((~icap_stall)&&(state != `ICAP_IDLE)) |
state <= state + 1; |
case(state) |
`ICAP_IDLE: begin |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
state <= `ICAP_IDLE; |
r_data <= i_wb_data[15:0]; |
r_we <= i_wb_we; |
if ((i_wb_cyc)&&(i_wb_stb)) |
begin |
state <= `ICAP_START; |
icap_stb <= i_wb_stb; |
icap_cyc <= i_wb_cyc; |
icap_we <= 1'b1; |
icap_data_i <= 16'hffff; |
r_cmd_word <= { (i_wb_we)? 2'b10:2'b01, i_wb_addr }; |
o_wb_stall <= 1'b1; |
end end |
`ICAP_START: begin |
if (~icap_stall) |
icap_data_i <= 16'hffff; |
end |
5'h2: begin |
if (~icap_stall) |
icap_data_i <= 16'haa99; |
end |
5'h3: begin |
if (~icap_stall) |
icap_data_i <= 16'h5566; |
end |
5'h4: begin |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h5: begin |
if (~icap_stall) |
begin |
icap_data_i <= w_cmd_word; // Includes address |
end end |
5'h6: begin // Write |
if (~icap_stall) |
begin |
if (r_we) |
icap_data_i <= r_data; |
else |
icap_data_i <= 16'h2000; |
end end |
5'h7: begin |
// Need to send four NOOPs before we can begin |
// reading. Send the four NOOPs for a write anyway. |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h8: begin |
if (~icap_stall) |
icap_data_i <= 16'h2000; |
end |
5'h9: begin |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
if (r_we) |
state <= `ICAP_CLOSE; |
end end |
5'ha: begin |
if (~icap_stall) |
begin |
// We now request the chip enable line be |
// dropped, so we can switch from writing to |
// reading |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
end end |
5'hb: begin |
if (~icap_stall) |
begin |
// Switch the write line to read, must be done |
// w/the chip enable off (hence _cyc=0). O/w |
// the interface will abort. |
icap_data_i <= 16'h2000; |
icap_we <=1'b0; |
end end |
5'hc: begin |
if (~icap_stall) |
begin |
// We can finally issue our read command |
// Re-activate the interface, and read |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b1; |
icap_cyc <= 1'b1; |
end end |
5'hd: begin |
if (~icap_stall) |
begin |
// De-activate the interface again so we can |
// switch back to write. |
icap_data_i <= 16'h2000; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
end end |
5'he: begin |
if (~icap_stall) |
begin |
// Switch back to write while the interface |
// is deactivated. |
icap_we <= 1'b1; |
icap_data_i <= 16'h2000; |
end end |
`ICAP_CLOSE: begin |
if (~icap_stall) |
begin |
icap_we <= 1'b1; |
// Type 1: Write 1 word to CMD register |
icap_data_i <= 16'h30a1; |
r_data <= icap_data_o; |
icap_stb <= 1'b1; |
icap_cyc <= 1'b1; |
end end |
5'h10: begin // DESYNC Command |
if (~icap_stall) |
begin |
icap_data_i <= 16'h000d; |
end end |
5'h11: begin // DESYNC must be followed by two NOOPs |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
end end |
5'h12: begin // NOOP |
if (~icap_stall) |
begin |
icap_data_i <= 16'h2000; |
state <= `ICAP_IDLE; |
o_wb_ack <= 1'b1; |
o_wb_stall <= 1'b0; |
end end |
default: begin |
// If we were in the middle of a bus cycle, and got |
// here then ... we just failed that cycle. Setting |
// the bus error flag would be appropriate, but we |
// have no such flag to our interface. Hence we just |
// drop things and depend upon a bus watchdog to |
// catch that we aren't answering. |
o_wb_ack <= 1'b0; |
o_wb_stall <= 1'b0; |
icap_stb <= 1'b0; |
icap_cyc <= 1'b0; |
state <= `ICAP_IDLE; |
end |
endcase |
end |
|
wbicapesimple spartancfg(i_clk, icap_cyc, icap_stb, icap_we, |
icap_data_i, |
icap_ack, icap_stall, icap_data_o, |
icap_dbg); |
|
|
assign o_wb_data = { 16'h0000, r_data }; |
|
reg [3:0] last_state; |
initial last_state = `ICAP_IDLE; |
always @(posedge i_clk) |
last_state <= state; |
|
reg [11:0] reset_ctr; |
always @(posedge i_clk) |
if (last_state != state) |
reset_ctr <= 0; |
else if (state == `ICAP_IDLE) |
reset_ctr <= 0; |
else |
reset_ctr <= reset_ctr + 1; |
always @(posedge i_clk) |
stalled_state <= (&reset_ctr); |
|
endmodule |
/wbicapetwo/trunk/rtl/wbicapetwo.v
66,7 → 66,7
// (CS/W) 0x20000000 NOOP |
// (Idle) |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
/wbicapetwo/trunk/rtl/wbicapesimple.v
0,0 → 1,170
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbicapesimple.v |
// |
// Project: Wishbone to ICAPE_SPARTAN6 interface conversion |
// |
// Purpose: This is a companion project to the ICAPE2 conversion, instead |
// involving a conversion from a 32-bit WISHBONE bus to read |
// and write the ICAPE_SPARTAN6 program. Since this is a simple interface |
// only, the smarts have been stripped out of it. Therefore, if you wish |
// to write to or read from particular registers, you will need to do all |
// the sequencing yourself. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbicapesimple(i_clk, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, icap_dbg); |
input i_clk; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [15:0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [15:0] o_wb_data; |
output wire [25:0] icap_dbg; |
|
|
// Divide our clock by 8. Thus, a 100 MHz clock with a 10 ns period |
// gets divided down to an 80 ns period, which is greater than the |
// minimum 50 ns as per the data sheet. |
reg [2:0] clk_divider; |
initial clk_divider=0; |
always @(posedge i_clk) |
clk_divider <= clk_divider + 3'h1; |
|
reg icap_posedge, icap_preedge; |
initial icap_posedge = 0; |
always @(posedge i_clk) |
icap_posedge <= (clk_divider == 3'b011); |
initial icap_preedge = 0; |
always @(posedge i_clk) |
icap_preedge <= (clk_divider == 3'b010); |
// icap_posedge <= (&clk_divider); |
|
wire icap_clk; |
assign icap_clk = clk_divider[2]; |
|
reg icap_ce_n, icap_we_n; |
reg [15:0] icap_data_i; |
|
|
wire icap_busy; |
wire [15:0] icap_data_o; |
ICAP_SPARTAN6 icap_inst( |
.BUSY(icap_busy), // Active high, low during all writes |
.O(icap_data_o), |
.CE(icap_ce_n), |
.CLK(icap_clk), |
.I(icap_data_i), |
.WRITE(icap_we_n)); |
|
// assign o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy))); |
|
wire [15:0] brev_i_wb_data; |
assign brev_i_wb_data[ 0] = i_wb_data[ 7]; |
assign brev_i_wb_data[ 1] = i_wb_data[ 6]; |
assign brev_i_wb_data[ 2] = i_wb_data[ 5]; |
assign brev_i_wb_data[ 3] = i_wb_data[ 4]; |
assign brev_i_wb_data[ 4] = i_wb_data[ 3]; |
assign brev_i_wb_data[ 5] = i_wb_data[ 2]; |
assign brev_i_wb_data[ 6] = i_wb_data[ 1]; |
assign brev_i_wb_data[ 7] = i_wb_data[ 0]; |
// |
assign brev_i_wb_data[ 8] = i_wb_data[15]; |
assign brev_i_wb_data[ 9] = i_wb_data[14]; |
assign brev_i_wb_data[10] = i_wb_data[13]; |
assign brev_i_wb_data[11] = i_wb_data[12]; |
assign brev_i_wb_data[12] = i_wb_data[11]; |
assign brev_i_wb_data[13] = i_wb_data[10]; |
assign brev_i_wb_data[14] = i_wb_data[ 9]; |
assign brev_i_wb_data[15] = i_wb_data[ 8]; |
// |
|
initial icap_data_i = 0; |
always @(posedge i_clk) |
if (icap_preedge) |
begin |
if (~i_wb_cyc) |
icap_data_i <= 16'hffff; |
else if ((icap_ce_n)||(~icap_busy)) |
icap_data_i <= brev_i_wb_data[15:0]; |
end |
|
initial icap_we_n = 1'b1; |
always @(posedge i_clk) |
if ((icap_preedge)&&((icap_ce_n)||(~icap_busy))) |
icap_we_n <= ~i_wb_we; |
initial icap_ce_n = 1'b1; |
always @(posedge i_clk) |
if ((icap_preedge)&&((icap_ce_n)||(~icap_busy))) |
icap_ce_n <= ~((i_wb_cyc)&&(i_wb_stb)); |
else if ((icap_preedge)&&(~i_wb_cyc)) |
icap_ce_n <= 1'b1; |
//initial r_wb_stall = 1'b0; |
//always @(posedge i_clk) |
//r_wb_stall <= (~icap_posedge)&&( |
//&&(icap_preedge)&&(~icap_busy)); |
// assign o_wb_stall = (i_wb_cyc)&&((~icap_posedge)||((~icap_ce_n)&&(icap_busy))); |
assign o_wb_stall = (~icap_posedge) |
||((i_wb_cyc)&&(~icap_ce_n)&&(icap_busy)); |
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= ((~icap_ce_n)&&(i_wb_cyc) |
&&(icap_preedge)&&(~icap_busy)); |
|
wire [15:0] brev_icap_data; |
assign brev_icap_data[ 0] = icap_data_o[ 7]; |
assign brev_icap_data[ 1] = icap_data_o[ 6]; |
assign brev_icap_data[ 2] = icap_data_o[ 5]; |
assign brev_icap_data[ 3] = icap_data_o[ 4]; |
assign brev_icap_data[ 4] = icap_data_o[ 3]; |
assign brev_icap_data[ 5] = icap_data_o[ 2]; |
assign brev_icap_data[ 6] = icap_data_o[ 1]; |
assign brev_icap_data[ 7] = icap_data_o[ 0]; |
// |
assign brev_icap_data[ 8] = icap_data_o[15]; |
assign brev_icap_data[ 9] = icap_data_o[14]; |
assign brev_icap_data[10] = icap_data_o[13]; |
assign brev_icap_data[11] = icap_data_o[12]; |
assign brev_icap_data[12] = icap_data_o[11]; |
assign brev_icap_data[13] = icap_data_o[10]; |
assign brev_icap_data[14] = icap_data_o[ 9]; |
assign brev_icap_data[15] = icap_data_o[ 8]; |
// |
initial o_wb_data = 16'h000; |
always @(posedge i_clk) |
if ((icap_posedge)&&((icap_ce_n)||(~icap_busy))) |
o_wb_data <= brev_icap_data; |
|
assign icap_dbg[25:0] = { |
i_wb_cyc,i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall, |
icap_posedge, icap_clk, icap_ce_n, icap_busy, icap_we_n, |
(icap_we_n)?icap_data_o : icap_data_i }; |
|
endmodule |
|