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URL https://opencores.org/ocsvn/RISCMCU/RISCMCU/trunk

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Rev 3 → Rev 4

/trunk/v_controlunit.vhd
102,7 → 102,6
 
signal ibr : std_logic_vector(11 downto 0);
signal state : statetype;
 
signal one, neg, imm : std_logic;
 
signal
130,19 → 129,13
 
begin
 
-- Decoder Begin ------------------------------------------------
--
-- Decode 46 instructions (48 - NOP - WDR)
--
-- Combine cbi,sbi (cbisbi) sbrc,sbrs (sbrcs) sbic,sbis (sbic,sbis)
--
-- Generate C2A and C2B
--
-- Instruction Decoder
-- Decode 51 instructions generate 46 'm signals
-- Combine brbcs+brbs (brbcs) cbi+sbi (cbisbi) sbrc+sbrs (sbrcs) sbic+sbis (sbics)
 
 
process(ir, wr_reg, get_io, ibr)
begin
-- 43 signal
 
cpcm <= '0'; sbcm <= '0'; addm <= '0';
cpsem <= '0'; cpm <= '0'; subm <= '0'; adcm <= '0';
andm <= '0'; eorm <= '0'; orm <= '0'; movm <= '0';
232,6 → 225,8
when others =>
end case;
 
 
-- Generate Fetch Stage Signals : C2A and C2B (C2A active also when fetch I/O)
if ((ibr(7 downto 4) = ir(7 downto 4)) and wr_reg = '1') or get_io = '1' then
c2a <= '1';
else
246,14 → 241,8
 
end process;
 
-- Decoder End ------------------------------------------------------------
 
 
 
-- Helper Signal Begin ---------------------------------------------------
--
-- 8 : ibr, imm, wcarry, one, neg, logicsel, rightsel, dirsel
--
-- Generate wcarry, logicsel, rightsel and dirsel
-- Load IBR with IR when EN active
process(clk,clrn)
begin
if clrn = '0' then
288,17 → 277,9
end if;
end process;
-- Helper Signal End -----------------------------------------------------
 
 
-- Control Unit Begin ----------------------------------------------------
--
-- Main Signal : 17
-- wr_reg, pass_a, sren, rd_io, wr_io
-- add, subcp, logic, right, dir
-- rjmp, rcall, ret, brbc, brbs
-- bclr, bset
--
-- Finite State Machine
 
irq <= (timerirq or extirq) and sr(7);
break <= branch or skip or irq;
310,7 → 291,6
 
state <= exes;
 
 
en <= '1'; get_io <= '0';
pass_a <= '0'; wr_reg <= '0'; sren <= "0000000";
rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0';
320,7 → 300,6
bclr <= '0'; bset <= '0'; bld <= '0';
cpse <= '0'; skiptest <= '0';
cbisbi <= '0';
 
vec2 <= '0'; vec4 <= '0'; set_i <= '0';
 
elsif clk'event and clk = '1' then
334,7 → 313,6
bclr <= '0'; bset <= '0'; bld <= '0';
cpse <= '0'; skiptest <= '0';
cbisbi <= '0';
 
vec2 <= '0'; vec4 <= '0'; set_i <= '0';
 
case state is
374,28 → 352,27
state <= sleeps;
end if;
 
-- PC signals
jmp <= rjmpm or rcallm; -- encoded
push <= rcallm;
pull <= retm or retim;
 
-- PC and IR signals
en <= not (cbisbim or sbicsm
or stm or st_incm or st_decm or
ldm or ld_incm or ld_decm);
 
-- General Purpose Register File signals
wr_reg <= addm or adcm or incm
or subm or subim or sbcm or sbcim or decm or negm
or andm or andim or orm or orim or eorm or comm
or lsrm or rorm or asrm
or ldim or movm or swapm
or inm;
 
pass_a <= outm or stm or st_incm or st_decm;
 
wr_io <= outm;
rd_io <= inm or sbicsm or cbisbim;
 
ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm;
ld_mbr <= stm or st_incm or st_decm;
 
or subm or subim or sbcm or sbcim or decm or negm
or andm or andim or orm or orim or eorm or comm
or lsrm or rorm or asrm
or ldim or movm or swapm
or inm;
inc_zp <= ld_incm or st_incm;
dec_zp <= ld_decm or st_decm;
 
-- ALU signals
add <= addm or adcm or incm;
subcp <= subm or subim or sbcm or sbcim or decm or negm
or cpm or cpim or cpcm;
402,25 → 379,18
logic <= andm or andim or orm or orim or eorm or comm;
right <= lsrm or rorm or asrm;
dir <= ldim or movm or swapm;
 
bclr <= bclrm;
bset <= bsetm;
bld <= bldm;
 
pass_a <= outm or stm or st_incm or st_decm;
cpse <= cpsem;
skiptest <= sbrcsm or cpsem;
skiptest <= sbrcsm;
 
branchtest <= brbcsm;
 
jmp <= rjmpm or rcallm;
push <= rcallm;
pull <= retm or retim;
-- SR signals
bclr <= bclrm;
bset <= bsetm;
set_i <= retim;
 
set_i <= retim;
 
get_io <= cbisbim or sbicsm;
 
sren(0) <= addm or adcm
or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm
or comm
436,8 → 406,15
sren(5) <= addm or adcm
or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm;
sren(6) <= bstm;
sren(6) <= bstm;
 
-- Data RAM signals
ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm;
ld_mbr <= stm or st_incm or st_decm;
-- I/O decoder signals
wr_io <= outm;
rd_io <= inm or sbicsm or cbisbim;
if inm = '1' or outm = '1' then
ioaddr <= conv_integer(ir(10 downto 9) & ir(3 downto 0));
else
444,6 → 421,14
ioaddr <= conv_integer('0' & ir(7 downto 3));
end if;
 
 
-- Branch Evaluation Unit signal
branchtest <= brbcsm;
 
 
-- Fetch I/O, generate C2A
get_io <= cbisbim or sbicsm;
 
end if;
 
when nop2s =>
488,6 → 473,7
end if;
end process;
 
-- Generate Delayed WR_RAM signal to avoid writing to wrong address
process(state, wr_ram_fast)
begin
if state = exes then
498,7 → 484,7
end process;
 
 
-- branch evaluation --------------------------------------------
-- Branch Evaluation Unit
process(branchtest, sr, ibr)
begin
if branchtest = '1' and (sr(conv_integer(ibr(2 downto 0))) = not ibr(10)) then
508,20 → 494,22
end if;
end process;
 
-------------------------------------------------
 
-- IO address decoder --------------------------
-- IO address decoder
iodec : v_iodecoder
port map (ioaddr, rd_io, wr_io, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind);
----------------------------------------------------
 
 
-- Intruction Buffer Register (IBR) to signals ------------------
dest <= conv_integer(ibr(7 downto 4));
 
srsel <= conv_integer(ibr(6 downto 4));
set <= ibr(9);
bitsel <= conv_integer(ibr(2 downto 0));
offset <= ibr(8 downto 0) when jmp = '1' else
ibr(9) & ibr(9) & ibr(9 downto 3);
 
 
-- Generate Fetch Stage Signals : ASEL and SEL
imm <= subim or sbcim or cpim or andim or orim or ldim;
one <= incm or decm;
neg <= negm;
528,21 → 516,18
 
asel <= 1 when neg = '1' and get_io = '0' else
0;
 
bsel <= 1 when neg = '1' else
2 when imm = '1' else
3 when one = '1' else
0;
 
offset <= ibr(8 downto 0) when jmp = '1' else
ibr(9) & ibr(9) & ibr(9 downto 3);
 
addoffset <= branch or jmp;
-- Decode Control Signal
addoffset <= branch or jmp; -- PC
clr_i <= vec2 or vec4; -- PC
clr_intf <= vec2; -- External Interrupt
clr_tov0 <= vec4; -- Timer
 
clr_i <= vec2 or vec4;
clr_intf <= vec2;
clr_tov0 <= vec4;
 
end controlunit;
 
 
/trunk/v_alu.vhd
85,7 → 85,8
 
begin
 
-- Fetch Operand To Buffer ------------------------------------------
-- Operand Fetch Unit --
 
process(clrn, clk)
begin
if clrn = '0' then
121,20 → 122,20
end process;
 
 
-- ALU START------------------------------------------------------------
-- Execution Unit --
 
 
cin <= c_flag when add = '1' and wcarry = '1' else
'0' when add = '1' and wcarry = '0' else
not c_flag when wcarry = '1' else
'1';
 
-- Adder, Logic, Shift Right, Direct, Bld, Cbisbi ---------------------------
 
-- Adder-Subtracter
adder1 : lpm_add_sub
generic map(lpm_width => 8)
port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
 
-- Logic Unit
with logicsel select
logic_out <= a and b when 0, -- and, andi
a or b when 1, -- or, ori
141,6 → 142,7
a xor b when 2, -- eor
not a when 3; -- com
 
-- Shifter
right_out(6 downto 0) <= a(7 downto 1);
with rightsel select
right_out(7) <= '0' when 0, -- lsr
147,10 → 149,12
c_flag when 1, -- ror
a(7) when 2; -- asr
 
-- Direct Unit
with dirsel select
dir_out <= b when 0, -- ldi, mov
(a(3 downto 0) & a(7 downto 4)) when 1; -- swap
 
-- Bit Loader
process(bld, bitsel, a, t_flag, set)
begin
for i in 0 to 7 loop
164,9 → 168,7
end loop;
end process;
 
 
-- Output correct result to Data Bus (C Bus) ------------------------
 
-- Results to Data Bus
process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
begin
 
197,16 → 199,15
c <= bldcbi_out;
end if;
 
-- out
-- out, st z, st z+, st -z
if pass_a = '1' then
c <= a;
end if;
 
end process;
---------------------------------------------------------------------------------
 
-- Perform Skip Test ----------------------------------------------------------
 
-- Skip Evaluation Unit --
process(cpse, skiptest, a, b, set, bitsel, c)
begin
 
226,10 → 227,8
 
end if;
end process;
--------------------------------------------------------------------------
 
-- Calculate Status Register's Flags -------------------------------------
 
-- Flags Evaluation Unit --
process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
begin
 
293,6 → 292,4
 
tosr <= sr;
 
------------------------------------------------------------------------
 
end alu;

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