OpenCores
URL https://opencores.org/ocsvn/System11/System11/trunk

Subversion Repositories System11

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/trunk/rtl/vhdl/clkunit.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/miniUART.vhd File deleted
/trunk/rtl/vhdl/rxunit.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/txunit.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/testbench1.vhd
14,13 → 14,13
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
entity my_testbench1 is
end my_testbench1;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-- Architecture for Testbench 1
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
architecture behavior of my_testbench1 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
86,9 → 86,7
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
xirq: in std_logic
);
end component;
 
103,9 → 101,7
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => uart_irq,
xirq => timer_irq,
test_alu => cpu_alu,
test_cc => cpu_cc
xirq => timer_irq
);
 
-- *** Test Bench - User Defined Section ***
/trunk/rtl/vhdl/testbench2.vhd
14,13 → 14,13
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
entity my_testbench2 is
end my_testbench2;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-- Architecture for CPU11 Testbench 2
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
architecture behavior of my_testbench2 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
/trunk/rtl/vhdl/testbench3.vhd
14,13 → 14,13
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
entity my_testbench3 is
end my_testbench3;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-- Architecture for CPU11 Testbench 3
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
architecture behavior of my_testbench3 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
/trunk/rtl/vhdl/testbench4.vhd
0,0 → 1,303
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 4
--
-- Complete system test
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench4 is
end my_testbench4;
 
-------------------------------------------------------------------------------
-- Architecture for System11 Testbench 4
-------------------------------------------------------------------------------
architecture behavior of my_testbench4 is
 
signal tb_SysClk : Std_Logic; -- System Clock input
signal tb_Reset_n : Std_logic; -- Master Reset input (active low)
signal tb_LED : std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
signal tb_ram_csn : Std_Logic;
signal tb_ram_wrln : Std_Logic;
signal tb_ram_wrun : Std_Logic;
signal tb_ram_addr : Std_Logic_Vector(16 downto 0);
signal tb_ram_data : Std_Logic_Vector(15 downto 0);
-- Uart Interface
signal tb_rxbit : Std_Logic;
signal tb_txbit : Std_Logic;
signal tb_rts_n : Std_Logic;
signal tb_cts_n : Std_Logic;
-- Compact Flash B5-CF Module
signal tb_cf_rst_n : std_logic;
signal tb_cf_cs0_n : std_logic;
signal tb_cf_cs1_n : std_logic;
signal tb_cf_rd_n : std_logic;
signal tb_cf_wr_n : std_logic;
signal tb_cf_cs16_n : std_logic;
signal tb_cf_a : std_logic_vector(2 downto 0);
signal tb_cf_d : std_logic_vector(15 downto 0);
-- I/O Ports
signal tb_Porta : std_logic_vector(7 downto 0);
signal tb_Portb : std_logic_vector(7 downto 0);
--signal tb_PortC : std_logic_vector(7 downto 0);
--signal tb_PortD : std_logic_vector(7 downto 0);
 
-- CPU bus
signal tb_bus_clk : std_logic;
signal tb_bus_reset : std_logic;
signal tb_bus_rw : std_logic;
signal tb_bus_cs : std_logic;
signal tb_bus_addr : std_logic_vector(15 downto 0);
signal tb_bus_data : std_logic_vector(7 downto 0);
 
signal tb_reset : std_logic;
signal tb_ram_cs : std_logic;
signal tb_ramlo_din : std_logic_vector(7 downto 0);
signal tb_ramlo_dout : std_logic_vector(7 downto 0);
signal tb_ramhi_din : std_logic_vector(7 downto 0);
signal tb_ramhi_dout : std_logic_vector(7 downto 0);
 
-- Timer I/O
signal tb_timer_out : std_logic;
 
component System11
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
 
-- PS/2 Keyboard
-- kb_clock : inout Std_logic;
-- kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic;
txbit : out Std_Logic;
rts_n : out Std_Logic;
cts_n : in Std_Logic;
 
-- CRTC output signals
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
-- green_lo : out std_logic;
-- green_hi : out std_logic;
-- red_lo : out std_logic;
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- Compact Flash B5-CF Module
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
cf_cs16_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
-- cf_intrq : in std_logic;
-- cf_iordy : in std_logic;
-- cf_dase : in std_logic;
-- cf_pdiag : in std_logic;
-- cf_present : in std_logic;
 
-- I/O Ports
Porta : inout std_logic_vector(7 downto 0);
Portb : inout std_logic_vector(7 downto 0);
-- PortC : inout std_logic_vector(7 downto 0);
-- PortD : inout std_logic_vector(7 downto 0);
 
-- CPU bus
bus_clk : out std_logic;
bus_reset : out std_logic;
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
timer_out : out std_logic
);
end component;
 
component my_ram
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(5 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
my_system11: System11 port map (
SysClk => tb_SysClk, -- System Clock input
Reset_n => tb_Reset_n, -- Master Reset input (active low)
LED => tb_LED, -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn => tb_ram_csn,
ram_wrln => tb_ram_wrln,
ram_wrun => tb_ram_wrun,
ram_addr => tb_ram_addr,
ram_data => tb_ram_data,
 
-- Stuff on the peripheral board
 
-- PS/2 Keyboard
-- kb_clock => tb_kb_clk.
-- kb_data => tb_kb_data,
 
-- PS/2 Mouse interface
-- mouse_clock => tb_mouse_clock,
-- mouse_data => tb_mouse_data,
 
-- Uart Interface
rxbit => tb_rxbit,
txbit => tb_txbit,
rts_n => tb_rts_n,
cts_n => tb_cts_n,
 
-- CRTC output signals
-- v_drive => tb_v_drive,
-- h_drive => tb_h_drive,
-- blue_lo => tb_blue_lo,
-- blue_hi => tb_blue_hi,
-- green_lo => tb_green_lo,
-- green_hi => tb_green_hi,
-- red_lo => tb_red_lo,
-- red_hi => tb_red_hi,
-- buzzer => tb_buzzer,
 
-- Compact Flash B5-CF Module
cf_rst_n => tb_cf_rst_n,
cf_cs0_n => tb_cf_cs0_n,
cf_cs1_n => tb_cf_cs1_n,
cf_rd_n => tb_cf_rd_n,
cf_wr_n => tb_cf_wr_n,
cf_cs16_n => tb_cf_cs16_n,
cf_a => tb_cf_a,
cf_d => tb_cf_d,
-- cf_intrq => tb_cf_intrq,
-- cf_iordy => tb_cf_iordy,
-- cf_dase => tb_cf_dase,
-- cf_pdiag => tb_cf_pdiag,
-- cf_present => tb_cf_present,
 
-- I/O Ports
Porta => tb_Porta,
Portb => tb_Portb,
-- PortC => tb_Portc,
-- PortD => tb_portd,
 
-- CPU bus
bus_clk => tb_bus_clk,
bus_reset => tb_bus_reset,
bus_rw => tb_bus_rw,
bus_cs => tb_bus_cs,
bus_addr => tb_bus_addr,
bus_data => tb_bus_data,
 
-- Timer I/O
timer_out => tb_timer_out
);
 
ramlo : my_ram port map (
clk => tb_bus_clk,
rst => tb_reset,
cs => tb_ram_cs,
rw => tb_ram_wrln,
addr => tb_ram_addr(5 downto 0),
data_in => tb_ramlo_din,
data_out => tb_ramlo_dout
);
 
ramhi : my_ram port map (
clk => tb_bus_clk,
rst => tb_reset,
cs => tb_ram_cs,
rw => tb_ram_wrun,
addr => tb_ram_addr(5 downto 0),
data_in => tb_ramhi_din,
data_out => tb_ramhi_dout
);
 
tb_ram : PROCESS( tb_reset_n, tb_ram_csn, tb_ram_wrln, tb_ram_wrun,
tb_ramlo_din, tb_ramlo_dout, tb_ramhi_din, tb_ramhi_dout,
tb_ram_data )
begin
tb_reset <= not tb_reset_n;
tb_ram_cs <= not tb_ram_csn;
 
if( tb_ram_wrln = '1' ) then
tb_ram_data( 7 downto 0) <= tb_ramlo_dout;
else
tb_ram_data( 7 downto 0) <= "ZZZZZZZZ";
tb_ramlo_din <= tb_ram_data(7 downto 0);
end if;
 
if( tb_ram_wrun = '1' ) then
tb_ram_data( 15 downto 8) <= tb_ramhi_dout;
else
tb_ram_data( 15 downto 8) <= "ZZZZZZZZ";
tb_ramhi_din <= tb_ram_data( 15 downto 8);
end if;
end process;
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
tb_rxbit <= '1';
tb_cts_n <= '0';
tb_reset_n <= '0';
tb_SysClk <= '0';
 
for count in 0 to 512 loop
tb_SysClk <= '0';
if count = 0 then
tb_reset_n <= '0';
elsif count = 1 then
tb_reset_n <= '1';
end if;
wait for 50 ns;
tb_SysClk <= '1';
wait for 50 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
end behavior; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/testbench5.vhd
0,0 → 1,264
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 5
--
-- CPU11, ROM & RAM test
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench5 is
end my_testbench5;
 
-------------------------------------------------------------------------------
-- Architecture for CPU11 Testbench 5
-------------------------------------------------------------------------------
architecture behavior of my_testbench5 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- Sequencer Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal rom_data_out: Std_Logic_Vector(7 downto 0);
signal ram0_data_out: Std_Logic_Vector(7 downto 0);
signal ram0_cs : std_logic;
signal ram1_data_out: Std_Logic_Vector(7 downto 0);
signal ram1_cs : std_logic;
signal ram2_data_out: Std_Logic_Vector(7 downto 0);
signal ram2_cs : std_logic;
signal ram3_data_out: Std_Logic_Vector(7 downto 0);
signal ram3_cs : std_logic;
signal ram4_data_out: Std_Logic_Vector(7 downto 0);
signal ram4_cs : std_logic;
signal ram5_data_out: Std_Logic_Vector(7 downto 0);
signal ram5_cs : std_logic;
signal ram6_data_out: Std_Logic_Vector(7 downto 0);
signal ram6_cs : std_logic;
signal ram7_data_out: Std_Logic_Vector(7 downto 0);
signal ram7_cs : std_logic;
 
component cpu11
port (
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
irq: in std_logic;
xirq: in std_logic
);
end component;
 
component my_ram
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
 
component boot_rom
port (
addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom
data : out Std_Logic_Vector(7 downto 0)
);
end component;
 
begin
cpu : cpu11 port map (
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
irq => uart_irq,
xirq => timer_irq
);
 
sram0 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram0_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram0_data_out
);
 
sram1 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram1_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram1_data_out
);
 
sram2 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram2_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram2_data_out
);
 
sram3 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram3_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram3_data_out
);
 
sram4 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram4_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram4_data_out
);
 
sram5 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram5_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram5_data_out
);
 
sram6 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram6_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram6_data_out
);
 
sram7 : my_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => ram7_cs,
rw => cpu_rw,
addr => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => ram7_data_out
);
 
rom : boot_rom port map (
addr => cpu_addr(9 downto 0),
data => rom_data_out
);
 
decode : process( cpu_addr, cpu_vma, rom_data_out,
ram0_data_out, ram1_data_out, ram2_data_out, ram3_data_out,
ram4_data_out, ram5_data_out, ram6_data_out, ram7_data_out )
begin
ram0_cs <= '0';
ram1_cs <= '0';
ram2_cs <= '0';
ram3_cs <= '0';
ram4_cs <= '0';
ram5_cs <= '0';
ram6_cs <= '0';
ram7_cs <= '0';
case cpu_addr(15 downto 13) is
when "111" =>
cpu_data_in <= rom_data_out;
when "101" =>
case cpu_addr(6 downto 4 ) is
when "000" =>
cpu_data_in <= ram0_data_out;
ram0_cs <= cpu_vma;
when "001" =>
cpu_data_in <= ram1_data_out;
ram1_cs <= cpu_vma;
when "010" =>
cpu_data_in <= ram2_data_out;
ram2_cs <= cpu_vma;
when "011" =>
cpu_data_in <= ram3_data_out;
ram3_cs <= cpu_vma;
when "100" =>
cpu_data_in <= ram4_data_out;
ram4_cs <= cpu_vma;
when "101" =>
cpu_data_in <= ram5_data_out;
ram5_cs <= cpu_vma;
when "110" =>
cpu_data_in <= ram6_data_out;
ram6_cs <= cpu_vma;
when "111" =>
cpu_data_in <= ram7_data_out;
ram7_cs <= cpu_vma;
when others =>
null;
end case;
when others =>
cpu_data_in <= "00000000";
end case;
end process;
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
end behavior; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/tb_ram.vhd
0,0 → 1,463
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 4
--
-- Complete system test
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_ram is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(5 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0));
end;
 
 
architecture ram_arch of my_ram is
signal ram_reg00 : std_logic_vector(7 downto 0);
signal ram_reg01 : std_logic_vector(7 downto 0);
signal ram_reg02 : std_logic_vector(7 downto 0);
signal ram_reg03 : std_logic_vector(7 downto 0);
signal ram_reg04 : std_logic_vector(7 downto 0);
signal ram_reg05 : std_logic_vector(7 downto 0);
signal ram_reg06 : std_logic_vector(7 downto 0);
signal ram_reg07 : std_logic_vector(7 downto 0);
signal ram_reg08 : std_logic_vector(7 downto 0);
signal ram_reg09 : std_logic_vector(7 downto 0);
signal ram_reg010 : std_logic_vector(7 downto 0);
signal ram_reg011 : std_logic_vector(7 downto 0);
signal ram_reg012 : std_logic_vector(7 downto 0);
signal ram_reg013 : std_logic_vector(7 downto 0);
signal ram_reg014 : std_logic_vector(7 downto 0);
signal ram_reg015 : std_logic_vector(7 downto 0);
signal ram_reg10 : std_logic_vector(7 downto 0);
signal ram_reg11 : std_logic_vector(7 downto 0);
signal ram_reg12 : std_logic_vector(7 downto 0);
signal ram_reg13 : std_logic_vector(7 downto 0);
signal ram_reg14 : std_logic_vector(7 downto 0);
signal ram_reg15 : std_logic_vector(7 downto 0);
signal ram_reg16 : std_logic_vector(7 downto 0);
signal ram_reg17 : std_logic_vector(7 downto 0);
signal ram_reg18 : std_logic_vector(7 downto 0);
signal ram_reg19 : std_logic_vector(7 downto 0);
signal ram_reg110 : std_logic_vector(7 downto 0);
signal ram_reg111 : std_logic_vector(7 downto 0);
signal ram_reg112 : std_logic_vector(7 downto 0);
signal ram_reg113 : std_logic_vector(7 downto 0);
signal ram_reg114 : std_logic_vector(7 downto 0);
signal ram_reg115 : std_logic_vector(7 downto 0);
signal ram_reg20 : std_logic_vector(7 downto 0);
signal ram_reg21 : std_logic_vector(7 downto 0);
signal ram_reg22 : std_logic_vector(7 downto 0);
signal ram_reg23 : std_logic_vector(7 downto 0);
signal ram_reg24 : std_logic_vector(7 downto 0);
signal ram_reg25 : std_logic_vector(7 downto 0);
signal ram_reg26 : std_logic_vector(7 downto 0);
signal ram_reg27 : std_logic_vector(7 downto 0);
signal ram_reg28 : std_logic_vector(7 downto 0);
signal ram_reg29 : std_logic_vector(7 downto 0);
signal ram_reg210 : std_logic_vector(7 downto 0);
signal ram_reg211 : std_logic_vector(7 downto 0);
signal ram_reg212 : std_logic_vector(7 downto 0);
signal ram_reg213 : std_logic_vector(7 downto 0);
signal ram_reg214 : std_logic_vector(7 downto 0);
signal ram_reg215 : std_logic_vector(7 downto 0);
signal ram_reg30 : std_logic_vector(7 downto 0);
signal ram_reg31 : std_logic_vector(7 downto 0);
signal ram_reg32 : std_logic_vector(7 downto 0);
signal ram_reg33 : std_logic_vector(7 downto 0);
signal ram_reg34 : std_logic_vector(7 downto 0);
signal ram_reg35 : std_logic_vector(7 downto 0);
signal ram_reg36 : std_logic_vector(7 downto 0);
signal ram_reg37 : std_logic_vector(7 downto 0);
signal ram_reg38 : std_logic_vector(7 downto 0);
signal ram_reg39 : std_logic_vector(7 downto 0);
signal ram_reg310 : std_logic_vector(7 downto 0);
signal ram_reg311 : std_logic_vector(7 downto 0);
signal ram_reg312 : std_logic_vector(7 downto 0);
signal ram_reg313 : std_logic_vector(7 downto 0);
signal ram_reg314 : std_logic_vector(7 downto 0);
signal ram_reg315 : std_logic_vector(7 downto 0);
 
begin
 
 
---------------------------------
--
-- Write DAT RAM
--
---------------------------------
 
ram_write : process( clk, rst, addr, cs, rw, data_in )
begin
if rst = '1' then
ram_reg00 <= "00000000";
ram_reg01 <= "00000000";
ram_reg02 <= "00000000";
ram_reg03 <= "00000000";
ram_reg04 <= "00000000";
ram_reg05 <= "00000000";
ram_reg06 <= "00000000";
ram_reg07 <= "00000000";
ram_reg08 <= "00000000";
ram_reg09 <= "00000000";
ram_reg010 <= "00000000";
ram_reg011 <= "00000000";
ram_reg012 <= "00000000";
ram_reg013 <= "00000000";
ram_reg014 <= "00000000";
ram_reg015 <= "00000000";
ram_reg10 <= "00000000";
ram_reg11 <= "00000000";
ram_reg12 <= "00000000";
ram_reg13 <= "00000000";
ram_reg14 <= "00000000";
ram_reg15 <= "00000000";
ram_reg16 <= "00000000";
ram_reg17 <= "00000000";
ram_reg18 <= "00000000";
ram_reg19 <= "00000000";
ram_reg110 <= "00000000";
ram_reg111 <= "00000000";
ram_reg112 <= "00000000";
ram_reg113 <= "00000000";
ram_reg114 <= "00000000";
ram_reg115 <= "00000000";
ram_reg20 <= "00000000";
ram_reg21 <= "00000000";
ram_reg22 <= "00000000";
ram_reg23 <= "00000000";
ram_reg24 <= "00000000";
ram_reg25 <= "00000000";
ram_reg26 <= "00000000";
ram_reg27 <= "00000000";
ram_reg28 <= "00000000";
ram_reg29 <= "00000000";
ram_reg210 <= "00000000";
ram_reg211 <= "00000000";
ram_reg212 <= "00000000";
ram_reg213 <= "00000000";
ram_reg214 <= "00000000";
ram_reg215 <= "00000000";
ram_reg30 <= "00000000";
ram_reg31 <= "00000000";
ram_reg32 <= "00000000";
ram_reg33 <= "00000000";
ram_reg34 <= "00000000";
ram_reg35 <= "00000000";
ram_reg36 <= "00000000";
ram_reg37 <= "00000000";
ram_reg38 <= "00000000";
ram_reg39 <= "00000000";
ram_reg310 <= "00000000";
ram_reg311 <= "00000000";
ram_reg312 <= "00000000";
ram_reg313 <= "00000000";
ram_reg314 <= "00000000";
ram_reg315 <= "00000000";
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
case addr is
when "000000" =>
ram_reg00(7 downto 0) <= data_in(7 downto 0);
when "000001" =>
ram_reg01(7 downto 0) <= data_in(7 downto 0);
when "000010" =>
ram_reg02(7 downto 0) <= data_in(7 downto 0);
when "000011" =>
ram_reg03(7 downto 0) <= data_in(7 downto 0);
when "000100" =>
ram_reg04(7 downto 0) <= data_in(7 downto 0);
when "000101" =>
ram_reg05(7 downto 0) <= data_in(7 downto 0);
when "000110" =>
ram_reg06(7 downto 0) <= data_in(7 downto 0);
when "000111" =>
ram_reg07(7 downto 0) <= data_in(7 downto 0);
when "001000" =>
ram_reg08(7 downto 0) <= data_in(7 downto 0);
when "001001" =>
ram_reg09(7 downto 0) <= data_in(7 downto 0);
when "001010" =>
ram_reg010(7 downto 0) <= data_in(7 downto 0);
when "001011" =>
ram_reg011(7 downto 0) <= data_in(7 downto 0);
when "001100" =>
ram_reg012(7 downto 0) <= data_in(7 downto 0);
when "001101" =>
ram_reg013(7 downto 0) <= data_in(7 downto 0);
when "001110" =>
ram_reg014(7 downto 0) <= data_in(7 downto 0);
when "001111" =>
ram_reg015(7 downto 0) <= data_in(7 downto 0);
when "010000" =>
ram_reg10(7 downto 0) <= data_in(7 downto 0);
when "010001" =>
ram_reg11(7 downto 0) <= data_in(7 downto 0);
when "010010" =>
ram_reg12(7 downto 0) <= data_in(7 downto 0);
when "010011" =>
ram_reg13(7 downto 0) <= data_in(7 downto 0);
when "010100" =>
ram_reg14(7 downto 0) <= data_in(7 downto 0);
when "010101" =>
ram_reg15(7 downto 0) <= data_in(7 downto 0);
when "010110" =>
ram_reg16(7 downto 0) <= data_in(7 downto 0);
when "010111" =>
ram_reg17(7 downto 0) <= data_in(7 downto 0);
when "011000" =>
ram_reg18(7 downto 0) <= data_in(7 downto 0);
when "011001" =>
ram_reg19(7 downto 0) <= data_in(7 downto 0);
when "011010" =>
ram_reg110(7 downto 0) <= data_in(7 downto 0);
when "011011" =>
ram_reg111(7 downto 0) <= data_in(7 downto 0);
when "011100" =>
ram_reg112(7 downto 0) <= data_in(7 downto 0);
when "011101" =>
ram_reg113(7 downto 0) <= data_in(7 downto 0);
when "011110" =>
ram_reg114(7 downto 0) <= data_in(7 downto 0);
when "011111" =>
ram_reg115(7 downto 0) <= data_in(7 downto 0);
when "100000" =>
ram_reg20(7 downto 0) <= data_in(7 downto 0);
when "100001" =>
ram_reg21(7 downto 0) <= data_in(7 downto 0);
when "100010" =>
ram_reg22(7 downto 0) <= data_in(7 downto 0);
when "100011" =>
ram_reg23(7 downto 0) <= data_in(7 downto 0);
when "100100" =>
ram_reg24(7 downto 0) <= data_in(7 downto 0);
when "100101" =>
ram_reg25(7 downto 0) <= data_in(7 downto 0);
when "100110" =>
ram_reg26(7 downto 0) <= data_in(7 downto 0);
when "100111" =>
ram_reg27(7 downto 0) <= data_in(7 downto 0);
when "101000" =>
ram_reg28(7 downto 0) <= data_in(7 downto 0);
when "101001" =>
ram_reg29(7 downto 0) <= data_in(7 downto 0);
when "101010" =>
ram_reg210(7 downto 0) <= data_in(7 downto 0);
when "101011" =>
ram_reg211(7 downto 0) <= data_in(7 downto 0);
when "101100" =>
ram_reg212(7 downto 0) <= data_in(7 downto 0);
when "101101" =>
ram_reg213(7 downto 0) <= data_in(7 downto 0);
when "101110" =>
ram_reg214(7 downto 0) <= data_in(7 downto 0);
when "101111" =>
ram_reg215(7 downto 0) <= data_in(7 downto 0);
when "110000" =>
ram_reg30(7 downto 0) <= data_in(7 downto 0);
when "110001" =>
ram_reg31(7 downto 0) <= data_in(7 downto 0);
when "110010" =>
ram_reg32(7 downto 0) <= data_in(7 downto 0);
when "110011" =>
ram_reg33(7 downto 0) <= data_in(7 downto 0);
when "110100" =>
ram_reg34(7 downto 0) <= data_in(7 downto 0);
when "110101" =>
ram_reg35(7 downto 0) <= data_in(7 downto 0);
when "110110" =>
ram_reg36(7 downto 0) <= data_in(7 downto 0);
when "110111" =>
ram_reg37(7 downto 0) <= data_in(7 downto 0);
when "111000" =>
ram_reg38(7 downto 0) <= data_in(7 downto 0);
when "111001" =>
ram_reg39(7 downto 0) <= data_in(7 downto 0);
when "111010" =>
ram_reg310(7 downto 0) <= data_in(7 downto 0);
when "111011" =>
ram_reg311(7 downto 0) <= data_in(7 downto 0);
when "111100" =>
ram_reg312(7 downto 0) <= data_in(7 downto 0);
when "111101" =>
ram_reg313(7 downto 0) <= data_in(7 downto 0);
when "111110" =>
ram_reg314(7 downto 0) <= data_in(7 downto 0);
when "111111" =>
ram_reg315(7 downto 0) <= data_in(7 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
 
dat_read : process( addr,
ram_reg00, ram_reg01, ram_reg02, ram_reg03,
ram_reg04, ram_reg05, ram_reg06, ram_reg07,
ram_reg08, ram_reg09, ram_reg010, ram_reg011,
ram_reg012, ram_reg013, ram_reg014, ram_reg015,
ram_reg10, ram_reg11, ram_reg12, ram_reg13,
ram_reg14, ram_reg15, ram_reg16, ram_reg17,
ram_reg18, ram_reg19, ram_reg110, ram_reg111,
ram_reg112, ram_reg113, ram_reg114, ram_reg115,
ram_reg20, ram_reg21, ram_reg22, ram_reg23,
ram_reg24, ram_reg25, ram_reg26, ram_reg27,
ram_reg28, ram_reg29, ram_reg210, ram_reg211,
ram_reg212, ram_reg213, ram_reg214, ram_reg215,
ram_reg30, ram_reg31, ram_reg32, ram_reg33,
ram_reg34, ram_reg35, ram_reg36, ram_reg37,
ram_reg38, ram_reg39, ram_reg310, ram_reg311,
ram_reg312, ram_reg313, ram_reg314, ram_reg315
)
begin
case addr is
when "000000" =>
data_out <= ram_reg00;
when "000001" =>
data_out <= ram_reg01;
when "000010" =>
data_out <= ram_reg02;
when "000011" =>
data_out <= ram_reg03;
when "000100" =>
data_out <= ram_reg04;
when "000101" =>
data_out <= ram_reg05;
when "000110" =>
data_out <= ram_reg06;
when "000111" =>
data_out <= ram_reg07;
when "001000" =>
data_out <= ram_reg08;
when "001001" =>
data_out <= ram_reg09;
when "001010" =>
data_out <= ram_reg010;
when "001011" =>
data_out <= ram_reg011;
when "001100" =>
data_out <= ram_reg012;
when "001101" =>
data_out <= ram_reg013;
when "001110" =>
data_out <= ram_reg014;
when "001111" =>
data_out <= ram_reg015;
when "010000" =>
data_out <= ram_reg10;
when "010001" =>
data_out <= ram_reg11;
when "010010" =>
data_out <= ram_reg12;
when "010011" =>
data_out <= ram_reg13;
when "010100" =>
data_out <= ram_reg14;
when "010101" =>
data_out <= ram_reg15;
when "010110" =>
data_out <= ram_reg16;
when "010111" =>
data_out <= ram_reg17;
when "011000" =>
data_out <= ram_reg18;
when "011001" =>
data_out <= ram_reg19;
when "011010" =>
data_out <= ram_reg110;
when "011011" =>
data_out <= ram_reg111;
when "011100" =>
data_out <= ram_reg112;
when "011101" =>
data_out <= ram_reg113;
when "011110" =>
data_out <= ram_reg114;
when "011111" =>
data_out <= ram_reg115;
when "100000" =>
data_out <= ram_reg20;
when "100001" =>
data_out <= ram_reg21;
when "100010" =>
data_out <= ram_reg22;
when "100011" =>
data_out <= ram_reg23;
when "100100" =>
data_out <= ram_reg24;
when "100101" =>
data_out <= ram_reg25;
when "100110" =>
data_out <= ram_reg26;
when "100111" =>
data_out <= ram_reg27;
when "101000" =>
data_out <= ram_reg28;
when "101001" =>
data_out <= ram_reg29;
when "101010" =>
data_out <= ram_reg210;
when "101011" =>
data_out <= ram_reg211;
when "101100" =>
data_out <= ram_reg212;
when "101101" =>
data_out <= ram_reg213;
when "101110" =>
data_out <= ram_reg214;
when "101111" =>
data_out <= ram_reg215;
when "110000" =>
data_out <= ram_reg30;
when "110001" =>
data_out <= ram_reg31;
when "110010" =>
data_out <= ram_reg32;
when "110011" =>
data_out <= ram_reg33;
when "110100" =>
data_out <= ram_reg34;
when "110101" =>
data_out <= ram_reg35;
when "110110" =>
data_out <= ram_reg36;
when "110111" =>
data_out <= ram_reg37;
when "111000" =>
data_out <= ram_reg38;
when "111001" =>
data_out <= ram_reg39;
when "111010" =>
data_out <= ram_reg310;
when "111011" =>
data_out <= ram_reg311;
when "111100" =>
data_out <= ram_reg312;
when "111101" =>
data_out <= ram_reg313;
when "111110" =>
data_out <= ram_reg314;
when "111111" =>
data_out <= ram_reg315;
when others =>
null;
end case;
end process;
 
end;
 
/trunk/rtl/vhdl/datram.vhd
91,7 → 91,6
 
dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
begin
if clk'event and clk = '0' then
if rst = '1' then
dat_reg0 <= "00000000";
dat_reg1 <= "00000001";
109,7 → 108,7
dat_reg13 <= "00001101";
dat_reg14 <= "00001110";
dat_reg15 <= "00001111";
else
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
case addr_lo is
when "0000" =>
149,7 → 148,6
end case;
end if;
end if;
end if;
end process;
 
dat_read : process( addr_hi,
/trunk/rtl/vhdl/miniUART3.vhd
0,0 → 1,394
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : miniuart2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
-- the RSBusCtrl did not process all possible situations
--
-- olupas@opencores.org
--
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
-- Added CTS, RTS, Baud rate control
-- & Software Reset
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
-- 3.3 John Kent 16 January 2004 Integrated clkunit in rxunit & txunit
-- Now has external TX 7 RX Baud Clock
-- inputs like the MC6850...
-- also supports x1 clock and DCD.
--
-- dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity miniUART is
port (
--
-- CPU signals
--
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
--
-- Uart Signals
--
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxData : Std_Logic_Vector(7 downto 0); --
signal TxData : Std_Logic_Vector(7 downto 0); --
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
-- StatReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
-----------+--------+--------+--------+--------+--------+--------+--------+
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
-- CtrlReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIEnb
-- 0 - Rx Interrupt disabled
-- 1 - Rx Interrupt enabled
-- TxCtl
-- 0 1 - Tx Interrupt Enable
-- 1 0 - RTS high
-- WdFmt
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
-- BdCtl
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
signal TxDbit : Std_Logic; -- Transmit data bit
signal DRdy : Std_Logic; -- Receive Data ready
signal TBufE : Std_Logic; -- Transmit buffer empty
signal FErr : Std_Logic; -- Frame error
signal OErr : Std_Logic; -- Output error
signal PErr : Std_Logic; -- Parity Error
signal TxIEnb : Std_Logic; -- Transmit interrupt enable
signal Read : Std_Logic; -- Read receive buffer
signal Load : Std_Logic; -- Load transmit buffer
signal ReadCS : Std_Logic; -- Read Status register
signal LoadCS : Std_Logic; -- Load Control register
signal Reset : Std_Logic; -- Reset (Software & Hardware)
signal RxRst : Std_Logic; -- Receive Reset (Software & Hardware)
signal TxRst : Std_Logic; -- Transmit Reset (Software & Hardware)
signal DCDDel : Std_Logic; -- Delayed DCD_n
signal DCDEdge : Std_Logic; -- Rising DCD_N Edge Pulse
signal DCDState : Std_Logic; -- DCD Reset sequencer
signal DCDInt : Std_Logic; -- DCD Interrupt
 
-----------------------------------------------------------------------------
-- Receive Unit
-----------------------------------------------------------------------------
component RxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
ReadD : in Std_Logic; -- Read data signal
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
RxClk : in Std_Logic; -- RS-232 clock input
RxDat : in Std_Logic; -- RS-232 data input
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0));
end component;
-----------------------------------------------------------------------------
-- Transmitter Unit
-----------------------------------------------------------------------------
component TxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
LoadD : in Std_Logic; -- Load transmit data
DAIn : in Std_Logic_Vector(7 downto 0);
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
TxClk : in Std_Logic; -- Enable input
TxDat : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic ); -- Tx buffer empty
end component;
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
RxDev : RxUnit port map (
Clk => clk,
Reset => RxRst,
ReadD => Read,
WdFmt => CtrlReg(4 downto 2),
BdFmt => CtrlReg(1 downto 0),
RxClk => RxC,
RxDat => RxD,
FRErr => FErr,
ORErr => OErr,
PAErr => PErr,
DARdy => DRdy,
DAOut => RxData
);
 
TxDev : TxUnit port map (
Clk => clk,
Reset => TxRst,
LoadD => Load,
DAIn => TxData,
WdFmt => CtrlReg(4 downto 2),
BdFmt => CtrlReg(1 downto 0),
TxClk => TxC,
TxDat => TxDbit,
TBE => TBufE
);
 
-----------------------------------------------------------------------------
-- Implements the controller for Rx&Tx units
-----------------------------------------------------------------------------
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
DRdy, TBufE, DCD_n, CTS_n, DCDInt,
FErr, OErr, PErr )
variable Int : Std_Logic;
begin
if Reset = '1' then
Int := '0';
StatReg <= "00000000";
irq <= '0';
elsif clk'event and clk='0' then
Int := (CtrlReg(7) and DRdy) or
(CtrlReg(7) and DCDInt) or
(TxIEnb and TBufE);
StatReg(0) <= DRdy; -- Receive Data Ready
StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
StatReg(2) <= DCDInt; -- Data Carrier Detect
StatReg(3) <= CTS_n; -- Clear To Send
StatReg(4) <= FErr; -- Framing error
StatReg(5) <= OErr; -- Overrun error
StatReg(6) <= PErr; -- Parity error
StatReg(7) <= Int;
irq <= Int;
end if;
end process;
 
 
-----------------------------------------------------------------------------
-- Transmit control
-----------------------------------------------------------------------------
 
miniUart_TxControl : process( CtrlReg, TxDbit )
begin
case CtrlReg(6 downto 5) is
when "00" => -- Disable TX Interrupts, Assert RTS
RTS_n <= '0';
TxIEnb <= '0';
TxD <= TxDbit;
when "01" => -- Enable TX interrupts, Assert RTS
RTS_n <= '0';
TxIEnb <= '1';
TxD <= TxDbit;
when "10" => -- Disable Tx Interrupts, Clear RTS
RTS_n <= '1';
TxIEnb <= '0';
TxD <= TxDbit;
when "11" => -- Disable Tx interrupts, Assert RTS, send break
RTS_n <= '0';
TxIEnb <= '0';
TxD <= '0';
when others =>
RTS_n <= '0';
TxIEnb <= '0';
TxD <= TxDbit;
end case;
end process;
 
-----------------------------------------------------------------------------
-- Write to control register
-----------------------------------------------------------------------------
 
miniUart_Control: process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
begin
if (reset = '1') then
TxData <= "00000000";
Load <= '0';
Read <= '0';
CtrlReg <= "00000000";
LoadCS <= '0';
ReadCS <= '0';
elsif clk'event and clk='0' then
if cs = '1' then
if Addr = '1' then -- Data Register
if rw = '0' then -- write data register
TxData <= DataIn;
Load <= '1';
Read <= '0';
else -- read Data Register
TxData <= TxData;
Load <= '0';
Read <= '1';
end if; -- rw
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '0';
else -- Control / Status register
TxData <= TxData;
Load <= '0';
Read <= '0';
if rw = '0' then -- write control register
CtrlReg <= DataIn;
LoadCS <= '1';
ReadCS <= '0';
else -- read status Register
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '1';
end if; -- rw
end if; -- Addr
else -- not selected
TxData <= TxData;
Load <= '0';
Read <= '0';
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '0';
 
end if; -- cs
end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
miniUart_data_read: process(Addr, StatReg, RxData)
begin
if Addr = '1' then
DataOut <= RxData; -- read data register
else
DataOut <= StatReg; -- read status register
end if; -- Addr
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Edge rising edge detect
--
---------------------------------------------------------------
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel )
begin
if reset = '1' then
DCDEdge <= '0';
DCDDel <= '0';
elsif clk'event and clk = '0' then
DCDDel <= DCD_n;
DCDEdge <= DCD_n and (not DCDDel);
end if;
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Interrupt
--
---------------------------------------------------------------
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
begin
if reset = '1' then
DCDInt <= '0';
DCDState <= '0';
elsif clk'event and clk = '0' then
if DCDEdge = '1' then
DCDInt <= '1';
DCDState <= '0';
elsif DCDState = '0' then
-- To reset DCD interrupt, First read status
if (ReadCS <= '1') and (DCDInt = '1') then
DCDState <= '1';
else
DCDState <= '0';
end if;
DCDInt <= DCDInt;
else -- DCDstate = '1'
-- Then read the data register
if Read <= '1' then
DCDState <= '0';
DCDInt <= '0';
else
DCDState <= DCDState;
DCDInt <= DCDInt;
end if;
end if; -- DCDState
end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
begin
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
TxRst <= Reset;
RxRst <= Reset or DCD_n;
end process;
 
end; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/rxunit3.vhd
0,0 → 1,396
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : rxunit3.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the cpu68 cpu and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164.all;
-- ieee.numeric_std.all;
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
-- olupas@opencores.org
--
-- 3.0 John Kent 5 January 2003 Added 6850 word format control
-- 3.1 John Kent 12 January 2003 Significantly revamped receive code.
-- 3.2 John Kent 10 January 2004 Rewrite of code.
-- dilbert57@opencores.org
-------------------------------------------------------------------------------
-- Description : Implements the receive unit of the miniUART core. Samples
-- 16 times the RxD line and retain the value in the middle of
-- the time interval.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
ReadD : in Std_Logic; -- Read data signal
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
RxClk : in Std_Logic; -- RS-232 clock input
RxDat : in Std_Logic; -- RS-232 data input
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0)
);
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxDebDel0 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel1 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel2 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel3 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDeb : Std_Logic; -- Debounced Rx Data
signal RxDatDel : Std_Logic; -- Delayed Rx Data
signal RxDatEdge : Std_Logic; -- Rx Data Edge pulse
signal RxClkDel : Std_Logic; -- Delayed Rx Input Clock
signal RxClkEdge : Std_Logic; -- Rx Input Clock Edge pulse
signal RxClkCnt : Std_Logic_Vector(5 downto 0); -- Rx Baud Clock Counter
signal RxBdClk : Std_Logic; -- Rx Baud Clock
signal RxBdDel : Std_Logic; -- Delayed Rx Baud Clock
signal RxBdEdge : Std_Logic; -- Rx Baud Clock Edge pulse
signal RxStart : Std_Logic; -- Rx Start bit detected
 
signal tmpDRdy : Std_Logic; -- Data Ready flag
signal RxValid : Std_Logic; -- Rx Data Valid
signal tmpRxVal : Std_Logic; -- Rx Data Valid
signal outErr : Std_Logic; -- Over run error bit
signal frameErr : Std_Logic; -- Framing error bit
signal ParityErr : Std_Logic; -- Parity Error Bit
signal RxParity : Std_Logic; -- Calculated RX parity bit
signal RxState : Std_Logic_Vector(3 downto 0); -- receive bit state
signal ShtReg : Std_Logic_Vector(7 downto 0); -- Shift Register
signal DataOut : Std_Logic_Vector(7 downto 0); -- Data Output register
 
begin
 
---------------------------------------------------------------------
-- Receiver Data Debounce
-- Input level must be stable for 4 Receive Clock cycles.
---------------------------------------------------------------------
rxunit_data_debounce : process(Clk, Reset, RxClkEdge, RxDat,
RxDebDel0, RxDebDel1, RxDebDel2, RxDebDel3 )
begin
if Reset = '1' then
RxDebDel0 <= RxDat;
RxDebDel1 <= RxDat;
RxDebDel2 <= RxDat;
RxDebDel3 <= RxDat;
elsif Clk'event and Clk = '0' then
if RxClkEdge = '1' then
RxDebDel0 <= RxDat;
RxDebDel1 <= RxDebDel0;
RxDebDel2 <= RxDebDel1;
RxDebDel3 <= RxDebDel2;
if (RxDebDel3 or RxDebDel2 or RxDebDel1 or RxDebDel0) = '0' then
RxDeb <= '0';
elsif (RxDebDel3 and RxDebDel2 and RxDebDel1 and RxDebDel0) = '1' then
RxDeb <= '1';
else
RxDeb <= RxDeb;
end if;
else
RxDebDel0 <= RxDebDel0;
RxDebDel1 <= RxDebDel1;
RxDebDel2 <= RxDebDel2;
RxDebDel3 <= RxDebDel3;
RxDeb <= RxDeb;
end if;
end if;
end process;
 
---------------------------------------------------------------------
-- Receiver Data Edge Detection
-- A falling edge will produce a one clock cycle pulse
---------------------------------------------------------------------
rxunit_data_edge : process(Clk, Reset, RxDeb, RxDatDel )
begin
if Reset = '1' then
RxDatDel <= RxDeb;
RxDatEdge <= '0';
elsif Clk'event and Clk = '0' then
RxDatDel <= RxDeb;
RxDatEdge <= RxDatDel and (not RxDeb);
end if;
end process;
 
---------------------------------------------------------------------
-- Receiver Clock Edge Detection
-- A rising edge will produce a one clock cycle pulse
-- RxClock
---------------------------------------------------------------------
rxunit_clock_edge : process(Clk, Reset, RxClk, RxClkDel )
begin
if Reset = '1' then
RxClkDel <= RxClk;
RxClkEdge <= '0';
elsif Clk'event and Clk = '0' then
RxClkDel <= RxClk;
RxClkEdge <= RxClk and (not RxClkDel);
end if;
end process;
 
 
---------------------------------------------------------------------
-- Receiver Clock Divider
-- Reset the Rx Clock divider on any data edge
-- Note that debounce data will be skewed by 4 clock cycles.
-- Advance the count only on an input clock pulse
---------------------------------------------------------------------
rxunit_clock_divide : process(Clk, Reset, RxDatEdge, RxState, RxStart,
RxClkEdge, RxClkCnt )
begin
if Reset = '1' then
RxClkCnt <= "000000";
RxStart <= '0';
elsif Clk'event and Clk = '0' then
 
if RxState = "1111" then -- idle state
if RxStart = '0' then -- in hunt mode
if RxDatEdge = '1' then -- falling edge starts counter
RxStart <= '1';
else
RxStart <= RxStart; -- other wise remain halted
end if;
else
RxStart <= RxStart; -- Acquired start, stay in this state
end if;
else
RxStart <= '0'; -- non idle, reset start flag
end if; -- RxState
 
if RxState = "1111" and RxStart = '0' then
RxClkCnt <= "000011"; -- Reset to 3 to account for debounce skew
else
if RxClkEdge = '1' then
RxClkCnt <= RxClkCnt + "000001";
else
RxClkCnt <= RxClkCnt;
end if; -- RxClkEdge
end if; -- RxState
end if; -- clk / reset
end process;
 
---------------------------------------------------------------------
-- Receiver Clock Selector
-- Select output then look for rising edge
---------------------------------------------------------------------
rxunit_clock_select : process(Clk, Reset, BdFmt, RxClk, RxClkCnt,
RxBdDel, RxBdEdge )
begin
-- BdFmt
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
case BdFmt is
when "00" => -- Div by 1
RxBdClk <= RxClk;
when "01" => -- Div by 16
RxBdClk <= RxClkCnt(3);
when "10" => -- Div by 64
RxBdClk <= RxClkCnt(5);
when others => -- reset
RxBdClk <= '0';
end case;
 
if Reset = '1' then
RxBdDel <= RxBdClk;
RxBdEdge <= '0';
elsif Clk'event and Clk = '0' then
RxBdDel <= RxBdClk;
RxBdEdge <= RxBdClk and (not RxBdDel);
end if;
 
end process;
 
 
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
rxunit_receive : process(Clk, Reset, RxState, RxBdEdge, RxDat )
begin
if Reset = '1' then
frameErr <= '0';
outErr <= '0';
parityErr <= '0';
 
ShtReg <= "00000000"; -- Shift register
DataOut <= "00000000";
RxParity <= '0'; -- Parity bit
RxValid <= '0'; -- Data RX data valid flag
RxState <= "1111";
elsif Clk'event and Clk='0' then
if RxBdEdge = '1' then
case RxState is
when "0000" | "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" => -- data bits 0 to 6
ShtReg <= RxDat & ShtReg(7 downto 1);
RxParity <= RxParity xor RxDat;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if RxState = "0110" then
if WdFmt(2) = '0' then
RxState <= "1000"; -- 7 data + parity
else
RxState <= "0111"; -- 8 data bits
end if; -- WdFmt(2)
else
RxState <= RxState + "0001";
end if; -- RxState
 
when "0111" => -- data bit 7
ShtReg <= RxDat & ShtReg(7 downto 1);
RxParity <= RxParity xor RxDat;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if WdFmt(1) = '1' then -- parity bit ?
RxState <= "1000"; -- yes, go to parity
else
RxState <= "1001"; -- no, must be 2 stop bit bits
end if;
 
when "1000" => -- parity bit
if WdFmt(2) = '0' then
ShtReg <= RxDat & ShtReg(7 downto 1); -- 7 data + parity
else
ShtReg <= ShtReg; -- 8 data + parity
end if;
RxParity <= RxParity;
if WdFmt(0) = '0' then -- parity polarity ?
if RxParity = RxDat then -- check even parity
parityErr <= '1';
else
parityErr <= '0';
end if;
else
if RxParity = RxDat then -- check for odd parity
parityErr <= '0';
else
parityErr <= '1';
end if;
end if;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
RxState <= "1001";
 
when "1001" => -- stop bit (Only one required for RX)
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
if RxDat = '1' then -- stop bit expected
frameErr <= '0'; -- yes, no framing error
else
frameErr <= '1'; -- no, framing error
end if;
if tmpDRdy = '1' then -- Has previous data been read ?
outErr <= '1'; -- no, overrun error
else
outErr <= '0'; -- yes, no over run error
end if;
RxValid <= '1';
DataOut <= ShtReg;
RxState <= "1111";
 
when others => -- this is the idle state
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if RxDat = '0' then -- look for start request
RxState <= "0000"; -- yes, read data
else
RxState <= "1111"; -- otherwise idle
end if;
end case; -- RxState
else -- RxBdEdge
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= RxValid;
DataOut <= DataOut;
RxState <= RxState;
end if; -- RxBdEdge
end if; -- clk / reset
end process;
 
 
---------------------------------------------------------------------
-- Receiver Read process
---------------------------------------------------------------------
rxunit_read : process(Clk, Reset, ReadD, RxValid, tmpRxVal, tmpDRdy )
begin
if Reset = '1' then
tmpDRdy <= '0';
tmpRxVal <= '0';
elsif Clk'event and Clk='0' then
if ReadD = '1' then
-- Data was read, reset data ready
tmpDRdy <= '0';
tmpRxVal <= tmpRxVal;
else
if RxValid = '1' and tmpRxVal = '0' then
-- Data was received, set Data ready
tmpDRdy <= '1';
tmpRxVal <= '1';
else
-- Test for falling edge of RxValid.
tmpDRdy <= tmpDRdy;
if RxValid = '0' and tmpRxVal = '1' then
tmpRxVal <= '0';
else
tmpRxVal <= tmpRxVal;
end if;
end if; -- RxValid
end if; -- ReadD
end if; -- clk / reset
end process;
 
 
DARdy <= tmpDRdy;
DAOut <= DataOut;
FRErr <= frameErr;
ORErr <= outErr;
PAErr <= parityErr;
 
end Behaviour; --==================== End of architecture ====================--
/trunk/rtl/vhdl/ioport.vhd
113,13 → 113,13
porta_data, portb_data,
porta_ddr, portb_ddr )
begin
if clk'event and clk = '0' then
if rst = '1' then
porta_data <= "00000000";
portb_data <= "00000000";
porta_ddr <= "00000000";
portb_ddr <= "00000000";
elsif cs = '1' and rw = '0' then
if rst = '1' then
porta_data <= "00000000";
portb_data <= "00000000";
porta_ddr <= "00000000";
portb_ddr <= "00000000";
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
case addr is
when "00" =>
porta_data <= data_in;
/trunk/rtl/vhdl/txunit3.vhd
0,0 → 1,302
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : txunit2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
-- olupas@opencores.org
--
-- 3.0 John Kent 5 January 2003 added 6850 word format control
-- 3.1 John Kent 12 January 2003 Rearranged state machine code
-- 3.2 John Kent 30 March 2003 Revamped State machine
-- 3.3 John Kent 16 January 2004 Major re-write - added baud rate gen
--
-- dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Entity for the Tx Unit --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Transmitter unit
-------------------------------------------------------------------------------
entity TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
LoadD : in Std_Logic; -- Load transmit data
DAIn : in Std_Logic_Vector(7 downto 0);
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
TxClk : in Std_Logic; -- Enable input
TxDat : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic ); -- Tx buffer empty
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for TxUnit
-------------------------------------------------------------------------------
architecture Behaviour of TxUnit is
type TxStateType is ( TxIdle_State, Start_State, Data_State, Parity_State, Stop_State );
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal TxClkDel : Std_Logic; -- Delayed Tx Input Clock
signal TxClkEdge : Std_Logic; -- Tx Input Clock Edge pulse
signal TxClkCnt : Std_Logic_Vector(5 downto 0); -- Tx Baud Clock Counter
signal TxBdDel : Std_Logic; -- Delayed Tx Baud Clock
signal TxBdEdge : Std_Logic; -- Tx Baud Clock Edge pulse
signal TxBdClk : Std_Logic; -- Tx Baud Clock
 
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
signal TBufE : Std_Logic; -- Transmit Buffer Empty
 
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal TxParity : Std_logic; -- Parity Bit
signal DataCnt : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
signal TRegE : Std_Logic; -- Transmit Register empty
signal TRegEDel : Std_Logic; -- Transmit Register empty
signal TRegEEdge : Std_Logic;
signal TxState : TxStateType;
signal TxDbit : Std_Logic;
begin
 
---------------------------------------------------------------------
-- Transmit Clock Edge Detection
-- A falling edge will produce a one clock cycle pulse
---------------------------------------------------------------------
txunit_clock_edge : process(Clk, Reset, TxClk, TxClkDel )
begin
if Reset = '1' then
TxClkDel <= TxClk;
TxClkEdge <= '0';
elsif Clk'event and Clk = '0' then
TxClkDel <= TxClk;
TxClkEdge <= TxClkDel and (not TxClk);
end if;
end process;
 
 
---------------------------------------------------------------------
-- Transmit Clock Divider
-- Advance the count only on an input clock pulse
---------------------------------------------------------------------
txunit_clock_divide : process(Clk, Reset, TxClkEdge, TxClkCnt )
begin
if Reset = '1' then
TxClkCnt <= "000000";
elsif Clk'event and Clk = '0' then
if TxClkEdge = '1' then
TxClkCnt <= TxClkCnt + "000001";
else
TxClkCnt <= TxClkCnt;
end if; -- TxClkEdge
end if; -- reset / clk
end process;
 
---------------------------------------------------------------------
-- Receiver Clock Selector
-- Select output then look for rising edge
---------------------------------------------------------------------
txunit_clock_select : process(Clk, Reset, BdFmt, TxClk, TxClkCnt,
TxBdDel, TxBdEdge )
begin
-- BdFmt
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
case BdFmt is
when "00" => -- Div by 1
TxBdClk <= TxClk;
when "01" => -- Div by 16
TxBdClk <= TxClkCnt(3);
when "10" => -- Div by 64
TxBdClk <= TxClkCnt(5);
when others => -- reset
TxBdClk <= '0';
end case;
 
if Reset = '1' then
TxBdDel <= TxBdClk;
TxBdEdge <= '0';
elsif Clk'event and Clk = '0' then
TxBdDel <= TxBdClk;
TxBdEdge <= TxBdClk and (not TxBdDel);
end if;
end process;
 
---------------------------------------------------------------------
-- Transmit Buffer Empty Edge
-- generate a negative edge pulse
---------------------------------------------------------------------
txunit_busy : process(Clk, Reset, TRegE, TRegEDel )
begin
if Reset = '1' then
TRegEDel <= '0';
TRegEEdge <= '0';
elsif Clk'event and Clk = '0' then
TRegEDel <= TRegE;
TRegEEdge <= TregEDel and (not TRegE ); -- falling edge
end if;
end process;
 
---------------------------------------------------------------------
-- Transmitter activation process
---------------------------------------------------------------------
txunit_write : process(Clk, Reset, LoadD, DAIn, TBufE, TRegEEdge )
begin
if Reset = '1' then
TBufE <= '1';
TBuff <= "00000000";
elsif Clk'event and Clk = '0' then
if LoadD = '1' then
TBuff <= DAIn;
TBufE <= '0';
else
TBuff <= TBuff;
if (TBufE = '0') and (TRegEEdge = '1') then
-- Once the transmitter is started
-- We can flag the buffer empty again.
TBufE <= '1';
else
TBufE <= TBufE;
end if;
end if;
end if; -- clk / reset
TBE <= TBufE;
 
end process;
 
-----------------------------------------------------------------------------
-- Implements the Tx unit
-----------------------------------------------------------------------------
txunit_transmit : process(Reset, Clk, TxState, TxDbit, TBuff, TReg,
TxBdEdge, TxParity, DataCnt, WdFmt,
TBufE, TRegE )
begin
if Reset = '1' then
TxDbit <= '1';
TReg <= "00000000";
TxParity <= '0';
DataCnt <= "0000";
TRegE <= '1';
TxState <= TxIdle_State;
elsif Clk'event and Clk = '0' then
if TxBdEdge = '1' then
case TxState is
when TxIdle_State => -- TxIdle_State (also 1st or 2nd Stop bit)
TxDbit <= '1';
TReg <= TBuff;
TxParity <= '0';
DataCnt <= "0000";
TRegE <= '1';
if TBufE = '0' then
TxState <= Start_State;
else
TxState <= TxIdle_State;
end if;
 
when Start_State =>
TxDbit <= '0'; -- Start bit
TReg <= TReg;
TxParity <= '0';
if WdFmt(2) = '0' then
DataCnt <= "0110"; -- 7 data + parity
else
DataCnt <= "0111"; -- 8 data
end if;
TRegE <= '0';
TxState <= Data_State;
 
when Data_State =>
TxDbit <= TReg(0);
TReg <= '1' & TReg(7 downto 1);
TxParity <= TxParity xor TReg(0);
TRegE <= '0';
DataCnt <= DataCnt - "0001";
if DataCnt = "0000" then
if (WdFmt(2) = '1') and (WdFmt(1) = '0') then
if WdFmt(0) = '0' then -- 8 data bits
TxState <= Stop_State; -- 2 stops
else
TxState <= TxIdle_State; -- 1 stop
end if;
else
TxState <= Parity_State; -- parity
end if;
else
TxState <= Data_State;
end if;
 
when Parity_State => -- 7/8 data + parity bit
if WdFmt(0) = '0' then
TxDbit <= not( TxParity ); -- even parity
else
TXDbit <= TxParity; -- odd parity
end if;
Treg <= Treg;
TxParity <= '0';
TRegE <= '0';
DataCnt <= "0000";
if WdFmt(1) = '0' then
TxState <= Stop_State; -- 2 stops
else
TxState <= TxIdle_State; -- 1 stop
end if;
 
when Stop_State => -- first stop bit
TxDbit <= '1'; -- 2 stop bits
Treg <= Treg;
TxParity <= '0';
DataCnt <= "0000";
TRegE <= '0';
TxState <= TxIdle_State;
 
when others => -- Undefined
TxDbit <= TxDbit;
Treg <= Treg;
TxParity <= '0';
DataCnt <= "0000";
TRegE <= TregE;
TxState <= TxIdle_State;
 
end case; -- TxState
 
else -- TxBdEdge
TxDbit <= TxDbit;
TReg <= TReg;
TxParity <= TxParity;
DataCnt <= DataCnt;
TRegE <= TRegE;
TxState <= TxState;
end if; -- TxBdEdge
end if; -- clk / reset
 
TxDat <= TxDbit;
end process;
 
end Behaviour; --=================== End of architecture ====================--
/trunk/rtl/vhdl/timer.vhd
91,11 → 91,11
timer_write : process( clk, rst, cs, rw, addr, data_in,
timer_reg, timer_ctrl, timer_count )
begin
if clk'event and clk = '0' then
if rst = '1' then
timer_reg <= "00000000";
timer_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
if rst = '1' then
timer_reg <= "00000000";
timer_ctrl <= "00000000";
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
if addr='0' then
timer_reg <= data_in;
timer_ctrl <= timer_ctrl;
119,8 → 119,8
else
timer_term <= timer_term;
end if;
end if;
end if;
end if; -- cs
end if; -- rst / clk
end process;
 
--
144,11 → 144,10
my_counter: process( clk, rst, timer_ctrl, timer_count, timer_in )
variable timer_tmp : std_logic;
begin
if clk'event and clk='0' then
if rst = '1' then
if rst = '1' then
timer_count <= "00000000";
timer_tmp := '0';
else
elsif clk'event and clk='0' then
if timer_ctrl( T_enab ) = '1' then
if timer_in = '0' and timer_tmp = '1' then
timer_tmp := '0';
168,7 → 167,6
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if; -- timer_ctrl
end if; -- rst
end if; -- clk
end process;
 
/trunk/rtl/vhdl/system11.ucf
1,5 → 1,4
#### UCF file created by Project Navigator
#### UCF file created by Project Navigator
#
NET "reset_n" LOC = "p57" ;
NET "sysclk" LOC = "p77" ;
44,240 → 43,188
#NET "cf_iordy" LOC = "P48" ; #J2-18
NET "cf_rst_n" LOC = "P49" ; #J2-19
#
# I/O Port
# For B5-Peripheral-Connectors
# Connector C
#
NET "porta<0>" LOC = "p55" ; #pin 3
NET "porta<1>" LOC = "p56" ; #pin 4
NET "porta<2>" LOC = "p58" ; #pin 5
NET "porta<3>" LOC = "p59" ; #pin 6
NET "porta<4>" LOC = "p60" ; #pin 7
NET "porta<5>" LOC = "p61" ; #pin 8
NET "porta<6>" LOC = "p62" ; #pin 8
NET "porta<7>" LOC = "p63" ; #pin 10
NET "portb<0>" LOC = "p64" ; #pin 11
NET "portb<1>" LOC = "p68" ; #pin 12
NET "portb<2>" LOC = "p69" ; #pin 13
NET "portb<3>" LOC = "p70" ; #pin 14
NET "portb<4>" LOC = "p71" ; #pin 15
NET "portb<5>" LOC = "p73" ; #pin 16
NET "portb<6>" LOC = "p74" ; #pin 17
NET "portb<7>" LOC = "p75" ; #pin 18
NET "timer_out" LOC = "p81" ; #pin 19
#NET "v_drive" LOC = "p55" ; #pin 3
#NET "h_drive" LOC = "p56" ; #pin 4
#NET "blue_lo" LOC = "p58" ; #pin 5
#NET "blue_hi" LOC = "p59" ; #pin 6
#NET "green_lo" LOC = "p60" ; #pin 7
#NET "green_hi" LOC = "p61" ; #pin 8
#NET "red_lo" LOC = "p62" ; #pin 9
#NET "red_hi" LOC = "p63" ; #pin 10
#NET "kb_clock" LOC = "p64" ; #pin 11
#NET "kb_data" LOC = "p68" ; #pin 12
#NET "mouse-clock" LOC = "p69" ; #pin 13
#NET "mouse_data" LOC = "p70" ; #pin 14
#NET "buzzer" LOC = "p71" ; #pin 15
NET "cts_n" LOC = "p73" ; #pin 16
NET "rxbit" LOC = "p74" ; #pin 17
NET "txbit" LOC = "p75" ; #pin 18
NET "rts_n" LOC = "p81" ; #pin 19
#
# For B3-FPGA-CPU-IO
# I/O Port
# Connector D
#
#NET "aux_clock" LOC = "p80" ; #pin 2
#NET "buzzer" LOC = "p82" ; #pin 3
NET "led" LOC = "p82" ; #pin 3
#NET "mouse_clock" LOC = "p83" ; #pin 4
#NET "mouse_data" LOC = "p84" ; #pin 5
NET "cts_n" LOC = "p86" ; #pin 6
NET "rts_n" LOC = "p87" ; #pin 7
NET "txbit" LOC = "p88" ; #pin 8
NET "rxbit" LOC = "p89" ; #pin 9
#NET "kb_clock" LOC = "p93" ; #pin 10
#NET "kb_data" LOC = "p94" ; #pin 11
#NET "v_drive" LOC = "p95" ; #pin 12
#NET "h_drive" LOC = "p96" ; #pin 13
#NET "blue_lo" LOC = "p97" ; #pin 14
#NET "blue_hi" LOC = "p98" ; #pin 15
#NET "green_lo" LOC = "p99" ; #pin 16
#NET "green_hi" LOC = "p100"; #pin 17
#NET "red_lo" LOC = "p101"; #pin 18
#NET "red_hi" LOC = "p102"; #pin 19
#NET "pin2clk" LOC = "p80" ; #pin 2 (Clock input)
NET "led" LOC = "p82" ; #pin 3
NET "porta<0>" LOC = "p83" ; #pin 4
NET "porta<1>" LOC = "p84" ; #pin 5
NET "porta<2>" LOC = "p86" ; #pin 6
NET "porta<3>" LOC = "p87" ; #pin 7
NET "porta<4>" LOC = "p88" ; #pin 8
NET "porta<5>" LOC = "p89" ; #pin 9
NET "porta<6>" LOC = "p93" ; #pin 10
NET "porta<7>" LOC = "p94" ; #pin 11
NET "portb<0>" LOC = "p95" ; #pin 12
NET "portb<1>" LOC = "p96" ; #pin 13
NET "portb<2>" LOC = "p97" ; #pin 14
NET "portb<3>" LOC = "p98" ; #pin 15
NET "portb<4>" LOC = "p99" ; #pin 16
NET "portb<5>" LOC = "p100"; #pin 17
NET "portb<6>" LOC = "p101"; #pin 18
NET "portb<7>" LOC = "p102"; #pin 19
#
# For modified B3-SRAM
# For B5-SRAM
# Connector E
#
NET "ram_addr<0>" LOC = "p108"; #J1.2
NET "ram_addr<1>" LOC = "p109"; #J1.3
NET "ram_addr<2>" LOC = "p110"; #J1.4
NET "ram_addr<3>" LOC = "p111"; #J1.5
NET "ram_addr<4>" LOC = "p112"; #J1.6
NET "ram_addr<5>" LOC = "p113"; #J1.7
NET "ram_addr<6>" LOC = "p114"; #J1.8
NET "ram_addr<7>" LOC = "p115"; #J1.9
NET "ram_csn" LOC = "p116"; #J1.10
NET "ram_csn" LOC = "p108"; #J1.2
NET "ram_addr<16>" LOC = "p109"; #J1.3
NET "ram_addr<15>" LOC = "p110"; #J1.4
NET "ram_addr<14>" LOC = "p111"; #J1.5
NET "ram_addr<13>" LOC = "p112"; #J1.6
NET "ram_addr<12>" LOC = "p113"; #J1.7
NET "ram_addr<11>" LOC = "p114"; #J1.8
NET "ram_addr<10>" LOC = "p115"; #J1.9
NET "ram_addr<9>" LOC = "p116"; #J1.10
NET "ram_addr<8>" LOC = "p120"; #J1.11
NET "ram_addr<9>" LOC = "p121"; #J1.12
NET "ram_addr<10>" LOC = "p122"; #J1.13
NET "ram_addr<11>" LOC = "p123"; #J1.14
NET "ram_addr<12>" LOC = "p125"; #J1.15
NET "ram_addr<13>" LOC = "p126"; #J1.16
NET "ram_addr<14>" LOC = "p127"; #J1.17
NET "ram_addr<15>" LOC = "p129"; #J1.18
NET "ram_addr<16>" LOC = "p132"; #J1.19
NET "ram_addr<7>" LOC = "p121"; #J1.12
NET "ram_addr<6>" LOC = "p122"; #J1.13
NET "ram_addr<5>" LOC = "p123"; #J1.14
NET "ram_addr<4>" LOC = "p125"; #J1.15
NET "ram_addr<3>" LOC = "p126"; #J1.16
NET "ram_addr<2>" LOC = "p127"; #J1.17
NET "ram_addr<1>" LOC = "p129"; #J1.18
NET "ram_addr<0>" LOC = "p132"; #J1.19
#
# For modified B3-SRAM
# For B5-SRAM
# Connector F
#
NET "ram_data<0>" LOC = "p133"; #J2.2
NET "ram_data<1>" LOC = "p134"; #J2.3
NET "ram_data<2>" LOC = "p135"; #J2.4
NET "ram_data<3>" LOC = "p136"; #J2.5
NET "ram_data<4>" LOC = "p138"; #J2.6
NET "ram_data<5>" LOC = "p139"; #J2.7
NET "ram_data<6>" LOC = "p140"; #J2.8
NET "ram_data<7>" LOC = "p141"; #J2.9
NET "ram_data<8>" LOC = "p145"; #J2.10
NET "ram_data<9>" LOC = "p146"; #J2.11
NET "ram_data<10>" LOC = "p147"; #J2.12
NET "ram_data<11>" LOC = "p148"; #J2.13
NET "ram_data<12>" LOC = "p149"; #J2.14
NET "ram_data<13>" LOC = "p150"; #J2.15
NET "ram_data<14>" LOC = "p151"; #J2.16
NET "ram_data<15>" LOC = "p152"; #J2.17
NET "ram_wrun" LOC = "p153"; #J2.18
NET "ram_wrln" LOC = "p154"; #J2.19
NET "ram_wrun" LOC = "p133"; #J2.2
NET "ram_wrln" LOC = "p134"; #J2.3
NET "ram_data<15>" LOC = "p135"; #J2.4
NET "ram_data<14>" LOC = "p136"; #J2.5
NET "ram_data<13>" LOC = "p138"; #J2.6
NET "ram_data<12>" LOC = "p139"; #J2.7
NET "ram_data<11>" LOC = "p140"; #J2.8
NET "ram_data<10>" LOC = "p141"; #J2.9
NET "ram_data<9>" LOC = "p145"; #J2.10
NET "ram_data<8>" LOC = "p146"; #J2.11
NET "ram_data<7>" LOC = "p147"; #J2.12
NET "ram_data<6>" LOC = "p148"; #J2.13
NET "ram_data<5>" LOC = "p149"; #J2.14
NET "ram_data<4>" LOC = "p150"; #J2.15
NET "ram_data<3>" LOC = "p151"; #J2.16
NET "ram_data<2>" LOC = "p152"; #J2.17
NET "ram_data<1>" LOC = "p153"; #J2.18
NET "ram_data<0>" LOC = "p154"; #J2.19
#
# Connector G
#
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "test_alu<0>" LOC = "p160"; #pin 3
NET "test_alu<1>" LOC = "p161"; #pin 4
NET "test_alu<2>" LOC = "p162"; #pin 5
NET "test_alu<3>" LOC = "p163"; #pin 6
NET "test_alu<4>" LOC = "p164"; #pin 7
NET "test_alu<5>" LOC = "p165"; #pin 8
NET "test_alu<6>" LOC = "p166"; #pin 9
NET "test_alu<7>" LOC = "p167"; #pin 10
NET "test_alu<8>" LOC = "p168"; #pin 11
NET "test_alu<9>" LOC = "p169"; #pin 12
NET "test_alu<10>" LOC = "p173"; #pin 13
NET "test_alu<11>" LOC = "p174"; #pin 14
NET "test_alu<12>" LOC = "p175"; #pin 15
NET "test_alu<13>" LOC = "p176"; #pin 16
NET "test_alu<14>" LOC = "p178"; #pin 17
NET "test_alu<15>" LOC = "p179"; #pin 18
#NET "pin19" LOC = "p180"; #pin 19
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "bus_addr<0>" LOC = "p160"; #pin 3
NET "bus_addr<1>" LOC = "p161"; #pin 4
NET "bus_addr<2>" LOC = "p162"; #pin 5
NET "bus_addr<3>" LOC = "p163"; #pin 6
NET "bus_addr<4>" LOC = "p164"; #pin 7
NET "bus_addr<5>" LOC = "p165"; #pin 8
NET "bus_addr<6>" LOC = "p166"; #pin 9
NET "bus_addr<7>" LOC = "p167"; #pin 10
NET "bus_addr<8>" LOC = "p168"; #pin 11
NET "bus_addr<9>" LOC = "p169"; #pin 12
NET "bus_addr<10>" LOC = "p173"; #pin 13
NET "bus_addr<11>" LOC = "p174"; #pin 14
NET "bus_addr<12>" LOC = "p175"; #pin 15
NET "bus_addr<13>" LOC = "p176"; #pin 16
NET "bus_addr<14>" LOC = "p178"; #pin 17
NET "bus_addr<15>" LOC = "p179"; #pin 18
NET "bus_cs" LOC = "p180"; #pin 19
#
# Connector H
#
#NET "pin2" LOC = "p185"; #pin 2 (clk input)
#NET "pin3" LOC = "p181"; #pin 3
#NET "uart_csn" LOC = "p187"; #pin 4
#NET "test_rw" LOC = "p188"; #pin 5
#NET "test_d0" LOC = "p189"; #pin 6
#NET "test_d1" LOC = "p191"; #pin 7
NET "bus_clk" LOC = "p181"; #pin 3
NET "bus_reset" LOC = "p187"; #pin 4
#NET "pin5" LOC = "p188"; #pin 5
#NET "pin6" LOC = "p189"; #pin 6
#NET "pin7" LOC = "p191"; #pin 7
#NET "pin8" LOC = "p192"; #pin 8
#NET "pin9" LOC = "p193"; #pin 9
#NET "pin10" LOC = "p194"; #pin 10
NET "test_cc<0>" LOC = "p198"; #pin 11
NET "test_cc<1>" LOC = "p199"; #pin 12
NET "test_cc<2>" LOC = "p200"; #pin 13
NET "test_cc<3>" LOC = "p201"; #pin 14
NET "test_cc<4>" LOC = "p202"; #pin 15
NET "test_cc<5>" LOC = "p203"; #pin 16
NET "test_cc<6>" LOC = "p204"; #pin 17
NET "test_cc<7>" LOC = "p205"; #pin 18
#NET "pin19" LOC = "p206"; #pin 19
NET "timer_out" LOC = "p194"; #pin 10
NET "bus_data<0>" LOC = "p198"; #pin 11
NET "bus_data<1>" LOC = "p199"; #pin 12
NET "bus_data<2>" LOC = "p200"; #pin 13
NET "bus_data<3>" LOC = "p201"; #pin 14
NET "bus_data<4>" LOC = "p202"; #pin 15
NET "bus_data<5>" LOC = "p203"; #pin 16
NET "bus_data<6>" LOC = "p204"; #pin 17
NET "bus_data<7>" LOC = "p205"; #pin 18
NET "bus_rw" LOC = "p206"; #pin 19
#
# Timing groups
# Timing Groups
#
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
INST "ram_addr<3>" TNM = "ram_addr";
INST "ram_addr<4>" TNM = "ram_addr";
INST "ram_addr<5>" TNM = "ram_addr";
INST "ram_addr<6>" TNM = "ram_addr";
INST "ram_addr<7>" TNM = "ram_addr";
INST "ram_addr<8>" TNM = "ram_addr";
INST "ram_addr<9>" TNM = "ram_addr";
INST "ram_addr<10>" TNM = "ram_addr";
INST "ram_addr<11>" TNM = "ram_addr";
INST "ram_addr<12>" TNM = "ram_addr";
INST "ram_addr<13>" TNM = "ram_addr";
INST "ram_addr<14>" TNM = "ram_addr";
INST "ram_addr<15>" TNM = "ram_addr";
INST "ram_addr<16>" TNM = "ram_addr";
INST "ram_data<0>" TNM = "ram_data";
INST "ram_data<1>" TNM = "ram_data";
INST "ram_data<2>" TNM = "ram_data";
INST "ram_data<3>" TNM = "ram_data";
INST "ram_data<4>" TNM = "ram_data";
INST "ram_data<5>" TNM = "ram_data";
INST "ram_data<6>" TNM = "ram_data";
INST "ram_data<7>" TNM = "ram_data";
INST "ram_data<8>" TNM = "ram_data";
INST "ram_data<9>" TNM = "ram_data";
INST "ram_data<10>" TNM = "ram_data";
INST "ram_data<11>" TNM = "ram_data";
INST "ram_data<12>" TNM = "ram_data";
INST "ram_data<13>" TNM = "ram_data";
INST "ram_data<14>" TNM = "ram_data";
INST "ram_data<15>" TNM = "ram_data";
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
TIMEGRP "ram_cs" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 90 ns AFTER "sysclk";
INST "ram_addr<0>" TNM = "gram_addr";
INST "ram_addr<1>" TNM = "gram_addr";
INST "ram_addr<2>" TNM = "gram_addr";
INST "ram_addr<3>" TNM = "gram_addr";
INST "ram_addr<4>" TNM = "gram_addr";
INST "ram_addr<5>" TNM = "gram_addr";
INST "ram_addr<6>" TNM = "gram_addr";
INST "ram_addr<7>" TNM = "gram_addr";
INST "ram_addr<8>" TNM = "gram_addr";
INST "ram_addr<9>" TNM = "gram_addr";
INST "ram_addr<10>" TNM = "gram_addr";
INST "ram_addr<11>" TNM = "gram_addr";
INST "ram_addr<12>" TNM = "gram_addr";
INST "ram_addr<13>" TNM = "gram_addr";
INST "ram_addr<14>" TNM = "gram_addr";
INST "ram_addr<15>" TNM = "gram_addr";
INST "ram_addr<16>" TNM = "gram_addr";
INST "ram_data<0>" TNM = "gram_data";
INST "ram_data<1>" TNM = "gram_data";
INST "ram_data<2>" TNM = "gram_data";
INST "ram_data<3>" TNM = "gram_data";
INST "ram_data<4>" TNM = "gram_data";
INST "ram_data<5>" TNM = "gram_data";
INST "ram_data<6>" TNM = "gram_data";
INST "ram_data<7>" TNM = "gram_data";
INST "ram_data<8>" TNM = "gram_data";
INST "ram_data<9>" TNM = "gram_data";
INST "ram_data<10>" TNM = "gram_data";
INST "ram_data<11>" TNM = "gram_data";
INST "ram_data<12>" TNM = "gram_data";
INST "ram_data<13>" TNM = "gram_data";
INST "ram_data<14>" TNM = "gram_data";
INST "ram_data<15>" TNM = "gram_data";
INST "ram_wrln" TNM = "gram_wr";
INST "ram_wrun" TNM = "gram_wr";
INST "ram_csn" TNM = "gram_cs";
#
# Timing Constraints
#
#TIMEGRP "gram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "sysclk";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns LOW 50 %;
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;
NET "ram_addr<3>" FAST;
NET "ram_addr<4>" FAST;
NET "ram_addr<5>" FAST;
NET "ram_addr<6>" FAST;
NET "ram_addr<7>" FAST;
NET "ram_addr<8>" FAST;
NET "ram_addr<9>" FAST;
NET "ram_addr<10>" FAST;
NET "ram_addr<11>" FAST;
NET "ram_addr<12>" FAST;
NET "ram_addr<13>" FAST;
NET "ram_addr<14>" FAST;
NET "ram_addr<15>" FAST;
NET "ram_addr<16>" FAST;
#
# Fast I/O Pins
#
NET "ram_csn" FAST;
NET "ram_data<0>" FAST;
NET "ram_data<1>" FAST;
NET "ram_data<2>" FAST;
NET "ram_data<3>" FAST;
NET "ram_data<4>" FAST;
NET "ram_data<5>" FAST;
NET "ram_data<6>" FAST;
NET "ram_data<7>" FAST;
NET "ram_data<8>" FAST;
NET "ram_data<9>" FAST;
NET "ram_data<10>" FAST;
NET "ram_data<11>" FAST;
NET "ram_data<12>" FAST;
NET "ram_data<13>" FAST;
NET "ram_data<14>" FAST;
NET "ram_data<15>" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;
/trunk/rtl/vhdl/System11.vhd
25,10 → 25,9
-- Uses : cpu11 (cpu11.vhd) CPU core
-- boot_rom (swtbug11.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- miniuart (miniUART.vhd) UART
-- clkunit (clkunit.vhd)
-- rxunit (rxunit.vhd)
-- txunit (txunit.vhd)
-- miniuart (miniUART3.vhd) UART
-- rxunit (rxunit3.vhd)
-- txunit (txunit3.vhd)
-- ioport (ioport.vhd) parallel i/o port
-- timer (timer.vhd) small counter timer
--
36,7 → 35,10
-- Revision list
-- Version Author Date Changes
-- 1.0 John Kent 6 September 2003 Initial release to open corse
--
-- 1.1 John Kent 3 April 2004 Change MiniUart to version with external Baud clock.
-- Added Baud Clock for 57.6 KBd at 25MHz
-- Added System clock divider to run CPU at 12.5MHz
-- Added Bus I/O in I/O map.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
57,8 → 59,11
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
 
-- PS/2 Keyboard
-- kb_clock : inout Std_logic;
-- kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
70,7 → 75,7
cts_n : in Std_Logic;
 
-- CRTC output signals
-- v_drive : out Std_Logic;
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
80,15 → 85,6
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- I/O Ports
PortA : inout std_logic_vector(7 downto 0);
PortB : inout std_logic_vector(7 downto 0);
-- PortC : inout std_logic_vector(7 downto 0);
-- PortD : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
timer_out : out std_logic;
 
-- Compact Flash B5-CF Module
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
104,9 → 100,22
-- cf_pdiag : in std_logic;
-- cf_present : in std_logic;
 
-- test signals
test_alu : out std_logic_vector(15 downto 0);
test_cc : out std_logic_vector(7 downto 0)
-- I/O Ports
Porta : inout std_logic_vector(7 downto 0);
Portb : inout std_logic_vector(7 downto 0);
-- PortC : inout std_logic_vector(7 downto 0);
-- PortD : inout std_logic_vector(7 downto 0);
 
-- CPU bus
bus_clk : out std_logic;
bus_reset : out std_logic;
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
timer_out : out std_logic
);
end;
 
135,6 → 144,8
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal baudclk : Std_Logic;
signal DCD_n : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
163,10 → 174,34
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal BaudCount : std_logic_vector(4 downto 0);
 
-- attribute buffer_type : string;
-- attribute buffer_type of cpu_clk : signal is "BUFG";
 
-----------------------------------------------------------------
--
-- CPU11 Core
--
-----------------------------------------------------------------
 
component cpu11
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic
);
end component;
 
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
173,20 → 208,24
 
component miniUART
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component;
 
 
--------------------------------------
--
-- Three port parallel I/O
228,21 → 267,6
);
end component;
 
component cpu11
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
component dat_ram
port (
264,12 → 288,12
);
end component;
 
-- component BUFG is
-- port (
-- i: in std_logic;
-- o: out std_logic
-- );
-- end component;
component BUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
 
begin
-----------------------------------------------------------------------------
276,23 → 300,39
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_cpu : cpu11 port map (
clk => cpu_clk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => cpu_irq,
xirq => cpu_xirq
);
 
my_uart : miniUART port map (
SysClk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => baudclk,
TxC => baudclk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
RTS_n => rts_n
);
 
 
my_ioport : ioport port map (
clk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
304,7 → 344,7
);
 
my_timer : timer port map (
clk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
316,23 → 356,9
timer_out => timer_out
);
 
my_cpu : cpu11 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => cpu_irq,
xirq => cpu_xirq,
test_alu => test_alu,
test_cc => test_cc
);
 
 
my_dat : dat_ram port map (
clk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
342,15 → 368,17
data_out => dat_data_out(7 downto 0)
);
 
rom : boot_rom port map (
my_rom : boot_rom port map (
addr => cpu_addr(9 downto 0),
data => rom_data_out
);
 
-- clk_buffer : BUFG port map(
-- i => e_clk,
-- o => cpu_clk
-- );
 
clk_buffer : BUFG port map(
i => countL(0),
o => cpu_clk
);
 
----------------------------------------------------------------------
--
360,10 → 388,10
 
my_decoder: process(
cpu_addr, cpu_vma,
rom_data_out, ram_data_out,
rom_data_out, ram_data_out, bus_data,
ioport_data_out, timer_data_out, uart_data_out, cf_data_out )
begin
case cpu_addr(15 downto 13) is
case cpu_addr(15 downto 13) is
--
-- ROM & DAT Space $E000 - $FFFF
--
375,6 → 403,8
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
 
--
-- I/O Space at $8000 - $9FFF
--
391,6 → 421,7
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
--
-- Compact Flash $8010
--
400,6 → 431,7
cf_cs <= cpu_vma;
timer_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
--
-- Timer $8020
--
409,6 → 441,7
cf_cs <= '0';
timer_cs <= cpu_vma;
ioport_cs <= '0';
bus_cs <= '0';
--
-- I/O Port $8030
--
418,15 → 451,17
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= cpu_vma;
bus_cs <= '0';
--
-- Empty
--
when others => -- $8040 to $9FFF
cpu_data_in <= "00000000";
cpu_data_in <= bus_data;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
bus_cs <= cpu_vma;
end case;
--
-- The rest is all RAM
439,7 → 474,8
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
end case;
bus_cs <= '0';
end case;
end process;
 
----------------------------------------------------------------------
448,18 → 484,18
--
----------------------------------------------------------------------
 
my_ram: process( SysClk, Reset_n,
my_ram: process( cpu_clk, Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
ram_cs, ram_wrl, ram_wru,
ram_data, dat_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not dat_data_out(5)) and (not cpu_rw) and SysClk;
ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrln <= not ram_wrl;
ram_wru <= dat_data_out(5) and (not cpu_rw) and SysClk;
ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
ram_wrun <= not ram_wru;
ram_addr(16 downto 12) <= dat_data_out(4 downto 0);
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
ram_addr(16 downto 11) <= dat_data_out(5 downto 0);
ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
473,7 → 509,7
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if dat_data_out(5) = '1' then
if cpu_addr(0) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
517,27 → 553,54
end process;
 
--
-- CPU bus signals
--
--clock_gen : process( SysClk, e_clk )
--begin
-- if SysClk'event and SysClk='0' then
-- e_clk <= not e_clk;
-- end if;
--end process;
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_rw <= cpu_rw;
bus_addr <= cpu_addr;
if( cpu_rw = '0' ) then
bus_data <= cpu_data_out;
else
bus_data <= "ZZZZZZZZ";
end if;
end process;
 
--
-- flash led to indicate code is working
--
increment: process (SysClk, CountL )
begin
if(SysClk'event and SysClk = '0') then
increment: process (SysClk, Reset_n, CountL )
begin
if( Reset_n = '0' ) then
countL <= "000000000000000000000000";
elsif(SysClk'event and SysClk = '0') then
countL <= countL + 1;
end if;
LED <= countL(21);
end process;
LED <= countL(22);
-- cpu_clk <= countL(0);
-- baudclk <= countL(5); -- 9.8MHz / 64 = 153,600 KHz = 9600Bd * 16
-- baudclk <= countL(4); -- 9.8MHz / 32 = 307,200 KHz = 19200Bd * 16
-- baudclk <= countL(3); -- 9.8MHz / 16 = 614,400 KHz = 38400Bd * 16
-- baudclk <= countL(2); -- 4.9MHz / 8 = 614,400 KHz = 38400Bd * 16
end process;
 
my_clock: process( SysClk, Reset_n, BaudCount )
begin
if(SysClk'event and SysClk = '0') then
if( Reset_n = '0' ) then
BaudCount <= "00000";
elsif( BaudCount = 26 ) then
BaudCount <= "00000";
else
BaudCount <= BaudCount + 1;
end if;
end if;
baudclk <= BaudCount(4); -- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
dcd_n <= '0';
end process;
 
 
--
-- CRTC output signals
--
/trunk/rtl/vhdl/cpu11.vhd
38,6 → 38,11
-- Basic 6800 instructions working
-- but not Divide and bit operations.
--
-- Version 1.1 - 4 April 2004
-- Removed Test_alu and Test_cc signals
-- Moved Dual operand execution into fetch state
-- Fixed Indexed bit operators
--
 
library ieee;
use ieee.std_logic_1164.all;
53,9 → 58,7
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
xirq: in std_logic
);
end;
 
71,16 → 74,16
constant CBIT : integer := 0;
 
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, direct_state, direct16_state, immediate16_state,
extended_state, indexed_state, read8_state, read16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state, spin_state,
exchange1_state, exchange2_state,
exchange_state,
mul_state, mulea_state, muld_state, mul0_state,
idiv_state,
div1_state, div2_state, div3_state, div4_state, div5_state,
jmp_state, jsr_state, jsr1_state,
branch_state, bsr_state, bsr1_state,
bitmask_state, brset_state, brclr_state, bset_state, bclr_state,
bitmask_state, brset_state, brclr_state,
rts_hi_state, rts_lo_state,
int_pcl_state, int_pch_state,
int_ixl_state, int_ixh_state,
92,7 → 95,7
rti_iyl_state, rti_iyh_state,
rti_pcl_state, rti_pch_state,
pula_state, psha_state, pulb_state, pshb_state,
pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state,
pulxy_lo_state, pulxy_hi_state, pshxy_lo_state, pshxy_hi_state,
vect_lo_state, vect_hi_state );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
type dout_type is ( acca_dout, accb_dout, cc_dout,
106,9 → 109,9
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea, add_ix_ea, add_iy_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, xirq_iv, irq_iv );
type count_type is (reset_count, latch_count, inc_count );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, iy_left, pc_left, sp_left, ea_left );
317,6 → 320,8
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when incr_pc =>
pc <= pc + "0000000000000001";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
336,7 → 341,7
--
----------------------------------
 
ea_reg: process( clk, ea_ctrl, ea, out_alu, data_in )
ea_reg: process( clk, ea_ctrl, ea, out_alu, data_in, xreg, yreg )
begin
 
if clk'event and clk = '0' then
349,6 → 354,10
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when add_ix_ea =>
ea <= ea + xreg;
when add_iy_ea =>
ea <= ea + yreg;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
422,7 → 431,7
if clk'event and clk = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00000001";
op_code <= "00000001"; -- nop
when fetch_op =>
op_code <= data_in;
when others =>
950,9 → 959,6
when others =>
cc_out(SBIT) <= cc(SBIT);
end case;
 
test_alu <= out_alu;
test_cc <= cc_out;
end process;
 
 
1053,51 → 1059,467
-- either from the timer
-- or from the external input.
--
when fetch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- service non maskable interrupts
if (xirq = '1') and (cc(XBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
-- service maskable interrupts
else
when fetch_state =>
case op_code(7 downto 4) is
when "0000" | -- inherent operators
"0001" | -- bit operators come here
"0010" | -- branch conditional
"0011" | -- stack operators
"0100" | -- acca single operand
"0101" | -- accb single operand
"0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0011" => -- subd / cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
if (pre_byte = "00011010") or (pre_byte = "11001101") then
-- CPD
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
else
-- SUBD
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end if;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1100" => -- cpx / cpy
if (pre_byte = "00011000") or (pre_byte = "00011010") then
-- cpy
left_ctrl <= iy_left;
else
-- cpx
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
when "1111" => -- sts / xgdx / xgdy
if op_code(7 downto 4) = "1000" then
--
-- exchange registers
-- at this point md holds accd
-- accd holds either X or Y
-- now transfer md to X or Y
--
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
else
-- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end if;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1110" => -- ldx / ldy
if ((pre_byte = "00011000") or (pre_byte = "00011010")) then
-- LDY
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- LDX
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
when "1111" => -- stx / sty
if ((pre_byte = "00011000") or (pre_byte = "00011010")) then
-- STY
left_ctrl <= iy_left;
else
-- STX
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
ea_ctrl <= reset_ea;
md_ctrl <= latch_md;
count_ctrl <= reset_count;
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
-- service non maskable interrupts
if (xirq = '1') and (cc(XBIT) = '0') then
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
-- service maskable interrupts
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= decode_state;
end if;
end if;
if (irq = '1') and (cc(IBIT) = '0') then
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
1107,9 → 1529,9
-- fetch first byte of address or immediate data
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
pre_ctrl <= latch_pre;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
pre_ctrl <= latch_pre;
case op_code(7 downto 4) is
when "0000" =>
md_ctrl <= reset_md;
1206,12 → 1628,14
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1000" => -- inx
when "1000" => -- inx / iny
if pre_byte = "00011000" then
-- iny
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- inx
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
1223,12 → 1647,14
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
next_state <= fetch_state;
when "1001" => -- dex
when "1001" => -- dex / dey
if pre_byte = "00011000" then
-- dey
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- dex
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
1239,7 → 1665,6
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
next_state <= fetch_state;
when "1010" => -- clv
left_ctrl <= acca_left;
1356,7 → 1781,7
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
next_state <= read8_state;
when "0011" => -- brclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
1366,7 → 1791,7
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
next_state <= read8_state;
when "0100" => -- bset direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
1376,7 → 1801,7
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
next_state <= read8_state;
when "0101" => -- bclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
1386,7 → 1811,7
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
next_state <= read8_state;
when "0110" => -- tab
op_ctrl <= latch_op;
left_ctrl <= acca_left;
1427,7 → 1852,7
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1010" => -- CPD & CPY ff,X prebyte
when "1010" => -- prebyte - CPD / CPY / LDY / STY ff,X
op_ctrl <= fetch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
1624,9 → 2049,11
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
if pre_byte = "00011000" then
-- tsy
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- tsx
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
1670,8 → 2097,10
next_state <= fetch_state;
when "0101" => -- txs / tys
if pre_byte = "00011000" then
-- tys
left_ctrl <= iy_left;
else
-- txs
left_ctrl <= ix_left;
end if;
right_ctrl <= one_right;
1699,7 → 2128,7
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshb_state;
when "1000" => -- pulx
when "1000" => -- pulxy
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
1707,7 → 2136,7
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pulx_hi_state;
next_state <= pulxy_hi_state;
when "1001" => -- rts
left_ctrl <= sp_left;
right_ctrl <= one_right;
1741,7 → 2170,7
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= rti_cc_state;
when "1100" => -- pshx
when "1100" => -- pshxy
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
1749,7 → 2178,7
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshx_lo_state;
next_state <= pshxy_lo_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= accb_right;
1793,8 → 2222,8
-- Do not advance PC
--
when "0100" => -- acca single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
1865,7 → 2294,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
1880,8 → 2309,8
-- Do not advance PC
--
when "0101" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
1952,7 → 2381,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
2006,7 → 2435,7
next_state <= extended_state;
 
when "1000" => -- acca immediate
ea_ctrl <= fetch_first_ea;
ea_ctrl <= fetch_first_ea; -- for BSR
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
2040,7 → 2469,7
alu_ctrl <= alu_st16;
pc_ctrl <= latch_pc;
md_ctrl <= load_md;
next_state <= exchange1_state;
next_state <= exchange_state;
when others =>
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
2047,12 → 2476,11
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= execute_state;
next_state <= fetch_state;
end case;
 
when "1001" => -- acca direct
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
2060,19 → 2488,36
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0111" | -- staa direct
"1111" => -- sts direct
next_state <= execute_state;
when "0111" => -- staa direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1111" => -- sts direct
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1101" => -- jsr direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= jsr_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
 
when "1010" => -- acca indexed
2110,7 → 2555,7
next_state <= extended_state;
 
when "1100" => -- accb immediate
ea_ctrl <= fetch_first_ea;
ea_ctrl <= latch_ea;
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
2126,7 → 2571,7
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldx #
"1110" => -- ldx # / ldy #
op_ctrl <= latch_op;
next_state <= immediate16_state;
when "1101" => -- indexed Y pre-byte $CD
2134,7 → 2579,7
next_state <= decode_state;
when others =>
op_ctrl <= latch_op;
next_state <= execute_state;
next_state <= fetch_state;
end case;
 
when "1101" => -- accb direct
2146,19 → 2591,40
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0111" | -- stab direct
"1101" | -- std direct
"1111" => -- stx / sty direct
next_state <= execute_state;
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty direct
if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
 
when "1110" => -- accb indexed
2235,7 → 2701,7
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
next_state <= fetch_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
2244,63 → 2710,150
when indexed_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- calculate effective address from index reg
-- index offest is not sign extended
if (pre_byte = "00011000") or (pre_byte = "11001101") then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
-- idle bus.
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- add 8 bit ea to ix or iy
if(( pre_byte = "00011000") or (pre_byte = "00011010")) then
ea_ctrl <= add_iy_ea;
else
left_ctrl <= ix_left;
ea_ctrl <= add_ix_ea;
end if;
right_ctrl <= ea_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- work out next state
case op_code(7 downto 4) is
when "0001" => -- BSET, BCLR, BRSET, BRCLR
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
case op_code(3 downto 0) is
when "1100" | -- BSET
"1101" | -- BCLR
"1110" | -- BRSET
"1111" => -- BRCLR
next_state <= read8_state;
when others =>
next_state <= fetch_state;
end case;
when "0110" => -- single op indexed
case op_code(3 downto 0) is
when "1011" => -- undefined
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jmp_state;
when "1111" => -- clr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" | -- staa
"1111" => -- sts
next_state <= execute_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" | -- stab
"1101" | -- std
"1111" => -- stx / sty
next_state <= execute_state;
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty direct
if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
2307,59 → 2860,128
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
when "1011" => -- undefined
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jmp_state;
when "1111" => -- clr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" | -- staa extended
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" | -- stab extended
"1101" | -- std
"1111" => -- stx / sty
next_state <= execute_state;
when others =>
next_state <= direct_state;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty
if(( pre_byte = "00011000" ) or ( pre_byte = "00011010" )) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
next_state <= fetch_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
2366,7 → 2988,7
-- read memory location
-- note that reads may be 8 or 16 bits
--
when direct_state => -- read data
when read8_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
2381,7 → 3003,7
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0001" => -- bset / bclr / brset / brclr
when "0001" => -- bset / bclr / brset / brclr
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
2409,7 → 3031,7
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
next_state <= read16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
2416,7 → 3038,7
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
next_state <= fetch_state;
end case;
when "1101" | "1110" | "1111" => -- accb
pc_ctrl <= latch_pc;
2430,7 → 3052,7
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
next_state <= read16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
2437,7 → 3059,7
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= ea_left;
2449,7 → 3071,7
next_state <= fetch_state;
end case;
 
when direct16_state => -- read second data byte from ea
when read16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
2471,7 → 3093,7
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
next_state <= fetch_state;
 
--
-- exchange registers
2478,7 → 3100,7
-- at this point md holds accd
-- transfer X or Y to accd
--
when exchange1_state => -- md holds accd
when exchange_state => -- md holds accd
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
2504,43 → 3126,8
-- idle the address bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= exchange2_state;
next_state <= fetch_state;
 
--
-- exchange registers
-- at this point md holds accd
-- accd holds either X or Y
-- now transfer md to X or Y
--
when exchange2_state => -- md holds accd
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer md to x or y
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
-- idle the address bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when bitmask_state => -- fetch bit mask from next op
-- default
acca_ctrl <= latch_acca;
2569,9 → 3156,9
when "00010011" | "00011111" => -- brclr
next_state <= brclr_state;
when "00010100" | "00011100" => -- bset
next_state <= bset_state;
next_state <= execute_state;
when "00010101" | "00011101" => -- bclr
next_state <= bclr_state;
next_state <= execute_state;
when others =>
next_state <= fetch_state;
end case;
2632,54 → 3219,7
next_state <= branch_state;
end if;
 
when bclr_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pc_ctrl <= latch_pc;
-- mask bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bclr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
ea_ctrl <= latch_ea;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
 
when bset_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pc_ctrl <= latch_pc;
-- mask bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bset;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
ea_ctrl <= latch_ea;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
 
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
3195,24 → 3735,31
dout_ctrl <= md_lo_dout;
next_state <= spin_state;
 
 
--
-- Execute cycle is performed by
-- single operand indexed and extended instructions
-- and bit operators.
--
when execute_state => -- execute
-- default
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
count_ctrl <= reset_count;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0001" => -- bit operators come here
case op_code(3 downto 0) is
when "0100" | "1100" => -- bset
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
when "0100" | "1100" => -- bset
-- OR bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
3219,19 → 3766,8
alu_ctrl <= alu_bset;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
when "0101" | "1101" => -- bclr
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
when "0101" | "1101" => -- bclr
-- AND bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
3238,19 → 3774,8
alu_ctrl <= alu_bclr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
when others =>
-- idle ALU
left_ctrl <= md_left;
right_ctrl <= pre_right;
3257,48 → 3782,11
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
when "0000" | -- inherent operators
"0010" | -- branch conditional
"0011" | -- stack operators
"0100" | -- acca single operand
"0101" => -- accb single operand
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when "0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
3387,7 → 3875,7
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
3399,478 → 3887,15
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
 
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- subd / cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
if (pre_byte = "00011010") or (pre_byte = "11001101") then
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
else
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end if;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- cpx / cpy
if (pre_byte = "00011000") or (pre_byte = "00011010") then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when "1110" => -- ldx / ldy
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- stx / sty
if pre_byte = "00011000" then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
end case;
--
-- 16 bit Write state
-- write high byte of ALU output.
4026,7 → 4051,7
dout_ctrl <= accb_dout;
next_state <= fetch_state;
 
when pshx_lo_state =>
when pshxy_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
4053,9 → 4078,9
else
dout_ctrl <= ix_lo_dout;
end if;
next_state <= pshx_hi_state;
next_state <= pshxy_hi_state;
 
when pshx_hi_state =>
when pshxy_hi_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
4083,7 → 4108,7
end if;
next_state <= fetch_state;
 
when pulx_hi_state =>
when pulxy_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
4111,9 → 4136,9
dout_ctrl <= ix_hi_dout;
end if;
addr_ctrl <= pull_ad;
next_state <= pulx_lo_state;
next_state <= pulxy_lo_state;
 
when pulx_lo_state =>
when pulxy_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
4756,12 → 4781,10
 
change_state: process( clk, rst, state )
begin
if clk'event and clk = '0' then
if rst = '1' then
state <= reset_state;
else
state <= next_state;
end if;
if rst = '1' then
state <= reset_state;
elsif clk'event and clk = '0' then
state <= next_state;
end if;
end process;
-- output
/trunk/rtl/vhdl/System11.npl
1,36 → 1,43
JDF E
// Created by ISE ver 1.0
JDF G
// Created by Project Navigator ver 1.0
PROJECT System11
DESIGN system11 Normal
DEVKIT xc2s300e-6pq208
DESIGN system11
DEVFAM spartan2e
FLOW XST VHDL
STIMULUS testbench1.vhd Normal
STIMULUS testbench2.vhd Normal
STIMULUS testbench3.vhd Normal
MODULE ioport.vhd
MODSTYLE ioport Normal
MODULE cpu11.vhd
MODSTYLE cpu11 Normal
MODULE rxunit.vhd
MODSTYLE rxunit Normal
MODULE swtbug11.vhd
MODSTYLE boot_rom Normal
MODULE txunit.vhd
MODSTYLE txunit Normal
MODULE datram.vhd
MODSTYLE dat_ram Normal
MODULE timer.vhd
MODSTYLE timer Normal
MODULE System11.vhd
MODSTYLE system11 Normal
MODULE clkunit.vhd
MODSTYLE clkunit Normal
MODULE miniUART.vhd
MODSTYLE miniuart Normal
 
DEVFAMTIME 315558000
DEVICE xc2s300e
DEVICETIME 315558000
DEVPKG pq208
DEVPKGTIME 315558000
DEVSPEED -6
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS testbench1.vhd
STIMULUS testbench2.vhd
STIMULUS testbench3.vhd
SOURCE ioport.vhd
SOURCE cpu11.vhd
SOURCE swtbug11.vhd
SOURCE datram.vhd
SOURCE timer.vhd
SOURCE System11.vhd
SOURCE rxunit3.vhd
SOURCE txunit3.vhd
SOURCE miniUART3.vhd
STIMULUS testbench4.vhd
SOURCE tb_ram.vhd
STIMULUS testbench5.vhd
DEPASSOC system11 system11.ucf
[Normal]
p_impactConfigMode=xstvhd, SPARTAN2E, VHDL.t_impactProgrammingTool, 1062755889, Slave Serial
 
p_impactConfigMode=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1062755889, Slave Serial
p_ModelSimSimRunTime_tbw=xstvhd, spartan2e, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
[STATUS-ALL]
system11.bitgenGroup=OK,1084885833
[STRATEGY-LIST]
Normal=True, 1062754578
Normal=True

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.