OpenCores

adaptive_lms_equalizer/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: adaptive_lms_equalizer/web_uploads =================================================================== --- adaptive_lms_equalizer/web_uploads (nonexistent) +++ adaptive_lms_equalizer/web_uploads (revision 4)

adaptive_lms_equalizer/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: adaptive_lms_equalizer/branches =================================================================== --- adaptive_lms_equalizer/branches (nonexistent) +++ adaptive_lms_equalizer/branches (revision 4)

adaptive_lms_equalizer/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: adaptive_lms_equalizer/tags/V10/code/add16.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/add16.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/add16.vhd (revision 4) @@ -0,0 +1,36 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- 16 bit adder + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + +entity add16 is + Port ( d1_in : in std_logic_vector(15 downto 0); + d2_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0)); +end add16; + +architecture Behavioral of add16 is + +begin + d_out <= d1_in + d2_in; + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/bin_to_7seg.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/bin_to_7seg.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/bin_to_7seg.vhd (revision 4) @@ -0,0 +1,56 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- seven segment display mapping from 8 bit no + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity bin_to_7seg is + Port ( din : in std_logic_vector(3 downto 0); + dis_out : out std_logic_vector(7 downto 0)); +end bin_to_7seg; + +architecture Behavioral of bin_to_7seg is + +begin + + +dis_out <= "00000010" when din = "0000" else + "10011110" when din = "0001" else + "00100100" when din = "0010" else + "00001100" when din = "0011" else + "10011000" when din = "0100" else + "01001000" when din = "0101" else + "01000000" when din = "0110" else + "00011110" when din = "0111" else + "00000000" when din = "1000" else + "00011000" when din = "1001" else + "00010000" when din = "1010" else + "11000000" when din = "1011" else + "01100010" when din = "1100" else + "10000100" when din = "1101" else + "01100000" when din = "1110" else + "01110000"; + + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/unit_calc.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/unit_calc.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/unit_calc.vhd (revision 4) @@ -0,0 +1,169 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- A.8 +-- unit program module of filter core +-- we have to cascade instance of this module to make multi tap filter + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + +entity unit_calc is + Port ( x_in : in std_logic_vector(7 downto 0); + x_N_in : in std_logic_vector(7 downto 0); + ue_in : in std_logic_vector(7 downto 0); + y_in : in std_logic_vector(7 downto 0); + x_out : out std_logic_vector(7 downto 0); + x_N_out : out std_logic_vector(7 downto 0); + ue_out : out std_logic_vector(7 downto 0); + y_out: out std_logic_vector(7 downto 0); + clock : in std_logic); + +end unit_calc; + +architecture standard of unit_calc is + -- component declarations + -- 8 bit multiplier + component mul8 + Port ( d1_in : in std_logic_vector(7 downto 0); + d2_in : in std_logic_vector(7 downto 0); + d_out : out std_logic_vector(15 downto 0)); + + end component; + -- 16 bit adder + component add16 + Port ( d1_in : in std_logic_vector(15 downto 0); + d2_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0)); + + end component; + + -- saturation circuit + component saturation + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0)); + end component; + + -- u scaling circuit + component u_scaling + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0); + clock : in std_logic); + end component; + + -- truncation circuit + component truncation + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(7 downto 0)); + end component; + -- one sample delay + component shift_1d + Port ( xin : in std_logic_vector(7 downto 0); + xout : out std_logic_vector(7 downto 0); + clock : in std_logic); + end component; + + -- shift regester + component shift_1d_16 + Port ( xin : in std_logic_vector(15 downto 0); + xout : out std_logic_vector(15 downto 0); + clock : in std_logic); + end component; + + + signal shiftx: std_logic_vector(31 downto 0); + signal shiftxn: std_logic_vector(31 downto 0); + signal shiftue: std_logic_vector(23 downto 0); + signal shifty: std_logic_vector(15 downto 0); + + signal coeff8: std_logic_vector(7 downto 0); + signal coeff16:std_logic_vector(15 downto 0); + signal xnin_ue:std_logic_vector(15 downto 0); + signal xnin_ue_scaled:std_logic_vector(15 downto 0); + signal new_coeff_true:std_logic_vector(15 downto 0); + signal delayed_new_coeff_true:std_logic_vector(15 downto 0); + signal y_out16:std_logic_vector(15 downto 0); + signal y_out8:std_logic_vector(7 downto 0); +begin + -- basic pipelining + unit_process: + process (clock) + begin + if(clock'event and clock = '1') then + + shiftx <= x_in & shiftx(31 downto 8); + shiftxn <= x_N_in & shiftxn(31 downto 8); + shiftue <= ue_in & shiftue(23 downto 8); + shifty <= y_in & shifty(15 downto 8); + + end if; + end process; + + x_out <= shiftx(7 downto 0); + x_N_out <= shiftxn(7 downto 0); + ue_out <= shiftue(7 downto 0); + + mul_xnin_ue: mul8 -- no delay + port map( d1_in => x_N_in, + d2_in => ue_in, + d_out => xnin_ue); + + u1:u_scaling -- 1 clock cycle + port map( d_in => xnin_ue, + d_out => xnin_ue_scaled, + clock => clock + ); + + add1:add16 -- no delay + port map( d1_in => xnin_ue_scaled, + d2_in => coeff16, + d_out => new_coeff_true + ); + + delay_2:shift_1d_16 -- each clock + port map( clock => clock, + xin => new_coeff_true, + xout => delayed_new_coeff_true + ); + + + sat_1:saturation + port map( d_in => delayed_new_coeff_true, + d_out => coeff16 + ); + trunc_1:truncation + port map( + d_in => coeff16, + d_out => coeff8 + ); + + mul_coeff_x_in:mul8 + port map( d1_in => coeff8, + d2_in => shiftx(31 downto 24), + d_out => y_out16 + ); + trunc_2:truncation + port map( + d_in => y_out16, + d_out => y_out8 + ); + y_out <= y_out8 + shifty(7 downto 0); +end standard; + Index: adaptive_lms_equalizer/tags/V10/code/test_data_gen.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/test_data_gen.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/test_data_gen.vhd (revision 4) @@ -0,0 +1,85 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- VHDL Test Bench Created from source file data_gen.vhd -- 09:38:13 03/25/2005 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT data_gen + PORT( + clock : IN std_logic; + reset : IN std_logic; + xout : OUT std_logic_vector(7 downto 0); + dxout : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + SIGNAL clock : std_logic; + SIGNAL reset : std_logic; + SIGNAL xout : std_logic_vector(7 downto 0); + SIGNAL dxout : std_logic_vector(7 downto 0); + + CONSTANT clk_high : time := 10 ns; + CONSTANT clk_low : time := 10 ns; + CONSTANT clk_period : time := 20 ns; + CONSTANT clk_hold : time := 4 ns; + + +BEGIN + + uut: data_gen PORT MAP( + clock => clock, + reset => reset, + xout => xout, + dxout => dxout + ); + + +-- *** Test Bench - User Defined Section *** + clk_gen: PROCESS + BEGIN + clock <= '1'; + WAIT FOR clk_high; + clock <= '0'; + WAIT FOR clk_low; + + END PROCESS clk_gen; + + reset_gen: process + begin + reset <= '1'; + wait for clk_period*5; + reset <= '0'; + + wait; + end process reset_gen; +-- *** End Test Bench - User Defined Section *** + +END; Index: adaptive_lms_equalizer/tags/V10/code/filt_test_system.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/filt_test_system.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/filt_test_system.vhd (revision 4) @@ -0,0 +1,173 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- This File is Testing System For Equalizer +-- It Includes DATA generator Equalizer core and Error Display unit + +-- File: Filt_test_system.vhd +-- Developer: Digish K. Pandya +-- Test bench file test_filt_test_sys.vhd + +-- Main Testing system for LMS adaptive filter +-- Synthesised and tested on SPARTAN II xc2s100-6qt144 + +--Libraries from vendor +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + +-- Pin Definations +entity filt_test_system is + Port ( clock : in std_logic; + error_led_out : out std_logic_vector(7 downto 0); + seg_select:out std_logic_vector(3 downto 0); + error_freq_out : out std_logic; + filt_data_out : out std_logic_vector(7 downto 0); + reset : in std_logic; + reset_clk : in std_logic; + adaption_enable : in std_logic); +end filt_test_system; + +-- Architecture body + +architecture test_chip of filt_test_system is + + -- Component Declarations + + -- 1 LMS filter Transpose form Architecture + component tf_lms + Port ( + xin : in std_logic_vector(7 downto 0); -- data input + dxin : in std_logic_vector(7 downto 0); -- desired response input + clock : in std_logic; -- clock + adapt_en: in std_logic; -- enable adaption + + err:out std_logic_vector(7 downto 0); -- error output + yout : out std_logic_vector(7 downto 0) -- output data + ); + end component ; + + -- 2 Data generator system + component data_gen + Port ( + clock : in std_logic; + reset : in std_logic; + + xout : out std_logic_vector(7 downto 0); + dxout : out std_logic_vector(7 downto 0) + ); + end component ; + + -- 3 Clock devider + -- Provides two clocks for different purpose + component clock_div + Port ( reset: in std_logic; + in_clk : in std_logic; + + out1 : out std_logic; -- fast + out2 : out std_logic); -- slow + end component; + + -- 4 Displays MSE on seven segment diplay + component Display_MSE + Port ( reset: in std_logic; + error_in : in std_logic_vector(7 downto 0); + clock : in std_logic; + + an_out: out std_logic; + seg_select_out : out std_logic_vector(3 downto 0); + seg_dis_out : out std_logic_vector(7 downto 0)); + end component; + + -- global clock buffer primary (for input pin) + -- [Not able to display linkage but available in RTL] + component BUFGP + port (I: in std_logic; O: out std_logic); + end component; + -- clock buffer Secondary (for internal logic) + -- [Not able to display linkage but available in RTL] + component BUFGS + port (I: in STD_LOGIC;O: out STD_LOGIC); + end component; + + + -- Local Interconnects + signal xout_tmp: std_logic_vector( 7 downto 0); + signal dxout_tmp: std_logic_vector( 7 downto 0); + signal clock_fast,clock_slow: std_logic; + signal error_dis_in : std_logic_vector(7 downto 0); + signal CLK_SIG,clock_f,clock_s: std_logic; + +begin + -- Clock Input through buffer + U1: BUFGP port map (I => clock, O => CLK_SIG); + + -- Test DATA generator + data_gen1: data_gen + port map( + + clock => clock_slow, + reset => reset, + xout => xout_tmp, + dxout => dxout_tmp + ); + + -- LMS core UNDER test + lms: tf_lms + Port map( + xin => xout_tmp, + dxin => dxout_tmp, + clock => clock_slow, + err => error_dis_in, + yout => filt_data_out, + adapt_en => adaption_enable + ); + + + -- Fast clock used to avoide flicker + err_display:display_mse + port map( + reset => reset, + error_in => error_dis_in, + clock => clock_fast, + + an_out => error_freq_out, + seg_select_out => seg_select, + seg_dis_out => error_led_out + + ); + + + -- Clock Devider + cd: clock_div + port map( + reset => reset_clk, + in_clk => clk_sig, + out1 => clock_f, + out2 => clock_s + ); + + -- Fast clock for Seven Segment Display refresh + U2: BUFGS port map (I => clock_f, O => clock_fast); + + -- Slow clock for Filtering (SO we can see changes in on Sevensegment) + -- In actual application we have to keep maximum possible clock here + U3: BUFGS port map (I => clock_s, O => clock_slow); + + +end test_chip; +-- The End -- \ No newline at end of file Index: adaptive_lms_equalizer/tags/V10/code/data_gen.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/data_gen.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/data_gen.vhd (revision 4) @@ -0,0 +1,76 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- A.3 data_gen.vhd +-- datagenerator system for generating test data feed to lms filter +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity data_gen is + Port ( clock : in std_logic; + reset : in std_logic; + xout : out std_logic_vector(7 downto 0); + dxout : out std_logic_vector(7 downto 0)); +end data_gen; + +architecture structural of data_gen is + -- training sequence generator + component tr_seq_gen + Port ( clock : in std_logic; + reset : in std_logic; + data_out : out std_logic_vector(7 downto 0) + ); + end component; + -- channel filter + component const_ch_filt + Port ( + clock : in std_logic; + data_in : in std_logic_vector(7 downto 0); + shifted_data_out : out std_logic_vector(7 downto 0); + filtered_data_out : out std_logic_vector(7 downto 0) + ); + end component; + + signal data : std_logic_vector (7 downto 0); + +begin + -- Test Data generator + data_generator: + process(clock,reset) + begin + if(clock'event and clock = '1') then + if (data = "01000000") then + data <= "11000000"; + else + data <= "01000000"; + end if; + end if; + if(reset = '0') then + data <= "01000000"; + end if; + + end process; + -- This Channel Filter will convolve our input Signal + channel: const_ch_filt + port map ( + clock => clock, + data_in => data, + shifted_data_out => dxout, + filtered_data_out => xout + ); + +end structural; Index: adaptive_lms_equalizer/tags/V10/code/u_scaling.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/u_scaling.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/u_scaling.vhd (revision 4) @@ -0,0 +1,44 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- A.10 +-- multiply by 0.0625 +-- only simple shift logic is applied + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + +entity u_scaling is + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0); + clock : in std_logic); +end u_scaling; + +architecture combinational of u_scaling is +signal sign_bit:std_logic_vector(4 downto 0); +begin + p1: + process(clock) + begin + + if(clock'event and clock = '1') then + d_out <= d_in(15) & d_in(15) & d_in(15) & d_in(15) & d_in(15) & d_in(14 downto 4); + end if; + end process; +end combinational; Index: adaptive_lms_equalizer/tags/V10/code/d_to_a_1bit.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/d_to_a_1bit.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/d_to_a_1bit.vhd (revision 4) @@ -0,0 +1,50 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- simple one bit analog output +-- is outputting frequency in responce to count no +-- so it repressent amount of error with frequency + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity d_a is + port ( + clk : in std_logic; + data_in : in std_logic_vector (15 downto 0); + an_out : out std_logic; + reset: in std_logic + ); +end d_a; + +architecture d_a_arch of d_a is + signal d_a_Accumulator : std_logic_vector(8 downto 0); +begin + process(clk) + begin + if (clk'event and clk = '1') then + if (reset = '0') then + d_a_Accumulator <= "000000000"; + else + d_a_Accumulator <= ("0" & d_a_Accumulator(7 downto 0)) + ("0" & data_in(7 downto 0)); + end if; + end if; + end process; + + an_out <= d_a_Accumulator(8); +end d_a_arch; + Index: adaptive_lms_equalizer/tags/V10/code/core_filt.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/core_filt.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/core_filt.vhd (revision 4) @@ -0,0 +1,141 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- A.7 +-- Filter core for adaptive equalizer +-- Five tap filter +-- structuaral description + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity core_filt is + Port ( + x_in : in std_logic_vector(7 downto 0); + x_N_in : in std_logic_vector(7 downto 0); + ue_in : in std_logic_vector(7 downto 0); + clock : in std_logic; + y_out : out std_logic_vector(7 downto 0)); +end core_filt; + +architecture pm_chain of core_filt is + + -- basic tap processing element + component unit_calc + Port ( x_in : in std_logic_vector(7 downto 0); + x_N_in : in std_logic_vector(7 downto 0); + ue_in : in std_logic_vector(7 downto 0); + y_in : in std_logic_vector(7 downto 0); + x_out : out std_logic_vector(7 downto 0); + x_N_out : out std_logic_vector(7 downto 0); + ue_out : out std_logic_vector(7 downto 0); + y_out: out std_logic_vector(7 downto 0); + clock : in std_logic); + end component ; + + + signal x_out_t1 :std_logic_vector(7 downto 0); + signal x_out_t2 :std_logic_vector(7 downto 0); + signal x_out_t3 :std_logic_vector(7 downto 0); + signal x_out_t4 :std_logic_vector(7 downto 0); + + signal x_N_out_t1 :std_logic_vector(7 downto 0); + signal x_N_out_t2 :std_logic_vector(7 downto 0); + signal x_N_out_t3 :std_logic_vector(7 downto 0); + signal x_N_out_t4 :std_logic_vector(7 downto 0); + + signal ue_out_t1 :std_logic_vector(7 downto 0); + signal ue_out_t2 :std_logic_vector(7 downto 0); + signal ue_out_t3 :std_logic_vector(7 downto 0); + signal ue_out_t4 :std_logic_vector(7 downto 0); + + signal y_out_t1 :std_logic_vector(7 downto 0); + signal y_out_t2 :std_logic_vector(7 downto 0); + signal y_out_t3 :std_logic_vector(7 downto 0); + signal y_out_t4 :std_logic_vector(7 downto 0); + + + +begin + + tap1: unit_calc + port map ( + x_in => x_in, + x_N_in => x_N_in, + ue_in => ue_in, + y_in => "00000000", + x_out => x_out_t1, + x_N_out => x_N_out_t1, + ue_out => ue_out_t1, + y_out => y_out_t1, + clock => clock + ); + tap2: unit_calc + port map ( + x_in => x_out_t1, + x_N_in => x_N_out_t1, + ue_in => ue_out_t1, + y_in => y_out_t1, + x_out => x_out_t2, + x_N_out => x_N_out_t2, + ue_out => ue_out_t2, + y_out => y_out_t2, + clock => clock + ); + tap3: unit_calc + port map ( + x_in => x_out_t2, + x_N_in => x_N_out_t2, + ue_in => ue_out_t2, + y_in => y_out_t2, + x_out => x_out_t3, + x_N_out => x_N_out_t3, + ue_out => ue_out_t3, + y_out => y_out_t3, + clock => clock + ); + tap4: unit_calc + port map ( + x_in => x_out_t3, + x_N_in => x_N_out_t3, + ue_in => ue_out_t3, + y_in => y_out_t3, + x_out => x_out_t4, + x_N_out => x_N_out_t4, + ue_out => ue_out_t4, + y_out => y_out_t4, + clock => clock + ); + tap5: unit_calc + port map ( + x_in => x_out_t4, + x_N_in => x_N_out_t4, + ue_in => ue_out_t4, + y_in => y_out_t4, + x_out => open, + x_N_out => open, + ue_out => open, + y_out => y_out, + clock => clock + ); + + + + +end pm_chain; Index: adaptive_lms_equalizer/tags/V10/code/shift_1d_16.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/shift_1d_16.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/shift_1d_16.vhd (revision 4) @@ -0,0 +1,47 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- 16 vit shift regester + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity shift_1d_16 is + Port ( xin : in std_logic_vector(15 downto 0); + xout : out std_logic_vector(15 downto 0); + clock : in std_logic); +end shift_1d_16; + +architecture Behavioral of shift_1d_16 is +signal shift_reg: std_logic_vector (15 downto 0); + +begin + shift: + process(clock) + begin + if(clock'event and clock = '1') then + + shift_reg <= xin ; + + end if; + end process; + xout <= shift_reg; + + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/Display_MSE.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/Display_MSE.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/Display_MSE.vhd (revision 4) @@ -0,0 +1,140 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- ******************--- +-- +-- To be used with LMS testing rutine +-- process Error signal for proper display +-- +-- ******************--- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + +-- Main BLOCK BODY +entity Display_MSE is + Port ( + reset: in std_logic; + error_in : in std_logic_vector(7 downto 0); + clock : in std_logic; + an_out: out std_logic; + seg_select_out : out std_logic_vector(3 downto 0); + seg_dis_out : out std_logic_vector(7 downto 0)); +end Display_MSE; + +-- Architecture +architecture mixed of Display_MSE is + +-- Components Used + + -- 1 Multiplexer For input to 7 segment module + component mux + Port ( in1 : in std_logic_vector(3 downto 0); + in2 : in std_logic_vector(3 downto 0); + in3 : in std_logic_vector(3 downto 0); + in4 : in std_logic_vector(3 downto 0); + sel : in std_logic_vector( 1 downto 0); + + o_ut : out std_logic_vector(3 downto 0)); + end component; + + -- 2 Binary to sevenseg Mapping module + component bin_to_7seg + Port ( din : in std_logic_vector(3 downto 0); + dis_out : out std_logic_vector(7 downto 0)); + end component; + + -- 3 Digital to analog output 1 bit (frequency) + component d_a + port ( + clk : in std_logic; + data_in : in std_logic_vector (15 downto 0); + reset:in std_logic; + + an_out : out std_logic + ); + end component; + + -- Local Interconnects + signal error_tmp: std_logic_vector( 15 downto 0); + signal error_led_out_tmp:std_logic_vector(7 downto 0); + signal seg_in: std_logic_vector( 3 downto 0); + signal seg_sel: std_logic_vector( 1 downto 0); + +begin + + -- FSM for Selcting 7 segment display (Multiplexed mode) + + mux_display_sel: + process (clock) + begin + if(clock'event and clock = '1') then + if reset = '0' then seg_sel <= "00"; + elsif seg_sel = "00" then seg_sel <= "01"; + elsif seg_sel = "01" then seg_sel <= "10"; + elsif seg_sel = "10" then seg_sel <= "11"; + elsif seg_sel = "11" then seg_sel <= "00"; + else seg_sel <= "ZZ"; + end if; + + end if; + end process; + + -- Selecting perticular segment for display + + seg_select_out <= "0ZZZ" when seg_sel = "00" else + "Z0ZZ" when seg_sel = "01" else + "ZZ0Z" when seg_sel = "10" else + "ZZZ0" when seg_sel = "11" else + "ZZZZ"; + + -- IT is Square of ERROR + error_tmp <= error_in * error_in; + + -- Converting Binary to Seven segment pattern + seven_seg:bin_to_7seg + Port map( + din => seg_in, + dis_out => error_led_out_tmp + ); + + -- Negative logic out + seg_dis_out <= not error_led_out_tmp; + + -- MULTIPLEXED DISPLAY thats why .. + m1:mux + port map(in1 => error_tmp(3 downto 0), + in2 => error_tmp(7 downto 4), + in3 => error_tmp(11 downto 8), + in4 => error_tmp(15 downto 12), + sel => seg_sel, -- Changing with fast clock + o_ut => seg_in + ); + + -- NUMBER to FREQ Generator (1 bit Analog) + d_to_a:d_a + port map( + clk => clock, + data_in => error_tmp, -- 16 bit + an_out => an_out, -- 1 bit + reset => reset + ); + +end mixed; +--************ END *******----- \ No newline at end of file Index: adaptive_lms_equalizer/tags/V10/code/Mux.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/Mux.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/Mux.vhd (revision 4) @@ -0,0 +1,43 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity Mux is + Port ( in1 : in std_logic_vector(3 downto 0); + in2 : in std_logic_vector(3 downto 0); + in3 : in std_logic_vector(3 downto 0); + in4 : in std_logic_vector(3 downto 0); + sel : in std_logic_vector(1 downto 0); + o_ut : out std_logic_vector(3 downto 0)); +end Mux; + +architecture Behavioral of Mux is + +begin + +o_ut <= in1 when sel = "00" else + in2 when sel = "01" else + in3 when sel = "10" else + in4 when sel = "11" else + "0000"; + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/ch_filt_tap.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/ch_filt_tap.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/ch_filt_tap.vhd (revision 4) @@ -0,0 +1,59 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- A.5 +-- simple logic for filter tap operation optimized for the fact that +-- that there are only two possible data at input + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + + +entity ch_filt_tap is + Port ( din : in std_logic_vector(7 downto 0); + dout : out std_logic_vector(7 downto 0); + c1_in : in std_logic_vector(7 downto 0); + c2_in : in std_logic_vector(7 downto 0); + add_in : in std_logic_vector(7 downto 0); + add_out : out std_logic_vector(7 downto 0); + clock : in std_logic); +end ch_filt_tap; + +architecture Behavioral of ch_filt_tap is + +signal mul_res:std_logic_vector(7 downto 0); + +begin + shift_process: + process (clock) + begin + if(clock'event and clock = '1') then + dout <= din; + end if; + end process; + + + with din select + mul_res <= c1_in when "11000000", -- -1 + c2_in when others; -- +1 + + add_out <= add_in + mul_res; + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/const_ch_filt.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/const_ch_filt.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/const_ch_filt.vhd (revision 4) @@ -0,0 +1,89 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- A.4 +-- channel filter with optimized for constant input data and +-- constant coefficients +-- coefficients are rounded to power of two + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity const_ch_filt is + Port ( clock : in std_logic; + data_in : in std_logic_vector(7 downto 0); + shifted_data_out : out std_logic_vector(7 downto 0); + filtered_data_out : out std_logic_vector(7 downto 0)); +end const_ch_filt; + +architecture structural of const_ch_filt is + + component ch_filt_tap + Port ( din : in std_logic_vector(7 downto 0); + dout : out std_logic_vector(7 downto 0); + c1_in : in std_logic_vector(7 downto 0); + c2_in : in std_logic_vector(7 downto 0); + add_in : in std_logic_vector(7 downto 0); + add_out : out std_logic_vector(7 downto 0); + clock : in std_logic); + end component; + + signal t_data_out1: std_logic_vector (7 downto 0); + signal t_data_out2: std_logic_vector (7 downto 0); + signal t_res_out1: std_logic_vector (7 downto 0); + signal t_res_out2: std_logic_vector (7 downto 0); + +begin + +tap1: ch_filt_tap -- -0.2031 + port map( + din => data_in, + dout => t_data_out1, + c1_in => "11110011", -- +1 + c2_in => "00001101", -- -1 + add_in => "00000000", + add_out => t_res_out1, + clock => clock + ); + +tap2: ch_filt_tap -- 0.4063 + port map( + din => t_data_out1, + dout => t_data_out2, + c1_in => "00011010", + c2_in => "11100110", + add_in => t_res_out1, + add_out => t_res_out2, + clock => clock + ); +tap3: ch_filt_tap -- -0.7969 + port map( + din => t_data_out2, + dout => shifted_data_out, + c1_in => "11001101", + c2_in => "00110011", + add_in => t_res_out2, + add_out => filtered_data_out, + clock => clock + ); + + + +end structural; Index: adaptive_lms_equalizer/tags/V10/code/data_gen_translate.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/data_gen_translate.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/data_gen_translate.vhd (revision 4) @@ -0,0 +1,828 @@ +-- Xilinx Vhdl produced by program ngd2vhdl F.28 +-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log data_gen.ngd data_gen_translate.vhd +-- Input file: data_gen.ngd +-- Output file: data_gen_translate.vhd +-- Design name: data_gen +-- Xilinx: E:/xilinx +-- # of Entities: 1 +-- Device: 2s100tq144-6 + +-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized, +-- or used in any other manner other than simulation. This netlist uses simulation +-- primitives which may not represent the true implementation of the device, however +-- the netlist is functionally correct. Do not modify this file. + +-- Model for ROC (Reset-On-Configuration) Cell +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +entity ROC is + generic (InstancePath: STRING := "*"; + WIDTH : Time := 100 ns); + port(O : out std_ulogic := '1') ; + attribute VITAL_LEVEL0 of ROC : entity is TRUE; +end ROC; + +architecture ROC_V of ROC is +attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE; +begin + ONE_SHOT : process + begin + if (WIDTH <= 0 ns) then + assert FALSE report + "*** Error: a positive value of WIDTH must be specified ***" + severity failure; + else + wait for WIDTH; + O <= '0'; + end if; + wait; + end process ONE_SHOT; +end ROC_V; + +-- Model for TOC (Tristate-On-Configuration) Cell +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +entity TOC is + generic (InstancePath: STRING := "*"; + WIDTH : Time := 0 ns); + port(O : out std_ulogic := '0'); + attribute VITAL_LEVEL0 of TOC : entity is TRUE; +end TOC; + +architecture TOC_V of TOC is +attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE; +begin + ONE_SHOT : process + begin + O <= '1'; + if (WIDTH <= 0 ns) then + O <= '0'; + else + wait for WIDTH; + O <= '0'; + end if; + wait; + end process ONE_SHOT; +end TOC_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; +entity data_gen is + port ( + reset : in STD_LOGIC := 'X'; + clock : in STD_LOGIC := 'X'; + dxout : out STD_LOGIC_VECTOR ( 7 downto 0 ); + xout : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); +end data_gen; + +architecture Structure of data_gen is + component ROC + generic (InstancePath: STRING := "*"; + WIDTH : Time := 100 ns); + port (O : out STD_ULOGIC := '1'); + end component; + component TOC + generic (InstancePath: STRING := "*"; + WIDTH : Time := 0 ns); + port (O : out STD_ULOGIC := '1'); + end component; + signal data_0_Q : STD_LOGIC; + signal reset_ibuf : STD_LOGIC; + signal clock_bufgp : STD_LOGIC; + signal Q_n0003 : STD_LOGIC; + signal xout_1_obuf : STD_LOGIC; + signal n2175 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_5 : STD_LOGIC; + signal xout_2_obuf : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_4 : STD_LOGIC; + signal data_7_Q : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_3 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_3 : STD_LOGIC; + signal channel_tap1_madd_add_out_inst_cy_6 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_5 : STD_LOGIC; + signal xout_7_obuf : STD_LOGIC; + signal xout_6_obuf : STD_LOGIC; + signal xout_5_obuf : STD_LOGIC; + signal xout_4_obuf : STD_LOGIC; + signal xout_3_obuf : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_3 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_1 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_6 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_7 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_6 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_1 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_4 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_3 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_1 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_5 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_2 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_lut2_2 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_1 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_2 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_2 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_6 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_5 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_cy_6 : STD_LOGIC; + signal channel_tap2_madd_add_out_inst_cy_4 : STD_LOGIC; + signal channel_tap3_madd_add_out_inst_lut2_4 : STD_LOGIC; + signal Q_n0003_O : STD_LOGIC; + signal clock_bufgp_IBUFG : STD_LOGIC; + signal GSR : STD_LOGIC; + signal dxout_7_obuf_GTS_TRI : STD_LOGIC; + signal GTS : STD_LOGIC; + signal dxout_6_obuf_GTS_TRI : STD_LOGIC; + signal dxout_5_obuf_GTS_TRI : STD_LOGIC; + signal dxout_4_obuf_GTS_TRI : STD_LOGIC; + signal dxout_3_obuf_GTS_TRI : STD_LOGIC; + signal dxout_2_obuf_GTS_TRI : STD_LOGIC; + signal dxout_1_obuf_GTS_TRI : STD_LOGIC; + signal dxout_0_obuf_GTS_TRI : STD_LOGIC; + signal xout_7_obuf_GTS_TRI : STD_LOGIC; + signal xout_6_obuf_GTS_TRI : STD_LOGIC; + signal xout_5_obuf_GTS_TRI : STD_LOGIC; + signal xout_4_obuf_GTS_TRI : STD_LOGIC; + signal xout_3_obuf_GTS_TRI : STD_LOGIC; + signal xout_2_obuf_GTS_TRI : STD_LOGIC; + signal xout_1_obuf_GTS_TRI : STD_LOGIC; + signal xout_0_obuf_GTS_TRI : STD_LOGIC; + signal VCC : STD_LOGIC; + signal GND : STD_LOGIC; + signal NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL : STD_LOGIC; + signal channel_tap3_dout : STD_LOGIC_VECTOR ( 7 downto 7 ); + signal channel_tap1_dout : STD_LOGIC_VECTOR ( 7 downto 7 ); + signal channel_t_res_out2 : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal channel_tap2_mul_res : STD_LOGIC_VECTOR ( 2 downto 2 ); + signal channel_tap3_mul_res : STD_LOGIC_VECTOR ( 5 downto 5 ); + signal channel_tap2_dout : STD_LOGIC_VECTOR ( 7 downto 7 ); +begin + channel_tap2_madd_add_out_inst_lut2_511 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap2_mul_res(2), + ADR1 => data_7_Q, + O => n2175 + ); + channel_tap3_madd_add_out_inst_sum_1 : X_XOR2 + port map ( + I0 => data_0_Q, + I1 => channel_tap3_madd_add_out_inst_lut2_1, + O => xout_1_obuf + ); + channel_tap2_madd_add_out_inst_lut2_41 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap1_dout(7), + ADR1 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_4 + ); + channel_tap3_madd_add_out_inst_sum_6 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_5, + I1 => channel_tap3_madd_add_out_inst_lut2_6, + O => xout_6_obuf + ); + data_7 : X_SFF + port map ( + I => Q_n0003, + SRST => reset_ibuf, + CLK => clock_bufgp, + O => data_7_Q, + CE => VCC, + SET => GND, + RST => GSR, + SSET => GND + ); + xout_0_obuf : X_BUF + port map ( + I => channel_tap1_madd_add_out_inst_cy_6, + O => xout_0_obuf_GTS_TRI + ); + channel_tap2_madd_add_out_inst_sum_6 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_5, + I1 => channel_tap2_madd_add_out_inst_lut2_6, + O => channel_t_res_out2(6) + ); + dxout_0_obuf : X_BUF + port map ( + I => data_0_Q, + O => dxout_0_obuf_GTS_TRI + ); + channel_tap3_madd_add_out_inst_lut2_21 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_t_res_out2(2), + ADR1 => channel_tap2_dout(7), + O => channel_tap3_madd_add_out_inst_lut2_2 + ); + channel_tap2_madd_add_out_inst_cy_1_0 : X_MUX2 + port map ( + IA => data_0_Q, + IB => channel_tap1_madd_add_out_inst_cy_6, + SEL => channel_tap2_madd_add_out_inst_lut2_1, + O => channel_tap2_madd_add_out_inst_cy_1 + ); + channel_tap2_madd_add_out_inst_lut2_111 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_1, + ADR1 => GND + ); + xst_vcc : X_ONE + port map ( + O => data_0_Q + ); + xst_gnd : X_ZERO + port map ( + O => channel_tap1_madd_add_out_inst_cy_6 + ); + channel_tap3_madd_add_out_inst_cy_6_1 : X_MUX2 + port map ( + IA => channel_t_res_out2(6), + IB => channel_tap3_madd_add_out_inst_cy_5, + SEL => channel_tap3_madd_add_out_inst_lut2_6, + O => channel_tap3_madd_add_out_inst_cy_6 + ); + channel_tap2_madd_add_out_inst_cy_6_2 : X_MUX2 + port map ( + IA => channel_tap2_mul_res(2), + IB => channel_tap2_madd_add_out_inst_cy_5, + SEL => channel_tap2_madd_add_out_inst_lut2_6, + O => channel_tap2_madd_add_out_inst_cy_6 + ); + channel_tap3_madd_add_out_inst_lut2_61 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_t_res_out2(6), + ADR1 => channel_tap2_dout(7), + O => channel_tap3_madd_add_out_inst_lut2_6 + ); + channel_tap2_madd_add_out_inst_lut2_31 : X_LUT2 + generic map( + INIT => X"9" + ) + port map ( + ADR0 => channel_tap1_dout(7), + ADR1 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_3 + ); + channel_tap3_madd_add_out_inst_lut2_71 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap2_dout(7), + ADR1 => channel_t_res_out2(7), + O => channel_tap3_madd_add_out_inst_lut2_7 + ); + channel_tap3_madd_add_out_inst_sum_5 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_4, + I1 => channel_tap3_madd_add_out_inst_lut2_5, + O => xout_5_obuf + ); + channel_tap3_dout_7 : X_FF + port map ( + I => channel_tap2_dout(7), + CLK => clock_bufgp, + O => channel_tap3_dout(7), + CE => VCC, + SET => GND, + RST => GSR + ); + channel_tap2_madd_add_out_inst_cy_5_3 : X_MUX2 + port map ( + IA => channel_tap2_mul_res(2), + IB => channel_tap2_madd_add_out_inst_cy_4, + SEL => n2175, + O => channel_tap2_madd_add_out_inst_cy_5 + ); + dxout_5_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_5_obuf_GTS_TRI + ); + xout_7_obuf_4 : X_BUF + port map ( + I => xout_7_obuf, + O => xout_7_obuf_GTS_TRI + ); + xout_1_obuf_5 : X_BUF + port map ( + I => xout_1_obuf, + O => xout_1_obuf_GTS_TRI + ); + dxout_4_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_4_obuf_GTS_TRI + ); + reset_ibuf_6 : X_BUF + port map ( + I => reset, + O => reset_ibuf + ); + xout_5_obuf_7 : X_BUF + port map ( + I => xout_5_obuf, + O => xout_5_obuf_GTS_TRI + ); + channel_tap2_madd_add_out_inst_lut2_51 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap2_mul_res(2), + ADR1 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_5 + ); + channel_tap3_madd_add_out_inst_cy_5_8 : X_MUX2 + port map ( + IA => channel_t_res_out2(5), + IB => channel_tap3_madd_add_out_inst_cy_4, + SEL => channel_tap3_madd_add_out_inst_lut2_5, + O => channel_tap3_madd_add_out_inst_cy_5 + ); + channel_tap3_madd_add_out_inst_lut2_41 : X_LUT2 + generic map( + INIT => X"9" + ) + port map ( + ADR0 => channel_t_res_out2(4), + ADR1 => channel_tap2_dout(7), + O => channel_tap3_madd_add_out_inst_lut2_4 + ); + channel_tap3_madd_add_out_inst_cy_1_9 : X_MUX2 + port map ( + IA => channel_tap3_mul_res(5), + IB => data_0_Q, + SEL => channel_tap3_madd_add_out_inst_lut2_1, + O => channel_tap3_madd_add_out_inst_cy_1 + ); + channel_tap3_mmux_mul_res_i2_result1 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => channel_tap2_dout(7), + O => channel_tap3_mul_res(5), + ADR1 => GND + ); + channel_tap2_madd_add_out_inst_sum_4 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_3, + I1 => channel_tap2_madd_add_out_inst_lut2_4, + O => channel_t_res_out2(4) + ); + channel_tap2_madd_add_out_inst_cy_2_10 : X_MUX2 + port map ( + IA => channel_tap2_mul_res(2), + IB => channel_tap2_madd_add_out_inst_cy_1, + SEL => channel_tap2_madd_add_out_inst_lut2_2, + O => channel_tap2_madd_add_out_inst_cy_2 + ); + channel_tap2_madd_add_out_inst_cy_3_11 : X_MUX2 + port map ( + IA => channel_tap1_dout(7), + IB => channel_tap2_madd_add_out_inst_cy_2, + SEL => channel_tap2_madd_add_out_inst_lut2_3, + O => channel_tap2_madd_add_out_inst_cy_3 + ); + channel_tap2_dout_7 : X_FF + port map ( + I => channel_tap1_dout(7), + CLK => clock_bufgp, + O => channel_tap2_dout(7), + CE => VCC, + SET => GND, + RST => GSR + ); + channel_tap2_madd_add_out_inst_sum_5 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_4, + I1 => n2175, + O => channel_t_res_out2(5) + ); + dxout_6_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_6_obuf_GTS_TRI + ); + dxout_3_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_3_obuf_GTS_TRI + ); + dxout_2_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_2_obuf_GTS_TRI + ); + xout_3_obuf_12 : X_BUF + port map ( + I => xout_3_obuf, + O => xout_3_obuf_GTS_TRI + ); + channel_tap3_madd_add_out_inst_sum_2 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_1, + I1 => channel_tap3_madd_add_out_inst_lut2_2, + O => xout_2_obuf + ); + channel_tap3_madd_add_out_inst_cy_2_13 : X_MUX2 + port map ( + IA => channel_t_res_out2(2), + IB => channel_tap3_madd_add_out_inst_cy_1, + SEL => channel_tap3_madd_add_out_inst_lut2_2, + O => channel_tap3_madd_add_out_inst_cy_2 + ); + channel_tap3_madd_add_out_inst_sum_4 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_3, + I1 => channel_tap3_madd_add_out_inst_lut2_4, + O => xout_4_obuf + ); + channel_tap2_madd_add_out_inst_lut2_21 : X_LUT2 + generic map( + INIT => X"9" + ) + port map ( + ADR0 => channel_tap2_mul_res(2), + ADR1 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_2 + ); + channel_tap2_mmux_mul_res_i5_result1 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => channel_tap1_dout(7), + O => channel_tap2_mul_res(2), + ADR1 => GND + ); + channel_tap3_madd_add_out_inst_cy_4_14 : X_MUX2 + port map ( + IA => channel_t_res_out2(4), + IB => channel_tap3_madd_add_out_inst_cy_3, + SEL => channel_tap3_madd_add_out_inst_lut2_4, + O => channel_tap3_madd_add_out_inst_cy_4 + ); + channel_tap3_madd_add_out_inst_lut2_31 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_t_res_out2(3), + ADR1 => channel_tap2_dout(7), + O => channel_tap3_madd_add_out_inst_lut2_3 + ); + channel_tap2_madd_add_out_inst_sum_3 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_2, + I1 => channel_tap2_madd_add_out_inst_lut2_3, + O => channel_t_res_out2(3) + ); + channel_tap3_madd_add_out_inst_lut2_51 : X_LUT2 + generic map( + INIT => X"9" + ) + port map ( + ADR0 => channel_t_res_out2(5), + ADR1 => channel_tap2_dout(7), + O => channel_tap3_madd_add_out_inst_lut2_5 + ); + xout_6_obuf_15 : X_BUF + port map ( + I => xout_6_obuf, + O => xout_6_obuf_GTS_TRI + ); + channel_tap3_madd_add_out_inst_sum_3 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_2, + I1 => channel_tap3_madd_add_out_inst_lut2_3, + O => xout_3_obuf + ); + channel_tap1_dout_7 : X_FF + port map ( + I => data_7_Q, + CLK => clock_bufgp, + O => channel_tap1_dout(7), + CE => VCC, + SET => GND, + RST => GSR + ); + channel_tap2_madd_add_out_inst_lut2_61 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap2_mul_res(2), + ADR1 => data_7_Q, + O => channel_tap2_madd_add_out_inst_lut2_6 + ); + dxout_7_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_7_obuf_GTS_TRI + ); + xout_2_obuf_16 : X_BUF + port map ( + I => xout_2_obuf, + O => xout_2_obuf_GTS_TRI + ); + xout_4_obuf_17 : X_BUF + port map ( + I => xout_4_obuf, + O => xout_4_obuf_GTS_TRI + ); + channel_tap2_madd_add_out_inst_sum_7 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_6, + I1 => channel_tap2_madd_add_out_inst_lut2_5, + O => channel_t_res_out2(7) + ); + channel_tap2_madd_add_out_inst_cy_4_18 : X_MUX2 + port map ( + IA => channel_tap1_dout(7), + IB => channel_tap2_madd_add_out_inst_cy_3, + SEL => channel_tap2_madd_add_out_inst_lut2_4, + O => channel_tap2_madd_add_out_inst_cy_4 + ); + channel_tap2_madd_add_out_inst_sum_2 : X_XOR2 + port map ( + I0 => channel_tap2_madd_add_out_inst_cy_1, + I1 => channel_tap2_madd_add_out_inst_lut2_2, + O => channel_t_res_out2(2) + ); + channel_tap3_madd_add_out_inst_cy_3_19 : X_MUX2 + port map ( + IA => channel_t_res_out2(3), + IB => channel_tap3_madd_add_out_inst_cy_2, + SEL => channel_tap3_madd_add_out_inst_lut2_3, + O => channel_tap3_madd_add_out_inst_cy_3 + ); + dxout_1_obuf : X_BUF + port map ( + I => channel_tap3_dout(7), + O => dxout_1_obuf_GTS_TRI + ); + channel_tap3_madd_add_out_inst_sum_7 : X_XOR2 + port map ( + I0 => channel_tap3_madd_add_out_inst_cy_6, + I1 => channel_tap3_madd_add_out_inst_lut2_7, + O => xout_7_obuf + ); + channel_tap3_madd_add_out_inst_lut2_11 : X_LUT2 + generic map( + INIT => X"6" + ) + port map ( + ADR0 => channel_tap2_dout(7), + ADR1 => data_7_Q, + O => channel_tap3_madd_add_out_inst_lut2_1 + ); + Q_n0003_22 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => data_7_Q, + ADR1 => GND, + O => Q_n0003_O + ); + Q_n0003_LUT1_L_BUF : X_BUF + port map ( + I => Q_n0003_O, + O => Q_n0003 + ); + clock_bufgp_IBUFG_23 : X_CKBUF + port map ( + I => clock, + O => clock_bufgp_IBUFG + ); + clock_bufgp_BUFG : X_CKBUF + port map ( + I => clock_bufgp_IBUFG, + O => clock_bufgp + ); + dxout_7_obuf_GTS_TRI_24 : X_TRI + port map ( + I => dxout_7_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL, + O => dxout(7) + ); + dxout_6_obuf_GTS_TRI_25 : X_TRI + port map ( + I => dxout_6_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL, + O => dxout(6) + ); + dxout_5_obuf_GTS_TRI_26 : X_TRI + port map ( + I => dxout_5_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL, + O => dxout(5) + ); + dxout_4_obuf_GTS_TRI_27 : X_TRI + port map ( + I => dxout_4_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL, + O => dxout(4) + ); + dxout_3_obuf_GTS_TRI_28 : X_TRI + port map ( + I => dxout_3_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL, + O => dxout(3) + ); + dxout_2_obuf_GTS_TRI_29 : X_TRI + port map ( + I => dxout_2_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL, + O => dxout(2) + ); + dxout_1_obuf_GTS_TRI_30 : X_TRI + port map ( + I => dxout_1_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL, + O => dxout(1) + ); + dxout_0_obuf_GTS_TRI_31 : X_TRI + port map ( + I => dxout_0_obuf_GTS_TRI, + CTL => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL, + O => dxout(0) + ); + xout_7_obuf_GTS_TRI_32 : X_TRI + port map ( + I => xout_7_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL, + O => xout(7) + ); + xout_6_obuf_GTS_TRI_33 : X_TRI + port map ( + I => xout_6_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL, + O => xout(6) + ); + xout_5_obuf_GTS_TRI_34 : X_TRI + port map ( + I => xout_5_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL, + O => xout(5) + ); + xout_4_obuf_GTS_TRI_35 : X_TRI + port map ( + I => xout_4_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL, + O => xout(4) + ); + xout_3_obuf_GTS_TRI_36 : X_TRI + port map ( + I => xout_3_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL, + O => xout(3) + ); + xout_2_obuf_GTS_TRI_37 : X_TRI + port map ( + I => xout_2_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL, + O => xout(2) + ); + xout_1_obuf_GTS_TRI_38 : X_TRI + port map ( + I => xout_1_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL, + O => xout(1) + ); + xout_0_obuf_GTS_TRI_39 : X_TRI + port map ( + I => xout_0_obuf_GTS_TRI, + CTL => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL, + O => xout(0) + ); + NlwBlock_data_gen_VCC : X_ONE + port map ( + O => VCC + ); + NlwBlock_data_gen_GND : X_ZERO + port map ( + O => GND + ); + NlwInverterBlock_dxout_7_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_6_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_5_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_4_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_3_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_2_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_1_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_dxout_0_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_7_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_6_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_5_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_4_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_3_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_2_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_1_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL + ); + NlwInverterBlock_xout_0_obuf_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL + ); + NlwBlockROC : ROC generic map ( WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : TOC port map (O => GTS); +end Structure; + Index: adaptive_lms_equalizer/tags/V10/code/tf_lms.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/tf_lms.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/tf_lms.vhd (revision 4) @@ -0,0 +1,101 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- A.6 tf_lms.vhd +-- Adaptive equalizer routine +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + +entity tf_lms is + Port ( + xin : in std_logic_vector(7 downto 0); -- data input + dxin : in std_logic_vector(7 downto 0); -- desired response input + clock : in std_logic; -- clock + err:out std_logic_vector(7 downto 0); -- error output + yout : out std_logic_vector(7 downto 0); -- output data + adapt_en: in std_logic -- enable adaption + ); +end tf_lms; + +architecture structural of tf_lms is + + -- filter core + component core_filt + Port ( + x_in : in std_logic_vector(7 downto 0); + x_N_in : in std_logic_vector(7 downto 0); + ue_in : in std_logic_vector(7 downto 0); + clock : in std_logic; + y_out : out std_logic_vector(7 downto 0)); + end component ; + + -- shift regesters + component shift_21d + Port ( xin : in std_logic_vector(7 downto 0); + x_N_out : out std_logic_vector(7 downto 0); + x_1_out : out std_logic_vector(7 downto 0); + clock : in std_logic); + end component; + + component shift_20d + Port ( xin : in std_logic_vector(7 downto 0); + xout : out std_logic_vector(7 downto 0); + clock : in std_logic); + end component; + + signal e,e_t,y_o,x_1,x_N:std_logic_vector(7 downto 0); + +begin + + -- if Adaption is not enabled then ERROR signal is ZERO + with adapt_en select + e <= y_o - e_t when '1', + "00000000" when others; + + err <= e; + + shift_1:shift_20d + port map ( + xin => dxin, + xout => e_t, + clock => clock + ); + + shift_2:shift_21d + port map ( + xin => xin, + x_N_out =>x_N, + x_1_out =>x_1, + clock => clock + ); + + cflt: core_filt + port map ( + x_in => x_1, + x_N_in => x_N, + ue_in => e, + y_out => y_o, + clock => clock + ); + + yout <= y_o; +end structural; Index: adaptive_lms_equalizer/tags/V10/code/mul8.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/mul8.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/mul8.vhd (revision 4) @@ -0,0 +1,36 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- 8 bit multi plier + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_SIGNED.ALL; + + +entity mul8 is + Port ( d1_in : in std_logic_vector(7 downto 0); + d2_in : in std_logic_vector(7 downto 0); + d_out : out std_logic_vector(15 downto 0)); +end mul8; + +architecture Behavioral of mul8 is + +begin + + d_out <= d1_in * d2_in; +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/shift_15d.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/shift_15d.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/shift_15d.vhd (revision 4) @@ -0,0 +1,47 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- producing delay of 20 unit + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity shift_20d is + Port ( xin : in std_logic_vector(7 downto 0); + xout : out std_logic_vector(7 downto 0); + clock : in std_logic); +end shift_20d; + +architecture Behavioral of shift_20d is +signal shift_reg: std_logic_vector (159 downto 0); +--signal shift_reg: std_logic_vector (119 downto 0); +begin + + shift: + process(clock) + begin + if(clock'event and clock = '1') then + + shift_reg <= xin & shift_reg(159 downto 8); + + end if; + end process; + xout <= shift_reg(7 downto 0); + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/tr_seq_gen.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/tr_seq_gen.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/tr_seq_gen.vhd (revision 4) @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tr_seq_gen is + Port ( clock : in std_logic; + reset : in std_logic; + data_out : out std_logic_vector(7 downto 0)); +end tr_seq_gen; + +architecture Behavioral of tr_seq_gen is + +begin + + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/truncation.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/truncation.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/truncation.vhd (revision 4) @@ -0,0 +1,36 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +-- simple 16 to 8 bit truncation circuit +-- it is only for fixed point(6,8) system +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity truncation is + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(7 downto 0)); +end truncation; + +architecture Behavioral of truncation is + +begin + + d_out <= d_in(13 downto 6); +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/shift_16d.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/shift_16d.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/shift_16d.vhd (revision 4) @@ -0,0 +1,48 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- delay of 21 and 1 unit + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity shift_21d is + Port ( xin : in std_logic_vector(7 downto 0); + x_N_out : out std_logic_vector(7 downto 0); + x_1_out : out std_logic_vector(7 downto 0); + clock : in std_logic); +end shift_21d; + +architecture Behavioral of shift_21d is +signal shift_reg: std_logic_vector (167 downto 0); +--signal shift_reg: std_logic_vector (127 downto 0); +begin + + shift: + process(clock) + begin + if(clock'event and clock = '1') then + + shift_reg <= xin & shift_reg(167 downto 8); + + end if; + end process; + x_N_out <= shift_reg(7 downto 0); + x_1_out <= shift_reg(167 downto 160); +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/saturation.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/saturation.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/saturation.vhd (revision 4) @@ -0,0 +1,45 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- A.9 saturation.vhd +-- saturation circuit +-- important for avoiding adverse effect of truncation + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity saturation is + Port ( d_in : in std_logic_vector(15 downto 0); + d_out : out std_logic_vector(15 downto 0)); +end saturation; + +architecture Behavioral of saturation is + signal sel:std_logic_vector(1 downto 0); +begin + + sel(1) <= not(d_in(12) xor d_in(13)xor d_in(14) xor d_in(15)); + sel(0) <= d_in(15); + + with sel select + d_out <= d_in when "11"|"10", + "0001000000000000" when "00", + "1111000000000000" when "01", + "0000000000000000" when others; + +end Behavioral; Index: adaptive_lms_equalizer/tags/V10/code/test_filt_test_sys.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/test_filt_test_sys.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/test_filt_test_sys.vhd (revision 4) @@ -0,0 +1,88 @@ + +-- VHDL Test Bench Created from source file filt_test_system.vhd -- 13:41:17 03/25/2005 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT filt_test_system + PORT( + clock : IN std_logic; + reset : IN std_logic; + adaption_enable : IN std_logic; + error_led_out : OUT std_logic_vector(7 downto 0); + seg_select : OUT std_logic_vector(3 downto 0); + error_freq_out : OUT std_logic; + reset_clk : in std_logic; + filt_data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + SIGNAL clock : std_logic; + SIGNAL error_led_out : std_logic_vector(7 downto 0); + SIGNAL seg_select : std_logic_vector(3 downto 0); + SIGNAL error_freq_out : std_logic; + SIGNAL filt_data_out : std_logic_vector(7 downto 0); + SIGNAL reset : std_logic; + signal reset_clk : std_logic; + SIGNAL adaption_enable : std_logic; + + CONSTANT clk_high : time := 10 ns; + CONSTANT clk_low : time := 10 ns; + CONSTANT clk_period : time := 20 ns; + CONSTANT clk_hold : time := 4 ns; + + + + +BEGIN + + uut: filt_test_system PORT MAP( + clock => clock, + error_led_out => error_led_out, + seg_select => seg_select, + error_freq_out => error_freq_out, + filt_data_out => filt_data_out, + reset => reset, + reset_clk => reset_clk, + adaption_enable => adaption_enable + ); + + +-- *** Test Bench - User Defined Section *** + clk_gen: PROCESS + BEGIN + clock <= '1'; + WAIT FOR clk_high; + clock <= '0'; + WAIT FOR clk_low; + + END PROCESS clk_gen; + + reset_gen: process + begin + reset <= '0'; + reset_clk <= '0'; + wait for clk_period*2; + reset_clk <= '1'; + adaption_enable <= '1'; + wait for clk_period*10; + reset <= '1'; + + wait; + end process reset_gen; +-- *** End Test Bench - User Defined Section *** + +END; Index: adaptive_lms_equalizer/tags/V10/code/test_lms.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/test_lms.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/test_lms.vhd (revision 4) @@ -0,0 +1,2185 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- VHDL Test Bench Created from source file tf_lms.vhd -- 14:23:32 02/24/2005 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY ieee; +USE IEEE.STD_LOGIC_TEXTIO.ALL; +USE STD.TEXTIO.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + FILE RESULTS: TEXT IS OUT "yout.txt"; + FILE ERRF: TEXT IS OUT "error.txt"; + + FUNCTION to_hex( x : IN std_logic_vector) RETURN string IS + VARIABLE result : STRING(1 TO 8); -- 1024 bits max + VARIABLE i : INTEGER; + VARIABLE imod : INTEGER; + VARIABLE j : INTEGER; + VARIABLE newx : std_logic_vector(1023 DOWNTO 0); + BEGIN + newx := (OTHERS => '0'); + newx(x'RANGE) := x; + i := 7; + j := 1; + + WHILE i >= 0 LOOP + IF newx(i) = '0' THEN result(j) := '0'; + elsif newx(i) = '1' THEN result(j) := '1'; + ELSE result(j) := 'X'; + END IF; + + i := i-1; + j := j+1; + END LOOP; + RETURN result(1 TO j-1); + END; + + COMPONENT tf_lms + PORT( + xin : IN std_logic_vector(7 downto 0); + dxin : IN std_logic_vector(7 downto 0); + clock : IN std_logic; + err: out std_logic_vector(7 downto 0); + adapt_en: in std_logic; + yout : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + SIGNAL xin : std_logic_vector(7 downto 0); + SIGNAL dxin : std_logic_vector(7 downto 0); + SIGNAL clock : std_logic; + SIGNAL yout : std_logic_vector(7 downto 0); + signal err: std_logic_vector(7 downto 0); + signal adapt_en : std_logic; + CONSTANT clk_high : time := 10 ns; + CONSTANT clk_low : time := 10 ns; + CONSTANT clk_period : time := 20 ns; + CONSTANT clk_hold : time := 4 ns; + + + + TYPE filter_data IS ARRAY (0 TO 999) OF std_logic_vector(7 downto 0); + TYPE filter_out_table IS ARRAY (0 TO 999)OF std_logic_vector(7 downto 0); + + -- Constants + CONSTANT filter_dx_in : filter_data := + ( + +"01000000", +"11000000", +"01000000", +"11000000", +"01000000", +"11000000", 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=> xin, + dxin => dxin, + clock => clock, + err => err, + adapt_en => adapt_en, + yout => yout + ); + + +-- *** Test Bench - User Defined Section *** + clk_gen: PROCESS + BEGIN + clock <= '1'; + WAIT FOR clk_high; + clock <= '0'; + WAIT FOR clk_low; + + END PROCESS clk_gen; + + tb: + PROCESS + variable IN_x,IN_dx:std_logic_vector(7 downto 0); + VARIABLE TX_STR : String(1 to 512); + VARIABLE TX_LOC : LINE; + VARIABLE RX_LOC : LINE; + + + BEGIN + + adapt_en <= '1'; + + FOR n IN 0 TO 500 LOOP +-- readline(F_XIN,xin); + --xin <= IN_X; + --Deallocate(RX_LOC); + xin <= filter_x_in(n); + dxin <= filter_dx_in(n); + wait for clk_period; + write(TX_LOC,string'("'")); + write(TX_LOC, yout); + write(TX_LOC,string'("'")); + writeline(results, TX_LOC); + Deallocate(TX_LOC); + write(TX_LOC,string'("'")); + write(TX_LOC, err); + write(TX_LOC,string'("'")); + writeline(ERRF, TX_LOC); + Deallocate(TX_LOC); + end loop; + + -- adapt_en <= '0'; + + FOR n IN 501 TO 999 LOOP +-- readline(F_XIN,xin); + --xin <= IN_X; + --Deallocate(RX_LOC); + xin <= filter_x_in(n); + dxin <= filter_dx_in(n); + wait for clk_period; + write(TX_LOC,string'("'")); + write(TX_LOC, yout); + write(TX_LOC,string'("'")); + writeline(results, TX_LOC); + Deallocate(TX_LOC); + write(TX_LOC,string'("'")); + write(TX_LOC, err); + write(TX_LOC,string'("'")); + writeline(ERRF, TX_LOC); + Deallocate(TX_LOC); + end loop; + + + wait; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END; Index: adaptive_lms_equalizer/tags/V10/code/clock_div.vhd =================================================================== --- adaptive_lms_equalizer/tags/V10/code/clock_div.vhd (nonexistent) +++ adaptive_lms_equalizer/tags/V10/code/clock_div.vhd (revision 4) @@ -0,0 +1,57 @@ +-- Copyright (C) 2004-2005 Digish Pandya + +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +-- clock devider routine + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity clock_div is + Port ( reset: in std_logic; + in_clk : in std_logic; + out1 : out std_logic; + out2 : out std_logic); +end clock_div; + +architecture Behavioral of clock_div is + +signal ct: std_logic_vector(19 downto 0); +--signal ct: std_logic_vector(1 downto 0); + +begin + + process(reset,in_clk) + begin + if reset = '0' then + ct <= "00000000000000000000"; +-- ct <= "00"; + elsif in_clk'event and in_clk = '1' then + ct <= ct + "00000000000000000001"; +-- ct <= ct + "01"; + end if; + end process; +-- Using this value we can adjust different clock speed +-- Fast Clock +out1 <= ct(5); +-- Slow clock +out2 <= ct(19); + +--out1 <= ct(0); +--out2 <= ct(1); + +end Behavioral; Index: adaptive_lms_equalizer/tags =================================================================== --- adaptive_lms_equalizer/tags (nonexistent) +++ adaptive_lms_equalizer/tags (revision 4)

adaptive_lms_equalizer/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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