URL
https://opencores.org/ocsvn/am9080_cpu_based_on_microcoded_am29xx_bit-slices/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk
Subversion Repositories am9080_cpu_based_on_microcoded_am29xx_bit-slices
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/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/rgb_leds.xreport
0,0 → 1,215
<?xml version='1.0' encoding='UTF-8'?> |
<report-views version="2.0" > |
<header> |
<DateModified>2017-11-18T10:58:22</DateModified> |
<ModuleName>sys9080</ModuleName> |
<SummaryTimeStamp>2017-11-18T10:58:14</SummaryTimeStamp> |
<SavedFilePath>C:/Users/zoltanp/Documents/HexCalc/Sys9080/iseconfig/rgb_leds.xreport</SavedFilePath> |
<ImplementationReportsDirectory>C:/Users/zoltanp/Documents/HexCalc/sys9080</ImplementationReportsDirectory> |
<DateInitialized>2017-11-18T10:13:03</DateInitialized> |
<EnableMessageFiltering>false</EnableMessageFiltering> |
</header> |
<body> |
<viewgroup label="Design Overview" > |
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="sys9080_summary.html" label="Summary" > |
<toc-item title="Design Overview" target="Design Overview" /> |
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> |
<toc-item title="Performance Summary" target="Performance Summary" /> |
<toc-item title="Failing Constraints" target="Failing Constraints" /> |
<toc-item title="Detailed Reports" target="Detailed Reports" /> |
</view> |
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="sys9080_envsettings.html" label="System Settings" /> |
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="sys9080_map.xrpt" label="IOB Properties" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="sys9080_map.xrpt" label="Control Set Information" /> |
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="sys9080_map.xrpt" label="Module Level Utilization" /> |
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="sys9080.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> |
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="sys9080_par.xrpt" label="Pinout Report" /> |
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="sys9080_par.xrpt" label="Clock Report" /> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="sys9080.twx" label="Static Timing" /> |
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="sys9080_html/fit/report.htm" label="CPLD Fitter Report" /> |
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="sys9080_html/tim/report.htm" label="CPLD Timing Report" /> |
</viewgroup> |
<viewgroup label="XPS Errors and Warnings" > |
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> |
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> |
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> |
</viewgroup> |
<viewgroup label="XPS Reports" > |
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> |
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> |
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> |
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="sys9080.log" label="System Log File" /> |
</viewgroup> |
<viewgroup label="Errors and Warnings" > |
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> |
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> |
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> |
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> |
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> |
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> |
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> |
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> |
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> |
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> |
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> |
</viewgroup> |
<viewgroup label="Detailed Reports" > |
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="sys9080.syr" label="Synthesis Report" > |
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> |
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> |
<toc-item title="HDL Compilation" target=" HDL Compilation " /> |
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> |
<toc-item title="HDL Analysis" target=" HDL Analysis " /> |
<toc-item title="HDL Parsing" target=" HDL Parsing " /> |
<toc-item title="HDL Elaboration" target=" HDL Elaboration " /> |
<toc-item title="HDL Synthesis" target=" HDL Synthesis " /> |
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> |
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> |
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> |
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> |
<toc-item title="Partition Report" target=" Partition Report " /> |
<toc-item title="Final Report" target=" Final Report " /> |
<toc-item title="Design Summary" target=" Design Summary " /> |
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> |
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> |
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> |
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> |
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> |
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> |
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> |
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> |
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> |
</view> |
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="sys9080.srr" label="Synplify Report" /> |
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="sys9080.prec_log" label="Precision Report" /> |
<view inputState="Synthesized" program="ngdbuild" type="Report" file="sys9080.bld" label="Translation Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Command Line" target="Command Line:" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> |
</view> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="sys9080_map.mrp" label="Map Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> |
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> |
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> |
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> |
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> |
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> |
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> |
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> |
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> |
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> |
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> |
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> |
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="sys9080.par" label="Place and Route Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Device Utilization" target="Device Utilization Summary:" /> |
<toc-item title="Router Information" target="Starting Router" /> |
<toc-item title="Partition Status" target="Partition Implementation Status" /> |
<toc-item title="Clock Report" target="Generating Clock Report" /> |
<toc-item title="Timing Results" target="Timing Score:" /> |
<toc-item title="Final Summary" target="Peak Memory Usage:" /> |
</view> |
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="sys9080.twr" label="Post-PAR Static Timing Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
<toc-item title="Timing Summary" target="Timing summary:" /> |
<toc-item title="Trace Settings" target="Trace Settings:" /> |
</view> |
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="sys9080.rpt" label="CPLD Fitter Report (Text)" > |
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> |
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> |
<toc-item title="Pin Resources" target="** Pin Resources **" /> |
<toc-item title="Global Resources" target="** Global Control Resources **" /> |
</view> |
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="sys9080.tim" label="CPLD Timing Report (Text)" > |
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> |
<toc-item title="Performance Summary" target="Performance Summary:" /> |
</view> |
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="sys9080.pwr" label="Power Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Power summary" target="Power summary" /> |
<toc-item title="Thermal summary" target="Thermal summary" /> |
</view> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="sys9080.bgn" label="Bitgen Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> |
<toc-item title="Final Summary" target="DRC detected" /> |
</view> |
</viewgroup> |
<viewgroup label="Secondary Reports" > |
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> |
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/sys9080_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/sys9080_translate.nlf" label="Post-Translate Simulation Model Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="sys9080_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> |
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="sys9080_map.map" label="Map Log File" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
<toc-item title="Design Information" target="Design Information" /> |
<toc-item title="Design Summary" target="Design Summary" /> |
</view> |
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> |
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080_preroute.twr" label="Post-Map Static Timing Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
<toc-item title="Timing Report Description" target="Device,package,speed:" /> |
<toc-item title="Informational Messages" target="INFO:" /> |
<toc-item title="Warning Messages" target="WARNING:" /> |
<toc-item title="Timing Constraints" target="Timing constraint:" /> |
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> |
<toc-item title="Data Sheet Report" target="Data Sheet report:" /> |
<toc-item title="Timing Summary" target="Timing summary:" /> |
<toc-item title="Trace Settings" target="Trace Settings:" /> |
</view> |
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/sys9080_map.nlf" label="Post-Map Simulation Model Report" /> |
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080_map.psr" label="Physical Synthesis Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="sys9080_pad.txt" label="Pad Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="sys9080.unroutes" label="Unroutes Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080_preroute.tsi" label="Post-Map Constraints Interaction Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.grf" label="Guide Results Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.dly" label="Asynchronous Delay Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.clk_rgn" label="Clock Region Report" /> |
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.tsi" label="Post-Place and Route Constraints Interaction Report" > |
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> |
</view> |
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="sys9080_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> |
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/sys9080_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> |
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="sys9080_sta.nlf" label="Primetime Netlist Report" > |
<toc-item title="Top of Report" target="Release" searchDir="Forward" /> |
</view> |
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="sys9080.ibs" label="IBIS Model" > |
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> |
<toc-item title="Component" target="Component " /> |
</view> |
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.lck" label="Back-annotate Pin Report" > |
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> |
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> |
</view> |
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="sys9080.lpc" label="Locked Pin Constraints" > |
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> |
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> |
</view> |
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/sys9080_timesim.nlf" label="Post-Fit Simulation Model Report" /> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> |
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> |
</viewgroup> |
</body> |
</report-views> |
am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/rgb_leds.xreport
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.projectmgr
===================================================================
--- am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.projectmgr (nonexistent)
+++ am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.projectmgr (revision 4)
@@ -0,0 +1,161 @@
+
+
+
+
+
+
+
+
+ 2
+ /UART_LOOPBACK - FULL C:|Users|zoltanp|Documents|HexCalc|Sys9080|uart-for-fpga-master|example|uart_loopback.vhd
+ /rgb_leds - Behavioral C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/acia0 - ACIA - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/acia1 - ACIA - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u33 - am2901 - am2901
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u34 - am2901 - am2901/u1 - ram_regs - ram_regs
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u34 - am2901 - am2901/u2 - q_reg - q_reg
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u43 - am2901 - am2901
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u43 - am2901 - am2901/u2 - q_reg - q_reg
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural/u44 - am2901 - am2901
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/debouncer_btn - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/debouncer_sw - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/iodevice - simpledevice - Behavioral/sio - UART - FULL/uart_rx_i - UART_RX - FULL
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/led4x7 - fourdigitsevensegled - structural
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/loopback - UART_LOOPBACK - FULL
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/cpu - Am9080a - structural/u33 - am2901 - am2901
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/cpu - Am9080a - structural/u43 - am2901 - am2901/u1 - ram_regs - ram_regs
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/cpu - Am9080a - structural/u43 - am2901 - am2901/u2 - q_reg - q_reg
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/cpu - Am9080a - structural/u44 - am2901 - am2901
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/debouncer_btn - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/debouncer_sw - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|sys9080|sys9080.vhd/led4x7 - fourdigitsevensegled - structural
+ /sys9080 - structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd
+
+
+ sys9080 - Structural (C:/Users/zoltanp/Documents/HexCalc/Sys9080/sys9080.vhd)
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002e6000000020000000000000000000000000200000064ffffffff000000810000000300000002000002e60000000100000003000000000000000100000003
+ true
+ sys9080 - Structural (C:/Users/zoltanp/Documents/HexCalc/Sys9080/sys9080.vhd)
+
+
+
+ 1
+ Configure Target Device
+ Implement Design
+ Synthesize - XST
+ User Constraints
+
+
+ Design Utilities
+
+ 0
+ 0
+ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000122000000010000000100000000000000000000000064ffffffff000000810000000000000001000001220000000100000000
+ false
+ Design Utilities
+
+
+
+ 1
+
+
+ 0
+ 0
+ 000000ff0000000000000001000000000000000001000000000000000000000000000000000000031c000000040101000100000000000000000000000064ffffffff000000810000000000000004000001bd0000000100000000000000950000000100000000000000660000000100000000000000640000000100000000
+ false
+ C:\Users\zoltanp\Documents\HexCalc\Sys9080\acia.vhd
+
+
+
+ 1
+
+
+ C:\Users\zoltanp\Documents\HexCalc\Sys9080\ipcore_dir\ram4kx8.xco
+
+ 24
+ 0
+ 000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
+ false
+ C:\Users\zoltanp\Documents\HexCalc\Sys9080\ipcore_dir\ram4kx8.xco
+
+
+
+ 1
+ Configure Target Device
+ Design Utilities
+ Implement Design
+ User Constraints
+
+
+ Generate Programming File
+
+ 8
+ 0
+ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000122000000010000000100000000000000000000000064ffffffff000000810000000000000001000001220000000100000000
+ false
+ Generate Programming File
+
+ 000000ff0000000000000002000001090000008001000000050100000002
+ Implementation
+
+
+ 1
+
+
+ Edit Constraints (Text)
+
+ 0
+ 0
+ 000000ff0000000000000001000000010000000000000000000000000000000000000000000000014e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014e0000000100000000
+ false
+ Edit Constraints (Text)
+
+
+
+ 2
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/cpu - Am9080a - structural
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/debouncer_btn - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/debouncer_sw - debouncer8channel - Behavioral
+ /sys9080 - Structural C:|Users|zoltanp|Documents|HexCalc|Sys9080|sys9080.vhd/led4x7 - fourdigitsevensegled - structural
+
+
+ Unassigned User Library Modules
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002e6000000020000000000000000000000000200000064ffffffff000000810000000300000002000002e60000000100000003000000000000000100000003
+ false
+ Unassigned User Library Modules
+
+
+
+ 1
+ Design Utilities
+
+
+
+
+ 0
+ 0
+ 000000ff0000000000000001000000010000000000000000000000000000000000000000000000014e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014e0000000100000000
+ false
+
+
+
+
+ 1
+
+
+ View HDL Functional Model
+
+ 0
+ 0
+ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000143000000010000000100000000000000000000000064ffffffff000000810000000000000001000001430000000100000000
+ false
+ View HDL Functional Model
+
+
am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.projectmgr
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.xreport
===================================================================
--- am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.xreport (nonexistent)
+++ am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.xreport (revision 4)
@@ -0,0 +1,215 @@
+
+
+
+ 2018-01-08T09:15:15
+ sys9080
+ 2018-01-08T09:07:14
+ C:/Users/zoltanp/Documents/HexCalc/Sys9080/iseconfig/sys9080.xreport
+ C:/Users/zoltanp/Documents/HexCalc/Sys9080\
+ 2017-11-18T11:23:52
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/iseconfig/sys9080.xreport
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property