OpenCores
URL https://opencores.org/ocsvn/astron_fifo/astron_fifo/trunk

Subversion Repositories astron_fifo

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Rev 3 → Rev 4

/astron_fifo/trunk/common_fifo_dc.vhd
20,14 → 20,14
 
-- Purpose: Dual clock FIFO
 
LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_fifo_lib;
LIBRARY IEEE, common_pkg_lib, common_components_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_fifo_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
g_dat_w : NATURAL := 36;
114,7 → 114,7
END IF;
END PROCESS;
u_fifo : ENTITY tech_fifo_lib.tech_fifo_dc
u_fifo : ENTITY work.tech_fifo_dc
GENERIC MAP (
g_technology => g_technology,
g_dat_w => g_dat_w,
/astron_fifo/trunk/common_fifo_sc.vhd
20,14 → 20,14
 
-- Purpose: Single clock FIFO
 
LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_fifo_lib;
LIBRARY IEEE, common_pkg_lib, common_components_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_fifo_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs via Altera eab="OFF",
152,7 → 152,7
 
-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
u_fifo : ENTITY tech_fifo_lib.tech_fifo_sc
u_fifo : ENTITY work.tech_fifo_sc
GENERIC MAP (
g_technology => g_technology,
g_use_eab => c_use_eab,
/astron_fifo/trunk/dp_fifo_core.vhd
38,16 → 38,16
-- combinatorially connected, so this can ease the timing closure for the
-- ready signal.
 
LIBRARY IEEE, common_pkg_lib, dp_components_lib, common_fifo_lib, dp_pkg_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_components_lib, dp_pkg_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_core IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_dual_clock : BOOLEAN := FALSE;
g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
168,7 → 168,7
nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_common_fifo_sc : ENTITY common_fifo_lib.common_fifo_sc
u_common_fifo_sc : ENTITY work.common_fifo_sc
GENERIC MAP (
g_technology => g_technology,
g_note_is_ful => g_note_is_ful,
193,7 → 193,7
END GENERATE;
gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
u_common_fifo_dc : ENTITY common_fifo_lib.common_fifo_dc
u_common_fifo_dc : ENTITY work.common_fifo_dc
GENERIC MAP (
g_technology => g_technology,
g_dat_w => c_fifo_dat_w,
/astron_fifo/trunk/dp_fifo_dc.vhd
21,16 → 21,16
-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
/astron_fifo/trunk/dp_fifo_fill.vhd
24,16 → 24,16
-- This wrapper is for backwards compatibility, better use dp_fifo_fill_sc.vhd
-- for new designs.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_fill IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
/astron_fifo/trunk/dp_fifo_fill_core.vhd
55,16 → 55,16
-- src_in.ready is often more clear to comprehend then using next_src_out
-- directly.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_fill_core IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_use_dual_clock : BOOLEAN := FALSE;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
/astron_fifo/trunk/dp_fifo_fill_sc.vhd
22,16 → 22,16
-- been filled with more than g_fifo_fill words.
-- Description: See dp_fifo_fill_core.vhd.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_fill_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
/astron_fifo/trunk/dp_fifo_sc.vhd
21,16 → 21,16
-- Purpose: DP FIFO for single clock (= sc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY dp_fifo_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
/astron_fifo/trunk/hdllib.cfg
1,10 → 1,10
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses_synth = technology ip_stratixiv_fifo
hdl_lib_name = astron_fifo
hdl_library_clause_name = astron_fifo_lib
hdl_lib_uses_synth = common_pkg common_components dp_pkg dp_components #ip_stratixiv_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_fifo ip_stratixiv_fifo_lib
#hdl_lib_disclose_library_clause_names =
# ip_stratixiv_fifo ip_stratixiv_fifo_lib
 
synth_files =
tech_fifo_component_pkg.vhd
/astron_fifo/trunk/tech_fifo_component_pkg.vhd
20,9 → 20,10
 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
 
LIBRARY IEEE, technology_lib;
LIBRARY ieee, common_pkg_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_pkg.ALL;
USE common_pkg_lib.common_pkg.ALL;
 
PACKAGE tech_fifo_component_pkg IS
 
45,7 → 46,7
empty : OUT STD_LOGIC;
full : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
63,9 → 64,9
wrreq : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
84,9 → 85,9
wrreq : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
110,7 → 111,7
-- empty : OUT STD_LOGIC ;
-- full : OUT STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
-- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
129,9 → 130,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
150,9 → 151,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
175,7 → 176,7
-- empty : OUT STD_LOGIC ;
-- full : OUT STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
-- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
194,9 → 195,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
215,9 → 216,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
240,7 → 241,7
-- empty : OUT STD_LOGIC ;
-- full : OUT STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
-- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
259,9 → 260,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
--
280,9 → 281,9
-- wrreq : IN STD_LOGIC ;
-- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
-- rdempty : OUT STD_LOGIC ;
-- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
-- wrfull : OUT STD_LOGIC ;
-- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
-- wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
-- );
-- END COMPONENT;
/astron_fifo/trunk/tech_fifo_dc.vhd
18,14 → 18,16
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee, common_pkg_lib;
USE ieee.std_logic_1164.all;
USE work.tech_fifo_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_pkg_lib.common_pkg.ALL;
 
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_arria10_fifo_lib;
--LIBRARY ip_arria10_e3sge3_fifo_lib;
--LIBRARY ip_arria10_e1sg_fifo_lib;
32,7 → 34,7
 
ENTITY tech_fifo_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
g_nof_words : NATURAL
46,9 → 48,9
wrreq : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END tech_fifo_dc;
 
57,7 → 59,7
 
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_fifo_dc
GENERIC MAP (g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
/astron_fifo/trunk/tech_fifo_dc_mixed_widths.vhd
18,14 → 18,16
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee, common_pkg_lib;
USE ieee.std_logic_1164.all;
USE work.tech_fifo_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_pkg_lib.common_pkg.ALL;
 
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_arria10_fifo_lib;
--LIBRARY ip_arria10_e3sge3_fifo_lib;
--LIBRARY ip_arria10_e1sg_fifo_lib;
32,7 → 34,7
 
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL;
g_rddat_w : NATURAL
46,9 → 48,9
wrreq : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC;
rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END tech_fifo_dc_mixed_widths;
 
57,7 → 59,7
 
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
/astron_fifo/trunk/tech_fifo_sc.vhd
18,14 → 18,16
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee, common_pkg_lib;
USE ieee.std_logic_1164.all;
USE work.tech_fifo_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_pkg_lib.common_pkg.ALL;
 
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_stratixiv_fifo_lib;
--LIBRARY ip_arria10_fifo_lib;
--LIBRARY ip_arria10_e3sge3_fifo_lib;
--LIBRARY ip_arria10_e1sg_fifo_lib;
32,7 → 34,7
 
ENTITY tech_fifo_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
g_nof_words : NATURAL
46,7 → 48,7
empty : OUT STD_LOGIC;
full : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END tech_fifo_sc;
 
55,7 → 57,7
 
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);

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