OpenCores
URL https://opencores.org/ocsvn/bluespec_md6/bluespec_md6/trunk

Subversion Repositories bluespec_md6

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Rev 3 → Rev 4

/trunk/lib/bsv/Avalon/build/Makefile
0,0 → 1,75
#/*
#Copyright (c) 2008 MIT
#
#Permission is hereby granted, free of charge, to any person
#obtaining a copy of this software and associated documentation
#files (the "Software"), to deal in the Software without
#restriction, including without limitation the rights to use,
#copy, modify, merge, publish, distribute, sublicense, and/or sell
#copies of the Software, and to permit persons to whom the
#Software is furnished to do so, subject to the following
#conditions:
#
#The above copyright notice and this permission notice shall be
#included in all copies or substantial portions of the Software.
#
#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
#EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
#OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
#NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
#HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
#WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
#FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
#OTHER DEALINGS IN THE SOFTWARE.
#
#Author: Kermin Fleming
#*/
srcdir = ../src
debugdir = ../../Debug
testdir = ../test
fpgadir = ../fpga
registermapperdir = ../../RegisterMapper/src
registerdir = ../../Register/src
cbusdir = ../../CBusUtils
clientserverdir = ../../ClientServerUtils
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -u -simdir $(simdir) -sim
 
#--------------------------------------------------------------------
# Build targets
#--------------------------------------------------------------------
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
avalontester : build
$(BSC) $(SIM_OPTS) -p +:$(srcdir):$(debugdir):$(bdir):$(registermapperdir):$(registerdir):$(fpgadir):$(cbusdir) -g mkAvalonTester $(testdir)/AvalonTester.bsv > out.log
$(BSC) $(EXE_OPTS) -o avalontester -p +:$(srcdir):$(debugdir):$(bdir):$(registermapperdir):$(fpgadir):$(registerdir):$(cbusdir) -e mkAvalonTester $(bdir)/mkAvalonTester.ba > out.log
 
avalonregisterfile_verilog : build
$(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0 -bdir $(bdir) -vdir $(vdir) -p +:$(srcdir):$(bramdir):$(cbusdir):$(debugdir):$(commondir):$(feederdir):$(bdir):$(fpgadir):$(registermapperdir):$(registerdir) -g mkSmallAvalonRegisterFile $(fpgadir)/AvalonRegisterFile.bsv > out.log
 
 
 
avalonfifo_verilog : build
$(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0 -bdir $(bdir) -vdir $(vdir) -p +:$(clientserverdir):$(cbusdir):$(srcdir):$(bramdir):$(debugdir):$(commondir):$(feederdir):$(bdir):$(fpgadir):$(registermapperdir):$(registerdir) -g mkAvalonCBusFIFOTop $(fpgadir)/AvalonFIFO.bsv > out.log
 
avalonfifo : build
$(BSC) $(SIM_OPTS) -p +:$(clientserverdir):$(cbusdir):$(srcdir):$(debugdir):$(bdir):$(registermapperdir):$(registerdir):$(fpgadir) -g mkAvalonCBusFIFOTester $(fpgadir)/AvalonFIFO.bsv > out.log
$(BSC) $(EXE_OPTS) -o avalonfifo -p +:$(clientserverdir):$(cbusdir):$(srcdir):$(debugdir):$(bdir):$(registermapperdir):$(fpgadir):$(registerdir) -e mkAvalonCBusFIFOTester $(bdir)/mkAvalonCBusFIFOTester.ba > out.log
 
clean :
rm -rf build
/trunk/lib/bsv/BRAMFIFO/build/Makefile
0,0 → 1,123
#//----------------------------------------------------------------------//
#// The MIT License
#//
#// Copyright (c) 2008 Kermin Fleming, kfleming@mit.edu
#//
#// Permission is hereby granted, free of charge, to any person
#// obtaining a copy of this software and associated documentation
#// files (the "Software"), to deal in the Software without
#// restriction, including without limitation the rights to use,
#// copy, modify, merge, publish, distribute, sublicense, and/or sell
#// copies of the Software, and to permit persons to whom the
#// Software is furnished to do so, subject to the following conditions:
#//
#// The above copyright notice and this permission notice shall be
#// included in all copies or substantial portions of the Software.
#//
#// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
#// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
#// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
#// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
#// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
#// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
#// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
#// OTHER DEALINGS IN THE SOFTWARE.
#//----------------------------------------------------------------------//
 
 
default : all
 
basedir = ../
bsvlibdir = ../../../bsclib
verilogdir = ./
 
 
#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
 
# Library components
 
bsvclibdir = $(MIT6375_HOME)/install/bsvclib
bsvclibsrcs = \
 
# Bluespec sources
 
toplevel_module = mkTestBench
 
srcdir = $(basedir)
 
 
fpgasrcs = \
$(srcdir)/BRAMFIFO.bsv \
$(srcdir)/mkTestBench.bsv \
$(srcdir)/top.v \
$(srcdir)/BRAMFIFOF.v
 
 
 
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
 
BSC_COMP = bsc
#BSC_OPTS = -u -show-module-use - -keep-fires -aggressive-conditions \
# -relax-method-earliness -relax-method-urgency -v
 
BSC_OPTS_SIM = +RTS -K400000k --RTS -u -v -sim -aggressive-conditions
 
 
BSC_OPTS_VERILOG = +RTS -K400000k --RTS -u -v -verilog -aggressive-conditions -dschedule
 
BSIM_OPTS = +RTS -K400000k --RTS -sim
 
# Copy over te bluespec source
 
$(notdir $(fpgasrcs)) : % : $(srcdir)/%
cp $< .
 
$(notdir $(bsvclibsrcs)) : % : $(bsvclibdir)/%
cp $< .
 
# Run the bluespec compiler
 
bsv_TH_vsrc = $(toplevel_module).v
$(bsv_TH_vsrc) $(bsv_lib_use) : $(notdir $(fpgasrcs) $(bsvclibsrcs))
$(BSC_COMP) $(BSC_OPTS_SIM) -g $(toplevel_module) $(toplevel_module).bsv > out.log
 
bsv : $(toplevel_module).v
 
 
blue_sim: $(bsv_TH_vsrc)
$(BSC_COMP) $(BSIM_OPTS) -e $(toplevel_module) *.ba > out.txt
 
verilog: $(notdir $(fpgasrcs) $(bsvclibsrcs))
$(BSC_COMP) $(BSC_OPTS_VERILOG) -g $(toplevel_module) $(toplevel_module).bsv > out.log
 
verilog_exec: verilog
iverilog -y$(bsvlibdir) -y$(verilogdir) *.v
 
 
# Create a schedule file
 
schedule_rpt = schedule.rpt
$(schedule_rpt) : $(notdir $(fpgasrcs) $(bsvclibsrcs))
rm -rf *.v
$(BSC_COMP) $(BSC_OPTS_SIM) -show-schedule -show-rule-rel \* \* -g $(toplevel_module) \
$(toplevel_module).bsv >& $(schedule_rpt)
 
junk += $(notdir $(fpgasrcs) ) $(notdir $(bsvclibsrcs)) \
$(schedule_rpt) *.use *.bi *.bo *.v bsc.log
 
#--------------------------------------------------------------------
# Default make target
#--------------------------------------------------------------------
 
all : verilog_exec
 
#--------------------------------------------------------------------
# Clean up
#--------------------------------------------------------------------
 
clean :
rm -rf $(junk) *~ \#* *.cxx *.o *.h *.ba
/trunk/lib/bsv/PLBMaster/build/Makefile
0,0 → 1,64
#/*
#Copyright (c) 2008 MIT
#
#Permission is hereby granted, free of charge, to any person
#obtaining a copy of this software and associated documentation
#files (the "Software"), to deal in the Software without
#restriction, including without limitation the rights to use,
#copy, modify, merge, publish, distribute, sublicense, and/or sell
#copies of the Software, and to permit persons to whom the
#Software is furnished to do so, subject to the following
#conditions:
#
#The above copyright notice and this permission notice shall be
#included in all copies or substantial portions of the Software.
#
#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
#EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
#OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
#NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
#HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
#WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
#FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
#OTHER DEALINGS IN THE SOFTWARE.
#
#Author: Kermin Fleming
#*/
srcdir = ../src
debugdir = ../../Debug
testdir = ../test
commondir = ../common
bramdir = ../../BRAM/
feederdir = ../../BRAMFeeder/src
fpgadir = ../fpga
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir ./
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule
EXE_OPTS = +RTS -K100000000 --RTS -sim
 
#--------------------------------------------------------------------
# Build targets
#--------------------------------------------------------------------
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
plbmaster : build
$(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0 -bdir $(bdir) -vdir $(vdir) -p +:$(srcdir):$(bramdir):$(debugdir):$(commondir):$(feederdir):$(bdir) -g mkPLBMaster $(srcdir)/PLBMaster.bsv > out.log
 
plbtester_verilog : build
$(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0 -bdir $(bdir) -vdir $(vdir) -p +:$(srcdir):$(bramdir):$(debugdir):$(commondir):$(feederdir):$(bdir):$(fpgadir) -g mkPLBMasterTester $(fpgadir)/PLBMasterTester.bsv > out.log
 
clean :
rm -rf build
/trunk/lib/bsv/SPI/build/Makefile
0,0 → 1,66
#/*
#Copyright (c) 2008 MIT
#
#Permission is hereby granted, free of charge, to any person
#obtaining a copy of this software and associated documentation
#files (the "Software"), to deal in the Software without
#restriction, including without limitation the rights to use,
#copy, modify, merge, publish, distribute, sublicense, and/or sell
#copies of the Software, and to permit persons to whom the
#Software is furnished to do so, subject to the following
#conditions:
#
#The above copyright notice and this permission notice shall be
#included in all copies or substantial portions of the Software.
#
#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
#EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
#OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
#NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
#HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
#WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
#FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
#OTHER DEALINGS IN THE SOFTWARE.
#
#Author: Kermin Fleming
#*/
srcdir = ../src
debugdir = ../../Debug
testdir = ../test
fpgadir = ../fpga
registermapperdir = ../../RegisterMapper/src
registerdir = ../../Register/src
cbusdir = ../../CBusUtils
fifoutilsdir = ../../FIFOUtility
clientserverdir = ../../ClientServerUtils
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule --keep-fires -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -u -simdir $(simdir) -sim
 
#--------------------------------------------------------------------
# Build targets
#--------------------------------------------------------------------
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
.PHONY: spitester
 
spitester : build
$(BSC) $(SIM_OPTS) -p +:$(srcdir):$(fifoutilsdir):$(debugdir):$(bdir):$(registermapperdir):$(registerdir):$(fpgadir) -g mkSPITester $(testdir)/SPITester.bsv > out.log
$(BSC) $(EXE_OPTS) -o spitester -p +:$(srcdir):$(fifoutilsdir):$(debugdir):$(bdir):$(registermapperdir):$(fpgadir):$(registerdir) -e mkSPITester $(bdir)/mkSPITester.ba > out.log
 
clean :
rm -rf build
/trunk/lib/bsv/BRAMFeeder/build/Makefile
0,0 → 1,32
srcdir = ../src
debugdir = ../../Debug
testdir = ../test
commondir = ../../common
bramdir = ../../BRAM/
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -simdir $(simdir) -sim
C_OPTS = -c -fPIC
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
BRAMFeeder: build
$(BSC) $(VER_OPTS) -p +:$(testdir):$(srcdir):$(bdir):$(bramdir):$(debugdir) -g mkBRAMFeeder $(srcdir)/BRAMFeeder.bsv
 
 
clean:
rm -rf build
 
.PHONY: build
/trunk/lib/bsv/Stats/Averager/build/Makefile
0,0 → 1,66
#/*
#Copyright (c) 2008 MIT
#
#Permission is hereby granted, free of charge, to any person
#obtaining a copy of this software and associated documentation
#files (the "Software"), to deal in the Software without
#restriction, including without limitation the rights to use,
#copy, modify, merge, publish, distribute, sublicense, and/or sell
#copies of the Software, and to permit persons to whom the
#Software is furnished to do so, subject to the following
#conditions:
#
#The above copyright notice and this permission notice shall be
#included in all copies or substantial portions of the Software.
#
#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
#EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
#OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
#NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
#HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
#WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
#FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
#OTHER DEALINGS IN THE SOFTWARE.
#
#Author: Kermin Fleming
#*/
srcdir = ../src
debugdir = ../../Debug
testdir = ../test
fpgadir = ../fpga
registermapperdir = ../../RegisterMapper/src
registerdir = ../../Register/src
cbusdir = ../../CBusUtils
fifoutilsdir = ../../FIFOUtility
clientserverdir = ../../ClientServerUtils
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule --keep-fires -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -u -simdir $(simdir) -sim
 
#--------------------------------------------------------------------
# Build targets
#--------------------------------------------------------------------
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
.PHONY: spitester
 
spitester : build
$(BSC) $(SIM_OPTS) -p +:$(srcdir):$(fifoutilsdir):$(debugdir):$(bdir):$(registermapperdir):$(registerdir):$(fpgadir) -g mkSPITester $(testdir)/SPITester.bsv > out.log
$(BSC) $(EXE_OPTS) -o spitester -p +:$(srcdir):$(fifoutilsdir):$(debugdir):$(bdir):$(registermapperdir):$(fpgadir):$(registerdir) -e mkSPITester $(bdir)/mkSPITester.ba > out.log
 
clean :
rm -rf build
/trunk/lib/bsv/bscClib/CReg/build/Makefile
0,0 → 1,28
BSC_COMP = bsc
vdir=./build/vdir
srcdir=../
blddir=build/bdir
VER_OPTS = +RTS -K100000000 --RTS -u -verilog -elab -no-show-method-conf \
-aggressive-conditions -vdir $(vdir) -bdir $(blddir) -dschedule
SIM_OPTS = +RTS -K100000000 --RTS -u -sim -aggressive-conditions -dschedule -vdir $(vdir) -bdir $(blddir) -show-schedule
EXE_OPTS = +RTS -K100000000 --RTS -sim -v -bdir $(blddir)
 
files: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
 
CReg.o: $(srcdir)/CReg.c files
gcc -c -m32 -fPIC -o $(blddir)/CReg.o $(srcdir)/CReg.c
 
 
CRegBaseTester: files CReg.o
$(BSC_COMP) $(SIM_OPTS) -p +:$(srcdir):./build/bdir -g mkCRegBaseTester $(srcdir)/CRegBaseTester.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -o CRegBaseTeseter.exe -e mkCRegBaseTester -p +:$(srcdir):./build/bdir $(blddir)/*.ba $(blddir)/*.o
 
.PHONY: clean
.PHONY: files
 
clean:
rm -rf build
rm -f *.cxx *.h *.o *.exe *~ *.log *.so
/trunk/lib/bsv/bscClib/CRegFile/build/Makefile
0,0 → 1,28
BSC_COMP = bsc
vdir=./build/vdir
srcdir=../
blddir=build/bdir
VER_OPTS = +RTS -K100000000 --RTS -u -verilog -elab -no-show-method-conf \
-aggressive-conditions -vdir $(vdir) -bdir $(blddir) -dschedule
SIM_OPTS = +RTS -K100000000 --RTS -u -sim -aggressive-conditions -dschedule -vdir $(vdir) -bdir $(blddir) -show-schedule
EXE_OPTS = +RTS -K100000000 --RTS -sim -v -bdir $(blddir) -Xc++ -m32 -Xc -m32
 
files: clean
mkdir -p build
mkdir -p build/bdir
mkdir -p build/vdir
 
CRegFileFull.o: $(srcdir)/CRegFileFull.c files
gcc -c -m64 -g -fPIC -o $(blddir)/CRegFileFull.o $(srcdir)/CRegFileFull.c
 
 
CRegFileBaseTester: files CRegFileFull.o
$(BSC_COMP) $(SIM_OPTS) -p +:$(srcdir):./build/bdir -g mkCRegFileBaseTester $(srcdir)/CRegFileBaseTester.bsv > out.log
$(BSC_COMP) $(EXE_OPTS) -o CRegFileBaseTeseter.exe -e mkCRegFileBaseTester -p +:$(srcdir):./build/bdir $(blddir)/*.ba $(blddir)/*.o
 
.PHONY: clean
.PHONY: files
 
clean:
rm -rf build
rm -f *.cxx *.h *.o *.exe *~ *.log *.so
/trunk/MD6Control/build/Makefile
0,0 → 1,62
srcdir = ../src
testdir = ../test
commondir = ../../common
fpgadir = ../fpga
compressiondir = ../../compressionFunction/src
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
libbase = ../../lib/bsv
goldendir = ../../C_implementation/
plbdir = $(libbase)/PLBMaster/src
plbconfigdir = $(libbase)/PLBMaster/common
feederdir = $(libbase)/BRAMFeeder/src
plbemdir = $(libbase)/PLBMaster/test
bramdir = $(libbase)/BRAM
regmapdir = $(libbase)/RegisterMapper/src
regdir = $(libbase)/Register/src
 
compressiondir = ../../compressionFunction/src
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -simdir $(simdir) -sim
C_OPTS = -c -fPIC
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
md6_encode: $(testdir)/encodeBits.c $(testdir)/encodeBits.h $(testdir)/md6_encode.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c $(goldendir)/md6.h
gcc -g -iquote$(goldendir) -I$(testdir) -o md6_encode $(testdir)/md6_encode.c $(testdir)/encodeBits.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c
 
md6_random: $(testdir)/encodeBits.c $(testdir)/encodeBits.h $(testdir)/md6_random.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c $(goldendir)/md6.h
gcc -g -iquote$(goldendir) -I$(testdir) -o md6_random $(testdir)/md6_random.c $(testdir)/encodeBits.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c
 
md6_setbits: $(testdir)/encodeBits.c $(testdir)/encodeBits.h $(testdir)/md6_setbits.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c $(goldendir)/md6.h
gcc -g -iquote$(goldendir) -I$(testdir) -o md6_setbits $(testdir)/md6_setbits.c $(testdir)/encodeBits.c $(goldendir)/md6_compress.c $(goldendir)/md6_mode.c
 
 
MD6Verify: md6_encode MD6TestBench
perl $(testdir)/runtest.pl $(testdir)/benchmarks
 
MD6TestBench: build
$(BSC) $(SIM_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(srcdir):$(bdir):$(commondir):$(compressiondir):$(plbdir):$(plbconfigdir):$(feederdir):$(bramdir):$(compressiondir):$(plbemdir) -g mkMD6ControlTest $(testdir)/MD6ControlTest.bsv
$(BSC) $(EXE_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(srcdir):$(bdir):$(commondir):$(compressiondir):$(plbdir):$(plbconfigdir):$(feederdir):$(bramdir):$(compressiondir):$(plbemdir) -o MD6TestBench -e mkMD6ControlTest $(bdir)/mkMD6ControlTest.ba
 
 
MD6TestBench_fpga: build
$(BSC) $(SIM_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(srcdir):$(bdir):$(commondir):$(compressiondir):$(plbdir):$(plbconfigdir):$(feederdir):$(bramdir):$(compressiondir):$(plbemdir):$(regmapdir):$(regdir) -g mkMD6ControlEngineTest $(fpgadir)/MD6ControlEngineTest.bsv
$(BSC) $(EXE_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(srcdir):$(bdir):$(commondir):$(compressiondir):$(plbdir):$(plbconfigdir):$(feederdir):$(bramdir):$(compressiondir):$(plbemdir) -o MD6TestBench -e mkMD6ControlEngineTest $(bdir)/mkMD6ControlEngineTest.ba
 
MD6ControlEngine_fpga: build
$(BSC) $(VER_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(fpgadir):$(srcdir):$(bdir):$(compressiondir):$(commondir):$(plbdir):$(plbconfigdir):$(feederdir):$(regmapdir):$(bramdir):$(regdir) -g mkMD6ControlEngine $(fpgadir)/MD6ControlEngine.bsv
 
clean:
rm -rf build
/trunk/compressionFunction/build/Makefile
0,0 → 1,109
srcdir = ../src
testdir = ../test
commondir = ../../common
fpgadir = ../fpga
bdir = build/bdir
vdir = build/vdir
cdir = build/cdir
simdir = build/simdir
libbase = ../../lib/bsv
goldendir = ../../C_implementation/
plbdir = $(libbase)/PLBMaster/src
plbconfigdir = $(libbase)/PLBMaster/common
feederdir = $(libbase)/BRAMFeeder/src
regdir = $(libbase)/Register/src
bramdir = $(libbase)/BRAM
 
BSC = bsc
 
VER_OPTS = +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir $(vdir) -bdir $(bdir)
SIM_OPTS = +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule -vdir $(vdir) -bdir $(bdir)
EXE_OPTS = +RTS -K100000000 --RTS -simdir $(simdir) -sim
C_OPTS = -c -fPIC
 
#Synthesis params
mkdir = ../../toolflow
bsclib = ../../../../lib/bsclib
comp16top = mkCompressionFunction16
comp16srcs = $(vdir)/mkCompressionFunction16.v
 
build:
mkdir -p build
mkdir -p $(bdir)
mkdir -p $(vdir)
mkdir -p $(cdir)
mkdir -p $(simdir)
 
SimpleCompressionFunction_verilog: build
$(BSC) $(VER_OPTS) -p +:$(srcdir):$(bdir):$(commondir) -g mkSimpleCompressionFunction1 $(srcdir)/CompressionFunction.bsv
 
 
 
SimpleCompressionFunctionTestbench64: build $(cdir)/md6_compress64.o $(cdir)/CompressionFunctionTestbench64.o
$(BSC) $(SIM_OPTS) -D BIT64=0 -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -g mkCompressionFunctionTestbench $(testdir)/CompressionFunctionTestbench.bsv
$(BSC) $(EXE_OPTS) -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -e mkCompressionFunctionTestbench $(bdir)/mkCompressionFunctionTestbench.ba $(cdir)/CompressionFunctionTestbench64.o $(cdir)/md6_compress64.o
 
SimpleCompressionFunctionTestbench32: build $(cdir)/md6_compress32.o $(cdir)/CompressionFunctionTestbench32.o
$(BSC) $(SIM_OPTS) -D BIT32=0 -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -g mkCompressionFunctionTestbench $(testdir)/CompressionFunctionTestbench.bsv
$(BSC) $(EXE_OPTS) -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -e mkCompressionFunctionTestbench $(bdir)/mkCompressionFunctionTestbench.ba $(cdir)/CompressionFunctionTestbench32.o $(cdir)/md6_compress32.o
 
SimpleCompressionFunctionTestbench16: build $(cdir)/md6_compress16.o $(cdir)/CompressionFunctionTestbench16.o
$(BSC) $(SIM_OPTS) -D BIT16=0 -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -g mkCompressionFunctionTestbench $(testdir)/CompressionFunctionTestbench.bsv
$(BSC) $(EXE_OPTS) -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -e mkCompressionFunctionTestbench $(bdir)/mkCompressionFunctionTestbench.ba $(cdir)/CompressionFunctionTestbench16.o $(cdir)/md6_compress16.o
 
SimpleCompressionFunctionTestbench8: build $(cdir)/md6_compress8.o $(cdir)/CompressionFunctionTestbench8.o
$(BSC) $(SIM_OPTS) -D BIT8=0 -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -g mkCompressionFunctionTestbench $(testdir)/CompressionFunctionTestbench.bsv
$(BSC) $(EXE_OPTS) -p +:$(testdir):$(srcdir):$(bdir):$(commondir) -e mkCompressionFunctionTestbench $(bdir)/mkCompressionFunctionTestbench.ba $(cdir)/CompressionFunctionTestbench8.o $(cdir)/md6_compress8.o
 
 
 
 
$(cdir)/md6_compress64.o: build $(goldendir)/md6_compress.c
gcc $(C_OPTS) -Dmd6_w=64 -Dmd6_n=89 -Dmd6_c=16 \
-Dmd6_b=64 -Dmd6_v=1 -Dmd6_u=1 -Dmd6_k=8 -Dmd6_q=15 \
-Dt0=17 -Dt1=18 -Dt2=21 -Dt3=31 -Dt4=67 -Dt5=89 \
-iquote$(goldendir) -o$(cdir)/md6_compress64.o $(goldendir)/md6_compress.c
 
$(cdir)/md6_compress32.o: build $(goldendir)/md6_compress.c
gcc $(C_OPTS) -Dmd6_w=32 -Dmd6_n=178 -Dmd6_c=32 \
-Dmd6_b=128 -Dmd6_v=2 -Dmd6_u=2 -Dmd6_k=16 -Dmd6_q=30 \
-Dt0=33 -Dt1=35 -Dt2=49 -Dt3=53 -Dt4=111 -Dt5=178 \
-iquote$(goldendir) -o$(cdir)/md6_compress32.o $(goldendir)/md6_compress.c
 
$(cdir)/md6_compress16.o: build $(goldendir)/md6_compress.c
gcc $(C_OPTS) -iquote$(goldendir) -o$(cdir)/md6_compress16.o $(goldendir)/md6_compress.c
 
$(cdir)/md6_compress8.o: build $(goldendir)/md6_compress.c
gcc $(C_OPTS) -quote$(goldendir) -o$(cdir)/md6_compress8.o $(goldendir)/md6_compress.c
 
 
 
$(cdir)/CompressionFunctionTestbench64.o: build $(testdir)/CompressionFunctionTestbench.c
gcc $(C_OPTS) -Dmd6_w=64 -Dmd6_n=89 -Dmd6_c=16 \
-Dmd6_b=64 -Dmd6_v=1 -Dmd6_u=1 -Dmd6_k=8 -Dmd6_q=15 \
-Dt0=17 -Dt1=18 -Dt2=21 -Dt3=31 -Dt4=67 -Dt5=89 \
-iquote$(goldendir) -o$(cdir)/CompressionFunctionTestbench64.o $(testdir)/CompressionFunctionTestbench.c
 
 
$(cdir)/CompressionFunctionTestbench32.o: build $(testdir)/CompressionFunctionTestbench.c
gcc $(C_OPTS) -Dmd6_w=32 -Dmd6_n=178 -Dmd6_c=32 \
-Dmd6_b=128 -Dmd6_v=2 -Dmd6_u=2 -Dmd6_k=16 -Dmd6_q=30 \
-Dt0=33 -Dt1=35 -Dt2=49 -Dt3=53 -Dt4=111 -Dt5=178 \
-iquote$(goldendir) -o$(cdir)/CompressionFunctionTestbench32.o $(testdir)/CompressionFunctionTestbench.c
 
$(cdir)/CompressionFunctionTestbench16.o: build $(testdir)/CompressionFunctionTestbench.c
gcc $(C_OPTS) -iquote$(goldendir) -o$(cdir)/CompressionFunctionTestbench16.o $(testdir)/CompressionFunctionTestbench.c
$(cdir)/CompressionFunctionTestbench8.o: build $(testdir)/CompressionFunctionTestbench.c
gcc $(C_OPTS) -iquote$(goldendir) -o$(cdir)/CompressionFunctionTestbench8.o $(testdir)/CompressionFunctionTestbench.c
 
MD6Engine_fpga: build
$(BSC) $(VER_OPTS) -D BIT64=0 -D PLB_DEFAULTS=0 -p +:$(fpgadir):$(srcdir):$(bdir):$(commondir):$(plbdir):$(plbconfigdir):$(feederdir):$(bramdir) -g mkMD6Engine $(fpgadir)/MD6Engine.bsv
 
MD6_comp16_toolflow90: MD6Engine_fpga
make -f $(mkdir)/rc.mk "synthdir=${mkdir}" "toplevel=${comp16top}" "bscdir = ${vdir}" "vsrcs=${comp16srcs}" "libdir=${bsclib}"
make -f $(mkdir)/par90.mk "synthdir=${mkdir}" "vsrcs=syn-current/synthesized.v" "toplevel=${verilogtop}"
 
 
 
clean:
rm -rf build

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