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URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

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Rev 3 → Rev 4

/trunk/rxClkgen.v
0,0 → 1,38
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:50:39 12/13/05
// Design Name:
// Module Name: rxClkgen
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxClkgen(rxclk_in, reset, rxclk, rxclk_180, rxclk_2x, locked);
input rxclk_in;
input reset;
output rxclk;
output rxclk_180;
output rxclk_2x;
output locked;
 
dcm0 rx_dcm(.CLKIN_IN(rxclk_in),
.RST_IN(reset),
.CLKIN_IBUFG_OUT(rxclk),
.CLK0_OUT(),
.CLK2X_OUT(rxclk_2x),
.CLK180_OUT(rxclk_180),
.LOCKED_OUT(locked)
);
 
endmodule
/trunk/rxStateMachine.v
0,0 → 1,161
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:59:01 11/21/05
// Design Name:
// Module Name: rxStateMachine
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, len_invalid, end_data_cnt, end_tagged_cnt,
tagged_frame, length_error, end_fcs, crc_check_valid, crc_check_invalid, start_da, start_lt, inband_fcs,
start_data_cnt, start_tagged_cnt, receiving, recv_end, good_frame_get, bad_frame_get, get_error_code, small_frame
, end_small_cnt,receiving_frame);
input rxclk;
input reset;
input recv_enable;
input inband_fcs;
//PRE & SFD
input get_sfd; // SFD has been received;
//DA field
input local_invalid;// The Frame's DA field is not Local MAC;
//Length/Type field
input len_invalid;// Indicate if Length field is valid;
input end_data_cnt;// Indicate end of receiving DATA field(not jumbo frame);
input end_tagged_cnt;// Indicate end of receiving DATA field of tagged Frame;
input end_small_cnt; // Indicate end of receiving small data field
input tagged_frame;// Indicate current frame is a jumbo_frame;
input small_frame; // Indicate current frame is a small frame;
input length_error;//Indicate Length received is not equal to the Length in LT field;
//FCS field
input end_fcs;//Indicate end of receiving FCS field;
input crc_check_valid;//Indicate the frame passed CRC Check;
input crc_check_invalid;//Indicate the frame failed in CRC Check;
input get_error_code;
//DA field
output start_da;// Start to receive Destination Address;
//Length/Type field
output start_lt;// Start to receive Length/Type field;
//DATA field
output start_data_cnt;// Start to receive DATA field;
output start_tagged_cnt;// Start to receive DATA field, but the frame is a tagged frame.
//Receive process control
output receiving;// Rx Engine is receiving valid part of frame;
output receiving_frame; //Rx Engine is working, not in IDLE state and Check state.
output recv_end; // Receive process ends, either because formal ending or faults happen;
output good_frame_get;// A good frame has been received;
output bad_frame_get; // A bad frame has been received;
parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 3;
parameter rxReceiveFCS = 4, rxWaitCheck = 5;
parameter TP =1;
 
wire start_da;
wire start_lt;
wire start_data_cnt;
wire start_tagged_cnt;
wire receiving_data;
wire receiving_frame;
wire receiving;
wire recv_end;
wire good_frame_get;
wire bad_frame_get;
reg[2:0] rxstate, rxstate_next;
 
always@(rxstate, get_sfd, local_invalid, len_invalid, recv_enable,
tagged_frame, end_data_cnt, end_tagged_cnt, get_error_code,
end_fcs, length_error, crc_check_valid,crc_check_invalid, reset)begin
if (reset) begin
rxstate_next <=#TP IDLE;
end
else begin
case (rxstate)
IDLE: begin
if (get_sfd & recv_enable)
rxstate_next <=#TP rxReceiveDA;
end
rxReceiveDA: begin
rxstate_next <=#TP rxReceiveLT;
end
rxReceiveLT: begin
rxstate_next <=#TP rxReceiveData;
end
rxReceiveData: begin
if (local_invalid | len_invalid | get_error_code)
rxstate_next <=#TP rxWaitCheck;
else if (end_data_cnt | end_tagged_cnt)
rxstate_next <=#TP rxReceiveFCS;
end
rxReceiveFCS: begin //length_error should have high priority to end_fcs
if (length_error)
rxstate_next <=#TP IDLE;
else if (end_fcs)
rxstate_next <=#TP rxWaitCheck;
end
rxWaitCheck: begin
if (crc_check_valid)
rxstate_next <=#TP IDLE;
else if (local_invalid | len_invalid | length_error | crc_check_invalid)
rxstate_next <=#TP IDLE;
end
endcase
end
end
 
always@(posedge rxclk or posedge reset) begin
if (reset)
rxstate <=#TP IDLE;
else
rxstate <=#TP rxstate_next;
end
 
reg end_small_cnt_d1;
reg end_small_cnt_d2;
always@(posedge rxclk or posedge reset) begin
if (reset)begin
end_small_cnt_d1 <= 0;
end_small_cnt_d2 <= 0;
end
else begin
end_small_cnt_d1 <=end_small_cnt;
if (end_small_cnt_d1)
end_small_cnt_d2 <= 1'b1;
else
end_small_cnt_d2 <= #TP end_small_cnt_d2;
end
end
 
assign start_da = (rxstate == rxReceiveDA);
assign start_lt = (rxstate == rxReceiveLT);
assign start_data_cnt = (rxstate == rxReceiveData) & (~tagged_frame);
assign start_tagged_cnt = (rxstate == rxReceiveData) & tagged_frame;
assign receiving_data = (~rxstate[2]&(rxstate[0] | rxstate[1])); // in DA,LT,DATA status
assign receiving_frame = receiving_data |(rxstate[2]&~rxstate[1]&~rxstate[0]); //in DA,LT,Data,FCS status
assign receiving_small = start_da | start_lt | ((rxstate == rxReceiveData) & ~end_small_cnt_d2);
assign receiving = inband_fcs? receiving_frame:(small_frame? receiving_small:receiving_data);
assign recv_end = ~receiving_frame;
assign bad_frame_get = ((rxstate == rxReceiveFCS) & length_error) | ((rxstate == rxWaitCheck) & (local_invalid | len_invalid | length_error | crc_check_invalid));
assign good_frame_get = (rxstate == rxWaitCheck) & crc_check_valid;
endmodule
/trunk/counter.v
0,0 → 1,42
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:53:19 11/22/05
// Design Name:
// Module Name: counter
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter(clk, reset, load, en, value);
input clk;
input reset;
input load;
input en;
 
parameter WIDTH = 8;
output[WIDTH-1:0] value;
 
reg [WIDTH-1:0] value;
always @(posedge clk or posedge reset)
if (reset)
value <= 0;
else begin
if (load)
value <= 0;
else if (en)
value <= value + 1;
end
endmodule
/trunk/rxReceiveEngine.v
0,0 → 1,180
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:35:47 11/21/05
// Design Name:
// Module Name: rxReceiveEngine
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxReceiveEngine(rxclk_in, reset_in, rxd64, rxc8, rxStatRegPlus,reset_out,
cfgRxRegData, rx_data, rx_data_valid, rx_good_frame, link_fault,
rx_bad_frame, rxCfgofRS, rxTxLinkFaul);
input rxclk_in;
input reset_in;
input [63:0] rxd64;
input [7:0] rxc8;
output reset_out;
output [12:0] rxStatRegPlus;
input [52:0] cfgRxRegData;
output [63:0] rx_data;
output [7:0] rx_data_valid;
output rx_good_frame;
output rx_bad_frame;
input [1:0] link_fault;
output[2:0] rxCfgofRS;
output [1:0] rxTxLinkFaul;
 
wire rxclk;
wire rxclk_180;
wire rxclk_2x;
wire locked;
wire reset_dcm;
wire reset;
 
wire [47:0]MAC_Addr; //MAC Address used in receiving control frame.
wire vlan_enable; //VLAN Enable
wire recv_enable; //Receiver Enable
wire inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
wire jumbo_enable;//Jumbo Frame Enable
wire recv_rst; //Receiver reset
 
wire start_da, start_lt;
wire tagged_frame, small_frame;
wire [15:0] tagged_len;
wire end_data_cnt, end_small_cnt, end_tagged_cnt, end_fcs;
wire pause_frame;
wire [47:0] da_addr;
wire [15:0] lt_data;
wire [31:0] crc_code;
wire [7:0] crc_valid;
wire [7:0] rxc_fifo;
wire length_error;
wire get_sfd, get_efd, get_error_code;
wire receiving;
wire receiving_frame;
 
wire local_invalid;
wire broad_valid;
wire multi_valid;
 
wire len_invalid;
wire [12:0] integer_cnt, small_integer_cnt;
wire [2:0] bits_more, small_bits_more;
wire good_frame_get, bad_frame_get;
 
wire crc_check_valid=0;
wire crc_check_invalid=0;
 
 
//////////////////////////////////////////
// Read Receiver Configuration Word
//////////////////////////////////////////
 
assign MAC_Addr = {cfgRxRegData[52:37], cfgRxRegData[31:0]};
assign vlan_enable = cfgRxRegData[36];
assign recv_enable = cfgRxRegData[35];
assign inband_fcs = cfgRxRegData[34];
assign jumbo_enable = cfgRxRegData[33];
assign recv_rst = cfgRxRegData[32];
assign reset_dcm = reset_in | recv_rst;
assign reset = ~locked;
assign reset_out = reset;
/////////////////////////////////////////
// Write Configuration Words of RS
/////////////////////////////////////////
 
assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault
assign rxCfgofRS[2] = locked; //Receive DCM locked
////////////////////////////////////////
// Receive Clock Generator
////////////////////////////////////////
 
rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
.reset(reset_dcm),
.rxclk(rxclk),
.rxclk_180(rxclk_180),
.rxclk_2x(rxclk_2x),
.locked(locked)
);
 
///////////////////////////////////////
// Upper Interface with client
///////////////////////////////////////
 
rxFIFOMgnt upperinterface(.rxclk_180(rxclk_180), .reset(reset), .rxd64(rxd64), .rxc_fifo(rxc_fifo), .receiving(receiving),
.recv_end(recv_end), .rx_data_valid(rx_data_valid), .inband_fcs(inband_fcs),
.rx_data(rx_data));
 
///////////////////////////////////////
// Reception Frame Spliter
///////////////////////////////////////
 
rxFrameDepart frame_spliter(.rxclk(rxclk), .reset(reset), .rxclk_180(rxclk_180), .rxd64(rxd64), .rxc8(rxc8),.inband_fcs(inband_fcs),
.start_da(start_da), .start_lt(start_lt), .tagged_frame(tagged_frame),.bits_more(bits_more),
.small_bits_more(small_bits_more), .tagged_len(tagged_len), .small_frame(small_frame),
.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt),.da_addr(da_addr),.lt_data(lt_data),
.crc_code(crc_code),.end_fcs(end_fcs), .crc_valid(crc_valid), .length_error(length_error),
.get_sfd(get_sfd), .get_efd(get_efd), .get_error_code(get_error_code),.receiving(receiving),
.rxc_fifo(rxc_fifo),.receiving_frame(receiving_frame)
);
 
//////////////////////////////////////
// Destination Address Checker
//////////////////////////////////////
 
rxDAchecker dachecker(.local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
.da_addr(da_addr));
defparam dachecker.Multicast = 48'h0180C2000001;
defparam dachecker.Broadcast = 48'hffffffffffff;
 
/////////////////////////////////////
// Length/Type field checker
/////////////////////////////////////
 
rxLenTypChecker lenchecker(.lt_data(lt_data), .tagged_len(tagged_len), .jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame),
.pause_frame(pause_frame), .small_frame(small_frame), .len_invalid(len_invalid), .vlan_enable(vlan_enable),
.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .inband_fcs(inband_fcs),
.bits_more(bits_more), .small_bits_more(small_bits_more)
);
 
/////////////////////////////////////
// Counters used in Receive Engine
/////////////////////////////////////
 
rxNumCounter counters(.rxclk(rxclk), .reset(reset), .start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .small_frame(small_frame),
.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .tagged_frame(tagged_frame),
.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt), .end_tagged_cnt(end_tagged_cnt)
);
/////////////////////////////////////
// State Machine in Receive Process
/////////////////////////////////////
 
rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid), .len_invalid(len_invalid),
.end_data_cnt(end_data_cnt), .end_tagged_cnt(end_tagged_cnt), .tagged_frame(tagged_frame),
.length_error(length_error), .end_fcs(end_fcs), .crc_check_valid(crc_check_valid), .get_error_code(get_error_code),
.crc_check_invalid(crc_check_invalid), .start_da(start_da), .start_lt(start_lt), .inband_fcs(inband_fcs),
.start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .receiving(receiving),
.recv_end(recv_end), .good_frame_get(good_frame_get), .bad_frame_get(bad_frame_get), .small_frame(small_frame),
.end_small_cnt(end_small_cnt),.receiving_frame(receiving_frame)
);
assign rx_good_frame = good_frame_get;
assign rx_bad_frame = bad_frame_get;
endmodule
/trunk/dcm0.v
0,0 → 1,106
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1i
// \ \ Application :
// / / Filename : dcm0.v
// /___/ /\ Timestamp : 12/22/2005 09:25:19
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name: dcm0
//
// Module dcm0
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
 
module dcm0(CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT,
CLK180_OUT,
LOCKED_OUT);
 
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
output CLK180_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK2X_BUF;
wire CLK180_BUF;
wire GND;
assign GND = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
.O(CLK2X_OUT));
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
.O(CLK180_OUT));
DCM DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND),
.PSCLK(GND),
.PSEN(GND),
.PSINCDEC(GND),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(CLK180_BUF),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is "2.000000"
// synthesis attribute CLKFX_DIVIDE of DCM_INST is "1"
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is "4"
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is "6.400000"
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute FACTORY_JF of DCM_INST is "C080"
// synthesis attribute PHASE_SHIFT of DCM_INST is "0"
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synopsys translate_off
defparam DCM_INST.CLK_FEEDBACK = "1X";
defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
defparam DCM_INST.CLKFX_DIVIDE = 1;
defparam DCM_INST.CLKFX_MULTIPLY = 4;
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_INST.CLKIN_PERIOD = 6.400000;
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST.FACTORY_JF = 16'hC080;
defparam DCM_INST.PHASE_SHIFT = 0;
defparam DCM_INST.STARTUP_WAIT = "FALSE";
// synopsys translate_on
endmodule
/trunk/rxDAchecker.v
0,0 → 1,44
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:54:17 11/21/05
// Design Name:
// Module Name: rxDAchecker
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
 
 
module rxDAchecker(local_invalid, broad_valid, multi_valid, MAC_Addr, da_addr);
 
output local_invalid;
output broad_valid;
output multi_valid;
 
input [47:0] MAC_Addr;
input [47:0] da_addr;
 
parameter Multicast = 48'h0180C2000001;
parameter Broadcast = 48'hffffffffffff;
 
// check individual MAC address
wire broad_valid_1;
 
assign multi_valid = (da_addr~^Multicast);
assign broad_valid_1 = (da_addr[7:0] ~^ Broadcast[7:0]);
assign broad_valid = broad_valid_1 &(da_addr[47:8] ~^ Broadcast[47:8]);
assign local_invalid = da_addr^MAC_Addr;
 
endmodule
/trunk/rxFIFOMgnt.v
0,0 → 1,63
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:23:08 11/24/05
// Design Name:
// Module Name: rxFIFOMgnt
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxFIFOMgnt(rxclk_180, reset, rxd64, rxc_fifo, inband_fcs, receiving, recv_end, rx_data_valid, rx_data);
input rxclk_180;
input reset;
input [63:0] rxd64;
input [7:0] rxc_fifo;
input receiving;
input recv_end;
input inband_fcs;
 
output[7:0] rx_data_valid;
output[63:0] rx_data;
 
wire rxfifo_full;
wire rxfifo_empty;
wire[7:0] byte_cnt;
wire fifo_rd_en;
wire fifo_wr_en;
 
assign fifo_rd_en = ~rxfifo_empty;
assign fifo_wr_en = receiving & ~recv_end;
rxdatafifo rxdatain(.clk(rxclk_180),
.sinit(reset),
.din(rxd64),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data),
.full(rxfifo_full),
.empty(rxfifo_empty),
.data_count(byte_cnt));
 
rxcntrlfifo rxcntrlin(.clk(rxclk_180),
.sinit(reset),
.din(rxc_fifo),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data_valid),
.full(),
.empty());
 
 
endmodule
/trunk/rxRSIO.v
0,0 → 1,132
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:22:59 12/22/05
// Design Name:
// Module Name: rxRSIO
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`define START 8'hdf
`define PREAMBLE 8'h55
`define SEQUENCE 8'h59
 
module rxRSIO(rxclk_2x, reset, rxd, rxc, rxd64, rxc8, local_fault, remote_fault);
input rxclk_2x;
input reset;
input [0:31] rxd;
input [0:3] rxc;
output [63:0] rxd64;
output [7:0] rxc8;
output local_fault;
output remote_fault;
 
parameter TP =1;
 
wire local_fault, remote_fault;
wire get_align, get_seq;
 
assign get_align = ((rxd[0:7]==`START) & rxc[0]) & ((rxd[8:15]==`PREAMBLE) & ~rxc[1]);
assign get_seq = (rxd[0:7] == `SEQUENCE) & (rxd[8:29] == 0) & (rxc[0:3]== 4'h8) & rxd[31];
assign local_fault = get_seq & ~rxd[30];
assign remote_fault = get_seq & rxd[30];
 
reg ddr_read_en;
always@(posedge rxclk_2x or posedge reset) begin
if (reset)
ddr_read_en<=#TP 0;
else if (get_align)
ddr_read_en <=#TP 0;
else
ddr_read_en<=#TP ~ddr_read_en;
end
 
//rxd ddr io registers
FDCE rxd64_0 (.Q(rxd64[0]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[7])); defparam rxd64_0.INIT = 1'b0;
FDCE rxd64_1 (.Q(rxd64[1]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[6])); defparam rxd64_1.INIT = 1'b0;
FDCE rxd64_2 (.Q(rxd64[2]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[5])); defparam rxd64_2.INIT = 1'b0;
FDCE rxd64_3 (.Q(rxd64[3]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[4])); defparam rxd64_3.INIT = 1'b0;
FDCE rxd64_4 (.Q(rxd64[4]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[3])); defparam rxd64_4.INIT = 1'b0;
FDCE rxd64_5 (.Q(rxd64[5]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[2])); defparam rxd64_5.INIT = 1'b0;
FDCE rxd64_6 (.Q(rxd64[6]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[1])); defparam rxd64_6.INIT = 1'b0;
FDCE rxd64_7 (.Q(rxd64[7]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[0])); defparam rxd64_7.INIT = 1'b0;
FDCE rxd64_8 (.Q(rxd64[8]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[15])); defparam rxd64_8.INIT = 1'b0;
FDCE rxd64_9 (.Q(rxd64[9]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[14])); defparam rxd64_9.INIT = 1'b0;
FDCE rxd64_10 (.Q(rxd64[10]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[13])); defparam rxd64_10.INIT = 1'b0;
FDCE rxd64_11 (.Q(rxd64[11]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[12])); defparam rxd64_11.INIT = 1'b0;
FDCE rxd64_12 (.Q(rxd64[12]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[11])); defparam rxd64_12.INIT = 1'b0;
FDCE rxd64_13 (.Q(rxd64[13]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[10])); defparam rxd64_13.INIT = 1'b0;
FDCE rxd64_14 (.Q(rxd64[14]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[9])); defparam rxd64_14.INIT = 1'b0;
FDCE rxd64_15 (.Q(rxd64[15]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[8])); defparam rxd64_15.INIT = 1'b0;
FDCE rxd64_16 (.Q(rxd64[16]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[23])); defparam rxd64_16.INIT = 1'b0;
FDCE rxd64_17 (.Q(rxd64[17]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[22])); defparam rxd64_17.INIT = 1'b0;
FDCE rxd64_18 (.Q(rxd64[18]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[21])); defparam rxd64_18.INIT = 1'b0;
FDCE rxd64_19 (.Q(rxd64[19]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[20])); defparam rxd64_19.INIT = 1'b0;
FDCE rxd64_20 (.Q(rxd64[20]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[19])); defparam rxd64_20.INIT = 1'b0;
FDCE rxd64_21 (.Q(rxd64[21]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[18])); defparam rxd64_21.INIT = 1'b0;
FDCE rxd64_22 (.Q(rxd64[22]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[17])); defparam rxd64_22.INIT = 1'b0;
FDCE rxd64_23 (.Q(rxd64[23]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[16])); defparam rxd64_23.INIT = 1'b0;
FDCE rxd64_24 (.Q(rxd64[24]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[31])); defparam rxd64_24.INIT = 1'b0;
FDCE rxd64_25 (.Q(rxd64[25]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[30])); defparam rxd64_25.INIT = 1'b0;
FDCE rxd64_26 (.Q(rxd64[26]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[29])); defparam rxd64_26.INIT = 1'b0;
FDCE rxd64_27 (.Q(rxd64[27]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[28])); defparam rxd64_27.INIT = 1'b0;
FDCE rxd64_28 (.Q(rxd64[28]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[27])); defparam rxd64_28.INIT = 1'b0;
FDCE rxd64_29 (.Q(rxd64[29]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[26])); defparam rxd64_29.INIT = 1'b0;
FDCE rxd64_30 (.Q(rxd64[30]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[25])); defparam rxd64_30.INIT = 1'b0;
FDCE rxd64_31 (.Q(rxd64[31]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxd[24])); defparam rxd64_31.INIT = 1'b0;
FDCE rxd64_32 (.Q(rxd64[32]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[7])); defparam rxd64_32.INIT = 1'b0;
FDCE rxd64_33 (.Q(rxd64[33]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[6])); defparam rxd64_33.INIT = 1'b0;
FDCE rxd64_34 (.Q(rxd64[34]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[5])); defparam rxd64_34.INIT = 1'b0;
FDCE rxd64_35 (.Q(rxd64[35]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[4])); defparam rxd64_35.INIT = 1'b0;
FDCE rxd64_36 (.Q(rxd64[36]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[3])); defparam rxd64_36.INIT = 1'b0;
FDCE rxd64_37 (.Q(rxd64[37]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[2])); defparam rxd64_37.INIT = 1'b0;
FDCE rxd64_38 (.Q(rxd64[38]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[1])); defparam rxd64_38.INIT = 1'b0;
FDCE rxd64_39 (.Q(rxd64[39]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[0])); defparam rxd64_39.INIT = 1'b0;
FDCE rxd64_40 (.Q(rxd64[40]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[15])); defparam rxd64_40.INIT = 1'b0;
FDCE rxd64_41 (.Q(rxd64[41]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[14])); defparam rxd64_41.INIT = 1'b0;
FDCE rxd64_42 (.Q(rxd64[42]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[13])); defparam rxd64_42.INIT = 1'b0;
FDCE rxd64_43 (.Q(rxd64[43]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[12])); defparam rxd64_43.INIT = 1'b0;
FDCE rxd64_44 (.Q(rxd64[44]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[11])); defparam rxd64_44.INIT = 1'b0;
FDCE rxd64_45 (.Q(rxd64[45]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[10])); defparam rxd64_45.INIT = 1'b0;
FDCE rxd64_46 (.Q(rxd64[46]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[9])); defparam rxd64_46.INIT = 1'b0;
FDCE rxd64_47 (.Q(rxd64[47]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[8])); defparam rxd64_47.INIT = 1'b0;
FDCE rxd64_48 (.Q(rxd64[48]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[23])); defparam rxd64_48.INIT = 1'b0;
FDCE rxd64_49 (.Q(rxd64[49]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[22])); defparam rxd64_49.INIT = 1'b0;
FDCE rxd64_50 (.Q(rxd64[50]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[21])); defparam rxd64_50.INIT = 1'b0;
FDCE rxd64_51 (.Q(rxd64[51]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[20])); defparam rxd64_51.INIT = 1'b0;
FDCE rxd64_52 (.Q(rxd64[52]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[19])); defparam rxd64_52.INIT = 1'b0;
FDCE rxd64_53 (.Q(rxd64[53]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[18])); defparam rxd64_53.INIT = 1'b0;
FDCE rxd64_54 (.Q(rxd64[54]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[17])); defparam rxd64_54.INIT = 1'b0;
FDCE rxd64_55 (.Q(rxd64[55]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[16])); defparam rxd64_55.INIT = 1'b0;
FDCE rxd64_56 (.Q(rxd64[56]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[31])); defparam rxd64_56.INIT = 1'b0;
FDCE rxd64_57 (.Q(rxd64[57]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[30])); defparam rxd64_57.INIT = 1'b0;
FDCE rxd64_58 (.Q(rxd64[58]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[29])); defparam rxd64_58.INIT = 1'b0;
FDCE rxd64_59 (.Q(rxd64[59]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[28])); defparam rxd64_59.INIT = 1'b0;
FDCE rxd64_60 (.Q(rxd64[60]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[27])); defparam rxd64_60.INIT = 1'b0;
FDCE rxd64_61 (.Q(rxd64[61]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[26])); defparam rxd64_61.INIT = 1'b0;
FDCE rxd64_62 (.Q(rxd64[62]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[25])); defparam rxd64_62.INIT = 1'b0;
FDCE rxd64_63 (.Q(rxd64[63]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxd[24])); defparam rxd64_63.INIT = 1'b0;
 
//rxc ddr io registers
FDCE rxc8_0 (.Q(rxc8[0]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[3])); defparam rxc8_0.INIT = 1'b0;
FDCE rxc8_1 (.Q(rxc8[1]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[2])); defparam rxc8_1.INIT = 1'b0;
FDCE rxc8_2 (.Q(rxc8[2]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[1])); defparam rxc8_2.INIT = 1'b0;
FDCE rxc8_3 (.Q(rxc8[3]), .C(rxclk_2x), .CE(~ddr_read_en), .CLR(reset), .D(rxc[0])); defparam rxc8_3.INIT = 1'b0;
FDCE rxc8_4 (.Q(rxc8[4]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[3])); defparam rxc8_4.INIT = 1'b0;
FDCE rxc8_5 (.Q(rxc8[5]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[2])); defparam rxc8_5.INIT = 1'b0;
FDCE rxc8_6 (.Q(rxc8[6]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[1])); defparam rxc8_6.INIT = 1'b0;
FDCE rxc8_7 (.Q(rxc8[7]), .C(rxclk_2x), .CE(ddr_read_en), .CLR(reset), .D(rxc[0])); defparam rxc8_7.INIT = 1'b0;
 
 
endmodule
/trunk/rxdatafifo.v
0,0 → 1,109
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2005 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rxdatafifo.v when simulating
// the core, rxdatafifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module rxdatafifo(
clk,
sinit,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count);
 
 
input clk;
input sinit;
input [63 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
output [7 : 0] data_count;
 
// synopsys translate_off
 
SYNC_FIFO_V5_0 #(
8, // c_dcount_width
0, // c_enable_rlocs
1, // c_has_dcount
0, // c_has_rd_ack
0, // c_has_rd_err
0, // c_has_wr_ack
0, // c_has_wr_err
1, // c_memory_type
0, // c_ports_differ
1, // c_rd_ack_low
1, // c_rd_err_low
64, // c_read_data_width
256, // c_read_depth
64, // c_write_data_width
256, // c_write_depth
1, // c_wr_ack_low
1) // c_wr_err_low
inst (
.CLK(clk),
.SINIT(sinit),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.RD_ACK(),
.WR_ACK(),
.RD_ERR(),
.WR_ERR());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of rxdatafifo is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rxdatafifo is "black_box"
 
endmodule
 
/trunk/rxtest.v
0,0 → 1,213
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:23:18 12/26/2005
// Design Name: rxReceiveEngine
// Module Name: rxtest.v
// Project Name: ethmac10g
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: rxReceiveEngine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module rxtest_v;
 
// Inputs
reg rxclk_in;
reg reset_in;
reg [63:0] rxd64;
reg [7:0] rxc8;
reg [52:0] cfgRxRegData;
reg [1:0] link_fault;
 
// Outputs
wire [12:0] rxStatRegPlus;
wire [63:0] rx_data;
wire [7:0] rx_data_valid;
wire rx_good_frame;
wire rx_bad_frame;
wire [2:0] rxCfgofRS;
wire [1:0] rxTxLinkFaul;
wire reset_out;
 
// Instantiate the Unit Under Test (UUT)
rxReceiveEngine uut (
.rxclk_in(rxclk_in),
.reset_in(reset_in),
.reset_out(reset_out),
.rxd64(rxd64),
.rxc8(rxc8),
.rxStatRegPlus(rxStatRegPlus),
.cfgRxRegData(cfgRxRegData),
.rx_data(rx_data),
.rx_data_valid(rx_data_valid),
.rx_good_frame(rx_good_frame),
.link_fault(link_fault),
.rx_bad_frame(rx_bad_frame),
.rxCfgofRS(rxCfgofRS),
.rxTxLinkFaul(rxTxLinkFaul)
);
 
initial begin
// Initialize Inputs
rxclk_in = 0;
rxd64 = 0;
rxc8 = 0;
cfgRxRegData = 0;
cfgRxRegData[35] = 1'b1;//recv_enable
cfgRxRegData[36] = 1'b1;//vlan enable
cfgRxRegData[34] = 1'b0;//inband fcs
cfgRxRegData[52:37] = 16'h00c0;
cfgRxRegData[31:0]=32'h9fe22972;
link_fault = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
 
end
 
wire [63:0]testvector1[15:0]; //normal frame
wire [7:0] testvector2[15:0];
wire [63:0]smallvector1[10:0]; //small frame
wire [7:0] smallvector2[10:0];
 
wire [63:0]taggedvector1[15:0];
wire [7:0] taggedvector2[15:0];
 
 
 
assign testvector1[0] = 64'h0707070707070707;
assign testvector1[1] = 64'hfbaaaaaaaaaaaaab;
assign testvector1[2] = 64'h00c09fe229720015;
assign testvector1[3] = 64'h0024ac34004e9889;
// assign testvector1[3] = 64'h0024ac3400639889; //length error frame
assign testvector1[4] = 64'h1234567890123456;
assign testvector1[5] = 64'h7890123456789012;
assign testvector1[6] = 64'h3456789012345678;
assign testvector1[7] = 64'h9012345678901234;
assign testvector1[8] = 64'h5678901234567890;
assign testvector1[9] = 64'h1234567890123456;
assign testvector1[10] = 64'h7890123456789012;
assign testvector1[11] = 64'h3456789012345678;
assign testvector1[12] = 64'h9012345678901234;
assign testvector1[13] = 64'h5678901234555555;
assign testvector1[14] = 64'h55fd070707070707;
assign testvector1[15] = 64'h0707070707070707;
assign testvector2[0] = 8'hff;
assign testvector2[1] = 8'h80;
assign testvector2[2] = 8'h00;
assign testvector2[3] = 8'h00;
assign testvector2[4] = 8'h00;
assign testvector2[5] = 8'h00;
assign testvector2[6] = 8'h00;
assign testvector2[7] = 8'h00;
assign testvector2[8] = 8'h00;
assign testvector2[9] = 8'h00;
assign testvector2[10] = 8'h00;
assign testvector2[11] = 8'h00;
assign testvector2[12] = 8'h00;
assign testvector2[13] = 8'h00;
assign testvector2[14] = 8'h4f;
assign testvector2[15] = 8'hff;
 
assign smallvector1[0] = 64'h0707070707070707;
assign smallvector1[1] = 64'hfbaaaaaaaaaaaaab;
assign smallvector1[2] = 64'h00c09fe229720015;
assign smallvector1[3] = 64'h0024ac3400039889;
assign smallvector1[4] = 64'h1234567890123456;
assign smallvector1[5] = 64'h7890123456789012;
assign smallvector1[6] = 64'h3456789012345678;
assign smallvector1[7] = 64'h9012345678901234;
assign smallvector1[8] = 64'h5678901234567890;
assign smallvector1[9] = 64'h1234567855555555;
assign smallvector1[10] = 64'hfd07070707070707;
 
assign smallvector2[0] = 8'hff;
assign smallvector2[1] = 8'h80;
assign smallvector2[2] = 8'h00;
assign smallvector2[3] = 8'h00;
assign smallvector2[4] = 8'h00;
assign smallvector2[5] = 8'h00;
assign smallvector2[6] = 8'h00;
assign smallvector2[7] = 8'h00;
assign smallvector2[8] = 8'h00;
assign smallvector2[9] = 8'h00;
assign smallvector2[10] = 8'hff;
assign taggedvector1[0] = 64'h0707070707070707;
assign taggedvector1[1] = 64'hfbaaaaaaaaaaaaab;
assign taggedvector1[2] = 64'h00c09fe229720015;
assign taggedvector1[3] = 64'h0024ac348100004f; // assign taggedvector1[3] = 64'h0024ac3400639889; //length error frame
assign taggedvector1[4] = 64'h004f123456789012;
assign taggedvector1[5] = 64'h3456789012345678;
assign taggedvector1[6] = 64'h9012345678901234;
assign taggedvector1[7] = 64'h5678901234567890;
assign taggedvector1[8] = 64'h1234567890123456;
assign taggedvector1[9] = 64'h7890123456789012;
assign taggedvector1[10] = 64'h7890123456789012;
assign taggedvector1[11] = 64'h3456789012345678;
assign taggedvector1[12] = 64'h9012345678901234;
assign taggedvector1[13] = 64'h5678901234567890;
assign taggedvector1[14] = 64'h1255555555fd0707;
assign taggedvector1[15] = 64'h0707070707070707;
assign taggedvector2[0] = 8'hff;
assign taggedvector2[1] = 8'h80;
assign taggedvector2[2] = 8'h00;
assign taggedvector2[3] = 8'h00;
assign taggedvector2[4] = 8'h00;
assign taggedvector2[5] = 8'h00;
assign taggedvector2[6] = 8'h00;
assign taggedvector2[7] = 8'h00;
assign taggedvector2[8] = 8'h00;
assign taggedvector2[9] = 8'h00;
assign taggedvector2[10] = 8'h00;
assign taggedvector2[11] = 8'h00;
assign taggedvector2[12] = 8'h00;
assign taggedvector2[13] = 8'h00;
assign taggedvector2[14] = 8'h07;
assign taggedvector2[15] = 8'hff;
 
initial begin
reset_in = 1;
#100
reset_in = 0;
end
 
always rxclk_in =#5 ~rxclk_in;
 
reg [3:0]i;
always@(posedge rxclk_in or posedge reset_out) begin
if (reset_out) begin
i <= 0;
rxd64 <=0;
rxc8 <=0;
end
else begin
i <= i+1;
rxd64 <=taggedvector1[i];
rxc8 <=taggedvector2[i];
// rxd64 <=testvector1[i];
// rxc8 <=testvector2[i];
// rxd64 <=smallvector1[i];
// rxc8 <=smallvector2[i];
end
end
 
endmodule
 
/trunk/rxRSLayer.v
0,0 → 1,51
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:11:04 12/22/05
// Design Name:
// Module Name: rxRSLayer
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxRSLayer(rxclk_2x, reset, link_fault, rxd64, rxc8, rxd, rxc);
input rxclk_2x;
input reset;
input [31:0] rxd;
input [3:0] rxc;
output [1:0] link_fault;
output [63:0] rxd64;
output [7:0] rxc8;
 
wire local_fault;
wire remote_fault;
wire[1:0] link_fault;
 
rxRSIO datapath(.rxclk_2x(rxclk_2x),
.reset(reset),
.rxd(rxd),
.rxc(rxc),
.rxd64(rxd64),
.rxc8(rxc8),
.local_fault(local_fault),
.remote_fault(remote_fault)
);
rxLinkFaultState statemachine(.rxclk_2x(rxclk_2x),
.reset(reset),
.local_fault(local_fault),
.remote_fault(remote_fault),
.link_fault(link_fault)
);
 
endmodule
/trunk/rxcntrlfifo.v
0,0 → 1,107
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2005 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rxcntrlfifo.v when simulating
// the core, rxcntrlfifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module rxcntrlfifo(
clk,
sinit,
din,
wr_en,
rd_en,
dout,
full,
empty);
 
 
input clk;
input sinit;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
 
// synopsys translate_off
 
SYNC_FIFO_V5_0 #(
1, // c_dcount_width
0, // c_enable_rlocs
0, // c_has_dcount
0, // c_has_rd_ack
0, // c_has_rd_err
0, // c_has_wr_ack
0, // c_has_wr_err
1, // c_memory_type
0, // c_ports_differ
1, // c_rd_ack_low
1, // c_rd_err_low
8, // c_read_data_width
2048, // c_read_depth
8, // c_write_data_width
2048, // c_write_depth
1, // c_wr_ack_low
1) // c_wr_err_low
inst (
.CLK(clk),
.SINIT(sinit),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_ACK(),
.WR_ACK(),
.RD_ERR(),
.WR_ERR(),
.DATA_COUNT());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of rxcntrlfifo is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rxcntrlfifo is "black_box"
 
endmodule
 
/trunk/M2_1E.v
0,0 → 1,34
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:54:49 12/27/05
// Design Name:
// Module Name: M2_1E
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module M2_1E(E, S0, D0, D1, O);
input E;
input S0;
input D0;
input D1;
output O;
 
wire M0,M1;
assign M0 = D0 & ~S0 & E;
assign M1 = D1 & S0 & E;
assign O = M0 | M1;
 
 
endmodule
/trunk/rxFrameDepart.v
0,0 → 1,303
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:45:58 12/13/05
// Design Name:
// Module Name: rxFrameDepart
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
`define START 8'hfb
`define TERMINATE 8'hfd
`define SFD 8'b10101011
`define SEQUENCE 8'h9c
`define ERROR 8'hfe
`define ALLONES 8'hff
`define ALLZEROS 8'h00
 
module rxFrameDepart(rxclk, reset, rxclk_180, rxd64, rxc8, start_da, start_lt, tagged_frame,
bits_more, small_bits_more, tagged_len, small_frame, end_data_cnt,inband_fcs,
end_small_cnt, da_addr, lt_data, crc_code, end_fcs, crc_valid, length_error,
get_sfd, get_efd, get_error_code,receiving, rxc_fifo, receiving_frame);
input rxclk;
input reset;
input rxclk_180;
input [63:0] rxd64;
input [7:0] rxc8;
 
input start_da;
input start_lt;
input tagged_frame;
input [2:0] bits_more;
input [2:0] small_bits_more;
input small_frame;
input end_data_cnt;
input end_small_cnt;
input inband_fcs;
input receiving;
input receiving_frame;
 
output[7:0] rxc_fifo;
output[47:0] da_addr; //destination address won't be changed until start_da was changed again
output[15:0] lt_data; //(Length/Type) field won't be changed until start_lt was changed again
output[15:0] tagged_len;
output[31:0] crc_code;
output end_fcs;
output[7:0] crc_valid;
output length_error;
 
output get_sfd;
output get_efd;
output get_error_code;
 
parameter TP = 1;
 
//////////////////////////////////////////
// Get Control Characters
//////////////////////////////////////////
wire get_sfd;
wire[7:0] get_t_chk;
wire get_efd;
wire get_error_code;
wire[7:0] get_e_chk;
 
//1. SFD
assign get_sfd = ~(rxd64[63:56] ^ `START) & ~(rxd64[7:0] ^ `SFD) & ~(rxc8 ^ 8'h80);
 
//2. EFD
assign get_t_chk[0] = rxc8[0] & (rxd64[7:0] ~^ `TERMINATE );
assign get_t_chk[1] = rxc8[1] & (rxd64[15:8] ~^ `TERMINATE );
assign get_t_chk[2] = rxc8[2] & (rxd64[23:16] ~^ `TERMINATE );
assign get_t_chk[3] = rxc8[3] & (rxd64[31:24] ~^ `TERMINATE );
assign get_t_chk[4] = rxc8[4] & (rxd64[39:32] ~^ `TERMINATE );
assign get_t_chk[5] = rxc8[5] & (rxd64[47:40] ~^ `TERMINATE );
assign get_t_chk[6] = rxc8[6] & (rxd64[55:48] ~^ `TERMINATE );
assign get_t_chk[7] = rxc8[7] & (rxd64[63:56] ~^ `TERMINATE );
assign get_efd = | get_t_chk;
 
//3. Error Character
assign get_e_chk[0] = rxc8[0] & (rxd64[7:0] ^`TERMINATE);
assign get_e_chk[1] = rxc8[1] & (rxd64[15:8] ^`TERMINATE);
assign get_e_chk[2] = rxc8[2] & (rxd64[23:16]^`TERMINATE);
assign get_e_chk[3] = rxc8[3] & (rxd64[31:24]^`TERMINATE);
assign get_e_chk[4] = rxc8[4] & (rxd64[39:32]^`TERMINATE);
assign get_e_chk[5] = rxc8[5] & (rxd64[47:40]^`TERMINATE);
assign get_e_chk[6] = rxc8[6] & (rxd64[55:48]^`TERMINATE);
assign get_e_chk[7] = rxc8[7] & (rxd64[63:56]^`TERMINATE);
assign get_error_code = | get_e_chk;
//////////////////////////////////////
// Get Destination Address
//////////////////////////////////////
 
reg[47:0] da_addr;
always@(posedge rxclk_180 or posedge reset)begin
if (reset)
da_addr <=#TP 0;
else if (start_da)
da_addr <=#TP rxd64[63:16];
else
da_addr <=#TP da_addr;
end
 
//////////////////////////////////////
// Get Length/Type Field
//////////////////////////////////////
 
reg[15:0] lt_data;
always@(posedge rxclk_180 or posedge reset)begin
if (reset)
lt_data <=#TP 0;
else if (start_lt)
lt_data <=#TP rxd64[31:16];
else if(~receiving_frame)
lt_data <=#TP 16'h0500;
else
lt_data <=#TP lt_data;
end
 
///////////////////////////////////////
// Get Tagged Frame Length
///////////////////////////////////////
 
reg tagged_frame_d1;
always@(posedge rxclk_180) begin
tagged_frame_d1<=#TP tagged_frame;
end
 
reg[15:0] tagged_len;
always@(posedge rxclk_180 or posedge reset) begin
if (reset)
tagged_len <=#TP 0;
else if(~tagged_frame_d1 & tagged_frame)
tagged_len <=#TP rxd64[63:48];
else if(~receiving_frame)
tagged_len <=#TP 16'h0500;
else
tagged_len <=#TP tagged_len;
end
 
////////////////////////////////////////
// Get FCS Field and Part of DATA
////////////////////////////////////////
wire [7:0]special;
 
wire[31:0] crc_code;
wire end_fcs;
wire[7:0] crc_valid;
wire length_error;
wire[7:0] tmp_crc_data[31:0];
wire[31:0] crc_code_tmp1;
wire[31:0] crc_code_tmp;
wire[4:0] shift_tmp;
wire next_cycle;
reg end_data_cnt_d1;
 
always@(posedge rxclk or posedge reset) begin
if (reset)
end_data_cnt_d1<= #TP 0;
else
end_data_cnt_d1<= #TP end_data_cnt;
end
 
reg[31:0] crc_code_tmp_d1;
always@(posedge rxclk or posedge reset) begin
if (reset)
crc_code_tmp_d1<= #TP 0;
else
crc_code_tmp_d1 <=#TP crc_code_tmp;
end
assign shift_tmp = (8-bits_more)<<3;
assign special = `ALLONES >> bits_more;
assign crc_code_tmp1 = rxd64[63:32] >> shift_tmp;
assign next_cycle = bits_more[2]&(bits_more[1] | bits_more[0]);
assign crc_valid = end_data_cnt? ~special: `ALLONES;
assign end_fcs = end_data_cnt_d1;
//timing constraint should be added here to make length_error be valid earlier than end_fcs
assign length_error = (end_data_cnt &(((bits_more == 0) & ~get_t_chk[3]) |
((bits_more == 1) & ~get_t_chk[2]) |
((bits_more == 2) & ~get_t_chk[1]) |
((bits_more == 3) & ~get_t_chk[0])))|
(end_data_cnt_d1 &(((bits_more == 4) & ~get_t_chk[7]) |
((bits_more == 5) & ~get_t_chk[6]) |
((bits_more == 6) & ~get_t_chk[5]) |
((bits_more == 7) & ~get_t_chk[4])));
 
assign tmp_crc_data[31] = {rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47],rxd64[55],rxd64[63]};
assign tmp_crc_data[30] = {rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46],rxd64[54],rxd64[62]};
assign tmp_crc_data[29] = {rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45],rxd64[53],rxd64[61]};
assign tmp_crc_data[28] = {rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44],rxd64[52],rxd64[60]};
assign tmp_crc_data[27] = {rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43],rxd64[51],rxd64[59]};
assign tmp_crc_data[26] = {rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42],rxd64[50],rxd64[58]};
assign tmp_crc_data[25] = {rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41],rxd64[49],rxd64[57]};
assign tmp_crc_data[24] = {rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40],rxd64[48],rxd64[56]};
assign tmp_crc_data[23] = {1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47],rxd64[55]};
assign tmp_crc_data[22] = {1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46],rxd64[54]};
assign tmp_crc_data[21] = {1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45],rxd64[53]};
assign tmp_crc_data[20] = {1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44],rxd64[52]};
assign tmp_crc_data[19] = {1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43],rxd64[51]};
assign tmp_crc_data[18] = {1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42],rxd64[50]};
assign tmp_crc_data[17] = {1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41],rxd64[49]};
assign tmp_crc_data[16] = {1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40],rxd64[48]};
assign tmp_crc_data[15] = {1'b0,1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39],rxd64[47]};
assign tmp_crc_data[14] = {1'b0,1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38],rxd64[46]};
assign tmp_crc_data[13] = {1'b0,1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37],rxd64[45]};
assign tmp_crc_data[12] = {1'b0,1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36],rxd64[44]};
assign tmp_crc_data[11] = {1'b0,1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35],rxd64[43]};
assign tmp_crc_data[10] = {1'b0,1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34],rxd64[42]};
assign tmp_crc_data[9] = {1'b0,1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33],rxd64[41]};
assign tmp_crc_data[8] = {1'b0,1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32],rxd64[40]};
assign tmp_crc_data[7] = {1'b0,1'b0,1'b0,rxd64[7],rxd64[15],rxd64[23],rxd64[31],rxd64[39]};
assign tmp_crc_data[6] = {1'b0,1'b0,1'b0,rxd64[6],rxd64[14],rxd64[22],rxd64[30],rxd64[38]};
assign tmp_crc_data[5] = {1'b0,1'b0,1'b0,rxd64[5],rxd64[13],rxd64[21],rxd64[29],rxd64[37]};
assign tmp_crc_data[4] = {1'b0,1'b0,1'b0,rxd64[4],rxd64[12],rxd64[20],rxd64[28],rxd64[36]};
assign tmp_crc_data[3] = {1'b0,1'b0,1'b0,rxd64[3],rxd64[11],rxd64[19],rxd64[27],rxd64[35]};
assign tmp_crc_data[2] = {1'b0,1'b0,1'b0,rxd64[2],rxd64[10],rxd64[18],rxd64[26],rxd64[34]};
assign tmp_crc_data[1] = {1'b0,1'b0,1'b0,rxd64[1],rxd64[9],rxd64[17],rxd64[25],rxd64[33]};
assign tmp_crc_data[0] = {1'b0,1'b0,1'b0,rxd64[0],rxd64[8],rxd64[16],rxd64[24],rxd64[32]};
 
M8_1E crc31(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[31]), .O(crc_code_tmp[31]));
M8_1E crc30(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[30]), .O(crc_code_tmp[30]));
M8_1E crc29(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[29]), .O(crc_code_tmp[29]));
M8_1E crc28(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[28]), .O(crc_code_tmp[28]));
M8_1E crc27(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[27]), .O(crc_code_tmp[27]));
M8_1E crc26(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[26]), .O(crc_code_tmp[26]));
M8_1E crc25(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[25]), .O(crc_code_tmp[25]));
M8_1E crc24(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[24]), .O(crc_code_tmp[24]));
M8_1E crc23(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[23]), .O(crc_code_tmp[23]));
M8_1E crc22(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[22]), .O(crc_code_tmp[22]));
M8_1E crc21(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[21]), .O(crc_code_tmp[21]));
M8_1E crc20(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[20]), .O(crc_code_tmp[20]));
M8_1E crc19(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[19]), .O(crc_code_tmp[19]));
M8_1E crc18(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[18]), .O(crc_code_tmp[18]));
M8_1E crc17(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[17]), .O(crc_code_tmp[17]));
M8_1E crc16(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[16]), .O(crc_code_tmp[16]));
M8_1E crc15(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[15]), .O(crc_code_tmp[15]));
M8_1E crc14(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[14]), .O(crc_code_tmp[14]));
M8_1E crc13(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[13]), .O(crc_code_tmp[13]));
M8_1E crc12(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[12]), .O(crc_code_tmp[12]));
M8_1E crc11(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[11]), .O(crc_code_tmp[11]));
M8_1E crc10(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[10]), .O(crc_code_tmp[10]));
M8_1E crc9(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[9]), .O(crc_code_tmp[9]));
M8_1E crc8(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[8]), .O(crc_code_tmp[8]));
M8_1E crc7(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[7]), .O(crc_code_tmp[7]));
M8_1E crc6(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[6]), .O(crc_code_tmp[6]));
M8_1E crc5(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[5]), .O(crc_code_tmp[5]));
M8_1E crc4(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[4]), .O(crc_code_tmp[4]));
M8_1E crc3(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[3]), .O(crc_code_tmp[3]));
M8_1E crc2(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[2]), .O(crc_code_tmp[2]));
M8_1E crc1(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[1]), .O(crc_code_tmp[1]));
M8_1E crc0(.E(end_data_cnt), .S(bits_more), .D(tmp_crc_data[0]), .O(crc_code_tmp[0]));
 
assign crc_code =next_cycle ? (crc_code_tmp_d1 | crc_code_tmp1): crc_code_tmp;
 
/////////////////////////////////////////////////////////////////////////////////
// Generate proper rxc to FIFO //
/////////////////////////////////////////////////////////////////////////////////
 
// FCS is provided by client, inband_fcs is valid
// receiving end_data_cnt end_fcs
// frame: |<------ Data ------>|<-- bits_more -->|<-- FCS -->|<--------
// rxc : |<------------------- all_one -------------------->|<--------all_zero
// |<--- 8bits, with 1s & 0s --->|
 
// FCS is provided by logic, inband_fcs is invalid
// receiving end_data_cnt end_fcs
// frame: |<------ Data ------>|<-- bits_more -->|<-- FCS -->|
// rxc : |<-------------- all_one ------------->|<----- all_zero
// |<-- 8bits, with 1s & 0s --->|
 
// receiving end_small_cnt end_fcs
// frame: |<------ Data ------>|<-- small_bits_more -->|<-- PAD -->|<-- FCS -->|
// rxc : |<----------------- all_one ---------------->|<----- all_zero
// |<-------- 1s --------->|<----- 0s
wire [7:0]rxc_pad;
wire [7:0]rxc_end_data;
wire [7:0]rxc_fcs;
wire [7:0]rxc_final[2:0];
wire [7:0]rxc_fifo; //rxc send to fifo
 
assign rxc_pad = ~(`ALLONES >> small_bits_more);
assign rxc_end_data = ~special;
assign rxc_fcs =~(bits_more[2]?(`ALLONES >> {1'b0,bits_more[1:0]}) : (`ALLONES >> {1'b1,bits_more[1:0]}));
 
assign rxc_final[0] = receiving? (((end_data_cnt & ~next_cycle) | (end_data_cnt_d1 & next_cycle))? rxc_fcs: `ALLONES): `ALLZEROS;
assign rxc_final[1] = receiving? (end_data_cnt? rxc_end_data: `ALLONES): `ALLZEROS;
assign rxc_final[2] = receiving? (end_small_cnt?rxc_pad: `ALLONES): `ALLZEROS;
assign rxc_fifo = inband_fcs? rxc_final[0]: (small_frame? rxc_final[2]: rxc_final[1]);
endmodule
/trunk/rxLinkFaultState.v
0,0 → 1,122
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:11:43 12/19/05
// Design Name:
// Module Name: rxLinkFaultState
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rxLinkFaultState(rxclk_2x, reset, local_fault, remote_fault, link_fault);
input rxclk_2x;
input reset;
input local_fault;
input remote_fault;
output[1:0] link_fault;
parameter TP =1;
parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
 
//------------------------------------------------
// Link Fault Signalling Statemachine
//------------------------------------------------
wire fault_type;
wire get_one_fault;
wire no_new_type;
 
reg[2:0] linkstate;
reg[7:0] col_cnt;
reg[1:0] seq_cnt;
reg[1:0] seq_type;
reg[1:0] last_seq_type;
reg[1:0] link_fault;
reg reset_col_cnt;
 
assign fault_type = {local_fault, remote_fault};
assign get_one_fault = local_fault | remote_fault;
assign no_new_type = (seq_type == last_seq_type);
assign col_cnt_128 = (col_cnt == 127);
 
always@(posedge rxclk_2x or posedge reset)begin
if (reset) begin
seq_type <=#TP 0;
seq_cnt <=#TP 0;
last_seq_type <=#TP 0;
reset_col_cnt<= #TP 1;
link_fault <=#TP 2'b00;
linkstate<= #TP IDLE;
end
else begin
seq_type <= #TP fault_type;
last_seq_type <=#TP seq_type;
case (linkstate)
IDLE: begin
linkstate <=#TP IDLE;
reset_col_cnt <= #TP 1;
seq_cnt <= #TP 0;
link_fault <= #TP 2'b00;
if (get_one_fault)
linkstate<=#TP LinkFaultDetect;
end
 
LinkFaultDetect: begin
linkstate <=#TP LinkFaultDetect;
reset_col_cnt <=#TP 1;
if (get_one_fault & no_new_type)
if (seq_cnt < 3)
seq_cnt <=#TP seq_cnt + 1;
else linkstate <=#TP GetFault;
else if(~get_one_fault)
if(col_cnt_128) begin
linkstate <=#TP IDLE;
reset_col_cnt <=#TP 1;
end
else reset_col_cnt <=#TP 0;
else if(get_one_fault & ~no_new_type)
linkstate <=#TP NewFaultType;
end
 
NewFaultType: begin
seq_cnt <=#TP 0;
linkstate <=#TP LinkFaultDetect;
reset_col_cnt<=#TP 1;
end
 
GetFault: begin
linkstate <=#TP GetFault;
reset_col_cnt <=#TP 1;
if (get_one_fault & no_new_type)
link_fault <=#TP seq_type;
else if (~get_one_fault) begin
reset_col_cnt<=#TP 0;
if(col_cnt_128)
linkstate <=#TP IDLE;
end
else if (get_one_fault & ~no_new_type)
linkstate <=#TP NewFaultType;
end
endcase
end
end
 
always@(posedge rxclk_2x or posedge reset) begin
if (reset)
col_cnt <=#TP 0;
else if (reset_col_cnt)
col_cnt <=#TP 0;
else
col_cnt <=#TP col_cnt + 1;
end
 
endmodule
/trunk/rxNumCounter.v
0,0 → 1,67
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:58 11/24/05
// Design Name:
// Module Name: rxNumCounter
// Project Name:
// Target Device:
// Tool versions:
// Description: This module only deals with cycles with 64bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module rxNumCounter(rxclk, reset, start_data_cnt, start_tagged_cnt, small_frame,
integer_cnt, small_integer_cnt, end_data_cnt, tagged_frame,
end_small_cnt, end_tagged_cnt);
input rxclk; //receive clk
input reset; //globe reset
 
input start_data_cnt; //start to count data field
input start_tagged_cnt; //start to count tagged frame
 
input small_frame;
input tagged_frame;
 
input[12:0] integer_cnt; //number of 64bits DATA field contains
input[12:0] small_integer_cnt;//number of 64bits real DATA field contains(without pad part)
 
output end_data_cnt; //end of data field(only 64bits aligned data)
output end_small_cnt; //end of true data field of small frame(only 64bits aligned data)
output end_tagged_cnt; //end of true data field of tagged frame(only 64bits aligned data)
wire end_cnt;
wire[12:0] data_cnt;
wire[12:0] tagged_data_cnt;
wire end_normal_data_cnt;
 
// Data counter
// used in rxReceiveData field,
// this counter is used for frames whose length is larger than 64
// Of course it also count actual bytes of frames whose length is shorter than 64.
counter data_counter(.clk(rxclk), .reset(reset), .load(end_cnt), .en(start_data_cnt), .value(data_cnt));
defparam data_counter.WIDTH = 13;
counter tagged_counter(.clk(rxclk), .reset(reset), .load(end_tagged_cnt), .en(start_tagged_cnt), .value(tagged_data_cnt));
defparam tagged_counter.WIDTH = 13;
 
assign end_cnt = end_data_cnt | start_tagged_cnt | ~start_data_cnt;
 
assign end_normal_data_cnt = (data_cnt == integer_cnt);
 
assign end_small_cnt = small_frame & (data_cnt == small_integer_cnt);
 
assign end_tagged_cnt = tagged_frame & (tagged_data_cnt == integer_cnt);
 
assign end_data_cnt = end_tagged_cnt | end_normal_data_cnt;
 
endmodule
/trunk/M8_1E.v
0,0 → 1,39
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:53:07 12/27/05
// Design Name:
// Module Name: M8_1E
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module M8_1E(E, S, D, O);
input E;
input [2:0] S;
input [7:0] D;
output O;
 
wire M01, M23, M45, M67;
M2_1E m01(.E(E), .S0(S[0]), .D0(D[0]), .D1(D[1]), .O(M01));
M2_1E m23(.E(E), .S0(S[0]), .D0(D[2]), .D1(D[3]), .O(M23));
M2_1E m45(.E(E), .S0(S[0]), .D0(D[4]), .D1(D[5]), .O(M45));
M2_1E m67(.E(E), .S0(S[0]), .D0(D[6]), .D1(D[7]), .O(M67));
MUXF5_L m03(.LO(M03), .I0(M01), .I1(M23), .S(S[1]));
MUXF5_L m47(.LO(M47), .I0(M45), .I1(M67), .S(S[1]));
MUXF6 m07(.O(O), .I0(M03), .I1(M47), .S(S[2]));
 
 
endmodule
/trunk/rxLenTypChecker.v
0,0 → 1,90
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:23:10 11/21/05
// Design Name:
// Module Name: rxLenTypChecker
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Length/Type:
// 1. <64: Length, we should remove PAD
// 2. >=64, <= 1518: Length, valid frame, we don't need remove PAD(0x2E, 0x5DC)
// 3. >=1518: <9k+18: Length, jumbo frame, if supported (0x5DC, 0x2400)
// 4. >9k+18, = 0x8100: Type, Tagged frame
// 5. >9k+18, = 0x8808: Type, pause frame
 
// |<------------------------------ Data Field ---------------------------->|
// |<------------- True Data Field --------------> <-----Padded bits------->|
// |____________________________|_________________|
// | | |
// | small_integer_cnt * 64 | small_bits_more |
// |____________________________|_________________|____
// |___________________________________________________|_____________________
// | | |
// | integer_cnt * 64 | bits_more |
// |___________________________________________________|____________________|
 
 
////////////////////////////////////////////////////////////////////////////////
 
module rxLenTypChecker(lt_data, tagged_len, jumbo_enable, tagged_frame, pause_frame, small_frame,
len_invalid, integer_cnt, small_integer_cnt, bits_more, inband_fcs,
small_bits_more, vlan_enable );
input[15:0] lt_data; //Length or Type field of a frame
input[15:0] tagged_len; //Actual length carried with tagged frame
input jumbo_enable; //Enable jumbo frame recieving
input inband_fcs; //In-band FCS
input vlan_enable; //VLAN mode enable bit
 
output pause_frame; //Indicate that current frame is a pause frame (a kind of control frame)
output small_frame;
output len_invalid; //Indicate that current frame is not an valid frame
 
output[12:0] integer_cnt; //number of 64bits DATA field contains
output[12:0] small_integer_cnt; //number of 64bits real DATA field contains(without pad part)
output tagged_frame; //number of 64bits DATA field of tagged frame contains
output[2:0] bits_more; //number that is less than 64bits(whole data field)
output[2:0] small_bits_more; //number that is less than 64bits(unpadded data field)
 
wire[15:0] current_len;
wire[15:0] current_cnt;
wire small_frame;
wire tagged_frame;
 
parameter TP =1 ;
 
assign current_len = tagged_frame?(tagged_len+2):(lt_data-2); //Data field length
 
assign current_cnt = current_len >> 3; //the number of 64bits data field has
 
assign padded_frame = (current_len[15:6]==0) & (~current_len[5] | (current_len[5] & ~current_len[4]));
 
assign small_frame = padded_frame & ~inband_fcs; //padded frame
 
assign bits_more = padded_frame? 4 :current_len[2:0]; // bits that is not 64bits enough
 
assign small_bits_more = current_len[2:0];// for situation smaller than 64
 
assign integer_cnt = padded_frame? 5 :current_cnt[12:0];
 
assign small_integer_cnt = current_cnt[12:0];
assign tagged_frame = (lt_data==16'h8100) & vlan_enable;
 
assign pause_frame = (lt_data==16'h8808);
 
assign len_invalid = ((~jumbo_enable & (lt_data > 1500)) & ~(tagged_frame|pause_frame)) | (~vlan_enable & tagged_frame);
//not a large frame(except LT is type interpretion) when jumbo is not enabled, not a tagged frame when vlan is not enbaled
endmodule

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