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URL https://opencores.org/ocsvn/gfir/gfir/trunk

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Rev 3 → Rev 4

/gfir/trunk/vhdl/ghdl.tcl
0,0 → 1,4
ghdl -i -v --ieee=standard -fexplicit --std=93c --warn-no-vital-generic --workdir=simu --work=work src/*.vhd testbench/fir_filter_stage_tb.vhd
ghdl -m -v --ieee=synopsys -fexplicit --std=93c --warn-no-vital-generic --workdir=simu --work=work fir_filter_stage_tb
ghdl -r -v fir_filter_stage_tb --stop-time=500ns --vcd=output.vcd
gtkwave output.vcd &
/gfir/trunk/vhdl/testbench/data.txt
0,0 → 1,16
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/gfir/trunk/vhdl/testbench/fir_filter_stage_tb.vhd
0,0 → 1,91
----------
--! @file
--! @brief The top-level test-bench.
----------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_integer, conv_signed
library work;
use work.tb_pack.all;
use work.fir_pkg.all;
library std;
use std.textio.all; -- write, writeline
 
entity fir_filter_stage_tb is
end fir_filter_stage_tb;
 
architecture tb of fir_filter_stage_tb is
 
constant clockperiod : time := 10 ns; --! Clock period
 
component fir_filter_stage_TF
port (fir_clk, fir_clr : in std_logic;
fir_in : in std_logic_vector(0 downto 0);
fir_out : out std_logic_vector(14 downto 0));
end component;
signal fir_clk, fir_clr : std_logic;
signal fir_in : std_logic_vector(0 downto 0);
signal fir_out : std_logic_vector(14 downto 0);
signal read_flag : std_ulogic;
signal write_finished, read_finished : std_ulogic := '0';
-- Internal deibugging signals
signal multi_add : std_logic_vector((order-1)*width_out-1 downto 0);
signal add_delay : std_logic_vector((order-2)*width_out-1 downto 0);
signal delay_add : std_logic_vector((order-1)*width_out-1 downto 0);
signal multi_delay : std_logic_vector(width_out-1 downto 0);
 
begin
 
process
begin
fir_in <= (others => '0');
wait until read_flag = '1';
ReadData ( "./testbench/data.txt", fir_in, fir_clk, read_finished); --! Input file for stimuli bit-stream
end process;
 
multi_add <= g_multi_add;
add_delay <= g_add_delay;
delay_add <= g_delay_add;
multi_delay <= g_multi_delay;
 
ExportOutput: process
file wr_file : text open write_mode is "./fir_filter_ouput.txt"; --! Output file
variable export_vector : integer;
variable export_line : line;
begin
wait until rising_edge(fir_clk);
export_vector := conv_integer(conv_signed(unsigned(fir_out),fir_out'length));
write(export_line, export_vector);
writeline(wr_file, export_line);
end process;
DUT : fir_filter_stage_TF
port map(
fir_clk => fir_clk,
fir_clr => fir_clr,
fir_in => fir_in,
fir_out => fir_out
);
process
begin
fir_clr <= '1'; read_flag <= '0';
wait for 43 ns;
fir_clr <= '0'; read_flag <= '1';
wait for 43 ns;
fir_clr <= '0'; read_flag <= '1';
wait for 500 ns;
end process;
process
begin
wait for (clockperiod/2);
fir_clk <= '1';
wait for (clockperiod/2);
fir_clk <= '0';
end process;
 
end tb;
/gfir/trunk/vhdl/src/multiplier_gen.vhd
0,0 → 1,27
----------
--! @file
--! @brief This is signed constant multiplier with unsigned input port.
----------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
 
ENTITY multiplier_gen IS
generic (multi_width_const : natural;
multi_width_in : natural);
port (multiplier_const : in std_logic_vector(multi_width_const-1 downto 0); --! Constant multiplier hardwired to the filter coefficient
multiplier_in : in std_logic_vector(multi_width_in-1 downto 0); --! Constant multiplier input port with variable bit-width
multiplier_out : out std_logic_vector((multi_width_const+multi_width_in)+1 downto 0)); --! Constant multiplier output port
END ENTITY multiplier_gen;
 
--
ARCHITECTURE behave OF multiplier_gen IS
signal tmp_multiplier_out : std_logic_vector((multi_width_const+multi_width_in) downto 0);
signal tmp_msb : std_logic;
BEGIN
tmp_multiplier_out <= unsigned(multiplier_in) * signed(multiplier_const);
tmp_msb <= tmp_multiplier_out(tmp_multiplier_out'left);
multiplier_out <= tmp_msb&tmp_multiplier_out;
END ARCHITECTURE behave;
 
/gfir/trunk/vhdl/src/fir_filter_stage_DF.vhd
0,0 → 1,142
---------------------------------------------------------------------------------------------------
--! @file
--! @brief This is the top-level design for a direct-form FIR digital filter. \n
--! @details It instantiate the three major components for constructing a digital filter such as;\n
--! adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen). \n
--! The top-level is a structural description in a generic/scalable form. \n
--! The filter coefficients and the quantization bit width should be edited/pasted \n
--! into the fir_pkg.vhd. The filter coefficients should be given in integer format. \n
--! Design specs: \n
--! Unsigned single/multi-bit input (fir_in) \n
--! Signed multi-bit output (fir_out) \n
--! Active high asynchronous reset (fir_clr) \n
--! Rising edge clock (fir_clk) \n
--
--! @image html firDF.png "Direct-form FIR Filter Structure"
--
--! @author Ahmed Shahein
--! @email ahmed.shahein@ieee.org
--! @date 04.2012
---------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.fir_pkg.all;
 
ENTITY fir_filter_stage_DF IS
port (fir_clk : in std_logic; --! Rising edge clock
fir_clr : in std_logic; --! Active high asynchronous reset
fir_in : in std_logic_vector(0 downto 0); --! Unsigned single/multi-bit input
fir_out : out std_logic_vector(14 downto 0)); --! Signed multi-bit output
END ENTITY fir_filter_stage_DF;
 
--
ARCHITECTURE struct OF fir_filter_stage_DF IS
-- COMPONENT DECLARATION
component multiplier_gen
generic (multi_width_const : natural;
multi_width_in : natural);
port (multiplier_const : in std_logic_vector(multi_width_const-1 downto 0);
multiplier_in : in std_logic_vector(multi_width_in-1 downto 0);
multiplier_out : out std_logic_vector((multi_width_const+multi_width_in)+1 downto 0));
end component;
 
component adder_gen
generic (add_width : natural);
port (add_a_in : in std_logic_vector(add_width-1 downto 0);
add_b_in : in std_logic_vector(add_width-1 downto 0);
add_out : out std_logic_vector(add_width-1 downto 0));
end component;
 
component delay_gen
generic (delay_width : natural);
port (clk, clr : in std_logic;
delay_in : in std_logic_vector(delay_width-1 downto 0);
delay_out : out std_logic_vector(delay_width-1 downto 0));
end component;
 
-- CONSTANT DECLARATION
constant coeff : int_vector := fir_coeff_thirdstage; --! Filter coefficients defined in the fir_pkg.vhd
constant width_in : natural := fir_in'length; --! Input bit-width
constant width_out : natural := fir_out'length; --! Output bit-width
constant width_const : positive := quantization; --! Quantization bit-width defined in the fir_pkg.vhd
constant order : natural := coeff'length; --! Filter length
 
-- SIGNAL DECLARATION
signal multi_add : std_logic_vector(order*width_out-1 downto 0); --! Internal signal holding multiplier's outputs and adder's inputs
signal add_add : std_logic_vector((order-1)*width_out-1 downto 0); --! Internal signal holding preced adder output and proceed adder input
signal delay_multi : std_logic_vector((order-1)*width_in-1 downto 0); --! Internal signal holding delay's output and multiplier's inputs
 
BEGIN
COEFFMULTIs: for i in 0 to order-1 generate --! Generate the filter multipliers set
FirstMULT: if i = 0 generate
MULTI: multiplier_gen
generic map(multi_width_const => width_const,
multi_width_in => width_in)
port map(
multiplier_const => conv_std_logic_vector(coeff(i), width_const),
multiplier_in => fir_in,
multiplier_out => multi_add((i+1)*width_out-1 downto i*width_out)
);
end generate;
InterMULTs: if i > 0 generate
MULTIs: multiplier_gen
generic map(multi_width_const => width_const,
multi_width_in => width_in)
port map(
multiplier_const => conv_std_logic_vector(coeff(i), width_const),
multiplier_in => delay_multi(i*width_in-1 downto (i-1)*width_in),
multiplier_out => multi_add((i+1)*width_out-1 downto i*width_out)
);
end generate;
end generate;
COEFFDELAY: for i in 1 to order-1 generate --! Generate the filter delays set
DELAY: if i = 1 generate
FirstDELAY: delay_gen
generic map(delay_width => width_in)
port map(
clr => fir_clr,
delay_in => fir_in,
delay_out => delay_multi(i*width_in-1 downto (i-1)*width_in),
clk => fir_clk
);
end generate;
InterDElAYs: if i > 1 generate
DELAYs: delay_gen
generic map(delay_width => width_in)
port map(
clr => fir_clr,
delay_in => delay_multi((i-1)*width_in-1 downto (i-2)*width_in),
delay_out => delay_multi(i*width_in-1 downto (i-1)*width_in),
clk => fir_clk
);
end generate;
end generate;
COEFFADD: for i in 1 to order-1 generate --! Generate the filter adders set
FirstADDER: if i = 1 generate
ADDER0: adder_gen
generic map(add_width => width_out)
port map(
add_a_in => multi_add((i+1)*width_out-1 downto i*width_out), -- from multipliers
add_b_in => multi_add(i*width_out-1 downto (i-1)*width_out),
add_out => add_add(i*width_out-1 downto (i-1)*width_out)
);
end generate;
InterADDER: if i > 1 generate
ADDERs: adder_gen
generic map(add_width => width_out)
port map(
add_a_in => multi_add((i+1)*width_out-1 downto i*width_out), -- from multipliers
add_b_in => add_add((i-1)*width_out-1 downto (i-2)*width_out),
add_out => add_add(i*width_out-1 downto (i-1)*width_out)
);
end generate;
end generate;
 
fir_out <= add_add((order-1)*width_out-1 downto (order-1)*width_out-width_out);
END ARCHITECTURE struct;
/gfir/trunk/vhdl/src/fir_filter_stage_TF.vhd
0,0 → 1,137
---------------------------------------------------------------------------------------------------
--! @file
--! @brief This is the top-level design for a transposed-form FIR digital filter. \n
--! @details It instantiate the three major components for constructing a digital filter such as;\n
--! adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen). \n
--! The top-level is a structural description in a generic/scalable form. \n
--! The filter coefficients and the quantization bit width should be edited/pasted \n
--! into the fir_pkg.vhd. The filter coefficients should be given in integer format. \n
--! Design specs: \n
--! Unsigned single/multi-bit input (fir_in) \n
--! Signed multi-bit output (fir_out) \n
--! Active high asynchronous reset (fir_clr) \n
--! Rising edge clock (fir_clk) \n
--
--! @image html firTF.png "Transposed-form FIR Filter Structure"
--
--! @author Ahmed Shahein
--! @email ahmed.shahein@ieee.org
--! @date 04.2012
---------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.fir_pkg.all;
 
ENTITY fir_filter_stage_TF IS
port (fir_clk : in std_logic; --! Rising edge clock
fir_clr : in std_logic; --! Active high asynchronous reset
fir_in : in std_logic_vector(0 downto 0); --! Unsigned single/multi-bit input
fir_out : out std_logic_vector(14 downto 0)); --! Signed multi-bit output
END ENTITY fir_filter_stage_TF;
 
--
ARCHITECTURE struct OF fir_filter_stage_TF IS
-- COMPONENT DECLARATION
component multiplier_gen
generic (multi_width_const : natural;
multi_width_in : natural);
port (multiplier_const : in std_logic_vector(multi_width_const-1 downto 0);
multiplier_in : in std_logic_vector(multi_width_in-1 downto 0);
multiplier_out : out std_logic_vector((multi_width_const+multi_width_in)+1 downto 0));
end component;
 
component adder_gen
generic (add_width : natural);
port (add_a_in : in std_logic_vector(add_width-1 downto 0);
add_b_in : in std_logic_vector(add_width-1 downto 0);
add_out : out std_logic_vector(add_width-1 downto 0));
end component;
 
component delay_gen
generic (delay_width : natural);
port (clk, clr : in std_logic;
delay_in : in std_logic_vector(delay_width-1 downto 0);
delay_out : out std_logic_vector(delay_width-1 downto 0));
end component;
 
-- CONSTANT DECLARATION
--constant coeff : int_vector := fir_coeff_thirdstage; --! Filter coefficients defined in the fir_pkg.vhd
constant width_in : natural := fir_in'length; --! Input bit-width
--constant width_out : natural := fir_out'length; --! Output bit-width
constant width_const : positive := quantization; --! Quantization bit-width defined in the fir_pkg.vhd
--constant order : natural := coeff'length; --! Filter length
 
-- SIGNAL DECLARATION
signal multi_add : std_logic_vector((order-1)*width_out-1 downto 0); --! Internal signal holding multiplier's outputs and adder's inputs
signal add_delay : std_logic_vector((order-2)*width_out-1 downto 0); --! Internal signal holding adder's outputs and delay's inputs
signal delay_add : std_logic_vector((order-1)*width_out-1 downto 0); --! Internal signal holding delay's output and adder's inputs
signal multi_delay : std_logic_vector(width_out-1 downto 0); --! internal signal for the left most multiplier since it is connected directly to delay
 
BEGIN
 
COEFFMULTIs: for i in 0 to order-1 generate --! Generate the filter multipliers set
LastMULT: if i = order-1 generate
MULTI: multiplier_gen
generic map(multi_width_const => width_const,
multi_width_in => width_in)
port map(multiplier_const => conv_std_logic_vector(coeff(i), width_const),
multiplier_in => fir_in,
multiplier_out => multi_delay);
end generate;
InterMULTs: if i < order-1 generate
MULTIs: multiplier_gen
generic map(multi_width_const => width_const,
multi_width_in => width_in)
port map(multiplier_const => conv_std_logic_vector(coeff(i), width_const),
multiplier_in => fir_in,
multiplier_out => multi_add((i+1)*width_out-1 downto i*width_out));
end generate;
end generate;
COEFFDELAY: for i in 0 to order-2 generate --! Generate the filter delays set
DELAY: if i = order-2 generate
LastDELAY: delay_gen
generic map(delay_width => width_out)
port map(clk => fir_clk,
clr => fir_clr,
delay_in => multi_delay,
delay_out => delay_add((i+1)*width_out-1 downto i*width_out));
end generate;
InterDElAYs: if i < order-2 generate
DELAYs: delay_gen
generic map(delay_width => width_out)
port map(clk => fir_clk,
clr => fir_clr,
delay_in => add_delay((i+1)*width_out-1 downto i*width_out),
delay_out => delay_add((i+1)*width_out-1 downto i*width_out));
end generate;
end generate;
COEFFADD: for i in 0 to order-2 generate --! Generate the filter adders set
FirstADDER: if i = 0 generate
ADDER0: adder_gen
generic map(add_width => width_out)
port map(
add_a_in => multi_add((i+1)*width_out-1 downto i*width_out),
add_b_in => delay_add((i+1)*width_out-1 downto i*width_out),
add_out => fir_out);
end generate;
InterADDER: if i > 0 generate
ADDERs: adder_gen
generic map(add_width => width_out)
port map(
add_a_in => multi_add((i+1)*width_out-1 downto i*width_out),
add_b_in => delay_add((i+1)*width_out-1 downto i*width_out),
add_out => add_delay(i*width_out-1 downto (i-1)*width_out));
end generate;
end generate;
 
-- Internal debugging signals
g_multi_add <= multi_add;
g_add_delay <= add_delay;
g_delay_add <= delay_add;
g_multi_delay <= multi_delay;
END ARCHITECTURE struct;
/gfir/trunk/vhdl/src/fir_pkg.vhd
0,0 → 1,85
----------
--! @file
--! @brief This is the supporting package. \b "JUST EDIT THIS FILE"
----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
package fir_pkg is
 
type int_vector is array (natural range <>) of integer;
constant coeff : int_vector := (-51,25,128,77,-203,-372,70,1122,2047,2047,1122,70,-372,-203,77,128,25,-51); --! Filter coefficients defined in the fir_pkg.vhd
-- Q 12, N 18
constant quantization : positive := 12; --! Filter quantization bit-width
constant order : natural := coeff'length;
constant width_out : natural := 15;
 
-- Global signals for internal debugging
signal g_multi_add : std_logic_vector((order-1)*width_out-1 downto 0);
signal g_add_delay : std_logic_vector((order-2)*width_out-1 downto 0);
signal g_delay_add : std_logic_vector((order-1)*width_out-1 downto 0);
signal g_multi_delay : std_logic_vector(width_out-1 downto 0);
function binary_width (
x : natural)
return natural;
function EOp (
M : positive
)
return natural;
function EOn (
M : positive
)
return natural;
end fir_pkg;
 
package body fir_pkg is
function binary_width (
x : natural)
return natural is
variable y : integer;
variable count : natural;
begin
y := abs(x);
count := 0;
while y > 0 loop
y := y/2;
count := count + 1;
end loop;
return count;
end function;
 
function EOp (
M : positive
)
return natural is
begin
if (M mod 2) = 0 then
return M/2-1;
else
return M/2;
end if;
end function;
function EOn (
M : positive
)
return natural is
begin
if (M mod 2) = 0 then
return M/2-1;
else
return M/2-1;
end if;
end function;
end fir_pkg;
/gfir/trunk/vhdl/src/tb_pack.vhd
0,0 → 1,46
----------
--! @file
--! @brief The test-bench supporting package.
----------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
 
package tb_pack is
procedure ReadData( constant filename : in string;
signal bpsdm_data : out std_logic_vector;
signal clk : in std_ulogic;
signal finished : out std_ulogic );
end tb_pack;
 
package body tb_pack is
procedure ReadData( constant filename : in string;
signal bpsdm_data : out std_logic_vector;
signal clk : in std_ulogic;
signal finished : out std_ulogic ) is
file inputfile : text open read_mode is filename;
variable inputline : line;
variable data : integer;
begin
while not endfile(inputfile) loop
-- read one line of the file
readline(inputfile, inputline);
-- read one integer number from that line
read(inputline, data);
-- output data at rising clock edge, converting the integer number to a
-- bit vector using the given vector length and either signed or unsigned
-- input
wait until rising_edge(clk);
bpsdm_data <= std_logic_vector(conv_signed(data, bpsdm_data'length)) after 0 ns;
end loop;
-- as soon as last line is reached, output information that finished
-- reading contents
finished <= '1';
end procedure ReadData;
 
end tb_pack;
/gfir/trunk/vhdl/src/delay_gen.vhd
0,0 → 1,28
----------
--! @file
--! @brief This is a positive edge triggered D-flip flop.
----------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY delay_gen IS
generic (delay_width : integer);
port (clk : in std_logic; --! Rising edge clock
clr : in std_logic; --! Active high asynchronous reset
delay_in : in std_logic_vector(delay_width-1 downto 0); --! Delay input port variable bit-width
delay_out : out std_logic_vector(delay_width-1 downto 0)); --! Delay output port variable bit-width
END ENTITY delay_gen;
 
ARCHITECTURE behave OF delay_gen IS
BEGIN
process (clr, clk)
begin
if clr = '1' then
delay_out <= (others => '0');
elsif rising_edge(clk) then
delay_out <= delay_in;
end if;
end process;
END ARCHITECTURE behave;
 
/gfir/trunk/vhdl/src/adder_gen.vhd
0,0 → 1,20
----------
--! @file
--! @brief This is a two input signed adder.
---------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
 
ENTITY adder_gen IS
generic (add_width : natural);
port (add_a_in : in std_logic_vector(add_width-1 downto 0); --! Two input adder element first input port with variable input bit-width
add_b_in : in std_logic_vector(add_width-1 downto 0); --! Two input adder element second input port with variable input bit-width
add_out : out std_logic_vector(add_width-1 downto 0));--! Two input adder element output port with variable input bit-width
END ENTITY adder_gen;
 
ARCHITECTURE behave OF adder_gen IS
BEGIN
add_out <= add_a_in + add_b_in;
END ARCHITECTURE behave;
 
/gfir/trunk/vhdl/help/html/classfir__filter__stage.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/gfir/trunk/vhdl/help/html/classfir__filter__stage.png
gfir/trunk/vhdl/help/html/classfir__filter__stage.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF-members.html (revision 4) @@ -0,0 +1,128 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

fir_filter_stage_TF Member List

+
+
+This is the complete list of members for fir_filter_stage_TF, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_b_inadder_gen [Port]
add_delaystruct [Signal]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
delay_addstruct [Signal]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
fir_clkfir_filter_stage_TF [Port]
fir_clrfir_filter_stage_TF [Port]
fir_infir_filter_stage_TF [Port]
fir_outfir_filter_stage_TF [Port]
fir_pkg (defined in fir_filter_stage_TF)fir_filter_stage_TF [Package]
ieeefir_filter_stage_TF [Library]
LastDELAYstruct [Component Instantiation]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_delaystruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in fir_filter_stage_TF)fir_filter_stage_TF [Package]
std_logic_arith (defined in fir_filter_stage_TF)fir_filter_stage_TF [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
std_logic_unsigned (defined in fir_filter_stage_TF)fir_filter_stage_TF [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/tabs.css =================================================================== --- gfir/trunk/vhdl/help/html/tabs.css (nonexistent) +++ gfir/trunk/vhdl/help/html/tabs.css (revision 4) @@ -0,0 +1,59 @@ +.tabs, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 13px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + line-height: 36px; + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} Index: gfir/trunk/vhdl/help/html/hierarchy.html =================================================================== --- gfir/trunk/vhdl/help/html/hierarchy.html (nonexistent) +++ gfir/trunk/vhdl/help/html/hierarchy.html (revision 4) @@ -0,0 +1,113 @@ + + + + +FIR Digital Filter: Design Unit Hierarchy + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

Design Unit Hierarchy

+
+
+
This inheritance list is sorted roughly, but not completely, alphabetically:
+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/class__tb__pack-members.html =================================================================== --- gfir/trunk/vhdl/help/html/class__tb__pack-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/class__tb__pack-members.html (revision 4) @@ -0,0 +1,86 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

tb_pack Member List

+
+
+This is the complete list of members for tb_pack, including all inherited members. + +
ReadDatafilename, bpsdm_data, clk, finished (defined in tb_pack)tb_pack [Procedure]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/installdox =================================================================== --- gfir/trunk/vhdl/help/html/installdox (nonexistent) +++ gfir/trunk/vhdl/help/html/installdox (revision 4) @@ -0,0 +1,112 @@ +#!/usr/bin/perl + +%subst = ( ); +$quiet = 0; + +while ( @ARGV ) { + $_ = shift @ARGV; + if ( s/^-// ) { + if ( /^l(.*)/ ) { + $v = ($1 eq "") ? shift @ARGV : $1; + ($v =~ /\/$/) || ($v .= "/"); + $_ = $v; + if ( /(.+)\@(.+)/ ) { + if ( exists $subst{$1} ) { + $subst{$1} = $2; + } else { + print STDERR "Unknown tag file $1 given with option -l\n"; + &usage(); + } + } else { + print STDERR "Argument $_ is invalid for option -l\n"; + &usage(); + } + } + elsif ( /^q/ ) { + $quiet = 1; + } + elsif ( /^\?|^h/ ) { + &usage(); + } + else { + print STDERR "Illegal option -$_\n"; + &usage(); + } + } + else { + push (@files, $_ ); + } +} + +foreach $sub (keys %subst) +{ + if ( $subst{$sub} eq "" ) + { + print STDERR "No substitute given for tag file `$sub'\n"; + &usage(); + } + elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" ) + { + print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; + } +} + +if ( ! @files ) { + if (opendir(D,".")) { + foreach $file ( readdir(D) ) { + $match = ".html"; + next if ( $file =~ /^\.\.?$/ ); + ($file =~ /$match/) && (push @files, $file); + ($file =~ /\.svg/) && (push @files, $file); + ($file =~ "navtree.js") && (push @files, $file); + } + closedir(D); + } +} + +if ( ! @files ) { + print STDERR "Warning: No input files given and none found!\n"; +} + +foreach $f (@files) +{ + if ( ! $quiet ) { + print "Editing: $f...\n"; + } + $oldf = $f; + $f .= ".bak"; + unless (rename $oldf,$f) { + print STDERR "Error: cannot rename file $oldf\n"; + exit 1; + } + if (open(F,"<$f")) { + unless (open(G,">$oldf")) { + print STDERR "Error: opening file $oldf for writing\n"; + exit 1; + } + if ($oldf ne "tree.js") { + while () { + s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g; + print G "$_"; + } + } + else { + while () { + s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g; + print G "$_"; + } + } + } + else { + print STDERR "Warning file $f does not exist\n"; + } + unlink $f; +} + +sub usage { + print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n"; + print STDERR "Options:\n"; + print STDERR " -l tagfile\@linkName tag file + URL or directory \n"; + print STDERR " -q Quiet mode\n\n"; + exit 1; +} Index: gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.html =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.html (revision 4) @@ -0,0 +1,120 @@ + + + + +FIR Digital Filter: behave Architecture Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+Signals
+
+

behave Architecture Reference

+
+
+
+Inheritance diagram for behave:
+
+
+ + +multiplier_gen +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +

List of all members.

+ +
+
+ + + +

+Signals

+tmp_multiplier_out  std_logic_vector ( ( multi_width_const+multi_width_in ) downto 0 )
+tmp_msb  std_logic
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave-members.html (revision 4) @@ -0,0 +1,92 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+

behave Member List

+
+
+This is the complete list of members for behave, including all inherited members. + +
PROCESS_0(clr, clk) (defined in behave)behave [Process]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.png =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.png (revision 4)
gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classtb__pack.html =================================================================== --- gfir/trunk/vhdl/help/html/classtb__pack.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classtb__pack.html (revision 4) @@ -0,0 +1,119 @@ + + + + +FIR Digital Filter: tb_pack Package Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Libraries | +Packages | +Procedures
+
+

tb_pack Package Reference

+
+
+ +

List of all members.

+ +
+
+Package Body >> tb_pack
+ + + + + + + + +

+Procedures

+  ReadData(
+constant filename: in string
+ signal bpsdm_data: out std_logic_vector
+ signal clk: in std_ulogic
+ signal finished: out std_ulogic
+ )

+Libraries

+IEEE 

+Packages

+std_logic_1164 
+std_logic_arith 
+textio 
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.html (revision 4) @@ -0,0 +1,166 @@ + + + + +FIR Digital Filter: struct Architecture Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+Components | +Constants | +Signals | +Component Instantiations
+
+

struct Architecture Reference

+
+
+
+Inheritance diagram for struct:
+
+
+ + +multiplier_gen +delay_gen +adder_gen +behave +behave +behave +fir_filter_stage_TF + +
+ +

List of all members.

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Components

+multiplier_gen  <Entity multiplier_gen>
+adder_gen  <Entity adder_gen>
+delay_gen  <Entity delay_gen>

+Constants

+width_in  natural := fir_in ' length
 Input bit-width.
+width_const  positive := quantization
 Quantization bit-width defined in the fir_pkg.vhd.

+Signals

+multi_add  std_logic_vector ( ( order-1 ) *width_out-1 downto 0 )
 Internal signal holding multiplier's outputs and adder's inputs.
+add_delay  std_logic_vector ( ( order-2 ) *width_out-1 downto 0 )
 Internal signal holding adder's outputs and delay's inputs.
+delay_add  std_logic_vector ( ( order-1 ) *width_out-1 downto 0 )
 Internal signal holding delay's output and adder's inputs.
+multi_delay  std_logic_vector ( width_out-1 downto 0 )
 internal signal for the left most multiplier since it is connected directly to delay

+Component Instantiations

+MULTI multiplier_gen <Entity multiplier_gen>
 Generate the filter multipliers set.
+MULTIs multiplier_gen <Entity multiplier_gen>
+LastDELAY delay_gen <Entity delay_gen>
 Generate the filter delays set.
+DELAYs delay_gen <Entity delay_gen>
+ADDER0 adder_gen <Entity adder_gen>
 Generate the filter adders set.
+ADDERs adder_gen <Entity adder_gen>
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/class__fir__pkg-members.html =================================================================== --- gfir/trunk/vhdl/help/html/class__fir__pkg-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/class__fir__pkg-members.html (revision 4) @@ -0,0 +1,88 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

fir_pkg Member List

+
+
+This is the complete list of members for fir_pkg, including all inherited members. + + + +
binary_widthx (defined in fir_pkg)fir_pkg [Function]
EOnM (defined in fir_pkg)fir_pkg [Function]
EOpM (defined in fir_pkg)fir_pkg [Function]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classdelay__gen.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classdelay__gen.png =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen.png (revision 4)
gfir/trunk/vhdl/help/html/classdelay__gen.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/doxygen.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/doxygen.png =================================================================== --- gfir/trunk/vhdl/help/html/doxygen.png (nonexistent) +++ gfir/trunk/vhdl/help/html/doxygen.png (revision 4)
gfir/trunk/vhdl/help/html/doxygen.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classadder__gen.html =================================================================== --- gfir/trunk/vhdl/help/html/classadder__gen.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classadder__gen.html (revision 4) @@ -0,0 +1,139 @@ + + + + +FIR Digital Filter: adder_gen Entity Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Generics | +Ports | +Libraries | +Packages
+
+

adder_gen Entity Reference

+
+
+
+Inheritance diagram for adder_gen:
+
+
+ + +behave +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + +

+Architectures

behave Architecture

+Libraries

+ieee 

+Packages

+std_logic_1164 
+std_logic_signed 

+Generics

+add_width  natural

+Ports

+add_a_in  in std_logic_vector ( add_width-1 downto 0 )
 Two input adder element first input port with variable input bit-width.
+add_b_in  in std_logic_vector ( add_width-1 downto 0 )
 Two input adder element second input port with variable input bit-width.
+add_out  out std_logic_vector ( add_width-1 downto 0 )
 Two input adder element output port with variable input bit-width.
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/fir__filter__stage_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/fir__filter__stage_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/fir__filter__stage_8vhd.html (revision 4) @@ -0,0 +1,96 @@ + + + + + +FIR Digital Filter: src/fir_filter_stage.vhd File Reference + + + + + + + + + +
+

src/fir_filter_stage.vhd File Reference

+

This is the top-level design for a transposed-form FIR digital filter.
+ It instantiate the three major components for constructing a digital filter such as;
+ adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen).
+ The top-level is a structural description in a generic/scalable form.
+ The filter coefficients and the quantization bit width should be edited/pasted
+ into the fir_pkg.vhd. The filter coefficients should be given in integer format.
+ Design specs:
+ Unsigned single/multi-bit input (fir_in)
+ Signed multi-bit output (fir_out)
+ Active high asynchronous reset (fir_clr)
+ Rising edge clock (fir_clk)
+. +More...

+ + + + +

Architectures

fir_filter_stage Entity
struct Architecture
+

Detailed Description

+

This is the top-level design for a transposed-form FIR digital filter.
+ It instantiate the three major components for constructing a digital filter such as;
+ adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen).
+ The top-level is a structural description in a generic/scalable form.
+ The filter coefficients and the quantization bit width should be edited/pasted
+ into the fir_pkg.vhd. The filter coefficients should be given in integer format.
+ Design specs:
+ Unsigned single/multi-bit input (fir_in)
+ Signed multi-bit output (fir_out)
+ Active high asynchronous reset (fir_clr)
+ Rising edge clock (fir_clk)
+.

+
+ + + + +
+ +
+ +
Generated on Mon Apr 9 16:26:39 2012 for FIR Digital Filter by  + +doxygen 1.6.3
+ + Index: gfir/trunk/vhdl/help/html/adder__gen_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/adder__gen_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/adder__gen_8vhd.html (revision 4) @@ -0,0 +1,94 @@ + + + + +FIR Digital Filter: src/adder_gen.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/adder_gen.vhd File Reference

+
+
+ +

This is a two input signed adder. +More...

+ + + + +

+Architectures

adder_gen Entity
behave Architecture
+

Detailed Description

+

This is a two input signed adder.

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct-members.html (revision 4) @@ -0,0 +1,135 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+

struct Member List

+
+
+This is the complete list of members for struct, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_addstruct [Signal]
add_b_inadder_gen [Port]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
coeffstruct [Constant]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_multistruct [Signal]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
FirstDELAYstruct [Component Instantiation]
ieee (defined in multiplier_gen)multiplier_gen [Library]
ieee (defined in delay_gen)delay_gen [Library]
ieee (defined in adder_gen)adder_gen [Library]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
orderstruct [Constant]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in multiplier_gen)multiplier_gen [Package]
std_logic_1164 (defined in delay_gen)delay_gen [Package]
std_logic_1164 (defined in adder_gen)adder_gen [Package]
std_logic_arith (defined in multiplier_gen)multiplier_gen [Package]
std_logic_arith (defined in delay_gen)delay_gen [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
width_outstruct [Constant]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/search/files_74.html =================================================================== --- gfir/trunk/vhdl/help/html/search/files_74.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/files_74.html (revision 4) @@ -0,0 +1,25 @@ + + + + + + + +
+
Loading...
+
+
+ tb_pack.vhd +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/files_66.html =================================================================== --- gfir/trunk/vhdl/help/html/search/files_66.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/files_66.html (revision 4) @@ -0,0 +1,35 @@ + + + + + + + +
+
Loading...
+ + +
+
+ fir_pkg.vhd +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_61.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_61.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_61.html (revision 4) @@ -0,0 +1,69 @@ + + + + + + + +
+
Loading...
+
+
+ add_a_in + adder_gen +
+
+
+
+ add_add + fir_filter_stage_DF::struct +
+
+
+
+ add_b_in + adder_gen +
+
+
+
+ add_delay + fir_filter_stage_TF::struct +
+
+
+
+ add_out + adder_gen +
+
+ +
+
+ adder_gen +
+
+
+
+ adder_gen.vhd +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_71.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_71.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_71.html (revision 4) @@ -0,0 +1,26 @@ + + + + + + + +
+
Loading...
+
+
+ quantization + fir_pkg +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_63.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_63.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_63.html (revision 4) @@ -0,0 +1,41 @@ + + + + + + + +
+
Loading...
+
+
+ clk + delay_gen +
+
+
+
+ clr + delay_gen +
+
+ +
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/nomatches.html =================================================================== --- gfir/trunk/vhdl/help/html/search/nomatches.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/nomatches.html (revision 4) @@ -0,0 +1,12 @@ + + + + + + + +
+
No Matches
+
+ + Index: gfir/trunk/vhdl/help/html/search/all_73.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_73.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_73.html (revision 4) @@ -0,0 +1,32 @@ + + + + + + + +
+
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+
+
+ struct + fir_filter_stage_TF +
+
+
+
+ struct + fir_filter_stage_DF +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/variables_64.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_64.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_64.html (revision 4) @@ -0,0 +1,44 @@ + + + + + + + +
+
Loading...
+
+
+ delay_add + fir_filter_stage_TF::struct +
+
+
+
+ delay_in + delay_gen +
+
+
+
+ delay_multi + fir_filter_stage_DF::struct +
+
+
+
+ delay_out + delay_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/variables_66.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_66.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_66.html (revision 4) @@ -0,0 +1,62 @@ + + + + + + + +
+
Loading...
+ + + + +
+
+ FirstDELAY + fir_filter_stage_DF::struct +
+
+
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+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_77.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_77.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_77.html (revision 4) @@ -0,0 +1,44 @@ + + + + + + + +
+
Loading...
+ + +
+
+ width_out + fir_filter_stage_DF::struct +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/search.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/search/search.png =================================================================== --- gfir/trunk/vhdl/help/html/search/search.png (nonexistent) +++ gfir/trunk/vhdl/help/html/search/search.png (revision 4)
gfir/trunk/vhdl/help/html/search/search.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/search/classes_6d.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_6d.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_6d.html (revision 4) @@ -0,0 +1,25 @@ + + + + + + + +
+
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+ +
Searching...
+
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+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_69.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_69.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_69.html (revision 4) @@ -0,0 +1,29 @@ + + + + + + + +
+
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+ +
Searching...
+
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+ +
+ + Index: gfir/trunk/vhdl/help/html/search/classes_5f.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_5f.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_5f.html (revision 4) @@ -0,0 +1,30 @@ + + + + + + + +
+
Loading...
+
+
+ _fir_pkg +
+
+
+
+ _tb_pack +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/variables_6c.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_6c.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_6c.html (revision 4) @@ -0,0 +1,26 @@ + + + + + + + +
+
Loading...
+
+
+ LastDELAY + fir_filter_stage_TF::struct +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_6d.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_6d.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_6d.html (revision 4) @@ -0,0 +1,72 @@ + + + + + + + +
+
Loading...
+ + +
+
+ multi_delay + fir_filter_stage_TF::struct +
+
+
+
+ multiplier_const + multiplier_gen +
+
+ + +
+
+ multiplier_in + multiplier_gen +
+
+
+
+ multiplier_out + multiplier_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_5f.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_5f.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_5f.html (revision 4) @@ -0,0 +1,30 @@ + + + + + + + +
+
Loading...
+
+
+ _fir_pkg +
+
+
+
+ _tb_pack +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_6f.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_6f.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_6f.html (revision 4) @@ -0,0 +1,26 @@ + + + + + + + +
+
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+
+
+ order + fir_filter_stage_DF::struct +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/classes_62.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_62.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_62.html (revision 4) @@ -0,0 +1,38 @@ + + + + + + + +
+
Loading...
+
+
+ behave + delay_gen +
+
+
+
+ behave + multiplier_gen +
+
+
+
+ behave + adder_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/classes_64.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_64.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_64.html (revision 4) @@ -0,0 +1,25 @@ + + + + + + + +
+
Loading...
+
+
+ delay_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/classes_74.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_74.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_74.html (revision 4) @@ -0,0 +1,25 @@ + + + + + + + +
+
Loading...
+
+
+ tb_pack +
+
+
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+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/files_61.html =================================================================== --- gfir/trunk/vhdl/help/html/search/files_61.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/files_61.html (revision 4) @@ -0,0 +1,25 @@ + + + + + + + +
+
Loading...
+
+
+ adder_gen.vhd +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/classes_66.html =================================================================== --- gfir/trunk/vhdl/help/html/search/classes_66.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/classes_66.html (revision 4) @@ -0,0 +1,35 @@ + + + + + + + +
+
Loading...
+ + +
+
+ fir_pkg +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/search.js =================================================================== --- gfir/trunk/vhdl/help/html/search/search.js (nonexistent) +++ gfir/trunk/vhdl/help/html/search/search.js (revision 4) @@ -0,0 +1,732 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111101001001101010110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110101000000100000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001001101010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "variables" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location.href = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} Index: gfir/trunk/vhdl/help/html/search/variables_61.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_61.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_61.html (revision 4) @@ -0,0 +1,59 @@ + + + + + + + +
+
Loading...
+
+
+ add_a_in + adder_gen +
+
+
+
+ add_add + fir_filter_stage_DF::struct +
+
+
+
+ add_b_in + adder_gen +
+
+
+
+ add_delay + fir_filter_stage_TF::struct +
+
+
+
+ add_out + adder_gen +
+
+ +
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_62.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_62.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_62.html (revision 4) @@ -0,0 +1,38 @@ + + + + + + + +
+
Loading...
+
+
+ behave + delay_gen +
+
+
+
+ behave + multiplier_gen +
+
+
+
+ behave + adder_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/variables_71.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_71.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_71.html (revision 4) @@ -0,0 +1,26 @@ + + + + + + + +
+
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+
+
+ quantization + fir_pkg +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/variables_63.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_63.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_63.html (revision 4) @@ -0,0 +1,41 @@ + + + + + + + +
+
Loading...
+
+
+ clk + delay_gen +
+
+
+
+ clr + delay_gen +
+
+ +
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_64.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_64.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_64.html (revision 4) @@ -0,0 +1,54 @@ + + + + + + + +
+
Loading...
+
+
+ delay_add + fir_filter_stage_TF::struct +
+
+
+
+ delay_gen +
+
+
+
+ delay_gen.vhd +
+
+
+
+ delay_in + delay_gen +
+
+
+
+ delay_multi + fir_filter_stage_DF::struct +
+
+
+
+ delay_out + delay_gen +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_74.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_74.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_74.html (revision 4) @@ -0,0 +1,30 @@ + + + + + + + +
+
Loading...
+
+
+ tb_pack +
+
+
+
+ tb_pack.vhd +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/all_66.html =================================================================== --- gfir/trunk/vhdl/help/html/search/all_66.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/all_66.html (revision 4) @@ -0,0 +1,92 @@ + + + + + + + +
+
Loading...
+ + + + + + + + +
+
+ fir_pkg +
+
+
+
+ fir_pkg.vhd +
+
+
+
+ FirstDELAY + fir_filter_stage_DF::struct +
+
+
Searching...
+
No Matches
+ +
+ + Index: gfir/trunk/vhdl/help/html/search/close.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/search/close.png =================================================================== --- gfir/trunk/vhdl/help/html/search/close.png (nonexistent) +++ gfir/trunk/vhdl/help/html/search/close.png (revision 4)
gfir/trunk/vhdl/help/html/search/close.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/search/variables_77.html =================================================================== --- gfir/trunk/vhdl/help/html/search/variables_77.html (nonexistent) +++ gfir/trunk/vhdl/help/html/search/variables_77.html (revision 4) @@ -0,0 +1,44 @@ + + + + + + + +
+
Loading...
+ + +
+
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+ LastDELAY + fir_filter_stage_TF::struct +
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+
+ multi_delay + fir_filter_stage_TF::struct +
+
+
+
+ multiplier_const + multiplier_gen +
+
+
+
+ multiplier_in + multiplier_gen +
+
+
+
+ multiplier_out + multiplier_gen +
+
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+ struct + fir_filter_stage_TF +
+
+
+
+ struct + fir_filter_stage_DF +
+
+
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+ +
+ + Index: gfir/trunk/vhdl/help/html/search/search_r.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/search/search_r.png =================================================================== --- gfir/trunk/vhdl/help/html/search/search_r.png (nonexistent) +++ gfir/trunk/vhdl/help/html/search/search_r.png (revision 4)
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+ delay_gen.vhd +
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+ + Index: gfir/trunk/vhdl/help/html/classfir__pkg.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__pkg.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__pkg.html (revision 4) @@ -0,0 +1,145 @@ + + + + +FIR Digital Filter: fir_pkg Package Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Types | +Constants | +Signals | +Libraries | +Packages | +Functions
+
+

fir_pkg Package Reference

+
+
+ +

List of all members.

+ +
+
+Package Body >> fir_pkg
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

+natural  binary_width ( x: in natural )
+natural  EOp ( M: in positive )
+natural  EOn ( M: in positive )

+Libraries

+ieee 

+Packages

+std_logic_1164 
+std_logic_arith 

+Constants

+coeff  int_vector := ( -51 , 25 , 128 , 77 , -203 , -372 , 70 , 1122 , 2047 , 2047 , 1122 , 70 , -372 , -203 , 77 , 128 , 25 , -51 )
 Filter coefficients defined in the fir_pkg.vhd.
+quantization  positive := 12
 Filter quantization bit-width.
+order  natural := coeff ' length
+width_out  natural := 15

+Types

+int_vector  array ( natural range<> ) of integer

+Signals

+g_multi_add  std_logic_vector ( ( order-1 ) *width_out-1 downto 0 )
+g_add_delay  std_logic_vector ( ( order-2 ) *width_out-1 downto 0 )
+g_delay_add  std_logic_vector ( ( order-1 ) *width_out-1 downto 0 )
+g_multi_delay  std_logic_vector ( width_out-1 downto 0 )
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave-members.html (revision 4) @@ -0,0 +1,93 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+

behave Member List

+
+
+This is the complete list of members for behave, including all inherited members. + + +
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/functions.html =================================================================== --- gfir/trunk/vhdl/help/html/functions.html (nonexistent) +++ gfir/trunk/vhdl/help/html/functions.html (revision 4) @@ -0,0 +1,239 @@ + + + + +FIR Digital Filter: Design Unit Members + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + + +
+
+
Here is a list of all documented class members with links to the class documentation for each member:
+ +

- a -

+ + +

- c -

+ + +

- d -

+ + +

- f -

+ + +

- i -

+ + +

- l -

+ + +

- m -

+ + +

- o -

+ + +

- q -

+ + +

- w -

+
+ + + + +
+ +
+ +
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+ + Index: gfir/trunk/vhdl/help/html/firDF.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/firDF.png =================================================================== --- gfir/trunk/vhdl/help/html/firDF.png (nonexistent) +++ gfir/trunk/vhdl/help/html/firDF.png (revision 4)
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+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

Class List

+
+
+
Here is a list of all design unit members with links to the Entities and Packages they belong to:
+ + + + + + + + + + + + + + +
package body fir_pkg
package body tb_pack
entity adder_gen
architecture behave
architecture behave
architecture behave
entity delay_gen
entity fir_filter_stage_DF
entity fir_filter_stage_TF
package fir_pkg
entity multiplier_gen
architecture struct
architecture struct
package tb_pack
+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/delay__gen_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/delay__gen_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/delay__gen_8vhd.html (revision 4) @@ -0,0 +1,94 @@ + + + + +FIR Digital Filter: src/delay_gen.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/delay_gen.vhd File Reference

+
+
+ +

This is a positive edge triggered D-flip flop. +More...

+ + + + +

+Architectures

delay_gen Entity
behave Architecture
+

Detailed Description

+

This is a positive edge triggered D-flip flop.

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classtb__pack-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classtb__pack-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classtb__pack-members.html (revision 4) @@ -0,0 +1,90 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

tb_pack Member List

+
+
+This is the complete list of members for tb_pack, including all inherited members. + + + + + +
IEEE (defined in tb_pack)tb_pack [Library]
ReadDatafilename, bpsdm_data, clk, finished (defined in tb_pack)tb_pack [Procedure]
std_logic_1164 (defined in tb_pack)tb_pack [Package]
std_logic_arith (defined in tb_pack)tb_pack [Package]
textio (defined in tb_pack)tb_pack [Package]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct-members.html (revision 4) @@ -0,0 +1,133 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+

struct Member List

+
+
+This is the complete list of members for struct, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_b_inadder_gen [Port]
add_delaystruct [Signal]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
delay_addstruct [Signal]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
ieee (defined in multiplier_gen)multiplier_gen [Library]
ieee (defined in delay_gen)delay_gen [Library]
ieee (defined in adder_gen)adder_gen [Library]
LastDELAYstruct [Component Instantiation]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_delaystruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in multiplier_gen)multiplier_gen [Package]
std_logic_1164 (defined in delay_gen)delay_gen [Package]
std_logic_1164 (defined in adder_gen)adder_gen [Package]
std_logic_arith (defined in multiplier_gen)multiplier_gen [Package]
std_logic_arith (defined in delay_gen)delay_gen [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classmultiplier__gen.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classmultiplier__gen.png =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen.png (revision 4)
gfir/trunk/vhdl/help/html/classmultiplier__gen.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.png =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.png (revision 4)
gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classadder__gen-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classadder__gen-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classadder__gen-members.html (revision 4) @@ -0,0 +1,92 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
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+
+ + +
+
+
+

adder_gen Member List

+
+
+This is the complete list of members for adder_gen, including all inherited members. + + + + + + + +
add_a_inadder_gen [Port]
add_b_inadder_gen [Port]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ieee (defined in adder_gen)adder_gen [Library]
std_logic_1164 (defined in adder_gen)adder_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/tab_a.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/tab_a.png =================================================================== --- gfir/trunk/vhdl/help/html/tab_a.png (nonexistent) +++ gfir/trunk/vhdl/help/html/tab_a.png (revision 4)
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gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/firTF.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/firTF.png =================================================================== --- gfir/trunk/vhdl/help/html/firTF.png (nonexistent) +++ gfir/trunk/vhdl/help/html/firTF.png (revision 4)
gfir/trunk/vhdl/help/html/firTF.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage.html (revision 4) @@ -0,0 +1,138 @@ + + + + + +FIR Digital Filter: fir_filter_stage Entity Reference + + + + + + + + + +
+

fir_filter_stage Entity Reference

+Inheritance diagram for fir_filter_stage:
+
+
+ + +struct +multiplier_gen +delay_gen +adder_gen +behave +behave +behave + +
+
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + + + +

Architectures

struct Architecture

Libraries

ieee 

Packages

+std_logic_1164 
+std_logic_arith 
+std_logic_unsigned 
+fir_pkg  Package <fir_pkg>

Ports

+fir_clk  in std_logic
 Rising edge clock.
+fir_clr  in std_logic
 Active high asynchronous reset.
+fir_in  in std_logic_vector ( 0 downto 0 )
 Unsigned single/multi-bit input.
+fir_out  out std_logic_vector ( 14 downto 0 )
 Signed multi-bit output.
+

Member Data Documentation

+ +
+
+ + + + +
ieee library [Library]
+
+
+
+firTF.png +

Transposed-form FIR Filter Structure

+
Author:
Ahmed Shahein ahmed.shahein@ieee.org
+
Date:
04.2012
+ +

Reimplemented from adder_gen.

+ +
+
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Mon Apr 9 16:26:40 2012 for FIR Digital Filter by  + +doxygen 1.6.3
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gfir/trunk/vhdl/help/html/tab_h.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__pkg-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__pkg-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__pkg-members.html (revision 4) @@ -0,0 +1,100 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

fir_pkg Member List

+
+
+This is the complete list of members for fir_pkg, including all inherited members. + + + + + + + + + + + + + + + +
binary_widthx (defined in fir_pkg)fir_pkg [Function]
coefffir_pkg [Constant]
EOnM (defined in fir_pkg)fir_pkg [Function]
EOpM (defined in fir_pkg)fir_pkg [Function]
g_add_delay (defined in fir_pkg)fir_pkg [Signal]
g_delay_add (defined in fir_pkg)fir_pkg [Signal]
g_multi_add (defined in fir_pkg)fir_pkg [Signal]
g_multi_delay (defined in fir_pkg)fir_pkg [Signal]
ieee (defined in fir_pkg)fir_pkg [Library]
int_vector (defined in fir_pkg)fir_pkg [Type]
order (defined in fir_pkg)fir_pkg [Constant]
quantizationfir_pkg [Constant]
std_logic_1164 (defined in fir_pkg)fir_pkg [Package]
std_logic_arith (defined in fir_pkg)fir_pkg [Package]
width_out (defined in fir_pkg)fir_pkg [Constant]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.png =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.png (revision 4)
gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/fir__filter__stage__DF_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/fir__filter__stage__DF_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/fir__filter__stage__DF_8vhd.html (revision 4) @@ -0,0 +1,107 @@ + + + + +FIR Digital Filter: src/fir_filter_stage_DF.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/fir_filter_stage_DF.vhd File Reference

+
+
+ +

This is the top-level design for a direct-form FIR digital filter.
+. +More...

+ + + + +

+Architectures

fir_filter_stage_DF Entity
struct Architecture
+

Detailed Description

+

This is the top-level design for a direct-form FIR digital filter.
+.

+

It instantiate the three major components for constructing a digital filter such as;
+ adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen).
+ The top-level is a structural description in a generic/scalable form.
+ The filter coefficients and the quantization bit width should be edited/pasted
+ into the fir_pkg.vhd. The filter coefficients should be given in integer format.
+ Design specs:
+ Unsigned single/multi-bit input (fir_in)
+ Signed multi-bit output (fir_out)
+ Active high asynchronous reset (fir_clr)
+ Rising edge clock (fir_clk)
+

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/tab_b.gif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/tab_b.gif =================================================================== --- gfir/trunk/vhdl/help/html/tab_b.gif (nonexistent) +++ gfir/trunk/vhdl/help/html/tab_b.gif (revision 4)
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+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/fir_pkg.vhd File Reference

+
+
+ +

This is the supporting package. "JUST EDIT THIS FILE". +More...

+ + + + +

+Architectures

fir_pkg Package
fir_pkg Package Body
+

Detailed Description

+

This is the supporting package. "JUST EDIT THIS FILE".

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.png =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF_1_1struct.png (revision 4)
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gfir/trunk/vhdl/help/html/nav_h.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classdelay__gen.html =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen.html (revision 4) @@ -0,0 +1,142 @@ + + + + +FIR Digital Filter: delay_gen Entity Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Generics | +Ports | +Libraries | +Packages
+
+

delay_gen Entity Reference

+
+
+
+Inheritance diagram for delay_gen:
+
+
+ + +behave +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + + + +

+Architectures

behave Architecture

+Libraries

+ieee 

+Packages

+std_logic_1164 
+std_logic_arith 

+Generics

+delay_width  integer

+Ports

+clk  in std_logic
 Rising edge clock.
+clr  in std_logic
 Active high asynchronous reset.
+delay_in  in std_logic_vector ( delay_width-1 downto 0 )
 Delay input port variable bit-width.
+delay_out  out std_logic_vector ( delay_width-1 downto 0 )
 Delay output port variable bit-width.
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classadder__gen.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classadder__gen.png =================================================================== --- gfir/trunk/vhdl/help/html/classadder__gen.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classadder__gen.png (revision 4)
gfir/trunk/vhdl/help/html/classadder__gen.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/tab_l.gif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/tab_l.gif =================================================================== --- gfir/trunk/vhdl/help/html/tab_l.gif (nonexistent) +++ gfir/trunk/vhdl/help/html/tab_l.gif (revision 4)
gfir/trunk/vhdl/help/html/tab_l.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage-members.html (revision 4) @@ -0,0 +1,113 @@ + + + + + +FIR Digital Filter: Member List + + + + + + + + + +
+

fir_filter_stage Member List

This is the complete list of members for fir_filter_stage, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_b_inadder_gen [Port]
add_delaystruct [Signal]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0 (defined in struct)struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
coeffstruct [Constant]
delay_addstruct [Signal]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
fir_clkfir_filter_stage [Port]
fir_clrfir_filter_stage [Port]
fir_infir_filter_stage [Port]
fir_outfir_filter_stage [Port]
fir_pkg (defined in fir_filter_stage)fir_filter_stage [Package]
ieeefir_filter_stage [Library]
LastDELAYstruct [Component Instantiation]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_delaystruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
orderstruct [Constant]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in fir_filter_stage)fir_filter_stage [Package]
std_logic_arith (defined in fir_filter_stage)fir_filter_stage [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
std_logic_unsigned (defined in fir_filter_stage)fir_filter_stage [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
width_outstruct [Constant]
+ + + + +
+ +
+ +
Generated on Mon Apr 9 16:26:40 2012 for FIR Digital Filter by  + +doxygen 1.6.3
+ + Index: gfir/trunk/vhdl/help/html/fir__filter__stage__TF_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/fir__filter__stage__TF_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/fir__filter__stage__TF_8vhd.html (revision 4) @@ -0,0 +1,107 @@ + + + + +FIR Digital Filter: src/fir_filter_stage_TF.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/fir_filter_stage_TF.vhd File Reference

+
+
+ +

This is the top-level design for a transposed-form FIR digital filter.
+. +More...

+ + + + +

+Architectures

fir_filter_stage_TF Entity
struct Architecture
+

Detailed Description

+

This is the top-level design for a transposed-form FIR digital filter.
+.

+

It instantiate the three major components for constructing a digital filter such as;
+ adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen).
+ The top-level is a structural description in a generic/scalable form.
+ The filter coefficients and the quantization bit width should be edited/pasted
+ into the fir_pkg.vhd. The filter coefficients should be given in integer format.
+ Design specs:
+ Unsigned single/multi-bit input (fir_in)
+ Signed multi-bit output (fir_out)
+ Active high asynchronous reset (fir_clr)
+ Rising edge clock (fir_clk)
+

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.png =================================================================== --- gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.png (revision 4)
gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/tab_r.gif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/tab_r.gif =================================================================== --- gfir/trunk/vhdl/help/html/tab_r.gif (nonexistent) +++ gfir/trunk/vhdl/help/html/tab_r.gif (revision 4)
gfir/trunk/vhdl/help/html/tab_r.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/closed.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/closed.png =================================================================== --- gfir/trunk/vhdl/help/html/closed.png (nonexistent) +++ gfir/trunk/vhdl/help/html/closed.png (revision 4)
gfir/trunk/vhdl/help/html/closed.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct.html (revision 4) @@ -0,0 +1,144 @@ + + + + + +FIR Digital Filter: struct Architecture Reference + + + + + + + + + +
+

struct Architecture Reference

+Inheritance diagram for struct:
+
+
+ + +multiplier_gen +delay_gen +adder_gen +behave +behave +behave +fir_filter_stage + +
+
+ +

List of all members.

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Components

+multiplier_gen  <Entity multiplier_gen>
+adder_gen  <Entity adder_gen>
+delay_gen  <Entity delay_gen>

Constants

+coeff  int_vector := fir_coeff_thirdstage
 Filter coefficients defined in the fir_pkg.vhd.
+width_in  natural := fir_in ' length
 Input bit-width.
+width_out  natural := fir_out ' length
 Output bit-width.
+width_const  positive := quantization
 Quantization bit-width defined in the fir_pkg.vhd.
+order  natural := coeff ' length
 Filter length.

Signals

+multi_add  std_logic_vector ( ( order -1 ) *width_out -1 downto 0 )
 Internal signal holding multiplier's outputs and adder's inputs.
+add_delay  std_logic_vector ( ( order -2 ) *width_out -1 downto 0 )
 Internal signal holding adder's outputs and delay's inputs.
+delay_add  std_logic_vector ( ( order -1 ) *width_out -1 downto 0 )
 Internal signal holding delay's output and adder's inputs.
+multi_delay  std_logic_vector ( width_out -1 downto 0 )
 internal signal for the left most multiplier since it is connected directly to delay

Component Instantiations

+MULTI multiplier_gen <Entity multiplier_gen>
 Generate the filter multipliers set.
+MULTIs multiplier_gen <Entity multiplier_gen>
+LastDELAY delay_gen <Entity delay_gen>
 Generate the filter delay set.
+DELAYs delay_gen <Entity delay_gen>
+ADDER0 adder_gen <Entity adder_gen>
+ADDERs adder_gen <Entity adder_gen>
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Mon Apr 9 16:26:40 2012 for FIR Digital Filter by  + +doxygen 1.6.3
+ + Index: gfir/trunk/vhdl/help/html/classmultiplier__gen.html =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen.html (revision 4) @@ -0,0 +1,143 @@ + + + + +FIR Digital Filter: multiplier_gen Entity Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Generics | +Ports | +Libraries | +Packages
+
+

multiplier_gen Entity Reference

+
+
+
+Inheritance diagram for multiplier_gen:
+
+
+ + +behave +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + + + +

+Architectures

behave Architecture

+Libraries

+ieee 

+Packages

+std_logic_1164 
+std_logic_signed 
+std_logic_arith 

+Generics

+multi_width_const  natural
+multi_width_in  natural

+Ports

+multiplier_const  in std_logic_vector ( multi_width_const-1 downto 0 )
 Constant multiplier hardwired to the filter coefficient.
+multiplier_in  in std_logic_vector ( multi_width_in-1 downto 0 )
 Constant multiplier input port with variable bit-width.
+multiplier_out  out std_logic_vector ( ( multi_width_const+multi_width_in ) +1 downto 0 )
 Constant multiplier output port.
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classdelay__gen-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen-members.html (revision 4) @@ -0,0 +1,94 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

delay_gen Member List

+
+
+This is the complete list of members for delay_gen, including all inherited members. + + + + + + + + + +
clkdelay_gen [Port]
clrdelay_gen [Port]
delay_indelay_gen [Port]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
ieee (defined in delay_gen)delay_gen [Library]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in delay_gen)delay_gen [Package]
std_logic_arith (defined in delay_gen)delay_gen [Package]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__DF.html (revision 4) @@ -0,0 +1,163 @@ + + + + +FIR Digital Filter: fir_filter_stage_DF Entity Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Ports | +Libraries | +Packages
+
+

fir_filter_stage_DF Entity Reference

+
+
+
+Inheritance diagram for fir_filter_stage_DF:
+
+
+ + +struct +multiplier_gen +delay_gen +adder_gen +behave +behave +behave + +
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + + + +

+Architectures

struct Architecture

+Libraries

ieee 

+Packages

+std_logic_1164 
+std_logic_arith 
+std_logic_unsigned 
+fir_pkg  Package <fir_pkg>

+Ports

+fir_clk  in std_logic
 Rising edge clock.
+fir_clr  in std_logic
 Active high asynchronous reset.
+fir_in  in std_logic_vector ( 0 downto 0 )
 Unsigned single/multi-bit input.
+fir_out  out std_logic_vector ( 14 downto 0 )
 Signed multi-bit output.
+

Member Data Documentation

+ +
+
+ + + + +
ieee library [Library]
+
+
+
+firDF.png +

Direct-form FIR Filter Structure

+
Author:
Ahmed Shahein ahmed.shahein@ieee.org
+
Date:
04.2012
+ +

Reimplemented from adder_gen.

+ +
+
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.png =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.png (revision 4)
gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/open.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/open.png =================================================================== --- gfir/trunk/vhdl/help/html/open.png (nonexistent) +++ gfir/trunk/vhdl/help/html/open.png (revision 4)
gfir/trunk/vhdl/help/html/open.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__TF.html (revision 4) @@ -0,0 +1,163 @@ + + + + +FIR Digital Filter: fir_filter_stage_TF Entity Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Ports | +Libraries | +Packages
+
+

fir_filter_stage_TF Entity Reference

+
+
+
+Inheritance diagram for fir_filter_stage_TF:
+
+
+ + +struct +multiplier_gen +delay_gen +adder_gen +behave +behave +behave + +
+ +

List of all members.

+ + + +
+
+ + + + + + + + + + + + + + + + +

+Architectures

struct Architecture

+Libraries

ieee 

+Packages

+std_logic_1164 
+std_logic_arith 
+std_logic_unsigned 
+fir_pkg  Package <fir_pkg>

+Ports

+fir_clk  in std_logic
 Rising edge clock.
+fir_clr  in std_logic
 Active high asynchronous reset.
+fir_in  in std_logic_vector ( 0 downto 0 )
 Unsigned single/multi-bit input.
+fir_out  out std_logic_vector ( 14 downto 0 )
 Signed multi-bit output.
+

Member Data Documentation

+ +
+
+ + + + +
ieee library [Library]
+
+
+
+firTF.png +

Transposed-form FIR Filter Structure

+
Author:
Ahmed Shahein ahmed.shahein@ieee.org
+
Date:
04.2012
+ +

Reimplemented from adder_gen.

+ +
+
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/class__tb__pack.html =================================================================== --- gfir/trunk/vhdl/help/html/class__tb__pack.html (nonexistent) +++ gfir/trunk/vhdl/help/html/class__tb__pack.html (revision 4) @@ -0,0 +1,105 @@ + + + + +FIR Digital Filter: tb_pack Package Body Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Procedures
+
+

tb_pack Package Body Reference

+
+
+ +

List of all members.

+ +
+
+Package >> tb_pack
+ + +

+Procedures

+  ReadData(
+constant filename: in string
+ signal bpsdm_data: out std_logic_vector
+ signal clk: in std_ulogic
+ signal finished: out std_ulogic
+ )
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/bc_s.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/bc_s.png =================================================================== --- gfir/trunk/vhdl/help/html/bc_s.png (nonexistent) +++ gfir/trunk/vhdl/help/html/bc_s.png (revision 4)
gfir/trunk/vhdl/help/html/bc_s.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.html =================================================================== --- gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classdelay__gen_1_1behave.html (revision 4) @@ -0,0 +1,118 @@ + + + + +FIR Digital Filter: behave Architecture Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+Processes
+
+

behave Architecture Reference

+
+
+
+Inheritance diagram for behave:
+
+
+ + +delay_gen +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +

List of all members.

+ +
+
+ + +

+Processes

+PROCESS_0  ( clr , clk )
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage_1_1struct-members.html (revision 4) @@ -0,0 +1,112 @@ + + + + + +FIR Digital Filter: Member List + + + + + + + + + +
+

struct Member List

This is the complete list of members for struct, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_b_inadder_gen [Port]
add_delaystruct [Signal]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0 (defined in struct)struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
coeffstruct [Constant]
delay_addstruct [Signal]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
ieee (defined in multiplier_gen)multiplier_gen [Library]
ieee (defined in delay_gen)delay_gen [Library]
ieee (defined in adder_gen)adder_gen [Library]
LastDELAYstruct [Component Instantiation]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_delaystruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
orderstruct [Constant]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in multiplier_gen)multiplier_gen [Package]
std_logic_1164 (defined in delay_gen)delay_gen [Package]
std_logic_1164 (defined in adder_gen)adder_gen [Package]
std_logic_arith (defined in multiplier_gen)multiplier_gen [Package]
std_logic_arith (defined in delay_gen)delay_gen [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
width_outstruct [Constant]
+ + + + +
+ +
+ +
Generated on Mon Apr 9 16:26:40 2012 for FIR Digital Filter by  + +doxygen 1.6.3
+ + Index: gfir/trunk/vhdl/help/html/tb__pack_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/tb__pack_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/tb__pack_8vhd.html (revision 4) @@ -0,0 +1,94 @@ + + + + +FIR Digital Filter: src/tb_pack.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/tb_pack.vhd File Reference

+
+
+ +

The test-bench supporting package. +More...

+ + + + +

+Architectures

tb_pack Package
tb_pack Package Body
+

Detailed Description

+

The test-bench supporting package.

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classmultiplier__gen-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen-members.html (revision 4) @@ -0,0 +1,96 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

multiplier_gen Member List

+
+
+This is the complete list of members for multiplier_gen, including all inherited members. + + + + + + + + + + + +
ieee (defined in multiplier_gen)multiplier_gen [Library]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
std_logic_1164 (defined in multiplier_gen)multiplier_gen [Package]
std_logic_arith (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF-members.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__DF-members.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__DF-members.html (revision 4) @@ -0,0 +1,130 @@ + + + + +FIR Digital Filter: Member List + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

fir_filter_stage_DF Member List

+
+
+This is the complete list of members for fir_filter_stage_DF, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
add_a_inadder_gen [Port]
add_addstruct [Signal]
add_b_inadder_gen [Port]
add_outadder_gen [Port]
add_width (defined in adder_gen)adder_gen [Generic]
ADDER0struct [Component Instantiation]
adder_gen (defined in struct)struct [Component]
ADDERs (defined in struct)struct [Component Instantiation]
clkdelay_gen [Port]
clrdelay_gen [Port]
coeffstruct [Constant]
delay_gen (defined in struct)struct [Component]
delay_indelay_gen [Port]
delay_multistruct [Signal]
delay_outdelay_gen [Port]
delay_width (defined in delay_gen)delay_gen [Generic]
DELAYs (defined in struct)struct [Component Instantiation]
fir_clkfir_filter_stage_DF [Port]
fir_clrfir_filter_stage_DF [Port]
fir_infir_filter_stage_DF [Port]
fir_outfir_filter_stage_DF [Port]
fir_pkg (defined in fir_filter_stage_DF)fir_filter_stage_DF [Package]
FirstDELAYstruct [Component Instantiation]
ieeefir_filter_stage_DF [Library]
MULTIstruct [Component Instantiation]
multi_addstruct [Signal]
multi_width_const (defined in multiplier_gen)multiplier_gen [Generic]
multi_width_in (defined in multiplier_gen)multiplier_gen [Generic]
multiplier_constmultiplier_gen [Port]
multiplier_gen (defined in struct)struct [Component]
multiplier_inmultiplier_gen [Port]
multiplier_outmultiplier_gen [Port]
MULTIs (defined in struct)struct [Component Instantiation]
orderstruct [Constant]
PROCESS_0(clr, clk) (defined in behave)behave [Process]
std_logic_1164 (defined in fir_filter_stage_DF)fir_filter_stage_DF [Package]
std_logic_arith (defined in fir_filter_stage_DF)fir_filter_stage_DF [Package]
std_logic_signed (defined in multiplier_gen)multiplier_gen [Package]
std_logic_signed (defined in adder_gen)adder_gen [Package]
std_logic_unsigned (defined in fir_filter_stage_DF)fir_filter_stage_DF [Package]
tmp_msb (defined in behave)behave [Signal]
tmp_multiplier_out (defined in behave)behave [Signal]
width_conststruct [Constant]
width_instruct [Constant]
width_outstruct [Constant]
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classes.html =================================================================== --- gfir/trunk/vhdl/help/html/classes.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classes.html (revision 4) @@ -0,0 +1,95 @@ + + + + +FIR Digital Filter: Design Units + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

Design Units

+
+
+
A | B | D | F | M | S | T | _
+ +
  A  
+		delay_gen::behave   fir_filter_stage_TF   
  S  
+		tb_pack   
adder_gen   
  D  
+		fir_pkg   fir_filter_stage_DF::struct   
  _  
+
  B  
+		delay_gen   
  M  
+		fir_filter_stage_TF::struct   _fir_pkg   
multiplier_gen::behave   
  F  
+		multiplier_gen   
  T  
+		_tb_pack   
adder_gen::behave   fir_filter_stage_DF   
A | B | D | F | M | S | T | _
+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.png =================================================================== --- gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.png (nonexistent) +++ gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.png (revision 4)
gfir/trunk/vhdl/help/html/classmultiplier__gen_1_1behave.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/html/doxygen.css =================================================================== --- gfir/trunk/vhdl/help/html/doxygen.css (nonexistent) +++ gfir/trunk/vhdl/help/html/doxygen.css (revision 4) @@ -0,0 +1,800 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 12px; +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; 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+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+

File List

+
+
+
Here is a list of all documented files with brief descriptions:
+ + + + + + + +
src/adder_gen.vhdThis is a two input signed adder
src/delay_gen.vhdThis is a positive edge triggered D-flip flop
src/fir_filter_stage_DF.vhdThis is the top-level design for a direct-form FIR digital filter.
+
src/fir_filter_stage_TF.vhdThis is the top-level design for a transposed-form FIR digital filter.
+
src/fir_pkg.vhdThis is the supporting package. "JUST EDIT THIS FILE"
src/multiplier_gen.vhdThis is signed constant multiplier with unsigned input port
src/tb_pack.vhdThe test-bench supporting package
+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:02 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/functions_vars.html =================================================================== --- gfir/trunk/vhdl/help/html/functions_vars.html (nonexistent) +++ gfir/trunk/vhdl/help/html/functions_vars.html (revision 4) @@ -0,0 +1,239 @@ + + + + +FIR Digital Filter: Design Unit Members - Variables + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + + +
+
+  + +

- a -

+ + +

- c -

+ + +

- d -

+ + +

- f -

+ + +

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+ + +

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- q -

+ + +

- w -

+
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+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/class__fir__pkg.html =================================================================== --- gfir/trunk/vhdl/help/html/class__fir__pkg.html (nonexistent) +++ gfir/trunk/vhdl/help/html/class__fir__pkg.html (revision 4) @@ -0,0 +1,104 @@ + + + + +FIR Digital Filter: fir_pkg Package Body Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Functions
+
+

fir_pkg Package Body Reference

+
+
+ +

List of all members.

+ +
+
+Package >> fir_pkg
+ + + + +

+Functions

+natural  binary_width ( x: in natural )
+natural  EOp ( M: in positive )
+natural  EOn ( M: in positive )
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/index.html =================================================================== --- gfir/trunk/vhdl/help/html/index.html (nonexistent) +++ gfir/trunk/vhdl/help/html/index.html (revision 4) @@ -0,0 +1,76 @@ + + + + +FIR Digital Filter: Main Page + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ +
+
+
+

FIR Digital Filter Documentation

+
+
+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/multiplier__gen_8vhd.html =================================================================== --- gfir/trunk/vhdl/help/html/multiplier__gen_8vhd.html (nonexistent) +++ gfir/trunk/vhdl/help/html/multiplier__gen_8vhd.html (revision 4) @@ -0,0 +1,94 @@ + + + + +FIR Digital Filter: src/multiplier_gen.vhd File Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + +
+
+
+Architectures
+
+

src/multiplier_gen.vhd File Reference

+
+
+ +

This is signed constant multiplier with unsigned input port. +More...

+ + + + +

+Architectures

multiplier_gen Entity
behave Architecture
+

Detailed Description

+

This is signed constant multiplier with unsigned input port.

+
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.html =================================================================== --- gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classadder__gen_1_1behave.html (revision 4) @@ -0,0 +1,108 @@ + + + + +FIR Digital Filter: behave Architecture Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+

behave Architecture Reference

+
+
+
+Inheritance diagram for behave:
+
+
+ + +adder_gen +struct +struct +fir_filter_stage_DF +fir_filter_stage_TF + +
+ +
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:00 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct.html =================================================================== --- gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct.html (nonexistent) +++ gfir/trunk/vhdl/help/html/classfir__filter__stage__DF_1_1struct.html (revision 4) @@ -0,0 +1,172 @@ + + + + +FIR Digital Filter: struct Architecture Reference + + + + + + + + +
+
+ + + + + + +
+
FIR Digital Filter
+
+
+ + + +
+
+
+Components | +Constants | +Signals | +Component Instantiations
+
+

struct Architecture Reference

+
+
+
+Inheritance diagram for struct:
+
+
+ + +multiplier_gen +delay_gen +adder_gen +behave +behave +behave +fir_filter_stage_DF + +
+ +

List of all members.

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Components

+multiplier_gen  <Entity multiplier_gen>
+adder_gen  <Entity adder_gen>
+delay_gen  <Entity delay_gen>

+Constants

+coeff  int_vector := fir_coeff_thirdstage
 Filter coefficients defined in the fir_pkg.vhd.
+width_in  natural := fir_in ' length
 Input bit-width.
+width_out  natural := fir_out ' length
 Output bit-width.
+width_const  positive := quantization
 Quantization bit-width defined in the fir_pkg.vhd.
+order  natural := coeff ' length
 Filter length.

+Signals

+multi_add  std_logic_vector ( order *width_out -1 downto 0 )
 Internal signal holding multiplier's outputs and adder's inputs.
+add_add  std_logic_vector ( ( order -1 ) *width_out -1 downto 0 )
 Internal signal holding preced adder output and proceed adder input.
+delay_multi  std_logic_vector ( ( order -1 ) *width_in -1 downto 0 )
 Internal signal holding delay's output and multiplier's inputs.

+Component Instantiations

+MULTI multiplier_gen <Entity multiplier_gen>
 Generate the filter multipliers set.
+MULTIs multiplier_gen <Entity multiplier_gen>
+FirstDELAY delay_gen <Entity delay_gen>
 Generate the filter delays set.
+DELAYs delay_gen <Entity delay_gen>
+ADDER0 adder_gen <Entity adder_gen>
 Generate the filter adders set.
+ADDERs adder_gen <Entity adder_gen>
+
The documentation for this class was generated from the following file: +
+ + + + +
+ +
+ +
Generated on Thu Apr 12 2012 22:44:01 for FIR Digital Filter by  + +doxygen 1.7.3
+ + Index: gfir/trunk/vhdl/help/doc/firTF.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/doc/firTF.jpg =================================================================== --- gfir/trunk/vhdl/help/doc/firTF.jpg (nonexistent) +++ gfir/trunk/vhdl/help/doc/firTF.jpg (revision 4)
gfir/trunk/vhdl/help/doc/firTF.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: gfir/trunk/vhdl/help/doc/firDF.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gfir/trunk/vhdl/help/doc/firDF.png =================================================================== --- gfir/trunk/vhdl/help/doc/firDF.png (nonexistent) +++ gfir/trunk/vhdl/help/doc/firDF.png (revision 4)
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