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/trunk/CODE/RX/CORE/flag_detect.vhd
32,6 → 32,14
-- Desccription : Created
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 10 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Code clean
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
49,8 → 57,6
end FlagDetect_ent;
 
architecture FlagDetect_beh of FlagDetect_ent is
type states_typ is (IDLE, ZERO, ONE1, ONE2, ONE3, ONE4, ONE5, ONE6);
-- State machine states
 
signal ShiftReg : std_logic_vector(7 downto 0); -- Shift Register
 
61,7 → 67,7
-- inputs : RXclk, rst
-- outputs:
bitstreem_proc : process (RXclk, rst)
variable state : states_typ; -- System State
 
variable FlagVar : std_logic; -- Flag detected variable
begin -- process bitstreem_proc
if rst = '0' then -- asynchronous reset (active low)
88,101 → 94,7
ShiftReg(7 downto 0) <= RX & ShiftReg(7 downto 1);
RXD <= ShiftReg(0);
 
-- case state is
 
-- when IDLE =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := IDLE;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
 
-- when ZERO =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE1;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
 
-- when ONE1 =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE2;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
-- when ONE2 =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE3;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
-- when ONE3 =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE4;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
-- when ONE4 =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE5;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
-- when ONE5 =>
-- if RX = '0' then
-- state := ZERO;
-- else
-- state := ONE6;
-- end if;
 
-- FlagDetect <= '0';
-- Abort <= '0';
---------------------------------------------------------------------------------
-- when ONE6 =>
-- if RX = '0' then
-- FlagDetect <= '1';
-- Abort <= '0';
-- else
 
-- FlagDetect <= '0';
-- Abort <= '1';
-- end if;
-- state := ZERO;
 
---------------------------------------------------------------------------------
-- when others =>
-- state := IDLE;
-- FlagDetect <= '0';
-- Abort <= '0';
 
-- end case;
 
-- RXD <= RX;
 
end if;
end process bitstreem_proc;
 
/trunk/CODE/RX/CORE/Rxcont.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/01/05
-- Last update: 2001/01/10
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
82,6 → 82,8
FlagInit := '0';
initzero <= '0';
FrameStatusReg := (others => '0');
FrameError <= '0';
FlagCounter := 0;
 
elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
-------------------------------------------------------------------------------

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