OpenCores
URL https://opencores.org/ocsvn/iota_pow_vhdl/iota_pow_vhdl/trunk

Subversion Repositories iota_pow_vhdl

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Rev 3 → Rev 4

/iota_pow_vhdl/trunk/pll.qip File deleted
/iota_pow_vhdl/trunk/curl.qpf File deleted
/iota_pow_vhdl/trunk/curl.qsf File deleted \ No newline at end of file
/iota_pow_vhdl/trunk/index_table.vhd File deleted
/iota_pow_vhdl/trunk/pll.cmp File deleted
/iota_pow_vhdl/trunk/pll.vhd File deleted
/iota_pow_vhdl/trunk/pll.ppf File deleted
/iota_pow_vhdl/trunk/curl.vhd File deleted
/iota_pow_vhdl/trunk/de1.vhd File deleted
/iota_pow_vhdl/trunk/spi_slave.vhd File deleted
/iota_pow_vhdl/trunk/vhdl_altera_de1/curl.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 12:30:40 April 16, 2018
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "13.0"
DATE = "12:30:40 April 16, 2018"
 
# Revisions
 
PROJECT_REVISION = "curl"
/iota_pow_vhdl/trunk/vhdl_altera_de1/curl.qsf
0,0 → 1,529
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 12:30:40 April 16, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# curl_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C6
set_global_assignment -name TOP_LEVEL_ENTITY de1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:30:40 APRIL 16, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE curl.vhd
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name QIP_FILE ram_curl.qip
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name VHDL_FILE de1.vhd
set_global_assignment -name SOURCE_FILE de1.qsf
set_location_assignment PIN_B6 -to AUD_ADCDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
set_location_assignment PIN_A4 -to AUD_BCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
set_location_assignment PIN_B4 -to AUD_XCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
set_location_assignment PIN_A12 -to CLOCK_24[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[1]
set_location_assignment PIN_B12 -to CLOCK_24[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[0]
set_location_assignment PIN_E12 -to CLOCK_27[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27[1]
set_location_assignment PIN_D12 -to CLOCK_27[0]
set_location_assignment PIN_L1 -to CLOCK_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
set_location_assignment PIN_N6 -to DRAM_ADDR[11]
set_location_assignment PIN_W3 -to DRAM_ADDR[10]
set_location_assignment PIN_N4 -to DRAM_ADDR[9]
set_location_assignment PIN_P3 -to DRAM_ADDR[8]
set_location_assignment PIN_P5 -to DRAM_ADDR[7]
set_location_assignment PIN_P6 -to DRAM_ADDR[6]
set_location_assignment PIN_R5 -to DRAM_ADDR[5]
set_location_assignment PIN_R6 -to DRAM_ADDR[4]
set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
set_location_assignment PIN_W5 -to DRAM_ADDR[1]
set_location_assignment PIN_W4 -to DRAM_ADDR[0]
set_location_assignment PIN_U3 -to DRAM_BA_0
set_location_assignment PIN_V4 -to DRAM_BA_1
set_location_assignment PIN_T3 -to DRAM_CAS_N
set_location_assignment PIN_N3 -to DRAM_CKE
set_location_assignment PIN_U4 -to DRAM_CLK
set_location_assignment PIN_T6 -to DRAM_CS_N
set_location_assignment PIN_T2 -to DRAM_DQ[15]
set_location_assignment PIN_T1 -to DRAM_DQ[14]
set_location_assignment PIN_R2 -to DRAM_DQ[13]
set_location_assignment PIN_R1 -to DRAM_DQ[12]
set_location_assignment PIN_P2 -to DRAM_DQ[11]
set_location_assignment PIN_P1 -to DRAM_DQ[10]
set_location_assignment PIN_N2 -to DRAM_DQ[9]
set_location_assignment PIN_N1 -to DRAM_DQ[8]
set_location_assignment PIN_Y2 -to DRAM_DQ[7]
set_location_assignment PIN_Y1 -to DRAM_DQ[6]
set_location_assignment PIN_W2 -to DRAM_DQ[5]
set_location_assignment PIN_W1 -to DRAM_DQ[4]
set_location_assignment PIN_V2 -to DRAM_DQ[3]
set_location_assignment PIN_V1 -to DRAM_DQ[2]
set_location_assignment PIN_U2 -to DRAM_DQ[1]
set_location_assignment PIN_U1 -to DRAM_DQ[0]
set_location_assignment PIN_R7 -to DRAM_LDQM
set_location_assignment PIN_T5 -to DRAM_RAS_N
set_location_assignment PIN_M5 -to DRAM_UDQM
set_location_assignment PIN_R8 -to DRAM_WE_N
set_location_assignment PIN_M21 -to EXT_CLOCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_CLOCK
set_location_assignment PIN_R13 -to FL_ADDR[21]
set_location_assignment PIN_U13 -to FL_ADDR[20]
set_location_assignment PIN_V14 -to FL_ADDR[19]
set_location_assignment PIN_U14 -to FL_ADDR[18]
set_location_assignment PIN_AA20 -to FL_ADDR[17]
set_location_assignment PIN_AB12 -to FL_ADDR[16]
set_location_assignment PIN_AA12 -to FL_ADDR[15]
set_location_assignment PIN_AB13 -to FL_ADDR[14]
set_location_assignment PIN_AA13 -to FL_ADDR[13]
set_location_assignment PIN_AB14 -to FL_ADDR[12]
set_location_assignment PIN_T12 -to FL_ADDR[11]
set_location_assignment PIN_R12 -to FL_ADDR[10]
set_location_assignment PIN_Y13 -to FL_ADDR[9]
set_location_assignment PIN_R14 -to FL_ADDR[8]
set_location_assignment PIN_W15 -to FL_ADDR[7]
set_location_assignment PIN_V15 -to FL_ADDR[6]
set_location_assignment PIN_U15 -to FL_ADDR[5]
set_location_assignment PIN_T15 -to FL_ADDR[4]
set_location_assignment PIN_R15 -to FL_ADDR[3]
set_location_assignment PIN_Y16 -to FL_ADDR[2]
set_location_assignment PIN_AA14 -to FL_ADDR[1]
set_location_assignment PIN_AB20 -to FL_ADDR[0]
set_location_assignment PIN_AB15 -to FL_CE_N
set_location_assignment PIN_AA19 -to FL_DQ[7]
set_location_assignment PIN_AB19 -to FL_DQ[6]
set_location_assignment PIN_AA18 -to FL_DQ[5]
set_location_assignment PIN_AB18 -to FL_DQ[4]
set_location_assignment PIN_AA17 -to FL_DQ[3]
set_location_assignment PIN_AB17 -to FL_DQ[2]
set_location_assignment PIN_AA16 -to FL_DQ[1]
set_location_assignment PIN_AB16 -to FL_DQ[0]
set_location_assignment PIN_AA15 -to FL_OE_N
set_location_assignment PIN_W14 -to FL_RST_N
set_location_assignment PIN_Y14 -to FL_WE_N
set_location_assignment PIN_L18 -to GPIO_0[35]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
set_location_assignment PIN_L19 -to GPIO_0[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
set_location_assignment PIN_K20 -to GPIO_0[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
set_location_assignment PIN_J18 -to GPIO_0[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
set_location_assignment PIN_J20 -to GPIO_0[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
set_location_assignment PIN_J19 -to GPIO_0[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
set_location_assignment PIN_K22 -to GPIO_0[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
set_location_assignment PIN_K21 -to GPIO_0[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
set_location_assignment PIN_J22 -to GPIO_0[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
set_location_assignment PIN_J21 -to GPIO_0[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
set_location_assignment PIN_G22 -to GPIO_0[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
set_location_assignment PIN_G21 -to GPIO_0[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
set_location_assignment PIN_F22 -to GPIO_0[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
set_location_assignment PIN_F21 -to GPIO_0[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
set_location_assignment PIN_E22 -to GPIO_0[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
set_location_assignment PIN_E21 -to GPIO_0[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
set_location_assignment PIN_D22 -to GPIO_0[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
set_location_assignment PIN_D21 -to GPIO_0[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
set_location_assignment PIN_C22 -to GPIO_0[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
set_location_assignment PIN_C21 -to GPIO_0[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
set_location_assignment PIN_B20 -to GPIO_0[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
set_location_assignment PIN_A20 -to GPIO_0[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
set_location_assignment PIN_B19 -to GPIO_0[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
set_location_assignment PIN_A19 -to GPIO_0[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
set_location_assignment PIN_B18 -to GPIO_0[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
set_location_assignment PIN_A18 -to GPIO_0[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
set_location_assignment PIN_B17 -to GPIO_0[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
set_location_assignment PIN_A17 -to GPIO_0[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
set_location_assignment PIN_B16 -to GPIO_0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
set_location_assignment PIN_A16 -to GPIO_0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
set_location_assignment PIN_B15 -to GPIO_0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
set_location_assignment PIN_A15 -to GPIO_0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
set_location_assignment PIN_B14 -to GPIO_0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
set_location_assignment PIN_A14 -to GPIO_0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
set_location_assignment PIN_B13 -to GPIO_0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
set_location_assignment PIN_A13 -to GPIO_0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
set_location_assignment PIN_P18 -to GPIO_1[35]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
set_location_assignment PIN_P17 -to GPIO_1[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
set_location_assignment PIN_N15 -to GPIO_1[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
set_location_assignment PIN_P15 -to GPIO_1[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
set_location_assignment PIN_N21 -to GPIO_1[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
set_location_assignment PIN_N22 -to GPIO_1[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
set_location_assignment PIN_H18 -to GPIO_1[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
set_location_assignment PIN_J15 -to GPIO_1[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
set_location_assignment PIN_H17 -to GPIO_1[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
set_location_assignment PIN_G17 -to GPIO_1[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
set_location_assignment PIN_G18 -to GPIO_1[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
set_location_assignment PIN_G20 -to GPIO_1[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
set_location_assignment PIN_E18 -to GPIO_1[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
set_location_assignment PIN_E19 -to GPIO_1[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
set_location_assignment PIN_F20 -to GPIO_1[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
set_location_assignment PIN_E20 -to GPIO_1[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
set_location_assignment PIN_D20 -to GPIO_1[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
set_location_assignment PIN_D19 -to GPIO_1[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
set_location_assignment PIN_C20 -to GPIO_1[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
set_location_assignment PIN_C19 -to GPIO_1[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
set_location_assignment PIN_C18 -to GPIO_1[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
set_location_assignment PIN_C17 -to GPIO_1[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
set_location_assignment PIN_D16 -to GPIO_1[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
set_location_assignment PIN_D15 -to GPIO_1[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
set_location_assignment PIN_D14 -to GPIO_1[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
set_location_assignment PIN_C14 -to GPIO_1[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
set_location_assignment PIN_F13 -to GPIO_1[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
set_location_assignment PIN_F12 -to GPIO_1[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
set_location_assignment PIN_G16 -to GPIO_1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
set_location_assignment PIN_F15 -to GPIO_1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
set_location_assignment PIN_E15 -to GPIO_1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
set_location_assignment PIN_E14 -to GPIO_1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
set_location_assignment PIN_G15 -to GPIO_1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
set_location_assignment PIN_H14 -to GPIO_1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
set_location_assignment PIN_H13 -to GPIO_1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
set_location_assignment PIN_H12 -to GPIO_1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
set_location_assignment PIN_E2 -to HEX0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
set_location_assignment PIN_F1 -to HEX0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
set_location_assignment PIN_F2 -to HEX0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
set_location_assignment PIN_H1 -to HEX0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
set_location_assignment PIN_H2 -to HEX0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
set_location_assignment PIN_J1 -to HEX0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
set_location_assignment PIN_J2 -to HEX0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
set_location_assignment PIN_D1 -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
set_location_assignment PIN_D2 -to HEX1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
set_location_assignment PIN_G3 -to HEX1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
set_location_assignment PIN_H4 -to HEX1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
set_location_assignment PIN_H5 -to HEX1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
set_location_assignment PIN_H6 -to HEX1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
set_location_assignment PIN_E1 -to HEX1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
set_location_assignment PIN_D3 -to HEX2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
set_location_assignment PIN_E4 -to HEX2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
set_location_assignment PIN_E3 -to HEX2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
set_location_assignment PIN_C1 -to HEX2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
set_location_assignment PIN_C2 -to HEX2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
set_location_assignment PIN_G6 -to HEX2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
set_location_assignment PIN_G5 -to HEX2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
set_location_assignment PIN_D4 -to HEX3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
set_location_assignment PIN_F3 -to HEX3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
set_location_assignment PIN_L8 -to HEX3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
set_location_assignment PIN_J4 -to HEX3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
set_location_assignment PIN_D6 -to HEX3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
set_location_assignment PIN_D5 -to HEX3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
set_location_assignment PIN_F4 -to HEX3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
set_location_assignment PIN_A3 -to I2C_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
set_location_assignment PIN_T21 -to KEY[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
set_location_assignment PIN_T22 -to KEY[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
set_location_assignment PIN_R21 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_R22 -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_location_assignment PIN_Y21 -to LEDG[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
set_location_assignment PIN_Y22 -to LEDG[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
set_location_assignment PIN_W21 -to LEDG[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
set_location_assignment PIN_W22 -to LEDG[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
set_location_assignment PIN_V21 -to LEDG[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
set_location_assignment PIN_V22 -to LEDG[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
set_location_assignment PIN_U21 -to LEDG[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
set_location_assignment PIN_U22 -to LEDG[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
set_location_assignment PIN_R17 -to LEDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
set_location_assignment PIN_R18 -to LEDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
set_location_assignment PIN_U18 -to LEDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
set_location_assignment PIN_Y18 -to LEDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
set_location_assignment PIN_V19 -to LEDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
set_location_assignment PIN_T18 -to LEDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
set_location_assignment PIN_Y19 -to LEDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
set_location_assignment PIN_U19 -to LEDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
set_location_assignment PIN_R19 -to LEDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
set_location_assignment PIN_R20 -to LEDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
set_location_assignment PIN_H15 -to PS2_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
set_location_assignment PIN_J14 -to PS2_DAT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
set_location_assignment PIN_T7 -to SRAM_ADDR[15]
set_location_assignment PIN_R10 -to SRAM_ADDR[14]
set_location_assignment PIN_U10 -to SRAM_ADDR[13]
set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
set_location_assignment PIN_T11 -to SRAM_ADDR[11]
set_location_assignment PIN_R11 -to SRAM_ADDR[10]
set_location_assignment PIN_W11 -to SRAM_ADDR[9]
set_location_assignment PIN_V11 -to SRAM_ADDR[8]
set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
set_location_assignment PIN_AB5 -to SRAM_CE_N
set_location_assignment PIN_U8 -to SRAM_DQ[15]
set_location_assignment PIN_V8 -to SRAM_DQ[14]
set_location_assignment PIN_W8 -to SRAM_DQ[13]
set_location_assignment PIN_R9 -to SRAM_DQ[12]
set_location_assignment PIN_U9 -to SRAM_DQ[11]
set_location_assignment PIN_V9 -to SRAM_DQ[10]
set_location_assignment PIN_W9 -to SRAM_DQ[9]
set_location_assignment PIN_Y9 -to SRAM_DQ[8]
set_location_assignment PIN_AB9 -to SRAM_DQ[7]
set_location_assignment PIN_AA9 -to SRAM_DQ[6]
set_location_assignment PIN_AB8 -to SRAM_DQ[5]
set_location_assignment PIN_AA8 -to SRAM_DQ[4]
set_location_assignment PIN_AB7 -to SRAM_DQ[3]
set_location_assignment PIN_AA7 -to SRAM_DQ[2]
set_location_assignment PIN_AB6 -to SRAM_DQ[1]
set_location_assignment PIN_AA6 -to SRAM_DQ[0]
set_location_assignment PIN_Y7 -to SRAM_LB_N
set_location_assignment PIN_T8 -to SRAM_OE_N
set_location_assignment PIN_W7 -to SRAM_UB_N
set_location_assignment PIN_AA10 -to SRAM_WE_N
set_location_assignment PIN_L2 -to SW[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
set_location_assignment PIN_M1 -to SW[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
set_location_assignment PIN_M2 -to SW[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
set_location_assignment PIN_U11 -to SW[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
set_location_assignment PIN_U12 -to SW[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
set_location_assignment PIN_W12 -to SW[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
set_location_assignment PIN_V12 -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_M22 -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_location_assignment PIN_L21 -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_location_assignment PIN_L22 -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_location_assignment PIN_C7 -to TCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK
set_location_assignment PIN_D8 -to TCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS
set_location_assignment PIN_E8 -to TDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI
set_location_assignment PIN_D7 -to TDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO
set_location_assignment PIN_F14 -to UART_RXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
set_location_assignment PIN_G12 -to UART_TXD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
set_location_assignment PIN_B10 -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_location_assignment PIN_A10 -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_location_assignment PIN_D11 -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_location_assignment PIN_A9 -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_location_assignment PIN_A8 -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_location_assignment PIN_B9 -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_location_assignment PIN_C10 -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_location_assignment PIN_B8 -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_location_assignment PIN_A11 -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_location_assignment PIN_B7 -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_location_assignment PIN_A7 -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_location_assignment PIN_C9 -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_location_assignment PIN_D9 -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_location_assignment PIN_B11 -to VGA_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
 
set_global_assignment -name VHDL_FILE spi_slave.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id TOP_LEVEL_ENTITY
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id TOP_LEVEL_ENTITY
set_global_assignment -name PARTITION_COLOR 16764057 -section_id TOP_LEVEL_ENTITY
set_global_assignment -name VHDL_FILE index_table.vhd
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id TOP_LEVEL_ENTITY
/iota_pow_vhdl/trunk/vhdl_altera_de1/curl.vhd
0,0 → 1,311
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
--
-- http://www.microengineer.eu
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.index_table.all;
 
entity curl is
generic
(
HASH_LENGTH : integer := 243;
STATE_LENGTH : integer := 729; -- 3 * HASH_LENGTH;
NONCE_LENGTH : integer := 81; -- HASH_LENGTH / 3;
NUMBER_OF_ROUNDS : integer := 81;
PARALLEL : integer := 5;
INTERN_NONCE_LENGTH : integer := 32;
BITS_MIN_WEIGHT_MAGINUTE_MAX : integer := 26;
DATA_WIDTH : integer := 9
);
 
port
(
clk : in std_logic;
clk_slow : in std_logic;
reset : in std_logic;
spi_data_rx : in std_logic_vector(31 downto 0);
spi_data_tx : out std_logic_vector(31 downto 0);
spi_data_rxen : in std_logic;
overflow : out std_logic;
running : out std_logic;
found : out std_logic
);
end curl;
 
architecture behv of curl is
 
subtype state_vector_type is std_logic_vector(PARALLEL-1 downto 0);
subtype mid_state_vector_type is std_logic_vector(DATA_WIDTH-1 downto 0);
 
type curl_state_array is array(integer range <>) of state_vector_type;
type mid_state_array is array(integer range <>) of mid_state_vector_type;
 
signal curl_state_low : curl_state_array(STATE_LENGTH-1 downto 0);
signal curl_state_high : curl_state_array(STATE_LENGTH-1 downto 0);
 
-- mid state data in 9bit packed format
signal curl_mid_state_low : mid_state_array((STATE_LENGTH/9)-1 downto 0);
signal curl_mid_state_high : mid_state_array((STATE_LENGTH/9)-1 downto 0);
 
signal flag_running : std_logic := '0';
signal flag_overflow : std_logic := '0';
signal flag_found : std_logic := '0';
signal flag_start : std_logic := '0';
 
signal binary_nonce : unsigned(INTERN_NONCE_LENGTH-1 downto 0);
signal mask : state_vector_type;
signal min_weight_magnitude : std_logic_vector(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0);
 
 
begin
overflow <= flag_overflow;
running <= flag_running;
found <= flag_found;
process (clk_slow)
-- because it looks prettier
variable spi_cmd : std_logic_vector(5 downto 0);
variable wraddr : integer range 0 to 127 := 0;
begin
if rising_edge(clk_slow) then
if reset='1' then
-- binary_nonce <= (others => '0');
min_weight_magnitude <= (others => '0');
flag_start <= '0';
else
flag_start <= '0';
-- new spi data received
if spi_data_rxen = '1' then
spi_cmd := spi_data_rx(31 downto 26);
case spi_cmd is
when "000000" => -- nop
when "100001" => -- start / stop
if spi_data_rx(0) = '1' then
flag_start <= '1';
end if;
when "100101" => -- write to wr address
wraddr := 0;
when "100010" => -- write to mid state
curl_mid_state_low(wraddr) <= std_logic_vector(spi_data_rx(DATA_WIDTH-1 downto 0));
curl_mid_state_high(wraddr) <= std_logic_vector(spi_data_rx(DATA_WIDTH+8 downto DATA_WIDTH));
wraddr := wraddr + 1;
when "100100" =>
min_weight_magnitude <= spi_data_rx(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0);
 
when "000001" => -- read flags
spi_data_tx <= "00000000000000000000000000000" & flag_overflow & flag_found & flag_running;
-- this costs an extreme amount of resources
-- interesting only for debugging
-- when "000010" =>
-- spi_addr := spi_data_rx(25 downto 16);
-- spi_data_tx(0+PARALLEL-1 downto 0) <= curl_state_low(to_integer(unsigned(spi_addr)));
-- spi_data_tx(8+PARALLEL-1 downto 8) <= curl_state_high(to_integer(unsigned(spi_addr)));
when "000011" => -- read nonce
spi_data_tx(31 downto INTERN_NONCE_LENGTH) <= (others => '0');
spi_data_tx(INTERN_NONCE_LENGTH-1 downto 0) <= std_logic_vector(binary_nonce);
when "000100" => -- read mask
spi_data_tx(PARALLEL-1 downto 0) <= mask;
spi_data_tx(31 downto PARALLEL) <= (others => '0');
when "000110" => -- read back parallel-level
spi_data_tx <= std_logic_vector(to_unsigned(PARALLEL, spi_data_tx'length));
when "010101" => -- loop back read test inverted bits
spi_data_tx <= not spi_data_rx;
when others =>
spi_data_tx <= (others => '1');
end case;
end if;
end if;
end if;
end process;
process (clk)
variable state : integer range 0 to 31 := 0;
variable round : integer range 0 to 127 := 0;
 
variable imask : state_vector_type;
variable i_min_weight_magnitude : std_logic_vector(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0);
 
-- temporary registers get optimized away
variable alpha : curl_state_array(STATE_LENGTH-1 downto 0);
variable beta : curl_state_array(STATE_LENGTH-1 downto 0);
variable gamma : curl_state_array(STATE_LENGTH-1 downto 0);
variable delta : curl_state_array(STATE_LENGTH-1 downto 0);
variable epsilon : curl_state_array(STATE_LENGTH-1 downto 0);
variable tmp_index : integer range 0 to 1023;
variable tmp_mod : integer range 0 to 31;
begin
if rising_edge(clk) then
if reset='1' then
state := 0;
flag_found <= '0';
flag_running <= '0';
flag_overflow <= '0';
binary_nonce <= (others => '0');
else
case state is
when 0 =>
flag_running <= '0';
if flag_start = '1' then
i_min_weight_magnitude := min_weight_magnitude;
state := 1;
end if;
-- nop until start from spi
when 1 =>
binary_nonce <= (others => '0');
flag_found <= '0';
flag_running <= '1';
flag_overflow <= '0';
state := 8;
when 8 => -- copy mid state and insert nonce
-- pipeline adder for speed
binary_nonce <= binary_nonce + 1;
-- copy and fully expand mid-state to curl-state
for I in 0 to (STATE_LENGTH/DATA_WIDTH)-1 loop
for J in 0 to DATA_WIDTH-1 loop
tmp_index := I*DATA_WIDTH+J;
if tmp_index < 162 or tmp_index > HASH_LENGTH-1 then
if curl_mid_state_low(I)(J) = '1' then
curl_state_low(tmp_index) <= (others => '1');
else
curl_state_low(tmp_index) <= (others => '0');
end if;
if curl_mid_state_high(I)(J) = '1' then
curl_state_high(tmp_index) <= (others => '1');
else
curl_state_high(tmp_index) <= (others => '0');
end if;
end if;
end loop;
end loop;
-- -- generate bitmuster in first two trit-arrays of counter depending from PARALLEL setting
-- -- doesn't need additional resources for pow or division because everything is constant
for J in 0 to 1 loop -- TODO make adjustable ... it's okay up to PARALLEL = 9
for I in 0 to PARALLEL-1 loop
tmp_mod := (I/(3**J)) mod 3;
if tmp_mod = 0 then
curl_state_low(162+J)(I) <= '1';
curl_state_high(162+J)(I) <= '1';
elsif tmp_mod = 1 then
curl_state_low(162+J)(I) <= '0';
curl_state_high(162+J)(I) <= '1';
elsif tmp_mod = 2 then
curl_state_low(162+J)(I) <= '1';
curl_state_high(162+J)(I) <= '0';
end if;
end loop;
end loop;
 
-- lowest trits for counter from 0 to 4 (for 5bit)
-- curl_state_low(162) <= "01101";
-- curl_state_high(162) <= "11011";
-- curl_state_low(163) <= "00111";
-- curl_state_high(163) <= "11111";
-- insert and convert binary nonce to trinary nonce
-- It's a fake trinary nonce but integer-values are strictly monotonously rising
-- with integer values of binary nonce.
-- Doesn't bring the exact same result like reference implementation with real
-- trinary adder - but it doesn't matter and it is way faster.
for I in 164 to 164+INTERN_NONCE_LENGTH-1 loop
if binary_nonce(I-164) = '1' then
curl_state_low(I) <= (others => '1');
curl_state_high(I) <= (others => '0');
else
curl_state_low(I) <= (others => '0');
curl_state_high(I) <= (others => '1');
end if;
end loop;
-- fill remaining trits with '11' (=0)
for I in 164+INTERN_NONCE_LENGTH to HASH_LENGTH-1 loop
curl_state_low(I) <= (others => '1');
curl_state_high(I) <= (others => '1');
end loop;
 
-- initialize round-counter
round := NUMBER_OF_ROUNDS;
state := 10;
when 10 => -- do the curl hash round without any copying needed
for I in 0 to STATE_LENGTH-1 loop
alpha(I) := curl_state_low(index_table(I));
beta(I) := curl_state_high(index_table(I));
gamma(I) := curl_state_high(index_table(I+1));
delta(I) := (alpha(I) or (not gamma(I))) and (curl_state_low(index_table(I+1)) xor beta(I));
 
curl_state_low(I) <= not delta(I);
curl_state_high(I) <= (alpha(I) xor gamma(I)) or delta(I);
end loop;
 
round := round - 1;
if round = 0 then
state := 16;
end if;
when 16 => -- find out which solution - if any
imask := (others => '1');
-- doesn't work like the 2nd variant ... why? TODO^^
for I in 0 to PARALLEL-1 loop
for J in 0 to BITS_MIN_WEIGHT_MAGINUTE_MAX-1 loop
if i_min_weight_magnitude(J) = '1' and (curl_state_low(HASH_LENGTH - 1 - J)(I) /= '1' or curl_state_high(HASH_LENGTH - 1 - J)(I) /= '1') then
imask(I) := '0';
end if;
end loop;
end loop;
-- imask := (others => '1');
-- for I in 0 to BITS_MIN_WEIGHT_MAGINUTE_MAX-1 loop
-- if i_min_weight_magnitude(I) = '1' then
-- imask := imask and not (curl_state_low(HASH_LENGTH - 1 - I) xor curl_state_high(HASH_LENGTH - 1 - I));
-- end if;
-- end loop;
-- mask <= imask;
 
-- no solution found?
if unsigned(imask) = 0 then
-- is overflow?
if binary_nonce = x"ffffffff" then
flag_overflow <= '1';
state := 0;
else
state := 8; -- and try again
end if;
else
state := 30; -- nonce found
end if;
when 30 =>
mask <= imask;
flag_found <= '1';
state := 0;
when others =>
state := 0;
end case;
end if;
end if;
end process;
end behv;
/iota_pow_vhdl/trunk/vhdl_altera_de1/de1.vhd
0,0 → 1,243
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
--
-- http://www.microengineer.eu
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity de1 is
port (
-- //////////////////// Clock Input ////////////////////
CLOCK_24 : in std_logic_vector (1 downto 0);
CLOCK_27 : in std_logic_vector (1 downto 0);
CLOCK_50 : in std_logic;
EXT_CLOCK : in std_logic;
-- //////////////////// Push Button ////////////////////
KEY : in std_logic_vector(3 downto 0);
-- //////////////////// DPDT Switch ////////////////////
SW : in std_logic_vector (9 downto 0);
-- //////////////////// 7-SEG Dispaly ////////////////////
HEX0 : out std_logic_vector (6 downto 0);
HEX1 : out std_logic_vector (6 downto 0);
HEX2 : out std_logic_vector (6 downto 0);
HEX3 : out std_logic_vector (6 downto 0);
-- //////////////////////// LED ////////////////////////
LEDG : out std_logic_vector (7 downto 0);
LEDR : out std_logic_vector (9 downto 0);
-- //////////////////////// UART ////////////////////////
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- ///////////////////// SDRAM Interface ////////////////
DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CKE : out std_logic;
-- //////////////////// Flash Interface ////////////////
FL_DQ : inout std_logic_vector (7 downto 0);
FL_ADDR : out std_logic_vector (21 downto 0);
FL_WE_N : out std_logic;
FL_RST_N : out std_logic;
FL_OE_N : out std_logic;
FL_CE_N : out std_logic;
-- //////////////////// SRAM Interface ////////////////
SRAM_DQ : inout std_logic_vector (15 downto 0);
SRAM_ADDR : out std_logic_vector (17 downto 0);
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_WE_N : out std_logic;
SRAM_CE_N : out std_logic;
SRAM_OE_N : out std_logic;
-- //////////////////// SD_Card Interface ////////////////
SD_DAT : inout std_logic;
SD_DAT3 : inout std_logic;
SD_CMD : inout std_logic;
SD_CLK : out std_logic;
-- //////////////////// USB JTAG link ////////////////////
TDI : in std_logic;
TCK : in std_logic;
TCS : in std_logic;
TDO : out std_logic;
-- //////////////////// I2C ////////////////////////////
I2C_SDAT : inout std_logic;
I2C_SCLK : out std_logic;
-- //////////////////// PS2 ////////////////////////////
PS2_DAT : in std_logic;
PS2_CLK : in std_logic;
-- //////////////////// VGA ////////////////////////////
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_R : out std_logic_vector (3 downto 0);
VGA_G: out std_logic_vector (3 downto 0);
VGA_B: out std_logic_vector (3 downto 0);
-- //////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK : inout std_logic;
AUD_ADCDAT : in std_logic;
AUD_DACLRCK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_BCLK : out std_logic;
AUD_XCK : out std_logic;
-- //////////////////// GPIO ////////////////////////////
GPIO_0 : inout std_logic_vector (35 downto 0);
GPIO_1 : inout std_logic_vector (35 downto 0)
);
end;
 
architecture beh of de1 is
 
 
signal reset : std_logic;
 
signal pll_clk : std_logic;
signal pll_reset : std_logic := '0';
signal pll_locked : std_logic;
 
signal spi_data_tx : std_logic_vector(31 downto 0);
signal spi_data_rx : std_logic_vector(31 downto 0);
signal spi_data_rx_en : std_logic;
 
signal running : std_logic := '0';
signal overflow : std_logic := '0';
signal found : std_logic := '0';
 
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal spi_sck : std_logic;
signal spi_ss : std_logic;
signal pll_slow : std_logic;
component spi_slave
port
(
clk : in std_logic;
reset : in std_logic;
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic;
ss : in std_logic;
data_rd : in std_logic_vector(31 downto 0);
data_wr : out std_logic_vector(31 downto 0);
data_wren : out std_logic
);
end component;
 
component pll
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : out std_logic;
locked : OUT STD_LOGIC
);
end component;
 
component curl
port
(
clk : in std_logic;
clk_slow : in std_logic;
reset : in std_logic;
spi_data_rx : in std_logic_vector(31 downto 0);
spi_data_tx : out std_logic_vector(31 downto 0);
spi_data_rxen : in std_logic;
 
overflow : out std_logic;
running : out std_logic;
found : out std_logic
);
end component;
 
begin
pll0 : pll port map (
areset => pll_reset,
inclk0 => CLOCK_50,
c0 => pll_clk,
c1 => pll_slow,
locked => pll_locked
);
spi0 : spi_slave port map (
clk => pll_slow,
reset => reset,
mosi => spi_mosi,
miso => spi_miso,
sck => spi_sck,
ss => spi_ss,
data_rd => spi_data_tx,
data_wr => spi_data_rx,
data_wren => spi_data_rx_en
);
curl0 : curl port map (
clk => pll_clk,
reset => reset,
clk_slow => pll_slow,
spi_data_rx => spi_data_rx,
spi_data_tx => spi_data_tx,
spi_data_rxen => spi_data_rx_en,
overflow => overflow,
running => running,
found => found
);
-- disable all DE1 stuff
DRAM_DQ <= (others => 'Z');
FL_DQ <= (others => 'Z');
SRAM_DQ <= (others => 'Z');
SD_DAT <= 'Z';
I2C_SDAT <= 'Z';
GPIO_0 <= (others => 'Z');
GPIO_1 <= (others => 'Z');
 
LEDR <= "0" & "1" & spi_ss & spi_sck & spi_mosi & spi_miso & reset & overflow & found & running;
LEDG <= (others => '0');
 
AUD_BCLK <= '0';
AUD_DACLRCK <= '0';
AUD_ADCLRCK <= '0';
AUD_XCK <= '0';
 
SRAM_ADDR(17)<='0';
 
reset <= not SW(0);
 
spi_mosi <= GPIO_0(0);
spi_sck <= GPIO_0(2);
spi_ss <= GPIO_0(3);
 
-- all pins except one is input
GPIO_0(3 downto 0) <= "ZZ" & spi_miso & "Z";
 
 
end architecture;
/iota_pow_vhdl/trunk/vhdl_altera_de1/index_table.vhd
0,0 → 1,763
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
--
-- http://www.microengineer.eu
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package index_table is
type const_index_table is array ( 0 to 729) of integer range 0 to 728;
constant index_table : const_index_table := (
0 => 0,
1 => 364,
2 => 728,
3 => 363,
4 => 727,
5 => 362,
6 => 726,
7 => 361,
8 => 725,
9 => 360,
10 => 724,
11 => 359,
12 => 723,
13 => 358,
14 => 722,
15 => 357,
16 => 721,
17 => 356,
18 => 720,
19 => 355,
20 => 719,
21 => 354,
22 => 718,
23 => 353,
24 => 717,
25 => 352,
26 => 716,
27 => 351,
28 => 715,
29 => 350,
30 => 714,
31 => 349,
32 => 713,
33 => 348,
34 => 712,
35 => 347,
36 => 711,
37 => 346,
38 => 710,
39 => 345,
40 => 709,
41 => 344,
42 => 708,
43 => 343,
44 => 707,
45 => 342,
46 => 706,
47 => 341,
48 => 705,
49 => 340,
50 => 704,
51 => 339,
52 => 703,
53 => 338,
54 => 702,
55 => 337,
56 => 701,
57 => 336,
58 => 700,
59 => 335,
60 => 699,
61 => 334,
62 => 698,
63 => 333,
64 => 697,
65 => 332,
66 => 696,
67 => 331,
68 => 695,
69 => 330,
70 => 694,
71 => 329,
72 => 693,
73 => 328,
74 => 692,
75 => 327,
76 => 691,
77 => 326,
78 => 690,
79 => 325,
80 => 689,
81 => 324,
82 => 688,
83 => 323,
84 => 687,
85 => 322,
86 => 686,
87 => 321,
88 => 685,
89 => 320,
90 => 684,
91 => 319,
92 => 683,
93 => 318,
94 => 682,
95 => 317,
96 => 681,
97 => 316,
98 => 680,
99 => 315,
100 => 679,
101 => 314,
102 => 678,
103 => 313,
104 => 677,
105 => 312,
106 => 676,
107 => 311,
108 => 675,
109 => 310,
110 => 674,
111 => 309,
112 => 673,
113 => 308,
114 => 672,
115 => 307,
116 => 671,
117 => 306,
118 => 670,
119 => 305,
120 => 669,
121 => 304,
122 => 668,
123 => 303,
124 => 667,
125 => 302,
126 => 666,
127 => 301,
128 => 665,
129 => 300,
130 => 664,
131 => 299,
132 => 663,
133 => 298,
134 => 662,
135 => 297,
136 => 661,
137 => 296,
138 => 660,
139 => 295,
140 => 659,
141 => 294,
142 => 658,
143 => 293,
144 => 657,
145 => 292,
146 => 656,
147 => 291,
148 => 655,
149 => 290,
150 => 654,
151 => 289,
152 => 653,
153 => 288,
154 => 652,
155 => 287,
156 => 651,
157 => 286,
158 => 650,
159 => 285,
160 => 649,
161 => 284,
162 => 648,
163 => 283,
164 => 647,
165 => 282,
166 => 646,
167 => 281,
168 => 645,
169 => 280,
170 => 644,
171 => 279,
172 => 643,
173 => 278,
174 => 642,
175 => 277,
176 => 641,
177 => 276,
178 => 640,
179 => 275,
180 => 639,
181 => 274,
182 => 638,
183 => 273,
184 => 637,
185 => 272,
186 => 636,
187 => 271,
188 => 635,
189 => 270,
190 => 634,
191 => 269,
192 => 633,
193 => 268,
194 => 632,
195 => 267,
196 => 631,
197 => 266,
198 => 630,
199 => 265,
200 => 629,
201 => 264,
202 => 628,
203 => 263,
204 => 627,
205 => 262,
206 => 626,
207 => 261,
208 => 625,
209 => 260,
210 => 624,
211 => 259,
212 => 623,
213 => 258,
214 => 622,
215 => 257,
216 => 621,
217 => 256,
218 => 620,
219 => 255,
220 => 619,
221 => 254,
222 => 618,
223 => 253,
224 => 617,
225 => 252,
226 => 616,
227 => 251,
228 => 615,
229 => 250,
230 => 614,
231 => 249,
232 => 613,
233 => 248,
234 => 612,
235 => 247,
236 => 611,
237 => 246,
238 => 610,
239 => 245,
240 => 609,
241 => 244,
242 => 608,
243 => 243,
244 => 607,
245 => 242,
246 => 606,
247 => 241,
248 => 605,
249 => 240,
250 => 604,
251 => 239,
252 => 603,
253 => 238,
254 => 602,
255 => 237,
256 => 601,
257 => 236,
258 => 600,
259 => 235,
260 => 599,
261 => 234,
262 => 598,
263 => 233,
264 => 597,
265 => 232,
266 => 596,
267 => 231,
268 => 595,
269 => 230,
270 => 594,
271 => 229,
272 => 593,
273 => 228,
274 => 592,
275 => 227,
276 => 591,
277 => 226,
278 => 590,
279 => 225,
280 => 589,
281 => 224,
282 => 588,
283 => 223,
284 => 587,
285 => 222,
286 => 586,
287 => 221,
288 => 585,
289 => 220,
290 => 584,
291 => 219,
292 => 583,
293 => 218,
294 => 582,
295 => 217,
296 => 581,
297 => 216,
298 => 580,
299 => 215,
300 => 579,
301 => 214,
302 => 578,
303 => 213,
304 => 577,
305 => 212,
306 => 576,
307 => 211,
308 => 575,
309 => 210,
310 => 574,
311 => 209,
312 => 573,
313 => 208,
314 => 572,
315 => 207,
316 => 571,
317 => 206,
318 => 570,
319 => 205,
320 => 569,
321 => 204,
322 => 568,
323 => 203,
324 => 567,
325 => 202,
326 => 566,
327 => 201,
328 => 565,
329 => 200,
330 => 564,
331 => 199,
332 => 563,
333 => 198,
334 => 562,
335 => 197,
336 => 561,
337 => 196,
338 => 560,
339 => 195,
340 => 559,
341 => 194,
342 => 558,
343 => 193,
344 => 557,
345 => 192,
346 => 556,
347 => 191,
348 => 555,
349 => 190,
350 => 554,
351 => 189,
352 => 553,
353 => 188,
354 => 552,
355 => 187,
356 => 551,
357 => 186,
358 => 550,
359 => 185,
360 => 549,
361 => 184,
362 => 548,
363 => 183,
364 => 547,
365 => 182,
366 => 546,
367 => 181,
368 => 545,
369 => 180,
370 => 544,
371 => 179,
372 => 543,
373 => 178,
374 => 542,
375 => 177,
376 => 541,
377 => 176,
378 => 540,
379 => 175,
380 => 539,
381 => 174,
382 => 538,
383 => 173,
384 => 537,
385 => 172,
386 => 536,
387 => 171,
388 => 535,
389 => 170,
390 => 534,
391 => 169,
392 => 533,
393 => 168,
394 => 532,
395 => 167,
396 => 531,
397 => 166,
398 => 530,
399 => 165,
400 => 529,
401 => 164,
402 => 528,
403 => 163,
404 => 527,
405 => 162,
406 => 526,
407 => 161,
408 => 525,
409 => 160,
410 => 524,
411 => 159,
412 => 523,
413 => 158,
414 => 522,
415 => 157,
416 => 521,
417 => 156,
418 => 520,
419 => 155,
420 => 519,
421 => 154,
422 => 518,
423 => 153,
424 => 517,
425 => 152,
426 => 516,
427 => 151,
428 => 515,
429 => 150,
430 => 514,
431 => 149,
432 => 513,
433 => 148,
434 => 512,
435 => 147,
436 => 511,
437 => 146,
438 => 510,
439 => 145,
440 => 509,
441 => 144,
442 => 508,
443 => 143,
444 => 507,
445 => 142,
446 => 506,
447 => 141,
448 => 505,
449 => 140,
450 => 504,
451 => 139,
452 => 503,
453 => 138,
454 => 502,
455 => 137,
456 => 501,
457 => 136,
458 => 500,
459 => 135,
460 => 499,
461 => 134,
462 => 498,
463 => 133,
464 => 497,
465 => 132,
466 => 496,
467 => 131,
468 => 495,
469 => 130,
470 => 494,
471 => 129,
472 => 493,
473 => 128,
474 => 492,
475 => 127,
476 => 491,
477 => 126,
478 => 490,
479 => 125,
480 => 489,
481 => 124,
482 => 488,
483 => 123,
484 => 487,
485 => 122,
486 => 486,
487 => 121,
488 => 485,
489 => 120,
490 => 484,
491 => 119,
492 => 483,
493 => 118,
494 => 482,
495 => 117,
496 => 481,
497 => 116,
498 => 480,
499 => 115,
500 => 479,
501 => 114,
502 => 478,
503 => 113,
504 => 477,
505 => 112,
506 => 476,
507 => 111,
508 => 475,
509 => 110,
510 => 474,
511 => 109,
512 => 473,
513 => 108,
514 => 472,
515 => 107,
516 => 471,
517 => 106,
518 => 470,
519 => 105,
520 => 469,
521 => 104,
522 => 468,
523 => 103,
524 => 467,
525 => 102,
526 => 466,
527 => 101,
528 => 465,
529 => 100,
530 => 464,
531 => 99,
532 => 463,
533 => 98,
534 => 462,
535 => 97,
536 => 461,
537 => 96,
538 => 460,
539 => 95,
540 => 459,
541 => 94,
542 => 458,
543 => 93,
544 => 457,
545 => 92,
546 => 456,
547 => 91,
548 => 455,
549 => 90,
550 => 454,
551 => 89,
552 => 453,
553 => 88,
554 => 452,
555 => 87,
556 => 451,
557 => 86,
558 => 450,
559 => 85,
560 => 449,
561 => 84,
562 => 448,
563 => 83,
564 => 447,
565 => 82,
566 => 446,
567 => 81,
568 => 445,
569 => 80,
570 => 444,
571 => 79,
572 => 443,
573 => 78,
574 => 442,
575 => 77,
576 => 441,
577 => 76,
578 => 440,
579 => 75,
580 => 439,
581 => 74,
582 => 438,
583 => 73,
584 => 437,
585 => 72,
586 => 436,
587 => 71,
588 => 435,
589 => 70,
590 => 434,
591 => 69,
592 => 433,
593 => 68,
594 => 432,
595 => 67,
596 => 431,
597 => 66,
598 => 430,
599 => 65,
600 => 429,
601 => 64,
602 => 428,
603 => 63,
604 => 427,
605 => 62,
606 => 426,
607 => 61,
608 => 425,
609 => 60,
610 => 424,
611 => 59,
612 => 423,
613 => 58,
614 => 422,
615 => 57,
616 => 421,
617 => 56,
618 => 420,
619 => 55,
620 => 419,
621 => 54,
622 => 418,
623 => 53,
624 => 417,
625 => 52,
626 => 416,
627 => 51,
628 => 415,
629 => 50,
630 => 414,
631 => 49,
632 => 413,
633 => 48,
634 => 412,
635 => 47,
636 => 411,
637 => 46,
638 => 410,
639 => 45,
640 => 409,
641 => 44,
642 => 408,
643 => 43,
644 => 407,
645 => 42,
646 => 406,
647 => 41,
648 => 405,
649 => 40,
650 => 404,
651 => 39,
652 => 403,
653 => 38,
654 => 402,
655 => 37,
656 => 401,
657 => 36,
658 => 400,
659 => 35,
660 => 399,
661 => 34,
662 => 398,
663 => 33,
664 => 397,
665 => 32,
666 => 396,
667 => 31,
668 => 395,
669 => 30,
670 => 394,
671 => 29,
672 => 393,
673 => 28,
674 => 392,
675 => 27,
676 => 391,
677 => 26,
678 => 390,
679 => 25,
680 => 389,
681 => 24,
682 => 388,
683 => 23,
684 => 387,
685 => 22,
686 => 386,
687 => 21,
688 => 385,
689 => 20,
690 => 384,
691 => 19,
692 => 383,
693 => 18,
694 => 382,
695 => 17,
696 => 381,
697 => 16,
698 => 380,
699 => 15,
700 => 379,
701 => 14,
702 => 378,
703 => 13,
704 => 377,
705 => 12,
706 => 376,
707 => 11,
708 => 375,
709 => 10,
710 => 374,
711 => 9,
712 => 373,
713 => 8,
714 => 372,
715 => 7,
716 => 371,
717 => 6,
718 => 370,
719 => 5,
720 => 369,
721 => 4,
722 => 368,
723 => 3,
724 => 367,
725 => 2,
726 => 366,
727 => 1,
728 => 365,
729 => 0
);
end index_table;
 
package body index_table is
-- subprogram bodies here
end index_table;
/iota_pow_vhdl/trunk/vhdl_altera_de1/pll.cmp
0,0 → 1,25
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component pll
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
/iota_pow_vhdl/trunk/vhdl_altera_de1/pll.ppf
0,0 → 1,12
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
 
</global>
</pinplan>
/iota_pow_vhdl/trunk/vhdl_altera_de1/pll.qip
0,0 → 1,5
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
/iota_pow_vhdl/trunk/vhdl_altera_de1/pll.vhd
0,0 → 1,397
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
 
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
 
 
ARCHITECTURE SYN OF pll IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
 
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
 
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
/iota_pow_vhdl/trunk/vhdl_altera_de1/spi_slave.vhd
0,0 → 1,98
-- IOTA Pearl Diver VHDL Port
--
-- Written 2018 by Thomas Pototschnig <microengineer18@gmail.com>
--
-- This source code is currently licensed under
-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0)
--
-- http://www.microengineer.eu
--
-- If you like my project please consider a donation to
--
-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY
--
-- As soon as donations reach 1000MIOTA, everything will become
-- GPL and open for any use - commercial included.
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity spi_slave is
port
(
clk : in std_logic;
reset : in std_logic;
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic;
ss : in std_logic;
data_rd : in std_logic_vector(31 downto 0);
data_wr : out std_logic_vector(31 downto 0);
data_wren : out std_logic
);
end spi_slave;
 
 
architecture behv of spi_slave is
signal sync_mosi : std_logic_vector(1 downto 0);
signal sync_sck : std_logic_vector(1 downto 0);
signal sync_ss : std_logic_vector(1 downto 0);
 
 
begin
 
process(clk)
variable cnt : integer range 0 to 32 := 0;
variable iwren : std_logic;
variable i_miso : std_logic;
variable i_shiftregister : std_logic_vector(31 downto 0);
 
begin
if rising_edge(clk) then
if reset='1' then
cnt := 0;
data_wren <= '0';
iwren := '0';
else
iwren := '0';
sync_mosi <= sync_mosi(0) & mosi;
sync_sck <= sync_sck(0) & sck;
sync_ss <= sync_ss(0) & ss;
 
case sync_ss is
when "11" =>
i_shiftregister := data_rd;
cnt := 0;
-- i_flip := '0';
when "10" =>
miso <= i_shiftregister(31);
when "01" =>
cnt := 0;
iwren := '1';
data_wr <= i_shiftregister;
when "00" =>
case sync_sck is
when "01" =>
i_shiftregister := i_shiftregister(30 downto 0) & sync_mosi(0);
cnt := cnt + 1;
when "10" =>
miso <= i_shiftregister(31);
when others =>
end case;
when others =>
end case;
data_wren <= iwren;
end if;
end if;
end process;
 
end behv;
/iota_pow_vhdl/trunk/vhdl_cyclone10_lp/output_files/curl-cyclone10.sof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iota_pow_vhdl/trunk/vhdl_cyclone10_lp/output_files/curl-cyclone10.sof
iota_pow_vhdl/trunk/vhdl_cyclone10_lp/output_files/curl-cyclone10.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qpf =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qpf (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qpf (revision 4) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 10:09:41 April 23, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "10:09:41 April 23, 2018" + +# Revisions + +PROJECT_REVISION = "curl-cyclone10" Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qsf =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qsf (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qsf (revision 4) @@ -0,0 +1,112 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 10:09:41 April 23, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# curl-cyclone10_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL025YE144C8G +set_global_assignment -name TOP_LEVEL_ENTITY de1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:09:41 APRIL 23, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE spi_slave.vhd +set_global_assignment -name VHDL_FILE de1.vhd +set_global_assignment -name VHDL_FILE index_table.vhd +set_global_assignment -name VHDL_FILE curl.vhd +set_global_assignment -name QIP_FILE pll.qip +set_location_assignment PIN_52 -to CLOCK_50 +set_location_assignment PIN_100 -to spi_miso +set_location_assignment PIN_99 -to spi_mosi +set_location_assignment PIN_98 -to spi_sck +set_location_assignment PIN_101 -to spi_ss +set_location_assignment PIN_72 -to reset +set_location_assignment PIN_68 -to led_running +set_location_assignment PIN_66 -to led_overflow +set_location_assignment PIN_67 -to led_found +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_location_assignment PIN_12 -to ~ALTERA_DCLK~ +set_location_assignment PIN_13 -to ~ALTERA_DATA0~ +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name QII_AUTO_PACKED_REGISTERS "MINIMIZE AREA" +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_global_assignment -name AUTO_RAM_RECOGNITION ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0 +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY +set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" +set_global_assignment -name ALLOW_REGISTER_DUPLICATION OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "EXTRA EFFORT" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws (revision 4)
iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl-cyclone10.qws Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl.vhd =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl.vhd (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/curl.vhd (revision 4) @@ -0,0 +1,311 @@ +-- IOTA Pearl Diver VHDL Port +-- +-- Written 2018 by Thomas Pototschnig +-- +-- This source code is currently licensed under +-- Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) +-- +-- http://www.microengineer.eu +-- +-- If you like my project please consider a donation to +-- +-- LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY +-- +-- As soon as donations reach 1000MIOTA, everything will become +-- GPL and open for any use - commercial included. + +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.index_table.all; + +entity curl is + generic + ( + HASH_LENGTH : integer := 243; + STATE_LENGTH : integer := 729; -- 3 * HASH_LENGTH; + NONCE_LENGTH : integer := 81; -- HASH_LENGTH / 3; + NUMBER_OF_ROUNDS : integer := 81; + PARALLEL : integer := 7; + INTERN_NONCE_LENGTH : integer := 32; + BITS_MIN_WEIGHT_MAGINUTE_MAX : integer := 26; + DATA_WIDTH : integer := 9 + ); + + port + ( + clk : in std_logic; + clk_slow : in std_logic; + reset : in std_logic; + + spi_data_rx : in std_logic_vector(31 downto 0); + spi_data_tx : out std_logic_vector(31 downto 0); + spi_data_rxen : in std_logic; + overflow : out std_logic; + running : out std_logic; + found : out std_logic + ); + +end curl; + +architecture behv of curl is + +subtype state_vector_type is std_logic_vector(PARALLEL-1 downto 0); +subtype mid_state_vector_type is std_logic_vector(DATA_WIDTH-1 downto 0); + +type curl_state_array is array(integer range <>) of state_vector_type; +type mid_state_array is array(integer range <>) of mid_state_vector_type; + +signal curl_state_low : curl_state_array(STATE_LENGTH-1 downto 0); +signal curl_state_high : curl_state_array(STATE_LENGTH-1 downto 0); + +-- mid state data in 9bit packed format +signal curl_mid_state_low : mid_state_array((STATE_LENGTH/9)-1 downto 0); +signal curl_mid_state_high : mid_state_array((STATE_LENGTH/9)-1 downto 0); + +signal flag_running : std_logic := '0'; +signal flag_overflow : std_logic := '0'; +signal flag_found : std_logic := '0'; +signal flag_start : std_logic := '0'; + +signal binary_nonce : unsigned(INTERN_NONCE_LENGTH-1 downto 0); +signal mask : state_vector_type; +signal min_weight_magnitude : std_logic_vector(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0); + + +begin + overflow <= flag_overflow; + running <= flag_running; + found <= flag_found; + + process (clk_slow) + -- because it looks prettier + variable spi_cmd : std_logic_vector(5 downto 0); + variable wraddr : integer range 0 to 127 := 0; + begin + if rising_edge(clk_slow) then + if reset='1' then +-- binary_nonce <= (others => '0'); + min_weight_magnitude <= (others => '0'); + flag_start <= '0'; + else + flag_start <= '0'; +-- new spi data received + if spi_data_rxen = '1' then + spi_cmd := spi_data_rx(31 downto 26); + case spi_cmd is + when "000000" => -- nop + when "100001" => -- start / stop + if spi_data_rx(0) = '1' then + flag_start <= '1'; + end if; + when "100101" => -- write to wr address + wraddr := 0; + when "100010" => -- write to mid state + curl_mid_state_low(wraddr) <= std_logic_vector(spi_data_rx(DATA_WIDTH-1 downto 0)); + curl_mid_state_high(wraddr) <= std_logic_vector(spi_data_rx(DATA_WIDTH+8 downto DATA_WIDTH)); + wraddr := wraddr + 1; + when "100100" => + min_weight_magnitude <= spi_data_rx(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0); + + when "000001" => -- read flags + spi_data_tx <= "00000000000000000000000000000" & flag_overflow & flag_found & flag_running; + +-- this costs an extreme amount of resources +-- interesting only for debugging +-- when "000010" => +-- spi_addr := spi_data_rx(25 downto 16); +-- spi_data_tx(0+PARALLEL-1 downto 0) <= curl_state_low(to_integer(unsigned(spi_addr))); +-- spi_data_tx(8+PARALLEL-1 downto 8) <= curl_state_high(to_integer(unsigned(spi_addr))); + when "000011" => -- read nonce + spi_data_tx(31 downto INTERN_NONCE_LENGTH) <= (others => '0'); + spi_data_tx(INTERN_NONCE_LENGTH-1 downto 0) <= std_logic_vector(binary_nonce); + when "000100" => -- read mask + spi_data_tx(PARALLEL-1 downto 0) <= mask; + spi_data_tx(31 downto PARALLEL) <= (others => '0'); + when "010101" => -- loop back read test inverted bits + spi_data_tx <= not spi_data_rx; + when "000110" => -- read back parallel-level + spi_data_tx <= std_logic_vector(to_unsigned(PARALLEL, spi_data_tx'length)); + when others => + spi_data_tx <= (others => '1'); + end case; + end if; + end if; + end if; + end process; + + process (clk) + variable state : integer range 0 to 31 := 0; + variable round : integer range 0 to 127 := 0; + + variable imask : state_vector_type; + + variable i_min_weight_magnitude : std_logic_vector(BITS_MIN_WEIGHT_MAGINUTE_MAX-1 downto 0); + + -- temporary registers get optimized away + variable alpha : curl_state_array(STATE_LENGTH-1 downto 0); + variable beta : curl_state_array(STATE_LENGTH-1 downto 0); + variable gamma : curl_state_array(STATE_LENGTH-1 downto 0); + variable delta : curl_state_array(STATE_LENGTH-1 downto 0); + variable epsilon : curl_state_array(STATE_LENGTH-1 downto 0); + + variable tmp_index : integer range 0 to 1023; + variable tmp_mod : integer range 0 to 31; + begin + if rising_edge(clk) then + if reset='1' then + state := 0; + flag_found <= '0'; + flag_running <= '0'; + flag_overflow <= '0'; + binary_nonce <= (others => '0'); + else + case state is + when 0 => + flag_running <= '0'; + if flag_start = '1' then + i_min_weight_magnitude := min_weight_magnitude; + state := 1; + end if; + -- nop until start from spi + when 1 => + binary_nonce <= (others => '0'); + flag_found <= '0'; + flag_running <= '1'; + flag_overflow <= '0'; + state := 8; + when 8 => -- copy mid state and insert nonce + -- pipeline adder for speed + binary_nonce <= binary_nonce + 1; + + -- copy and fully expand mid-state to curl-state + for I in 0 to (STATE_LENGTH/DATA_WIDTH)-1 loop + for J in 0 to DATA_WIDTH-1 loop + tmp_index := I*DATA_WIDTH+J; + if tmp_index < 162 or tmp_index > HASH_LENGTH-1 then + if curl_mid_state_low(I)(J) = '1' then + curl_state_low(tmp_index) <= (others => '1'); + else + curl_state_low(tmp_index) <= (others => '0'); + end if; + + if curl_mid_state_high(I)(J) = '1' then + curl_state_high(tmp_index) <= (others => '1'); + else + curl_state_high(tmp_index) <= (others => '0'); + end if; + end if; + end loop; + end loop; + +-- -- generate bitmuster in first two trit-arrays of counter depending from PARALLEL setting +-- -- doesn't need additional resources for pow or division because everything is constant + for J in 0 to 1 loop -- TODO make adjustable ... it's okay up to PARALLEL = 9 + for I in 0 to PARALLEL-1 loop + tmp_mod := (I/(3**J)) mod 3; + if tmp_mod = 0 then + curl_state_low(162+J)(I) <= '1'; + curl_state_high(162+J)(I) <= '1'; + elsif tmp_mod = 1 then + curl_state_low(162+J)(I) <= '0'; + curl_state_high(162+J)(I) <= '1'; + elsif tmp_mod = 2 then + curl_state_low(162+J)(I) <= '1'; + curl_state_high(162+J)(I) <= '0'; + end if; + end loop; + end loop; + + + -- lowest trits for counter from 0 to 4 (for 5bit) +-- curl_state_low(162) <= "01101"; +-- curl_state_high(162) <= "11011"; +-- curl_state_low(163) <= "00111"; +-- curl_state_high(163) <= "11111"; + + -- insert and convert binary nonce to trinary nonce + -- It's a fake trinary nonce but integer-values are strictly monotonously rising + -- with integer values of binary nonce. + -- Doesn't bring the exact same result like reference implementation with real + -- trinary adder - but it doesn't matter and it is way faster. + for I in 164 to 164+INTERN_NONCE_LENGTH-1 loop + if binary_nonce(I-164) = '1' then + curl_state_low(I) <= (others => '1'); + curl_state_high(I) <= (others => '0'); + else + curl_state_low(I) <= (others => '0'); + curl_state_high(I) <= (others => '1'); + end if; + end loop; + + -- fill remaining trits with '11' (=0) + for I in 164+INTERN_NONCE_LENGTH to HASH_LENGTH-1 loop + curl_state_low(I) <= (others => '1'); + curl_state_high(I) <= (others => '1'); + end loop; + + -- initialize round-counter + round := NUMBER_OF_ROUNDS; + + state := 10; + when 10 => -- do the curl hash round without any copying needed + for I in 0 to STATE_LENGTH-1 loop + alpha(I) := curl_state_low(index_table(I)); + beta(I) := curl_state_high(index_table(I)); + gamma(I) := curl_state_high(index_table(I+1)); + + delta(I) := (alpha(I) or (not gamma(I))) and (curl_state_low(index_table(I+1)) xor beta(I)); + + curl_state_low(I) <= not delta(I); + curl_state_high(I) <= (alpha(I) xor gamma(I)) or delta(I); + end loop; + + round := round - 1; + if round = 0 then + state := 16; + end if; + when 16 => -- find out which solution - if any + imask := (others => '1'); + + -- doesn't work like the 2nd variant ... why? TODO^^ + for I in 0 to PARALLEL-1 loop + for J in 0 to BITS_MIN_WEIGHT_MAGINUTE_MAX-1 loop + if i_min_weight_magnitude(J) = '1' and (curl_state_low(HASH_LENGTH - 1 - J)(I) /= '1' or curl_state_high(HASH_LENGTH - 1 - J)(I) /= '1') then + imask(I) := '0'; + end if; + end loop; + end loop; + +-- imask := (others => '1'); +-- for I in 0 to BITS_MIN_WEIGHT_MAGINUTE_MAX-1 loop +-- if i_min_weight_magnitude(I) = '1' then +-- imask := imask and not (curl_state_low(HASH_LENGTH - 1 - I) xor curl_state_high(HASH_LENGTH - 1 - I)); +-- end if; +-- end loop; +-- mask <= imask; + + -- no solution found? + if unsigned(imask) = 0 then + -- is overflow? + if binary_nonce = x"ffffffff" then + flag_overflow <= '1'; + state := 0; + else + state := 8; -- and try again + end if; + else + state := 30; -- nonce found + end if; + when 30 => + mask <= imask; + flag_found <= '1'; + state := 0; + when others => + state := 0; + end case; + end if; + end if; + end process; +end behv; Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/de1.vhd =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/de1.vhd (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/de1.vhd (revision 4) @@ -0,0 +1,123 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity de1 is + port ( + CLOCK_50 : in std_logic; + reset : in std_logic; + led_running : out std_logic; + led_found : out std_logic; + led_overflow : out std_logic; +-- //////////////////////// UART //////////////////////// + spi_mosi : in std_logic; + spi_sck : in std_logic; + spi_ss : in std_logic; + spi_miso : out std_logic + + ); +end; + +architecture beh of de1 is + + + + +signal pll_clk : std_logic; +signal pll_reset : std_logic := '0'; +signal pll_locked : std_logic; + +signal spi_data_tx : std_logic_vector(31 downto 0); +signal spi_data_rx : std_logic_vector(31 downto 0); +signal spi_data_rx_en : std_logic; + + +signal pll_slow : std_logic; + +component spi_slave + port + ( + clk : in std_logic; + reset : in std_logic; + + mosi : in std_logic; + miso : out std_logic; + sck : in std_logic; + ss : in std_logic; + + + data_rd : in std_logic_vector(31 downto 0); + data_wr : out std_logic_vector(31 downto 0); + data_wren : out std_logic + ); +end component; + +component pll + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : out std_logic; + locked : OUT STD_LOGIC + ); +end component; + +component curl + port + ( + clk : in std_logic; + clk_slow : in std_logic; + reset : in std_logic; + + spi_data_rx : in std_logic_vector(31 downto 0); + spi_data_tx : out std_logic_vector(31 downto 0); + spi_data_rxen : in std_logic; + + overflow : out std_logic; + running : out std_logic; + found : out std_logic + ); +end component; + +begin + pll0 : pll port map ( + areset => pll_reset, + inclk0 => CLOCK_50, + c0 => pll_clk, + c1 => pll_slow, + locked => pll_locked + ); + + + spi0 : spi_slave port map ( + clk => pll_slow, + reset => reset, + + mosi => spi_mosi, + miso => spi_miso, + sck => spi_sck, + ss => spi_ss, + + data_rd => spi_data_tx, + data_wr => spi_data_rx, + data_wren => spi_data_rx_en + ); + + curl0 : curl port map ( + clk => pll_clk, + reset => reset, + clk_slow => pll_slow, + + spi_data_rx => spi_data_rx, + spi_data_tx => spi_data_tx, + spi_data_rxen => spi_data_rx_en, + + overflow => led_overflow, + running => led_running, + found => led_found + ); + + +end architecture; \ No newline at end of file Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/index_table.vhd =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/index_table.vhd (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/index_table.vhd (revision 4) @@ -0,0 +1,747 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package index_table is + +type const_index_table is array ( 0 to 729) of integer range 0 to 728; + constant index_table : const_index_table := ( + 0 => 0, + 1 => 364, + 2 => 728, + 3 => 363, + 4 => 727, + 5 => 362, + 6 => 726, + 7 => 361, + 8 => 725, + 9 => 360, + 10 => 724, + 11 => 359, + 12 => 723, + 13 => 358, + 14 => 722, + 15 => 357, + 16 => 721, + 17 => 356, + 18 => 720, + 19 => 355, + 20 => 719, + 21 => 354, + 22 => 718, + 23 => 353, + 24 => 717, + 25 => 352, + 26 => 716, + 27 => 351, + 28 => 715, + 29 => 350, + 30 => 714, + 31 => 349, + 32 => 713, + 33 => 348, + 34 => 712, + 35 => 347, + 36 => 711, + 37 => 346, + 38 => 710, + 39 => 345, + 40 => 709, + 41 => 344, + 42 => 708, + 43 => 343, + 44 => 707, + 45 => 342, + 46 => 706, + 47 => 341, + 48 => 705, + 49 => 340, + 50 => 704, + 51 => 339, + 52 => 703, + 53 => 338, + 54 => 702, + 55 => 337, + 56 => 701, + 57 => 336, + 58 => 700, + 59 => 335, + 60 => 699, + 61 => 334, + 62 => 698, + 63 => 333, + 64 => 697, + 65 => 332, + 66 => 696, + 67 => 331, + 68 => 695, + 69 => 330, + 70 => 694, + 71 => 329, + 72 => 693, + 73 => 328, + 74 => 692, + 75 => 327, + 76 => 691, + 77 => 326, + 78 => 690, + 79 => 325, + 80 => 689, + 81 => 324, + 82 => 688, + 83 => 323, + 84 => 687, + 85 => 322, + 86 => 686, + 87 => 321, + 88 => 685, + 89 => 320, + 90 => 684, + 91 => 319, + 92 => 683, + 93 => 318, + 94 => 682, + 95 => 317, + 96 => 681, + 97 => 316, + 98 => 680, + 99 => 315, + 100 => 679, + 101 => 314, + 102 => 678, + 103 => 313, + 104 => 677, + 105 => 312, + 106 => 676, + 107 => 311, + 108 => 675, + 109 => 310, + 110 => 674, + 111 => 309, + 112 => 673, + 113 => 308, + 114 => 672, + 115 => 307, + 116 => 671, + 117 => 306, + 118 => 670, + 119 => 305, + 120 => 669, + 121 => 304, + 122 => 668, + 123 => 303, + 124 => 667, + 125 => 302, + 126 => 666, + 127 => 301, + 128 => 665, + 129 => 300, + 130 => 664, + 131 => 299, + 132 => 663, + 133 => 298, + 134 => 662, + 135 => 297, + 136 => 661, + 137 => 296, + 138 => 660, + 139 => 295, + 140 => 659, + 141 => 294, + 142 => 658, + 143 => 293, + 144 => 657, + 145 => 292, + 146 => 656, + 147 => 291, + 148 => 655, + 149 => 290, + 150 => 654, + 151 => 289, + 152 => 653, + 153 => 288, + 154 => 652, + 155 => 287, + 156 => 651, + 157 => 286, + 158 => 650, + 159 => 285, + 160 => 649, + 161 => 284, + 162 => 648, + 163 => 283, + 164 => 647, + 165 => 282, + 166 => 646, + 167 => 281, + 168 => 645, + 169 => 280, + 170 => 644, + 171 => 279, + 172 => 643, + 173 => 278, + 174 => 642, + 175 => 277, + 176 => 641, + 177 => 276, + 178 => 640, + 179 => 275, + 180 => 639, + 181 => 274, + 182 => 638, + 183 => 273, + 184 => 637, + 185 => 272, + 186 => 636, + 187 => 271, + 188 => 635, + 189 => 270, + 190 => 634, + 191 => 269, + 192 => 633, + 193 => 268, + 194 => 632, + 195 => 267, + 196 => 631, + 197 => 266, + 198 => 630, + 199 => 265, + 200 => 629, + 201 => 264, + 202 => 628, + 203 => 263, + 204 => 627, + 205 => 262, + 206 => 626, + 207 => 261, + 208 => 625, + 209 => 260, + 210 => 624, + 211 => 259, + 212 => 623, + 213 => 258, + 214 => 622, + 215 => 257, + 216 => 621, + 217 => 256, + 218 => 620, + 219 => 255, + 220 => 619, + 221 => 254, + 222 => 618, + 223 => 253, + 224 => 617, + 225 => 252, + 226 => 616, + 227 => 251, + 228 => 615, + 229 => 250, + 230 => 614, + 231 => 249, + 232 => 613, + 233 => 248, + 234 => 612, + 235 => 247, + 236 => 611, + 237 => 246, + 238 => 610, + 239 => 245, + 240 => 609, + 241 => 244, + 242 => 608, + 243 => 243, + 244 => 607, + 245 => 242, + 246 => 606, + 247 => 241, + 248 => 605, + 249 => 240, + 250 => 604, + 251 => 239, + 252 => 603, + 253 => 238, + 254 => 602, + 255 => 237, + 256 => 601, + 257 => 236, + 258 => 600, + 259 => 235, + 260 => 599, + 261 => 234, + 262 => 598, + 263 => 233, + 264 => 597, + 265 => 232, + 266 => 596, + 267 => 231, + 268 => 595, + 269 => 230, + 270 => 594, + 271 => 229, + 272 => 593, + 273 => 228, + 274 => 592, + 275 => 227, + 276 => 591, + 277 => 226, + 278 => 590, + 279 => 225, + 280 => 589, + 281 => 224, + 282 => 588, + 283 => 223, + 284 => 587, + 285 => 222, + 286 => 586, + 287 => 221, + 288 => 585, + 289 => 220, + 290 => 584, + 291 => 219, + 292 => 583, + 293 => 218, + 294 => 582, + 295 => 217, + 296 => 581, + 297 => 216, + 298 => 580, + 299 => 215, + 300 => 579, + 301 => 214, + 302 => 578, + 303 => 213, + 304 => 577, + 305 => 212, + 306 => 576, + 307 => 211, + 308 => 575, + 309 => 210, + 310 => 574, + 311 => 209, + 312 => 573, + 313 => 208, + 314 => 572, + 315 => 207, + 316 => 571, + 317 => 206, + 318 => 570, + 319 => 205, + 320 => 569, + 321 => 204, + 322 => 568, + 323 => 203, + 324 => 567, + 325 => 202, + 326 => 566, + 327 => 201, + 328 => 565, + 329 => 200, + 330 => 564, + 331 => 199, + 332 => 563, + 333 => 198, + 334 => 562, + 335 => 197, + 336 => 561, + 337 => 196, + 338 => 560, + 339 => 195, + 340 => 559, + 341 => 194, + 342 => 558, + 343 => 193, + 344 => 557, + 345 => 192, + 346 => 556, + 347 => 191, + 348 => 555, + 349 => 190, + 350 => 554, + 351 => 189, + 352 => 553, + 353 => 188, + 354 => 552, + 355 => 187, + 356 => 551, + 357 => 186, + 358 => 550, + 359 => 185, + 360 => 549, + 361 => 184, + 362 => 548, + 363 => 183, + 364 => 547, + 365 => 182, + 366 => 546, + 367 => 181, + 368 => 545, + 369 => 180, + 370 => 544, + 371 => 179, + 372 => 543, + 373 => 178, + 374 => 542, + 375 => 177, + 376 => 541, + 377 => 176, + 378 => 540, + 379 => 175, + 380 => 539, + 381 => 174, + 382 => 538, + 383 => 173, + 384 => 537, + 385 => 172, + 386 => 536, + 387 => 171, + 388 => 535, + 389 => 170, + 390 => 534, + 391 => 169, + 392 => 533, + 393 => 168, + 394 => 532, + 395 => 167, + 396 => 531, + 397 => 166, + 398 => 530, + 399 => 165, + 400 => 529, + 401 => 164, + 402 => 528, + 403 => 163, + 404 => 527, + 405 => 162, + 406 => 526, + 407 => 161, + 408 => 525, + 409 => 160, + 410 => 524, + 411 => 159, + 412 => 523, + 413 => 158, + 414 => 522, + 415 => 157, + 416 => 521, + 417 => 156, + 418 => 520, + 419 => 155, + 420 => 519, + 421 => 154, + 422 => 518, + 423 => 153, + 424 => 517, + 425 => 152, + 426 => 516, + 427 => 151, + 428 => 515, + 429 => 150, + 430 => 514, + 431 => 149, + 432 => 513, + 433 => 148, + 434 => 512, + 435 => 147, + 436 => 511, + 437 => 146, + 438 => 510, + 439 => 145, + 440 => 509, + 441 => 144, + 442 => 508, + 443 => 143, + 444 => 507, + 445 => 142, + 446 => 506, + 447 => 141, + 448 => 505, + 449 => 140, + 450 => 504, + 451 => 139, + 452 => 503, + 453 => 138, + 454 => 502, + 455 => 137, + 456 => 501, + 457 => 136, + 458 => 500, + 459 => 135, + 460 => 499, + 461 => 134, + 462 => 498, + 463 => 133, + 464 => 497, + 465 => 132, + 466 => 496, + 467 => 131, + 468 => 495, + 469 => 130, + 470 => 494, + 471 => 129, + 472 => 493, + 473 => 128, + 474 => 492, + 475 => 127, + 476 => 491, + 477 => 126, + 478 => 490, + 479 => 125, + 480 => 489, + 481 => 124, + 482 => 488, + 483 => 123, + 484 => 487, + 485 => 122, + 486 => 486, + 487 => 121, + 488 => 485, + 489 => 120, + 490 => 484, + 491 => 119, + 492 => 483, + 493 => 118, + 494 => 482, + 495 => 117, + 496 => 481, + 497 => 116, + 498 => 480, + 499 => 115, + 500 => 479, + 501 => 114, + 502 => 478, + 503 => 113, + 504 => 477, + 505 => 112, + 506 => 476, + 507 => 111, + 508 => 475, + 509 => 110, + 510 => 474, + 511 => 109, + 512 => 473, + 513 => 108, + 514 => 472, + 515 => 107, + 516 => 471, + 517 => 106, + 518 => 470, + 519 => 105, + 520 => 469, + 521 => 104, + 522 => 468, + 523 => 103, + 524 => 467, + 525 => 102, + 526 => 466, + 527 => 101, + 528 => 465, + 529 => 100, + 530 => 464, + 531 => 99, + 532 => 463, + 533 => 98, + 534 => 462, + 535 => 97, + 536 => 461, + 537 => 96, + 538 => 460, + 539 => 95, + 540 => 459, + 541 => 94, + 542 => 458, + 543 => 93, + 544 => 457, + 545 => 92, + 546 => 456, + 547 => 91, + 548 => 455, + 549 => 90, + 550 => 454, + 551 => 89, + 552 => 453, + 553 => 88, + 554 => 452, + 555 => 87, + 556 => 451, + 557 => 86, + 558 => 450, + 559 => 85, + 560 => 449, + 561 => 84, + 562 => 448, + 563 => 83, + 564 => 447, + 565 => 82, + 566 => 446, + 567 => 81, + 568 => 445, + 569 => 80, + 570 => 444, + 571 => 79, + 572 => 443, + 573 => 78, + 574 => 442, + 575 => 77, + 576 => 441, + 577 => 76, + 578 => 440, + 579 => 75, + 580 => 439, + 581 => 74, + 582 => 438, + 583 => 73, + 584 => 437, + 585 => 72, + 586 => 436, + 587 => 71, + 588 => 435, + 589 => 70, + 590 => 434, + 591 => 69, + 592 => 433, + 593 => 68, + 594 => 432, + 595 => 67, + 596 => 431, + 597 => 66, + 598 => 430, + 599 => 65, + 600 => 429, + 601 => 64, + 602 => 428, + 603 => 63, + 604 => 427, + 605 => 62, + 606 => 426, + 607 => 61, + 608 => 425, + 609 => 60, + 610 => 424, + 611 => 59, + 612 => 423, + 613 => 58, + 614 => 422, + 615 => 57, + 616 => 421, + 617 => 56, + 618 => 420, + 619 => 55, + 620 => 419, + 621 => 54, + 622 => 418, + 623 => 53, + 624 => 417, + 625 => 52, + 626 => 416, + 627 => 51, + 628 => 415, + 629 => 50, + 630 => 414, + 631 => 49, + 632 => 413, + 633 => 48, + 634 => 412, + 635 => 47, + 636 => 411, + 637 => 46, + 638 => 410, + 639 => 45, + 640 => 409, + 641 => 44, + 642 => 408, + 643 => 43, + 644 => 407, + 645 => 42, + 646 => 406, + 647 => 41, + 648 => 405, + 649 => 40, + 650 => 404, + 651 => 39, + 652 => 403, + 653 => 38, + 654 => 402, + 655 => 37, + 656 => 401, + 657 => 36, + 658 => 400, + 659 => 35, + 660 => 399, + 661 => 34, + 662 => 398, + 663 => 33, + 664 => 397, + 665 => 32, + 666 => 396, + 667 => 31, + 668 => 395, + 669 => 30, + 670 => 394, + 671 => 29, + 672 => 393, + 673 => 28, + 674 => 392, + 675 => 27, + 676 => 391, + 677 => 26, + 678 => 390, + 679 => 25, + 680 => 389, + 681 => 24, + 682 => 388, + 683 => 23, + 684 => 387, + 685 => 22, + 686 => 386, + 687 => 21, + 688 => 385, + 689 => 20, + 690 => 384, + 691 => 19, + 692 => 383, + 693 => 18, + 694 => 382, + 695 => 17, + 696 => 381, + 697 => 16, + 698 => 380, + 699 => 15, + 700 => 379, + 701 => 14, + 702 => 378, + 703 => 13, + 704 => 377, + 705 => 12, + 706 => 376, + 707 => 11, + 708 => 375, + 709 => 10, + 710 => 374, + 711 => 9, + 712 => 373, + 713 => 8, + 714 => 372, + 715 => 7, + 716 => 371, + 717 => 6, + 718 => 370, + 719 => 5, + 720 => 369, + 721 => 4, + 722 => 368, + 723 => 3, + 724 => 367, + 725 => 2, + 726 => 366, + 727 => 1, + 728 => 365, + 729 => 0 + ); + + +end index_table; + +package body index_table is + -- subprogram bodies here +end index_table; \ No newline at end of file Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.cmp =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.cmp (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.cmp (revision 4) @@ -0,0 +1,25 @@ +--Copyright (C) 2017 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component pll + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.ppf =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.ppf (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.ppf (revision 4) @@ -0,0 +1,12 @@ + + + + + + + + + + + + Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.qip =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.qip (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.qip (revision 4) @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.vhd =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.vhd (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/pll.vhd (revision 4) @@ -0,0 +1,397 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2017 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + locked <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 5, + clk0_duty_cycle => 50, + clk0_multiply_by => 14, + clk0_phase_shift => "0", + clk1_divide_by => 5, + clk1_duty_cycle => 50, + clk1_multiply_by => 7, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone 10 LP", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "140.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "70.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "140.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "70.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON Index: iota_pow_vhdl/trunk/vhdl_cyclone10_lp/spi_slave.vhd =================================================================== --- iota_pow_vhdl/trunk/vhdl_cyclone10_lp/spi_slave.vhd (nonexistent) +++ iota_pow_vhdl/trunk/vhdl_cyclone10_lp/spi_slave.vhd (revision 4) @@ -0,0 +1,82 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity spi_slave is + port + ( + clk : in std_logic; + reset : in std_logic; + + mosi : in std_logic; + miso : out std_logic; + sck : in std_logic; + ss : in std_logic; + + + data_rd : in std_logic_vector(31 downto 0); + data_wr : out std_logic_vector(31 downto 0); + data_wren : out std_logic + + ); +end spi_slave; + + +architecture behv of spi_slave is +signal sync_mosi : std_logic_vector(1 downto 0); +signal sync_sck : std_logic_vector(1 downto 0); +signal sync_ss : std_logic_vector(1 downto 0); + + +begin + + process(clk) + variable cnt : integer range 0 to 32 := 0; + variable iwren : std_logic; + variable i_miso : std_logic; + variable i_shiftregister : std_logic_vector(31 downto 0); + + begin + if rising_edge(clk) then + if reset='1' then + cnt := 0; + data_wren <= '0'; + iwren := '0'; + else + iwren := '0'; + + sync_mosi <= sync_mosi(0) & mosi; + sync_sck <= sync_sck(0) & sck; + sync_ss <= sync_ss(0) & ss; + + case sync_ss is + when "11" => + i_shiftregister := data_rd; + cnt := 0; +-- i_flip := '0'; + when "10" => + miso <= i_shiftregister(31); + when "01" => + cnt := 0; + iwren := '1'; + data_wr <= i_shiftregister; + when "00" => + case sync_sck is + when "01" => + i_shiftregister := i_shiftregister(30 downto 0) & sync_mosi(0); + cnt := cnt + 1; + when "10" => + miso <= i_shiftregister(31); + when others => + end case; + when others => + end case; + data_wren <= iwren; + end if; + end if; + end process; + + +end behv;

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