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/branches/avendor/input.vhd
0,0 → 1,107
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity input is
Port ( clk : in std_logic;
rst : in std_logic;
serial : in std_logic;
mem_block : in std_logic;
mem_ready : out std_logic;
wen : out std_logic;
address : out std_logic_vector (5 downto 0);
i : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0)
);
end input;
 
architecture input of input is
 
type state is (s0, s1, s2, s3, s4, s5, s6, s7);
signal st: state;
signal meta, sync : std_logic;
signal addr : std_logic_vector(5 downto 0);
begin
 
process(clk,rst)
--constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
constant mais1 : std_logic_vector(11 downto 0) := x"080";
constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
begin
-- 0123.45678901 bits
-- 0011.00000000 = +1
-- 1101.00000000 = -1
 
-- Q
-- o | o
-- 01 | 00
-- |
-- ----------------- I
-- |
-- 11 | 10
-- o | o
 
if rst = '1' then
st <= s0;
mem_ready <= '0';
wen <= '0';
addr <= (others => '0');
address <= (others => '0');
i <= mais1;
q <= mais1;
elsif clk'event and clk='1' then
case st is
when s0 =>
st <= s1;
meta <= serial;
wen <= '0';
when s1 =>
st <= s2;
sync <= meta;
when s2 =>
st <= s3;
if sync='0' then
i <= mais1;
else
i <= menos1;
end if;
when s3 =>
st <= s4;
when s4 =>
st <= s5;
meta <= serial;
addr <= addr +1;
when s5 =>
st <= s6;
sync <= meta;
if unsigned(addr) = 32 then
addr <= conv_std_logic_vector(1,6);
mem_ready <= '1';
end if;
when s6 =>
st <= s7;
mem_ready <= '0';
if sync='0' then
q <= mais1;
else
q <= menos1;
end if;
when s7 =>
st <= s0;
if mem_block = '0' then
address <= addr+32;
else
address <= addr;
end if;
wen <= '1';
end case;
end if;
end process;
 
end input;
/branches/avendor/output.vhd
0,0 → 1,88
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity output is
Port ( clk : in std_logic;
rst : in std_logic;
Iout : in std_logic_vector(13 downto 0);
Qout : in std_logic_vector(13 downto 0);
Output_enable : in std_logic;
addrout_out : out std_logic_vector(5 downto 0);
txserial : out std_logic
);
end output;
 
architecture output of output is
 
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal st : state;
 
signal addr : std_logic_vector(5 downto 0);
begin
 
addrout_out <= addr;
 
acoes:process(clk,rst)
begin
if rst ='1' then
addr <= conv_std_logic_vector(1,6);
txserial <= '1';
elsif clk'event and clk='1' then
case st is
when s0 => -- espera output_enable
txserial <= '1';
addr <= conv_std_logic_vector(1,6);
when s1|s2|s3|s4 => -- qam decoder
txserial <= Iout(13);
when s5|s6|s8 =>
txserial <= Qout(13);
when s7 =>
txserial <= Qout(13);
if addr /= 31 then
addr <= addr+1;
else
addr <= conv_std_logic_vector(1,6);
end if;
end case;
end if;
end process;
 
estados:process(clk,rst)
begin
if rst ='1' then
st <= s0;
elsif clk'event and clk='1' then
case st is
when s0 =>
if Output_enable = '1' then
st <= s1;
else
st <= s0;
end if;
when s1 =>
st <= s2;
when s2 =>
st <= s3;
when s3 =>
st <= s4;
when s4 =>
st <= s5;
when s5 =>
st <= s6;
when s6 =>
st <= s7;
when s7=>
st <= s8;
when s8=>
st <= s1;
end case;
end if;
end process;
end output;
/branches/avendor/modem.vhd
0,0 → 1,126
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity modem is
port ( clk : in std_logic;
rsti : in std_logic;
rxserial : in std_logic;
txserial : out std_logic;
pmem_ready : out std_logic;
pIin : out std_logic_vector(13 downto 0);
pmem_block : out std_logic;
pOutput_enable : out std_logic;
pwen : out std_logic;
paddress_read : out std_logic_vector(5 downto 0);
paddress_write : out std_logic_vector(6 downto 0);
Iout_rx : out std_logic_vector(13 downto 0);
Qout_rx : out std_logic_vector(13 downto 0);
Output_enable_rx : out std_logic;
addrout_out_rx : out std_logic_vector(5 downto 0);
mem_block_tx : out std_logic;
mem_ready_tx : out std_logic;
wen_tx : out std_logic;
address_tx : out std_logic_vector (5 downto 0);
i_tx : out std_logic_vector(11 downto 0);
q_tx : out std_logic_vector(11 downto 0)
);
end modem;
 
architecture modem of modem is
 
component txmodem
port (
clk : in std_logic;
rst : in std_logic;
serial : in std_logic;
Iout : out std_logic_vector(13 downto 0);
Output_enable : out std_logic;
addrout_out : in std_logic_vector(5 downto 0)
);
end component;
 
component txrx
port (
clk : in std_logic;
rst : in std_logic;
Output_enable : in std_logic;
mem_block : in std_logic;
mem_ready : out std_logic;
wen : out std_logic;
address_read : out std_logic_vector(5 downto 0);
address_write: out std_logic_vector(6 downto 0)
);
end component;
 
component rxmodem
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
Iin : in std_logic_vector(11 downto 0);
mem_block : out std_logic;
wen : in std_logic;
addrin_in : in std_logic_vector(6 downto 0);
txserial : out std_logic
);
end component;
 
component BUFGP
port (I: in std_logic; O: out std_logic);
end component;
signal rst: std_logic;
 
 
signal mem_ready : std_logic;
signal Iin : std_logic_vector(13 downto 0);
signal mem_block : std_logic;
signal Output_enable : std_logic;
signal wen : std_logic;
signal address_read : std_logic_vector(5 downto 0);
signal address_write : std_logic_vector(6 downto 0);
begin
U1: BUFGP port map (I => rsti, O => rst);
 
 
txmodem_1 : txmodem
port map (
clk => clk,
rst => rst,
serial => rxserial,
Iout => Iin,
Output_enable => Output_enable,
addrout_out => address_read
);
 
txrx_1 : txrx
port map (
clk => clk,
rst => rst,
Output_enable => Output_enable,
mem_block => mem_block,
mem_ready => mem_ready,
wen => wen,
address_read => address_read,
address_write => address_write);
 
rxmodem_1 : rxmodem
port map (
clk => clk,
rst => rst,
mem_ready => mem_ready,
Iin => Iin(13 downto 2),
mem_block => mem_block,
wen => wen,
addrin_in => address_write,
txserial => txserial
);
 
end modem;
/branches/avendor/p2r_CordicPipe.vhd
0,0 → 1,170
--
-- file: p2r_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
--
 
--
-- This file is come from WWW.OPENCORES.ORG
 
---------------------------------------------------------------------------------------------------
--
-- Title : p2r_CordicPipe
-- Design : cfft
--
---------------------------------------------------------------------------------------------------
--
-- File : p2r_CordicPipe.vhd
--
---------------------------------------------------------------------------------------------------
--
-- Description : Cordic arith pilepline
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming <sradio@opencores.org>
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity p2r_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
 
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
 
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity p2r_CordicPipe;
 
architecture dataflow of p2r_CordicPipe is
 
--
-- functions
--
 
-- Function CATAN (constante arc-tangent).
-- This is a lookup table containing pre-calculated arc-tangents.
-- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
-- The numbers are calculated as follows: Z(n) = atan(1/2^n)
-- examples:
-- 20bit values => 2^20 = 2pi(rad)
-- 1(rad) = 2^20/2pi = 166886.053....
-- n:0, atan(1/1) = 0.7853...(rad)
-- 0.7853... * 166886.053... = 131072(dec) = 20000(hex)
-- n:1, atan(1/2) = 0.4636...(rad)
-- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
-- n:2, atan(1/4) = 0.2449...(rad)
-- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
-- n:3, atan(1/8) = 0.1243...(rad)
-- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
--
function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#09FB4#;
when 3 => result := 16#05111#;
when 4 => result := 16#028B1#;
when 5 => result := 16#0145D#;
when 6 => result := 16#0A2F#;
when 7 => result := 16#0518#;
when 8 => result := 16#028C#;
when 9 => result := 16#0146#;
when 10 => result := 16#0A3#;
when 11 => result := 16#051#;
when 12 => result := 16#029#;
when 13 => result := 16#014#;
when 14 => result := 16#0A#;
when 15 => result := 16#05#;
when 16 => result := 16#03#;
when 17 => result := 16#01#;
when others => result := 16#0#;
end case;
return result;
end CATAN;
 
-- function Delta is actually an arithmatic shift right
-- This strange construction is needed for compatibility with Xilinx WebPack
function Delta(Arg : signed; Cnt : natural) return signed is
variable tmp : signed(Arg'range);
constant lo : integer := Arg'high -cnt +1;
begin
for n in Arg'high downto lo loop
tmp(n) := Arg(Arg'high);
end loop;
for n in Arg'high -cnt downto 0 loop
tmp(n) := Arg(n +cnt);
end loop;
return tmp;
end function Delta;
 
function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
begin
if (add_sub = '1') then
return dataa + datab;
else
return dataa - datab;
end if;
end;
 
--
-- ARCHITECTURE BODY
--
signal dX, Xresult : signed(WIDTH -1 downto 0);
signal dY, Yresult : signed(WIDTH -1 downto 0);
signal atan, Zresult : signed(19 downto 0);
 
signal Zneg, Zpos : std_logic;
begin
 
dX <= Delta(Xi, PIPEID);
dY <= Delta(Yi, PIPEID);
atan <= conv_signed( catan(PIPEID), 20);
 
-- generate adder structures
Zneg <= Zi(19);
Zpos <= not Zi(19);
 
-- xadd
Xresult <= AddSub(Xi, dY, Zneg);
 
-- yadd
Yresult <= AddSub(Yi, dX, Zpos);
 
-- zadd
Zresult <= AddSub(Zi, atan, Zneg);
 
gen_regs: process(clk)
begin
if(clk'event and clk='1') then
if (ena = '1') then
Xo <= Xresult;
Yo <= Yresult;
Zo <= Zresult;
end if;
end if;
end process;
 
end architecture dataflow;
/branches/avendor/txrx.vhd
0,0 → 1,96
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity txrx is
Port ( clk : in std_logic;
rst : in std_logic;
Output_enable : in std_logic;
mem_block : in std_logic;
mem_ready : out std_logic;
wen : out std_logic;
address_read : out std_logic_vector(5 downto 0);
address_write: out std_logic_vector(6 downto 0)
);
end txrx;
 
architecture interface of txrx is
 
type state is (s0,s1,s2,s3);
signal st : state;
 
signal add : std_logic_vector(6 downto 0);
signal wen_aux : std_logic;
begin
 
address_read <= add(5 downto 0);
 
process(clk,rst)
begin
if rst ='1' then
address_write <= (others => '0');
wen <= '0';
elsif clk'event and clk='1' then
address_write <= add;
wen <= wen_aux;
end if;
end process;
 
process(clk,rst)
begin
if rst = '1' then
add <= (others => '0');
wen_aux <= '0';
mem_ready <= '0';
elsif clk'event and clk='1' then
case st is
when s0 => -- para contagem
wen_aux <= '0';
add <= add;
mem_ready <= '0';
 
wen_aux <= '1';
if mem_block = '1' then
add <= (others => '0');
else
add <= conv_std_logic_vector(64,7);
end if;
when s2 => --contagem
add <= add + 1;
when s3 => --fim contagem
add <= add + 1;
mem_ready <= '1';
end case;
end if;
end process;
 
 
process(clk,rst)
begin
if rst = '1' then
st <= s0;
elsif clk'event and clk='1' then
case st is
when s0 => -- para contagem
if Output_enable = '1' then
st <= s1;
end if;
 
st <= s2;
when s2 => -- contagem
if (add(5 downto 0) = 61) then
st <= s3;
end if;
when s3 => -- fim contagem
st <= s0;
end case;
end if;
end process;
 
end interface;
/branches/avendor/div4limit.vhd
0,0 → 1,63
---------------------------------------------------------------------------------------------------
--
-- Title : div4limit
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : div4limit.vhd
-- Generated : Tue Jul 16 10:39:17 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : Div 4 Limit to 12 bit
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity div4limit is
generic (
WIDTH : Natural
);
port(
clk : in std_logic;
D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
);
end div4limit;
 
architecture div4limit of div4limit is
begin
 
process( clk )
variable Temp_D:std_logic_vector( WIDTH+1 downto 0 );
begin
if clk'event and clk='1' then
Temp_D:=D( WIDTH+3 downto 2 )+D(1);
if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then
Temp_D(WIDTH+1 downto WIDTH-1):="111";
Temp_D(WIDTH-2 downto 1):=( others=>'0' );
Temp_D(0):='1';
elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then
Temp_D(WIDTH+1 downto WIDTH-1):="000";
Temp_D(WIDTH-2 downto 0):=( others=>'1' );
end if;
Q<=Temp_D(WIDTH-1 downto 0 );
end if;
end process;
end div4limit;
/branches/avendor/cfft4.vhd
0,0 → 1,128
---------------------------------------------------------------------------------------------------
--
-- Title : cfft4
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : cfft4.vhd
-- Generated : Wed Oct 2 15:49:06 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : 4 point fft
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1.1.0
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
 
entity cfft4 is
generic (
WIDTH : Natural
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
invert : in std_logic;
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
);
end cfft4;
 
 
architecture cfft4 of cfft4 is
type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0);
type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0);
 
signal counter : std_logic_vector( 1 downto 0 ):="00";
signal RegAI,RegAQ : RegAtype;
signal RegBI,RegBQ : RegBtype;
begin
 
 
count:process( clk,rst )
begin
if rst='1' then
counter<="00";
elsif clk'event and clk='1' then
if start='1' then
counter<="00";
else
counter<=counter+1;
end if;
end if;
end process count;
 
 
-------------------------------------------------------------------------
--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
-------------------------------------------------------------------------
calculate:process( clk )
begin
if clk'event and clk='1' then
case counter is
--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
when "00" =>
RegAI(0)<=I;
RegAQ(0)<=Q;
RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1);
RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1);
RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1);
RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1);
Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2);
Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
when "01" =>
RegAI(1)<=I;
RegAQ(1)<=Q;
if invert='0' then
-- for fft *(-j)
RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
else
-- for fft *(j)
RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1);
RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1);
end if;
Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2);
Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2);
--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
when "10" =>
RegAI(2)<=I;
RegAQ(2)<=Q;
Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2);
Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2);
--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
when "11" =>
RegAI(3)<=I;
RegAQ(3)<=Q;
RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1);
RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1);
Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2);
Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2);
when others => null;
end case;
end if;
end process calculate;
end cfft4;
/branches/avendor/io_control.vhd
0,0 → 1,64
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity io_control is
generic (
stage : natural:=3);
 
port (
clk : in std_logic;
rst : in std_logic;
mem_bk : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
bank0_busy : out std_logic;
bank1_busy : out std_logic;
Output_enable: out std_logic);
end io_control;
 
architecture io_control of io_control is
 
alias state: std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
alias counter: std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
 
begin
 
Outen:process (clk, rst)
begin -- process
if rst = '1' then -- asynchronous reset (active low)
Output_enable <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if unsigned(state)=stage-1 and unsigned(counter)=55 then
Output_enable <= '1';
else
Output_enable <= '0';
end if;
end if;
end process;
 
Bank_busy:process(clk, rst)
begin
if rst = '1' then
bank0_busy <= '0';
bank1_busy <= '0';
elsif clk'event and clk = '1' then
if unsigned(state)=0 then
if mem_bk = '0' then
bank0_busy <= '1';
else
bank1_busy <= '1';
end if;
else
bank0_busy <= '0';
bank1_busy <= '0';
end if;
end if;
end process;
 
end io_control;
/branches/avendor/mux.vhd
0,0 → 1,74
-------------------------------------------------------------------------------
-- Title : mux
-- Project :
-------------------------------------------------------------------------------
-- File : mux.vhd
-- Author :
-- Company :
-- Created : 2003-11-28
-- Last update: 2003-12-05
-- Platform :
-------------------------------------------------------------------------------
-- Description: Multiplixador de 2-1
-------------------------------------------------------------------------------
-- Copyright (c) 2003
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2003-11-28 1.0 tmsiqueira Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity mux is
generic (
width : natural);
 
port (
inRa : in std_logic_vector(WIDTH-1 downto 0);
inIa : in std_logic_vector(WIDTH-1 downto 0);
inRb : in std_logic_vector(WIDTH-1 downto 0);
inIb : in std_logic_vector(WIDTH-1 downto 0);
outR : out std_logic_vector(WIDTH-1 downto 0);
outI : out std_logic_vector(WIDTH-1 downto 0);
clk : in std_logic;
sel : in std_logic);
 
end mux;
 
architecture mux of mux is
 
begin -- mux
 
-- outR <= inRa when (sel='0') else (others => 'Z');
-- outR <= inRb when (sel='1') else (others => 'Z');
-- outI <= inIa when (sel='0') else (others => 'Z');
-- outI <= inIb when (sel='1') else (others => 'Z');
 
-- with sel select
-- outR <= inRa when '0',
-- inRb when others;
-- with sel select
-- outI <= inIa when '0',
-- inIb when others;
 
process (clk)
begin
if clk'event and clk='1' then
case sel is
when '0' =>
outR <= inRa;
outI <= inIa;
when '1' =>
outR <= inRb;
outI <= inIb;
when others =>
null;
end case;
end if;
end process;
end mux;
/branches/avendor/mux_control.vhd
0,0 → 1,38
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
entity mux_control is
generic (
stage : natural);
 
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(8 downto 0);
sel_mux : out std_logic);
end mux_control;
 
architecture mux_control of mux_control is
 
alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
 
begin
 
process(clk, rst)
begin
if rst = '1' then
sel_mux <= '0';
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and unsigned(counter) = 1 then
sel_mux <= '0';
elsif unsigned(state) = 1 and unsigned(counter) = 1 then
sel_mux <= '1';
end if;
end if;
end process;
 
end mux_control;
/branches/avendor/rxmodem.vhd
0,0 → 1,97
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity rxmodem is
Port ( clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
Iin : in std_logic_vector(11 downto 0);
mem_block : out std_logic;
wen : in std_logic;
addrin_in : in std_logic_vector(6 downto 0);
txserial : out std_logic
);
end rxmodem;
 
architecture rxmodem of rxmodem is
 
component ofdm
generic (
Tx_nRx : natural;
WIDTH : natural;
POINT : natural;
STAGE : natural);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
Iin : in std_logic_vector(WIDTH-1 downto 0);
--Qin : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0);
mem_block : out std_logic;
Output_enable : out std_logic;
--bank0_busy : out std_logic;
--bank1_busy : out std_logic;
wen_in : in std_logic;
addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
addrout_out : in std_logic_vector(2*stage-1 downto 0));
end component;
 
component output
Port ( clk : in std_logic;
rst : in std_logic;
Iout : in std_logic_vector(13 downto 0);
Qout : in std_logic_vector(13 downto 0);
Output_enable : in std_logic;
addrout_out : out std_logic_vector(5 downto 0);
txserial : out std_logic
);
end component;
 
signal Iout : std_logic_vector(13 downto 0);
signal Qout : std_logic_vector(13 downto 0);
signal Output_enable : std_logic;
signal addrout_out : std_logic_vector(5 downto 0);
 
begin
ofdm_1: ofdm
generic map (
Tx_nRx => 0,
WIDTH => 12,
POINT => 64,
STAGE => 3)
port map (
clk => clk,
rst => rst,
mem_ready => mem_ready,
Iin => Iin,
--Qin => (others => '0'),
Iout => Iout, --tratado
Qout => Qout, --tratado
mem_block => mem_block,
Output_enable => Output_enable, --tratado
wen_in => wen,
addrin_in => addrin_in,
addrout_out => addrout_out); --tratado
 
output_1: output
Port map (
clk => clk ,
rst => rst ,
Iout => Iout ,
Qout => Qout ,
Output_enable => Output_enable,
addrout_out => addrout_out ,
txserial => txserial
);
 
 
end rxmodem;
/branches/avendor/txmodem.vhd
0,0 → 1,104
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity txmodem is
port ( clk : in std_logic;
rst : in std_logic;
serial : in std_logic;
Iout : out std_logic_vector(13 downto 0);
Output_enable : out std_logic;
addrout_out : in std_logic_vector(5 downto 0)
);
end txmodem;
 
architecture txmodem of txmodem is
 
component input
port (
clk : in std_logic;
rst : in std_logic;
serial : in std_logic;
mem_block : in std_logic;
mem_ready : out std_logic;
wen : out std_logic;
address : out std_logic_vector (5 downto 0);
i : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0)
);
end component;
 
component ofdm
generic (
Tx_nRx : natural;
WIDTH : natural;
POINT : natural;
STAGE : natural);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
Iin : in std_logic_vector(WIDTH-1 downto 0);
Qin : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0);
mem_block : out std_logic;
Output_enable : out std_logic;
bank0_busy : out std_logic;
bank1_busy : out std_logic;
wen_in : in std_logic;
addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
addrout_out : in std_logic_vector(2*stage-1 downto 0));
end component;
 
signal mem_block : std_logic;
signal mem_ready : std_logic;
signal wen : std_logic;
signal address : std_logic_vector (5 downto 0);
signal i : std_logic_vector(11 downto 0);
signal q : std_logic_vector(11 downto 0);
begin
input_1 : input
port map (
clk => clk,
rst => rst,
serial => serial,
mem_block => mem_block,
mem_ready => mem_ready,
wen => wen,
address => address,
i => i,
q => q
);
 
 
ofdm_1 : ofdm
generic map (
Tx_nRx => 1,
WIDTH => 12,
POINT => 64,
STAGE => 3)
port map (
clk => clk,
rst => rst,
mem_ready => mem_ready,
Iin => I,
Qin => Q,
Iout => Iout,
Qout => open,
mem_block => mem_block,
Output_enable => Output_enable,
bank0_busy => open,
bank1_busy => open,
wen_in => wen,
addrin_in => address,
addrout_out => addrout_out);
 
end txmodem;
/branches/avendor/vhdl/input.vhd
17,7 → 17,7
wen : out std_logic;
address : out std_logic_vector (5 downto 0);
i : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0)
);
end input;
 
/branches/avendor/vhdl/modem.vhd
68,7 → 68,7
mem_block : out std_logic;
wen : in std_logic;
addrin_in : in std_logic_vector(6 downto 0);
txserial : out std_logic;
txserial : out std_logic
);
end component;
 
98,13 → 98,6
Iout => Iin,
Output_enable => Output_enable,
addrout_out => address_read
--pmem_block => mem_block_tx ,
--pmem_ready => mem_ready_tx ,
--pwen => wen_tx ,
--paddress => address_tx ,
--pi => i_tx ,
--pq => q_tx
 
);
 
txrx_1 : txrx
127,10 → 120,7
mem_block => mem_block,
wen => wen,
addrin_in => address_write,
txserial => txserial,
pIout => Iout_rx ,
pQout => Qout_rx ,
pOutput_enable => Output_enable_rx,
paddrout_out => addrout_out_rx );
txserial => txserial
);
 
end modem;
/branches/avendor/vhdl/rxmodem.vhd
16,7 → 16,7
mem_block : out std_logic;
wen : in std_logic;
addrin_in : in std_logic_vector(6 downto 0);
txserial : out std_logic;
txserial : out std_logic
);
end rxmodem;
 
/branches/avendor/vhdl/txmodem.vhd
30,7 → 30,7
wen : out std_logic;
address : out std_logic_vector (5 downto 0);
i : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0);
q : out std_logic_vector(11 downto 0)
);
end component;
 
75,10 → 75,8
wen => wen,
address => address,
i => i,
q => q,
pmeta => open,
psync => open,
paddr => open);
q => q
);
 
 
ofdm_1 : ofdm
/branches/avendor/vhdl/ofdm.npl
0,0 → 1,52
JDF G
// Created by Project Navigator ver 1.0
PROJECT ofdm
DESIGN ofdm
DEVFAM spartan2
DEVFAMTIME 1145426085
DEVICE xc2s200
DEVICETIME 1145426085
DEVPKG pq208
DEVPKGTIME 1145425004
DEVSPEED -5
DEVSPEEDTIME 1145426085
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE modem.vhd
SOURCE ram.vhd
SOURCE mux.vhd
SOURCE rxmodem.vhd
SOURCE cfft.vhd
SOURCE input.vhd
SOURCE p2r_CordicPipe.vhd
SOURCE txmodem.vhd
SOURCE blockdram.vhd
SOURCE conj.vhd
SOURCE ofdm.vhd
SOURCE mulfactor.vhd
SOURCE counter.vhd
SOURCE div4limit.vhd
SOURCE cfft4.vhd
SOURCE inv_control.vhd
SOURCE ram_control.vhd
SOURCE rofactor.vhd
SOURCE mux_control.vhd
SOURCE starts.vhd
SOURCE txrx.vhd
SOURCE cfft_control.vhd
SOURCE io_control.vhd
SOURCE output.vhd
SOURCE p2r_cordic.vhd
SOURCE sc_corproc.vhd
[Normal]
p_xstVerilog2001=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, Normal
_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
[STRATEGY-LIST]
Normal=True
/branches/avendor/ram_control.vhd
0,0 → 1,214
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
entity ram_control is
generic (
Tx_nRX : natural := 0;
stage : natural := 3);
 
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
mem_bk : in std_logic;
addrout_in : out std_logic_vector(stage*2-Tx_nRX downto 0);
wen_proc : out std_logic;
addrin_proc : out std_logic_vector(stage*2-1 downto 0);
addrout_proc : out std_logic_vector(stage*2-1 downto 0);
wen_out : out std_logic;
addrin_out : out std_logic_vector(stage*2-1 downto 0));
 
 
end ram_control;
 
architecture ram_control of ram_control is
 
function counter2addr(
counter : std_logic_vector;
mask1 : std_logic_vector;
mask2 : std_logic_vector
) return std_logic_vector is
variable result : std_logic_vector(counter'range);
begin
for n in mask1'range loop
if mask1(n) = '1' then
result( 2*n+1 downto 2*n ) := counter( 1 downto 0 );
elsif mask2(n) = '1' and n /= STAGE-1 then
result( 2*n+1 downto 2*n ) := counter( 2*n+3 downto 2*n+2 );
else
result( 2*n+1 downto 2*n ) := counter( 2*n+1 downto 2*n );
end if;
end loop;
return result;
end counter2addr;
 
function outcounter2addr(counter : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(counter'range);
begin
for n in 0 to STAGE-1 loop
result( 2*n+1 downto 2*n ) := counter( counter'high-2*n downto counter'high-2*n-1 );
end loop;
return result;
end outcounter2addr;
 
alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
 
constant FFTDELAY : integer := 13+2*STAGE;
constant FACTORDELAY : integer := 6;
constant OUTDELAY : integer := 9;
 
-- read
signal rmask1, rmask2 : std_logic_vector( STAGE-1 downto 0 );
-- proc
signal wmask1, wmask2 : std_logic_vector( STAGE-1 downto 0 );
signal wcounter : std_logic_vector( STAGE*2-1 downto 0 );
-- out
signal outcounter : std_logic_vector( STAGE*2-1 downto 0 );
 
begin
 
-- Read
Tx_read : if Tx_nRx = 1 generate
readaddr : process( clk, rst )
variable aux_addrout : std_logic_vector(stage*2-1 downto 0);
variable aux_addrout_abs : std_logic_vector(stage*2-1 downto 0);
begin
if rst = '1' then
addrout_in <= ( others => '0' );
addrout_proc <= ( others => '0' );
aux_addrout := ( others => '0' );
aux_addrout_abs := ( others => '0' );
rmask1 <= ( others => '0' );
rmask2 <= ( others => '0' );
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and signed(counter) = 0 then
rmask1(STAGE-1) <= '1';
rmask1(STAGE-2 downto 0) <= (others => '0');
rmask2(STAGE-1) <= '0';
rmask2(STAGE-2 downto 0) <= (others => '1');
elsif signed(counter) = -1 then
rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
end if;
aux_addrout := counter2addr(counter, rmask1, rmask2);
aux_addrout_abs := abs(aux_addrout);
if unsigned(state) = 0 then
if mem_bk = '0' then
addrout_in <= aux_addrout_abs;
else
addrout_in <= aux_addrout_abs+32;
end if;
end if;
addrout_proc <= aux_addrout;
end if;
end process readaddr;
end generate;
 
Rx_read : if Tx_nRx = 0 generate
readaddr : process( clk, rst )
variable aux_addrout : std_logic_vector(stage*2 downto 0);
begin
if rst = '1' then
addrout_in <= ( others => '0' );
addrout_proc <= ( others => '0' );
aux_addrout := ( others => '0' );
rmask1 <= ( others => '0' );
rmask2 <= ( others => '0' );
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and signed(counter) = 0 then
rmask1(STAGE-1) <= '1';
rmask1(STAGE-2 downto 0) <= (others => '0');
rmask2(STAGE-1) <= '0';
rmask2(STAGE-2 downto 0) <= (others => '1');
elsif signed(counter) = -1 then
rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
end if;
aux_addrout := '0'&counter2addr(counter, rmask1, rmask2);
if unsigned(state) = 0 and mem_bk = '1' then
addrout_in <= aux_addrout+64;
else
addrout_in <= aux_addrout;
end if;
addrout_proc <= aux_addrout(stage*2-1 downto 0);
end if;
end process readaddr;
end generate;
 
 
-- Escrita em proc
 
writeaddr_proc : process( clk, rst )
begin
if rst = '1' then
addrin_proc <= ( others => '0' );
wcounter <= ( others => '0' );
wmask1 <= ( others => '0' );
wmask2 <= ( others => '0' );
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and unsigned(counter) = FFTDELAY-1 then
wmask1(STAGE-1) <= '1';
wmask1(STAGE-2 downto 0) <= (others => '0');
wmask2(STAGE-1) <= '0';
wmask2(STAGE-2 downto 0) <= (others => '1');
elsif unsigned(counter) = FFTDELAY-1 then
wmask1 <= '0'&wmask1( STAGE-1 downto 1 );
wmask2 <= '0'&wmask2( STAGE-1 downto 1 );
end if;
if unsigned(state) < STAGE and unsigned(counter) = FFTDELAY-1 then
wcounter <= ( others => '0' );
else
wcounter <= unsigned(wcounter)+1;
end if;
addrin_proc <= counter2addr(wcounter, wmask1, wmask2 );
end if;
end process writeaddr_proc;
 
writeen_proc : process( clk, rst )
begin
if rst = '1' then
wen_proc <= '0';
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and unsigned(counter) = FFTDELAY then
wen_proc <= '1';
elsif unsigned(state) = STAGE-1 and unsigned(counter) = FFTDELAY then
wen_proc <= '0';
end if;
end if;
end process writeen_proc;
 
-- Escrite em OutRam
 
writeaddr_out : process( clk, rst )
begin
if rst = '1' then
outcounter <= (others => '0');
elsif clk'event and clk = '1' then
if unsigned(state) = stage-1 and unsigned(counter) = OUTDELAY then
outcounter <= (others => '0');
else
outcounter <= unsigned(outcounter)+1;
end if;
end if;
end process writeaddr_out;
 
addrin_out <= outcounter2addr(outcounter);
 
writeen_out : process( clk, rst )
begin
if rst = '1' then
wen_out <= '0';
elsif clk'event and clk = '1' then
if unsigned(state) = STAGE-1 and unsigned(counter) = OUTDELAY then
wen_out <= '1';
elsif unsigned(outcounter) = 63 then
wen_out <= '0';
end if;
end if;
end process writeen_out;
end ram_control;
 
 
/branches/avendor/ram.vhd
0,0 → 1,91
-------------------------------------------------------------------------------
-- Title : ram.vhd
-- Project :
-------------------------------------------------------------------------------
-- File : ram.vhd
-- Author :
-- Company :
-- Created : 2003-12-05
-- Last update: 2003-12-05
-- Platform :
-------------------------------------------------------------------------------
-- Description: Bloco de ram para armazenar a parte real e a imaginaria.
-------------------------------------------------------------------------------
-- Copyright (c) 2003
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2003-12-05 1.0 tmsiqueira Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
entity ram is
generic (
width : natural;
depth : natural;
Addr_width : natural);
 
port (
clkin : in std_logic; -- clock para a porta de entrada
wen : in std_logic; -- write enable
addrin : in std_logic_vector(Addr_width-1 downto 0); -- endereco de entrada
dinR : in std_logic_vector(width-1 downto 0); -- imag data in
dinI : in std_logic_vector(width-1 downto 0); -- real data in
clkout : in std_logic; -- clock para a porta de saida
addrout : in std_logic_vector(Addr_width-1 downto 0); -- endereco de leitura
doutR : out std_logic_vector(width-1 downto 0); -- real data out
doutI : out std_logic_vector(width-1 downto 0)); -- imag data out
 
end ram;
 
architecture ram of ram is
 
component blockdram
generic (
depth : natural;
Dwidth : natural;
Awidth : natural);
port (
clkin : in std_logic;
wen : in std_logic;
addrin : in std_logic_vector(Awidth-1 downto 0);
din : in std_logic_vector(Dwidth-1 downto 0);
clkout : in std_logic;
addrout : in std_logic_vector(Awidth-1 downto 0);
dout : out std_logic_vector(Dwidth-1 downto 0));
end component;
begin -- ram
 
Real_ram : blockdram
generic map (
depth => depth,
Dwidth => width,
Awidth => Addr_width)
port map (
clkin => clkin,
wen => wen,
addrin => addrin,
din => dinR,
clkout => clkout,
addrout => addrout,
dout => doutR);
 
Imag_ram : blockdram
generic map (
depth => depth,
Dwidth => width,
Awidth => Addr_width)
port map (
clkin => clkin,
wen => wen,
addrin => addrin,
din => dinI,
clkout => clkout,
addrout => addrout,
dout => doutI);
 
end ram;
/branches/avendor/counter.vhd
0,0 → 1,51
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity counter is
generic (
stage : natural := 3);
 
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
mem_bk : out std_logic;
count : out std_logic_vector(2*stage+2 downto 0));
 
end counter;
 
architecture counter of counter is
 
signal aux_mem_bk : std_logic;
signal count_aux : std_logic_vector(2*stage+2 downto 0);
constant max_count : std_logic_vector(2*stage+2 downto 0) := conv_std_logic_vector(stage-1,3)&conv_std_logic_vector(-1,2*stage);
 
begin
count <= count_aux;
mem_bk <= aux_mem_bk;
 
process (clk, rst)
variable initialize : std_logic_vector(1 downto 0);
begin -- process
if rst = '1' then -- asynchronous reset (active low)
count_aux <= max_count;
aux_mem_bk <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if count_aux = max_count then
if mem_ready = '1' then
aux_mem_bk <= not(aux_mem_bk);
count_aux <= (others => '0');
end if;
else
count_aux <= count_aux + 1;
end if;
end if;
end process;
 
end counter;
/branches/avendor/rofactor.vhd
0,0 → 1,126
---------------------------------------------------------------------------------------------------
--
-- Title : rofactor
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : rofactor.vhd
-- Generated : Thu Oct 3 00:12:16 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : Generate FFT rotation factor
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1.1.0
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 2
-- Version : 1.2.0
-- Date : Oct 18 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
 
entity rofactor is
generic (
POINT : Natural := 64;
STAGE : Natural := 3
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
invert : in std_logic;
-- step : in STD_LOGIC_VECTOR(2 downto 0);
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
);
end rofactor;
 
 
architecture rofactor of rofactor is
signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
signal comp : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' );
 
 
begin
angle<=phase;
 
count:process( clk,rst )
begin
if rst='1' then
counter<=( others=>'0' );
inc<=( others=>'0' );
mask<=( others=>'0' );
elsif clk'event and clk='1' then
if start='1' then
counter<=( others=>'0' );
mask<=( others=>'0' );
-- state<="000";
if invert='1' then
inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
else
inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
end if;
else
counter<=unsigned(counter)+1;
if signed(counter)=-1 then
inc<=inc(STAGE*2-3 downto 0 )&"00";
mask<="11"&mask( STAGE*2-1 downto 2 );
-- if state/="100" then
-- state<=state+1;
-- end if;
end if;
end if;
end if;
end process count;
 
output : process( clk, rst )
begin
if rst='1' then
phase<=( others=>'0' );
iinc<=( others=>'0' );
elsif clk'event and clk='1' then
if start='1' then
iinc<=( others=>'0' );
phase<=( others=>'0' );
else
if unsigned(counter( 1 downto 0 ))=3 then
phase<=( others=>'0' );
else
phase<=unsigned(phase)+unsigned(iinc);
end if;
-- if signed(counter or mask)=-1 then -- modified by Tonny Matos Siqueira
if signed(comp)=-1 then
iinc<=(others => '0');
elsif unsigned(counter( 1 downto 0 ))=3 then
iinc<=unsigned(iinc)+unsigned(inc);
end if;
end if;
end if;
end process output;
 
comp <= counter or mask;
 
end rofactor;
/branches/avendor/starts.vhd
0,0 → 1,44
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
entity starts is
generic (
stage : natural);
 
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
factorstart : out std_logic;
cfft4start : out std_logic);
end starts;
 
architecture starts of starts is
 
alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
 
begin
 
process( clk, rst )
begin
if rst = '1' then
factorstart <= '0';
cfft4start <= '0';
elsif clk'event and clk = '1' then
if unsigned(state) = 0 and unsigned(counter) = 2 then
cfft4start <= '1';
else
cfft4start <= '0';
end if;
if unsigned(state) = 0 and unsigned(counter) = 8 then
factorstart <= '1';
else
factorstart <= '0';
end if;
end if;
end process;
 
end starts;
/branches/avendor/cfft_control.vhd
0,0 → 1,181
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
entity cfft_control is
generic (
Tx_nRx : natural := 0; -- tx = 1, rx = 0
stage : natural := 3);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
 
sel_mux : out std_logic;
factorstart : out std_logic;
cfft4start : out std_logic;
inv : out std_logic;
Output_enable : out std_logic;
bank0_busy : out std_logic;
bank1_busy : out std_logic;
 
mem_block : out std_logic;
 
addrout_in : out std_logic_vector(stage*2-Tx_nRx downto 0);
wen_proc : out std_logic;
addrin_proc : out std_logic_vector(stage*2-1 downto 0);
addrout_proc : out std_logic_vector(stage*2-1 downto 0);
wen_out : out std_logic;
addrin_out : out std_logic_vector(stage*2-1 downto 0));
end cfft_control;
 
architecture cfft_control of cfft_control is
 
component counter
generic (
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
mem_bk : out std_logic;
count : out std_logic_vector(2*stage+2 downto 0));
end component;
 
component ram_control
generic (
Tx_nRX : natural;
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
mem_bk : in std_logic;
addrout_in : out std_logic_vector(stage*2-Tx_nRX downto 0);
wen_proc : out std_logic;
addrin_proc : out std_logic_vector(stage*2-1 downto 0);
addrout_proc : out std_logic_vector(stage*2-1 downto 0);
wen_out : out std_logic;
addrin_out : out std_logic_vector(stage*2-1 downto 0));
end component;
 
component mux_control
generic (
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(8 downto 0);
sel_mux : out std_logic);
end component;
 
component starts
generic (
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
factorstart : out std_logic;
cfft4start : out std_logic);
end component;
 
component inv_control
generic (
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
inv : out std_logic);
end component;
 
component io_control
generic (
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
mem_bk : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
bank0_busy : out std_logic;
bank1_busy : out std_logic;
Output_enable : out std_logic);
end component;
 
signal count : std_logic_vector(2*stage+2 downto 0);
signal mem_bk : std_logic;
begin
 
mem_block <= mem_bk;
 
counter_1 : counter
generic map (
stage => stage)
port map (
clk => clk,
rst => rst,
mem_ready => mem_ready,
mem_bk => mem_bk,
count => count);
 
ram_control_1 : ram_control
generic map (
Tx_nRX => Tx_nRX,
stage => stage)
port map (
clk => clk,
rst => rst,
Gen_state => count,
mem_bk => mem_bk,
addrout_in => addrout_in,
wen_proc => wen_proc,
addrin_proc => addrin_proc,
addrout_proc => addrout_proc,
wen_out => wen_out,
addrin_out => addrin_out);
 
mux_control_1 : mux_control
generic map (
stage => stage)
port map (
clk => clk,
rst => rst,
Gen_state => count,
sel_mux => sel_mux);
 
starts_1 : starts
generic map (
stage => stage)
port map (
clk => clk,
rst => rst,
Gen_state => count,
factorstart => factorstart,
cfft4start => cfft4start);
 
TX_inv : if Tx_nRx = 1 generate
inv_control_1 : inv_control
generic map (
stage => stage)
port map (
clk => clk,
rst => rst,
Gen_state => count,
inv => inv);
end generate;
 
io_control_1 : io_control
generic map (
stage => stage)
port map (
clk => clk,
rst => rst,
mem_bk => mem_bk,
Gen_state => count,
bank0_busy => bank0_busy,
bank1_busy => bank1_busy,
Output_enable => Output_enable);
 
end cfft_control;
/branches/avendor/cfft.vhd
0,0 → 1,425
---------------------------------------------------------------------------------------------------
--
-- Title : cfft
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : cfft.vhd
-- Generated : Thu Oct 3 03:03:58 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with
-- limit and overfall processing internal
--
-- The gain is 0.0287 for FFT and 29.4 for IFFT
--
-- The output is 4-based reversed ordered, it means
-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
--
--
---------------------------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------------------------
--
-- port :
-- clk : main clk -- I have test 90M with Xilinx virtex600E
-- rst : globe reset -- '1' for reset
-- start : start fft -- one clock '1' before data input
-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
-- Iin,Qin : data input-- following start immediately, input data
-- -- power should not be too big
-- inputbusy : if it change to '0' then next fft is enable
-- outdataen : when it is '1', the valid data is output
-- Iout,Qout : fft data output when outdataen is '1'
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1.1.0
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 2
-- Version : 1.2.0
-- Date : Oct 18 2002
-- Modifier : ZHAO Ming
-- Desccription : Point configurable
-- FFT Gain IFFT GAIN
-- 256 0.0698 17.9
-- 1024 0.0287 29.4
-- 4096 0.0118 48.2742
--
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 3
-- Version : 1.3.0
-- Date : Nov 19 2002
-- Modifier : ZHAO Ming
-- Desccription : add output data position indication
--
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity cfft is
generic (
Tx_nRx : natural :=1; -- tx = 1, rx = 0
WIDTH : natural := 12;
POINT : natural := 64;
STAGE : natural := 3 -- STAGE=log4(POINT)
);
port(
rst : in std_logic;
Iin : in std_logic_vector(WIDTH-1 downto 0);
Qin : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0);
factorstart : in std_logic;
cfft4start : in std_logic;
 
ClkIn : in std_logic;
 
sel_mux : in std_logic;
inv : in std_logic;
 
wen_in : in std_logic;
addrin_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
 
wen_proc : in std_logic;
addrin_proc : in std_logic_vector(2*stage-1 downto 0);
addrout_proc : in std_logic_vector(2*stage-1 downto 0);
 
wen_out : in std_logic;
addrin_out : in std_logic_vector(2*stage-1 downto 0);
addrout_out : in std_logic_vector(2*stage-1 downto 0));
 
end cfft;
 
 
architecture cfft of cfft is
 
component mux
generic (
width : natural);
port (
inRa : in std_logic_vector(WIDTH-1 downto 0);
inIa : in std_logic_vector(WIDTH-1 downto 0);
inRb : in std_logic_vector(WIDTH-1 downto 0);
inIb : in std_logic_vector(WIDTH-1 downto 0);
outR : out std_logic_vector(WIDTH-1 downto 0);
outI : out std_logic_vector(WIDTH-1 downto 0);
 
clk : in std_logic;
sel : in std_logic);
end component;
 
component conj
generic (
width : natural);
port (
 
inR : in std_logic_vector(WIDTH-1 downto 0);
inI : in std_logic_vector(WIDTH-1 downto 0);
outR : out std_logic_vector(WIDTH-1 downto 0);
outI : out std_logic_vector(WIDTH-1 downto 0);
 
clk : in std_logic;
conj : in std_logic);
end component;
 
component ram
generic (
width : natural;
depth : natural;
Addr_width : natural);
port (
clkin : in std_logic;
wen : in std_logic;
addrin : in std_logic_vector(Addr_width-1 downto 0);
dinR : in std_logic_vector(width-1 downto 0);
dinI : in std_logic_vector(width-1 downto 0);
clkout : in std_logic;
addrout : in std_logic_vector(Addr_width-1 downto 0);
doutR : out std_logic_vector(width-1 downto 0);
doutI : out std_logic_vector(width-1 downto 0));
end component;
 
component cfft4
generic (
width : natural
);
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
invert : in std_logic;
I : in std_logic_vector(WIDTH-1 downto 0);
Q : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0)
);
end component;
 
component div4limit
generic (
WIDTH : natural
);
port(
clk : in std_logic;
D : in std_logic_vector(WIDTH+3 downto 0);
Q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
 
component mulfactor
generic (
WIDTH : natural;
STAGE : natural
);
port(
clk : in std_logic;
rst : in std_logic;
angle : in signed(2*STAGE-1 downto 0);
I : in signed(WIDTH+1 downto 0);
Q : in signed(WIDTH+1 downto 0);
Iout : out signed(WIDTH+3 downto 0);
Qout : out signed(WIDTH+3 downto 0)
);
end component;
 
component rofactor
generic (
POINT : natural;
STAGE : natural
);
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
invert : in std_logic;
angle : out std_logic_vector(2*STAGE-1 downto 0)
);
end component;
 
 
component blockdram
generic (
depth : natural;
Dwidth : natural;
Awidth : natural);
port (
clkin : in std_logic;
wen : in std_logic;
addrin : in std_logic_vector(Awidth-1 downto 0);
din : in std_logic_vector(Dwidth-1 downto 0);
clkout : in std_logic;
addrout : in std_logic_vector(Awidth-1 downto 0);
dout : out std_logic_vector(Dwidth-1 downto 0));
end component;
signal MuxInRa, MuxInIa, MuxInRb, MuxInIb : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal conjInR, conjInI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal cfft4InR, cfft4InI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal cfft4outR, cfft4outI : std_logic_vector(WIDTH+1 downto 0) := (others => '0');
signal MulOutR, MulOutI : signed(WIDTH+3 downto 0) := (others => '0');
signal fftR, fftI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal angle : std_logic_vector(2*STAGE-1 downto 0 ) := ( others => '0');
signal invert : std_logic;
 
begin
 
TX:if Tx_nRx = 1 generate
RamIn : ram
generic map (
width => WIDTH,
depth => POINT,
Addr_width => 2*STAGE)
port map (
clkin => ClkIn,
wen => wen_in,
addrin => addrin_in,
dinR => Iin,
dinI => Qin,
clkout => ClkIn,
addrout => addrout_in,
doutR => MuxInRa,
doutI => MuxInIa);
 
RamOut : ram
generic map (
width => WIDTH+2,
depth => POINT,
Addr_width => 2*STAGE)
port map (
clkin => ClkIn,
wen => wen_out,
addrin => addrin_out,
dinR => cfft4outR,
dinI => cfft4outR,
clkout => ClkIn,
addrout => addrout_out,
doutR => Iout,
doutI => open);
end generate;
 
RX:if Tx_nRx = 0 generate
RamIn : ram
generic map (
width => WIDTH,
depth => 2*POINT,
Addr_width => 2*STAGE+1)
port map (
clkin => ClkIn,
wen => wen_in,
addrin => addrin_in,
dinR => Iin,
dinI => Qin,
clkout => ClkIn,
addrout => addrout_in,
doutR => MuxInRa,
doutI => open);
 
MuxinIa <= (others => '0');
 
RamOut : ram
generic map (
width => WIDTH+2,
depth => POINT,
Addr_width => 2*STAGE)
port map (
clkin => ClkIn,
wen => wen_out,
addrin => addrin_out,
dinR => cfft4outR,
dinI => cfft4outR,
clkout => ClkIn,
addrout => addrout_out,
doutR => Iout,
doutI => Qout);
 
end generate;
 
 
RamProc : ram
generic map (
width => WIDTH,
depth => POINT,
Addr_width => 2*STAGE)
port map (
clkin => ClkIn,
wen => wen_proc,
addrin => addrin_proc,
dinR => fftR,
dinI => fftI,
clkout => ClkIn,
addrout => addrout_proc,
doutR => MuxInRb,
doutI => MuxInIb);
 
mux_1 : mux
generic map (
width => width)
port map (
inRa => MuxInRa,
inIa => MuxInIa,
inRb => MuxInRb,
inIb => MuxInIb,
outR => conjInR,
outI => conjInI,
clk => clkin,
sel => sel_mux);
 
invert <= (inv and conv_std_logic_vector(Tx_nRx,1)(0));
 
conj_1: conj
generic map (
width => width)
port map (
 
inR => conjInR,
inI => conjInI,
outR => cfft4InR,
outI => cfft4InI,
clk => Clkin,
conj => invert);
 
acfft4 : cfft4
generic map (
WIDTH => WIDTH
)
port map (
clk => ClkIn,
rst => rst,
start => cfft4start,
invert => conv_std_logic_vector(Tx_nRx,1)(0),
I => cfft4InR,
Q => cfft4InI,
Iout => cfft4outR,
Qout => cfft4outI
);
 
amulfactor : mulfactor
generic map (
WIDTH => WIDTH,
STAGE => STAGE
)
port map (
clk => ClkIn,
rst => rst,
angle => signed(angle),
I => signed(cfft4outR),
Q => signed(cfft4outI),
Iout => MulOutR,
Qout => MulOutI
);
 
arofactor : rofactor
generic map (
POINT => POINT,
STAGE => STAGE
)
port map (
clk => ClkIn,
rst => rst,
start => factorstart,
invert => conv_std_logic_vector(Tx_nRx,1)(0), -- IFFT
angle => angle
);
 
Rlimit : div4limit
generic map (
WIDTH => WIDTH
)
port map (
clk => ClkIn,
D => std_logic_vector(MulOutR),
Q => fftR
);
Ilimit : div4limit
generic map (
WIDTH => WIDTH
)
port map (
clk => ClkIn,
D => std_logic_vector(MulOutI),
Q => fftI
);
end cfft;
/branches/avendor/ofdm.vhd
0,0 → 1,145
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity ofdm is
generic (
Tx_nRx : natural := 1;
WIDTH : natural := 12;
POINT : natural := 64;
STAGE : natural := 3 -- STAGE=log4(POINT)
);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
Iin : in std_logic_vector(WIDTH-1 downto 0);
Qin : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0);
mem_block : out std_logic;
Output_enable : out std_logic;
bank0_busy : out std_logic;
bank1_busy : out std_logic;
wen_in : in std_logic;
addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
addrout_out : in std_logic_vector(2*stage-1 downto 0));
 
end ofdm;
 
architecture ofdm of ofdm is
 
component cfft_control
generic (
Tx_nRx : natural;
stage : natural);
port (
clk : in std_logic;
rst : in std_logic;
mem_ready : in std_logic;
sel_mux : out std_logic;
factorstart : out std_logic;
cfft4start : out std_logic;
inv : out std_logic;
Output_enable : out std_logic;
bank0_busy : out std_logic;
bank1_busy : out std_logic;
mem_block : out std_logic;
addrout_in : out std_logic_vector(stage*2-Tx_nRX downto 0);
wen_proc : out std_logic;
addrin_proc : out std_logic_vector(stage*2-1 downto 0);
addrout_proc : out std_logic_vector(stage*2-1 downto 0);
wen_out : out std_logic;
addrin_out : out std_logic_vector(stage*2-1 downto 0));
end component;
 
component cfft
generic (
Tx_nRx : natural;
WIDTH : natural;
POINT : natural;
STAGE : natural);
port (
rst : in std_logic;
Iin : in std_logic_vector(WIDTH-1 downto 0);
Qin : in std_logic_vector(WIDTH-1 downto 0);
Iout : out std_logic_vector(WIDTH+1 downto 0);
Qout : out std_logic_vector(WIDTH+1 downto 0);
factorstart : in std_logic;
cfft4start : in std_logic;
ClkIn : in std_logic;
sel_mux : in std_logic;
inv : in std_logic;
wen_in : in std_logic;
addrin_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
wen_proc : in std_logic;
addrin_proc : in std_logic_vector(2*stage-1 downto 0);
addrout_proc : in std_logic_vector(2*stage-1 downto 0);
wen_out : in std_logic;
addrin_out : in std_logic_vector(2*stage-1 downto 0);
addrout_out : in std_logic_vector(2*stage-1 downto 0));
end component;
 
signal sel_mux : std_logic;
signal factorstart : std_logic;
signal cfft4start : std_logic;
signal inv : std_logic;
signal addrout_in : std_logic_vector(stage*2-Tx_nRx downto 0);
signal wen_proc : std_logic;
signal addrin_proc : std_logic_vector(stage*2-1 downto 0);
signal addrout_proc : std_logic_vector(stage*2-1 downto 0);
signal wen_out : std_logic;
signal addrin_out : std_logic_vector(stage*2-1 downto 0);
begin
 
cfft_control_1 : cfft_control
generic map (
Tx_nRx => Tx_nRx,
stage => stage)
port map (
clk => clk,
rst => rst,
mem_ready => mem_ready,
sel_mux => sel_mux,
factorstart => factorstart,
cfft4start => cfft4start,
inv => inv,
Output_enable => Output_enable,
bank0_busy => bank0_busy,
bank1_busy => bank1_busy,
mem_block => mem_block,
addrout_in => addrout_in,
wen_proc => wen_proc,
addrin_proc => addrin_proc,
addrout_proc => addrout_proc,
wen_out => wen_out,
addrin_out => addrin_out);
 
cfft_1 : cfft
generic map (
Tx_nRx => Tx_nRx,
WIDTH => WIDTH,
POINT => POINT,
STAGE => STAGE)
port map (
rst => rst,
Iin => Iin,
Qin => Qin,
Iout => Iout,
Qout => Qout,
factorstart => factorstart,
cfft4start => cfft4start,
ClkIn => Clk,
sel_mux => sel_mux,
inv => inv,
wen_in => wen_in,
addrin_in => addrin_in,
addrout_in => addrout_in,
wen_proc => wen_proc,
addrin_proc => addrin_proc,
addrout_proc => addrout_proc,
wen_out => wen_out,
addrin_out => addrin_out,
addrout_out => addrout_out);
end ofdm;
/branches/avendor/p2r_cordic.vhd
0,0 → 1,131
--
-- VHDL implementation of cordic algorithm
--
-- File: p2r_cordic.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
--
 
--
--
-- This file is come from www.opencores.org
--
-- It has been modified by zhaom to enable 20 bit phase input
--
---------------------------------------------------------------------------------------------------
--
-- Title : p2r_cordic
-- Design : cfft
--
---------------------------------------------------------------------------------------------------
--
-- File : p2r_cordic.vhd
--
---------------------------------------------------------------------------------------------------
--
-- Description : Cordic arith pilepline
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming <sradio@opencores.org>
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity p2r_cordic is
generic(
PIPELINE : integer := 15;
WIDTH : integer := 16);
port(
clk : in std_logic;
ena : in std_logic;
 
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0) := (others => '0');
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0)
);
end entity p2r_Cordic;
 
 
architecture dataflow of p2r_cordic is
 
--
-- TYPE defenitions
--
type XYVector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0);
type ZVector is array(PIPELINE downto 0) of signed(19 downto 0);
 
--
-- COMPONENT declarations
--
component p2r_CordicPipe
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
 
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
 
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end component p2r_CordicPipe;
 
--
-- SIGNALS
--
signal X, Y : XYVector;
signal Z : ZVector;
 
--
-- ACHITECTURE BODY
--
begin
-- fill first nodes
 
-- fill X
X(0) <= Xi;
 
-- fill Y
Y(0) <= Yi;
 
-- fill Z
Z(0)(19 downto 0) <= Zi; -- modified by zhaom
--Z(0)(3 downto 0) <= (others => '0'); -- modified by zhaom
 
--
-- generate pipeline
--
gen_pipe:
for n in 1 to PIPELINE generate
Pipe: p2r_CordicPipe
generic map(WIDTH => WIDTH, PIPEID => n -1)
port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) );
end generate gen_pipe;
 
--
-- assign outputs
--
Xo <= X(PIPELINE);
Yo <= Y(PIPELINE);
end dataflow;
 
 
/branches/avendor/conj.vhd
0,0 → 1,66
-------------------------------------------------------------------------------
-- Title : Conj.vhd
-- Project :
-------------------------------------------------------------------------------
-- File : invsignal.vhd
-- Author :
-- Company :
-- Created : 2003-11-28
-- Last update: 2003-12-05
-- Platform :
-------------------------------------------------------------------------------
-- Description: Faz o conjugado do sinal de entrada
-------------------------------------------------------------------------------
-- Copyright (c) 2003
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2003-11-28 1.0 tmsiqueira Created
-------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity conj is
generic (
width : natural);
 
port (
inR : in std_logic_vector(WIDTH-1 downto 0);
inI : in std_logic_vector(WIDTH-1 downto 0);
outR : out std_logic_vector(WIDTH-1 downto 0);
outI : out std_logic_vector(WIDTH-1 downto 0);
clk : in std_logic;
conj : in std_logic);
 
end conj;
 
architecture conj of conj is
 
begin
 
process(clk)
begin
if clk'event and clk='1' then
case conj is
when '0' =>
outR <= inR;
outI <= inI;
when '1' =>
outR <= inR;
outI <= 0-inI;
when others =>
null;
end case;
end if;
end process;
 
end conj;
/branches/avendor/mulfactor.vhd
0,0 → 1,126
---------------------------------------------------------------------------------------------------
--
-- Title : mulfactor
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : mulfactor.vhd
-- Generated : Thu Oct 3 00:37:40 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : 360 degee complex rotation
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1.1.0
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 2
-- Version : 1.2.1
-- Date : Oct 18 2002
-- Modifier : ZHAO Ming
-- Desccription : Point configurable
--
---------------------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
 
entity mulfactor is
generic (
WIDTH : Natural:=12;
STAGE : Natural:=3
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
angle : in signed(2*STAGE-1 downto 0);
I : in signed(WIDTH+1 downto 0);
Q : in signed(WIDTH+1 downto 0);
Iout : out signed(WIDTH+3 downto 0);
Qout : out signed(WIDTH+3 downto 0)
);
end mulfactor;
 
 
architecture mulfactor of mulfactor is
signal phase : signed( 2*STAGE-3 downto 0 );
signal Xi,Yi : signed( WIDTH+1 downto 0 );
component sc_corproc
generic(
WIDTH : Natural;
STAGE : Natural
);
port(
clk : in std_logic;
ena : in std_logic;
Xin : in signed(WIDTH+1 downto 0);
Yin : in signed(WIDTH+1 downto 0);
Ain : in signed(2*STAGE-3 downto 0 );
sin : out signed(WIDTH+3 downto 0);
cos : out signed(WIDTH+3 downto 0));
end component;
 
begin
u1: sc_corproc
generic map(
WIDTH=>WIDTH,
STAGE=>STAGE
)
port map (
clk=>clk,
ena=>'1',
Xin=>Xi,
Yin=>Yi,
Ain=>phase,
sin=>Qout,
cos=>Iout
);
 
process( clk, rst )
variable temp : std_logic_vector( 1 downto 0 );
begin
if rst='1' then
phase<=( others=>'0' );
Xi<=( others=>'0' );
Yi<=( others=>'0' );
elsif clk'event and clk='1' then
phase<=angle( 2*STAGE-3 downto 0 );
temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
case temp is
when "00" =>
Xi<=I;
Yi<=Q;
when "01" =>
Xi<=0-Q;
Yi<=I;
when "10" =>
Xi<=0-I;
Yi<=0-Q;
when "11" =>
Xi<=Q;
Yi<=0-I;
when others=>
null;
end case;
end if;
end process;
end mulfactor;
/branches/avendor/inv_control.vhd
0,0 → 1,37
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity inv_control is
generic (
stage : natural:=3);
 
port (
clk : in std_logic;
rst : in std_logic;
Gen_state : in std_logic_vector(2*stage+2 downto 0);
inv : out std_logic);
end inv_control;
 
architecture inv_control of inv_control is
 
alias state : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
 
begin
 
process (clk, rst)
begin -- process
if rst = '1' then -- asynchronous reset (active low)
inv <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if (unsigned(state) = 0) or (unsigned(state) = 1 and unsigned(counter)< 4) then
inv <= not(counter(1));
else
inv <= '0';
end if;
end if;
end process;
 
end inv_control;
/branches/avendor/sc_corproc.vhd
0,0 → 1,100
--
-- This file is come from www.opencores.org
--
-- It has been modified by ZHAO Ming for 20 bit complex rotation
--
 
---------------------------------------------------------------------------------------------------
--
-- Title : sc_corproc
-- Design : cfft
-- Author : ZHAO Ming
-- email : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File : sc_corproc.vhd
-- Generated : Tue Jul 16 10:39:17 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : complex rotation
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 1
-- Version : 1.1.0
-- Date : Oct 17 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
--
-- Revisions : 0
-- Revision Number : 2
-- Version : 1.2.0
-- Date : Oct 18 2002
-- Modifier : ZHAO Ming
-- Desccription : Data width configurable
--
---------------------------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
 
entity sc_corproc is
generic (
WIDTH : Natural;
STAGE : Natural
);
port(
clk : in std_logic;
ena : in std_logic;
Xin : in signed(WIDTH+1 downto 0);
Yin : in signed(WIDTH+1 downto 0);
Ain : in signed(2*STAGE-3 downto 0 );
sin : out signed(WIDTH+3 downto 0);
cos : out signed(WIDTH+3 downto 0)
);
end entity sc_corproc;
 
architecture dataflow of sc_corproc is
constant PipeLength : natural := 2*STAGE+2;
component p2r_cordic is
generic(
PIPELINE : integer := 15;
WIDTH : integer := 16);
port(
clk : in std_logic;
ena : in std_logic;
 
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0) := (others => '0');
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0)
);
end component p2r_cordic;
signal phase:signed( 19 downto 0 );
signal Xi,Yi:signed( WIDTH+7 downto 0 );
signal Xo,Yo:signed( WIDTH+7 downto 0 );
signal zeros:signed( 19-STAGE*2 downto 0 );
begin
Xi<= Xin(WIDTH+1)&Xin&"00000";
Yi<= Yin(WIDTH+1)&Yin&"00000";
zeros<=(others=>'0');
phase<="00"&Ain&zeros;
cos<=Xo(WIDTH+7)&Xo( WIDTH+7 downto 5 );
sin<=Yo(WIDTH+7)&Yo( WIDTH+7 downto 5 );
u1: p2r_cordic
generic map(PIPELINE => PipeLength, WIDTH => WIDTH+8)
port map(clk => clk, ena => ena, Xi => Xi, Yi=>Yi,Zi => phase, Xo => Xo, Yo => Yo);
end architecture dataflow;
/branches/avendor/ofdm.npl
0,0 → 1,52
JDF G
// Created by Project Navigator ver 1.0
PROJECT ofdm
DESIGN ofdm
DEVFAM spartan2
DEVFAMTIME 1145426085
DEVICE xc2s200
DEVICETIME 1145426085
DEVPKG pq208
DEVPKGTIME 1145425004
DEVSPEED -5
DEVSPEEDTIME 1145426085
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE modem.vhd
SOURCE ram.vhd
SOURCE mux.vhd
SOURCE rxmodem.vhd
SOURCE cfft.vhd
SOURCE input.vhd
SOURCE p2r_CordicPipe.vhd
SOURCE txmodem.vhd
SOURCE blockdram.vhd
SOURCE conj.vhd
SOURCE ofdm.vhd
SOURCE mulfactor.vhd
SOURCE counter.vhd
SOURCE div4limit.vhd
SOURCE cfft4.vhd
SOURCE inv_control.vhd
SOURCE ram_control.vhd
SOURCE rofactor.vhd
SOURCE mux_control.vhd
SOURCE starts.vhd
SOURCE txrx.vhd
SOURCE cfft_control.vhd
SOURCE io_control.vhd
SOURCE output.vhd
SOURCE p2r_cordic.vhd
SOURCE sc_corproc.vhd
[Normal]
p_xstVerilog2001=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, Normal
_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
[STRATEGY-LIST]
Normal=True
/branches/avendor/blockdram.vhd
0,0 → 1,68
---------------------------------------------------------------------------------------------------
--
-- Title : blockram
-- Design : cfft
-- Author : MENG Lin
-- email :
--
---------------------------------------------------------------------------------------------------
--
-- File : blockram.vhd
-- Generated : unknown
--
---------------------------------------------------------------------------------------------------
--
-- Description : Dual port ram
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
 
entity blockdram is
generic(
depth: natural;
Dwidth: natural;
Awidth: natural
);
port (
clkin : in std_logic;
wen : in std_logic;
addrin : in std_logic_vector(Awidth-1 downto 0);
din : in std_logic_vector(Dwidth-1 downto 0);
clkout : in std_logic;
addrout : in std_logic_vector(Awidth-1 downto 0);
dout : out std_logic_vector(Dwidth-1 downto 0));
end blockdram;
 
architecture blockdram of blockdram is
 
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
(Dwidth-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
--attribute syn_ramstyle of mem : signal is "block_ram";
 
signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
 
begin
wr: process( clkin )
begin
if rising_edge(clkin) then
if wen = '1' then
mem(conv_integer(addrin)) <= din;
end if;
end if;
end process wr;
 
rd: process( clkout )
begin
if rising_edge(clkout) then
addrb_reg <= addrout;
end if;
end process rd;
dout <= mem(conv_integer(addrb_reg));
end blockdram;
 

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