OpenCores
URL https://opencores.org/ocsvn/opb_psram_controller/opb_psram_controller/trunk

Subversion Repositories opb_psram_controller

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    from Rev 3 to Rev 4
    Reverse comparison

Rev 3 → Rev 4

/trunk/pcore/opb_psram_v1_00_a/hdl/vhdl/opb_psram.vhd
38,7 → 38,9
C_FAMILY : string := "spartan-3";
-- user generic
C_PSRAM_DQ_WIDTH : integer := 16;
C_PSRAM_A_WIDTH : integer := 23);
C_PSRAM_A_WIDTH : integer := 23;
C_PSRAM_LATENCY : integer range 0 to 7 := 3;
C_DRIVE_STRENGTH : integer range 0 to 3 := 1);
port
(
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
118,7 → 120,9
C_OPB_DWIDTH : integer;
C_FAMILY : string;
C_PSRAM_DQ_WIDTH : integer;
C_PSRAM_A_WIDTH : integer);
C_PSRAM_A_WIDTH : integer;
C_PSRAM_LATENCY : integer range 0 to 7 := 3;
C_DRIVE_STRENGTH : integer range 0 to 3 := 1);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
275,7 → 279,9
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_PSRAM_DQ_WIDTH => C_PSRAM_DQ_WIDTH,
C_PSRAM_A_WIDTH => C_PSRAM_A_WIDTH)
C_PSRAM_A_WIDTH => C_PSRAM_A_WIDTH,
C_PSRAM_LATENCY => C_PSRAM_LATENCY,
C_DRIVE_STRENGTH => C_DRIVE_STRENGTH)
port map (
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,

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