URL
https://opencores.org/ocsvn/opb_usblite/opb_usblite/trunk
Subversion Repositories opb_usblite
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Rev 3 → Rev 4
/opb_usblite/trunk/refdesign/system.mss
0,0 → 1,101
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PARAMETER VERSION = 2.2.0 |
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BEGIN OS |
PARAMETER OS_NAME = standalone |
PARAMETER OS_VER = 2.00.a |
PARAMETER PROC_INSTANCE = microblaze_0 |
PARAMETER STDIN = opb_usblite_0 |
PARAMETER STDOUT = opb_usblite_0 |
END |
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BEGIN PROCESSOR |
PARAMETER DRIVER_NAME = cpu |
PARAMETER DRIVER_VER = 1.12.b |
PARAMETER HW_INSTANCE = microblaze_0 |
PARAMETER COMPILER = mb-gcc |
PARAMETER ARCHIVER = mb-ar |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = dlmb_cntlr |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = ilmb_cntlr |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = lmb_bram |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = gpio |
PARAMETER DRIVER_VER = 2.13.a |
PARAMETER HW_INSTANCE = LEDs_8Bit |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = gpio |
PARAMETER DRIVER_VER = 2.13.a |
PARAMETER HW_INSTANCE = DIP_Switches_4Bit |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = gpio |
PARAMETER DRIVER_VER = 2.13.a |
PARAMETER HW_INSTANCE = Buttons_4Bit |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = mpmc |
PARAMETER DRIVER_VER = 3.01.a |
PARAMETER HW_INSTANCE = DDR_SDRAM |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = clock_generator_0 |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = uartlite |
PARAMETER DRIVER_VER = 1.14.a |
PARAMETER HW_INSTANCE = mdm_0 |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = proc_sys_reset_0 |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = opb_usblite |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = opb_usblite_0 |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = opbarb |
PARAMETER DRIVER_VER = 1.02.a |
PARAMETER HW_INSTANCE = opb_v20_0 |
END |
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BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = plbv46_opb_bridge_0 |
END |
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/opb_usblite/trunk/refdesign/system.xmp
0,0 → 1,29
#Please do not modify this file by hand |
XmpVersion: 11.4 |
VerMgmt: 11.4 |
IntStyle: default |
MHS File: system.mhs |
MSS File: system.mss |
Architecture: spartan3e |
Device: xc3s500e |
Package: fg320 |
SpeedGrade: -4 |
UserCmd1: |
UserCmd1Type: 0 |
UserCmd2: |
UserCmd2Type: 0 |
GenSimTB: 0 |
SdkExportBmmBit: 1 |
SdkExportDir: SDK/SDK_Export |
InsertNoPads: 0 |
WarnForEAArch: 1 |
HdlLang: VHDL |
SimModel: BEHAVIORAL |
UcfFile: data/system.ucf |
EnableParTimingError: 1 |
ShowLicenseDialog: 1 |
ICacheAddr: DDR_SDRAM, |
DCacheAddr: DDR_SDRAM, |
Processor: microblaze_0 |
BootLoop: 1 |
XmdStub: 0 |
/opb_usblite/trunk/refdesign/system.mhs
0,0 → 1,275
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# ############################################################################## |
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68 |
# Wed Jun 02 12:30:45 2010 |
# Target Board: Xilinx Spartan-3E Starter Board Rev D |
# Family: spartan3e |
# Device: XC3S500e |
# Package: FG320 |
# Speed Grade: -4 |
# Processor number: 1 |
# Processor 1: microblaze_0 |
# System clock frequency: 50.0 |
# Debug Interface: On-Chip HW Debug Module |
# ############################################################################## |
PARAMETER VERSION = 2.1.0 |
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PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7] |
PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3] |
PORT fpga_0_Buttons_4Bit_GPIO_IO_I_pin = fpga_0_Buttons_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3] |
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O |
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0] |
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0] |
PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0] |
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0] |
PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0] |
PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO |
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 |
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1 |
PORT opb_usblite_0_txdp_pin = opb_usblite_0_txdp, DIR = O |
PORT opb_usblite_0_txdn_pin = opb_usblite_0_txdn, DIR = O |
PORT opb_usblite_0_txdoe_pin = opb_usblite_0_txoe, DIR = O |
PORT opb_usblite_0_rxd_pin = opb_usblite_0_rxd, DIR = I |
PORT opb_usblite_0_rxdp_pin = opb_usblite_0_rxdp, DIR = I |
PORT opb_usblite_0_rxdn_pin = opb_usblite_0_rxdn, DIR = I |
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BEGIN microblaze |
PARAMETER INSTANCE = microblaze_0 |
PARAMETER C_AREA_OPTIMIZED = 1 |
PARAMETER C_INTERCONNECT = 1 |
PARAMETER C_DEBUG_ENABLED = 1 |
PARAMETER C_ICACHE_BASEADDR = 0x44000000 |
PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff |
PARAMETER C_CACHE_BYTE_SIZE = 8192 |
PARAMETER C_ICACHE_ALWAYS_USED = 1 |
PARAMETER C_DCACHE_BASEADDR = 0x44000000 |
PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff |
PARAMETER C_DCACHE_BYTE_SIZE = 8192 |
PARAMETER C_DCACHE_ALWAYS_USED = 1 |
PARAMETER HW_VER = 7.20.d |
PARAMETER C_USE_ICACHE = 1 |
PARAMETER C_USE_DCACHE = 1 |
BUS_INTERFACE DPLB = mb_plb |
BUS_INTERFACE IPLB = mb_plb |
BUS_INTERFACE DXCL = microblaze_0_DXCL |
BUS_INTERFACE IXCL = microblaze_0_IXCL |
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus |
BUS_INTERFACE DLMB = dlmb |
BUS_INTERFACE ILMB = ilmb |
PORT MB_RESET = mb_reset |
END |
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BEGIN plb_v46 |
PARAMETER INSTANCE = mb_plb |
PARAMETER HW_VER = 1.04.a |
PORT PLB_Clk = clk_50_0000MHz |
PORT SYS_Rst = sys_bus_reset |
END |
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BEGIN lmb_v10 |
PARAMETER INSTANCE = ilmb |
PARAMETER HW_VER = 1.00.a |
PORT LMB_Clk = clk_50_0000MHz |
PORT SYS_Rst = sys_bus_reset |
END |
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BEGIN lmb_v10 |
PARAMETER INSTANCE = dlmb |
PARAMETER HW_VER = 1.00.a |
PORT LMB_Clk = clk_50_0000MHz |
PORT SYS_Rst = sys_bus_reset |
END |
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BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = dlmb_cntlr |
PARAMETER HW_VER = 2.10.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x00001fff |
BUS_INTERFACE SLMB = dlmb |
BUS_INTERFACE BRAM_PORT = dlmb_port |
END |
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BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = ilmb_cntlr |
PARAMETER HW_VER = 2.10.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x00001fff |
BUS_INTERFACE SLMB = ilmb |
BUS_INTERFACE BRAM_PORT = ilmb_port |
END |
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BEGIN bram_block |
PARAMETER INSTANCE = lmb_bram |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE PORTA = ilmb_port |
BUS_INTERFACE PORTB = dlmb_port |
END |
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BEGIN xps_gpio |
PARAMETER INSTANCE = LEDs_8Bit |
PARAMETER C_ALL_INPUTS = 0 |
PARAMETER C_GPIO_WIDTH = 8 |
PARAMETER C_INTERRUPT_PRESENT = 0 |
PARAMETER C_IS_DUAL = 0 |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_BASEADDR = 0x81400000 |
PARAMETER C_HIGHADDR = 0x8140ffff |
BUS_INTERFACE SPLB = mb_plb |
PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin |
END |
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BEGIN xps_gpio |
PARAMETER INSTANCE = DIP_Switches_4Bit |
PARAMETER C_ALL_INPUTS = 1 |
PARAMETER C_GPIO_WIDTH = 4 |
PARAMETER C_INTERRUPT_PRESENT = 0 |
PARAMETER C_IS_DUAL = 0 |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_BASEADDR = 0x81420000 |
PARAMETER C_HIGHADDR = 0x8142ffff |
BUS_INTERFACE SPLB = mb_plb |
PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin |
END |
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BEGIN xps_gpio |
PARAMETER INSTANCE = Buttons_4Bit |
PARAMETER C_ALL_INPUTS = 1 |
PARAMETER C_GPIO_WIDTH = 4 |
PARAMETER C_INTERRUPT_PRESENT = 0 |
PARAMETER C_IS_DUAL = 0 |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_BASEADDR = 0x81440000 |
PARAMETER C_HIGHADDR = 0x8144ffff |
BUS_INTERFACE SPLB = mb_plb |
PORT GPIO_IO_I = fpga_0_Buttons_4Bit_GPIO_IO_I_pin |
END |
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BEGIN mpmc |
PARAMETER INSTANCE = DDR_SDRAM |
PARAMETER C_NUM_PORTS = 1 |
PARAMETER C_SPECIAL_BOARD = S3E_STKIT |
PARAMETER C_MEM_TYPE = DDR |
PARAMETER C_MEM_PARTNO = MT46V32M16-6 |
PARAMETER C_MEM_BANKADDR_WIDTH = 2 |
PARAMETER C_MEM_DATA_WIDTH = 16 |
PARAMETER C_MEM_DM_WIDTH = 2 |
PARAMETER C_MEM_DQS_WIDTH = 2 |
PARAMETER C_PIM0_BASETYPE = 1 |
PARAMETER C_XCL0_B_IN_USE = 1 |
PARAMETER HW_VER = 5.04.a |
PARAMETER C_MPMC_BASEADDR = 0x44000000 |
PARAMETER C_MPMC_HIGHADDR = 0x47ffffff |
BUS_INTERFACE XCL0 = microblaze_0_IXCL |
BUS_INTERFACE XCL0_B = microblaze_0_DXCL |
PORT MPMC_Clk0 = clk_100_0000MHzDCM0 |
PORT MPMC_Clk90 = clk_100_0000MHz90DCM0 |
PORT MPMC_Rst = sys_periph_reset |
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin |
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin |
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin |
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin |
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin |
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin |
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin |
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin |
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin |
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin |
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin |
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin |
PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin |
PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin |
END |
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BEGIN clock_generator |
PARAMETER INSTANCE = clock_generator_0 |
PARAMETER C_EXT_RESET_HIGH = 1 |
PARAMETER C_CLKIN_FREQ = 50000000 |
PARAMETER C_CLKOUT0_FREQ = 100000000 |
PARAMETER C_CLKOUT0_PHASE = 90 |
PARAMETER C_CLKOUT0_GROUP = DCM0 |
PARAMETER C_CLKOUT0_BUF = TRUE |
PARAMETER C_CLKOUT1_FREQ = 100000000 |
PARAMETER C_CLKOUT1_PHASE = 0 |
PARAMETER C_CLKOUT1_GROUP = DCM0 |
PARAMETER C_CLKOUT1_BUF = TRUE |
PARAMETER C_CLKOUT2_FREQ = 50000000 |
PARAMETER C_CLKOUT2_PHASE = 0 |
PARAMETER C_CLKOUT2_GROUP = NONE |
PARAMETER C_CLKOUT2_BUF = TRUE |
PARAMETER HW_VER = 3.02.a |
PARAMETER C_CLKOUT3_FREQ = 48000000 |
PARAMETER C_CLKOUT3_PHASE = 0 |
PARAMETER C_CLKOUT3_GROUP = NONE |
PARAMETER C_CLKOUT3_BUF = TRUE |
PORT CLKIN = dcm_clk_s |
PORT CLKOUT0 = clk_100_0000MHz90DCM0 |
PORT CLKOUT1 = clk_100_0000MHzDCM0 |
PORT CLKOUT2 = clk_50_0000MHz |
PORT RST = sys_rst_s |
PORT LOCKED = Dcm_all_locked |
PORT CLKOUT3 = clk_48_0000MHz |
END |
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BEGIN mdm |
PARAMETER INSTANCE = mdm_0 |
PARAMETER C_MB_DBG_PORTS = 1 |
PARAMETER C_USE_UART = 1 |
PARAMETER C_UART_WIDTH = 8 |
PARAMETER HW_VER = 1.00.g |
PARAMETER C_BASEADDR = 0x84400000 |
PARAMETER C_HIGHADDR = 0x8440ffff |
BUS_INTERFACE SPLB = mb_plb |
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus |
PORT Debug_SYS_Rst = Debug_SYS_Rst |
END |
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BEGIN proc_sys_reset |
PARAMETER INSTANCE = proc_sys_reset_0 |
PARAMETER C_EXT_RESET_HIGH = 1 |
PARAMETER HW_VER = 2.00.a |
PORT Slowest_sync_clk = clk_50_0000MHz |
PORT Ext_Reset_In = sys_rst_s |
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst |
PORT Dcm_locked = Dcm_all_locked |
PORT MB_Reset = mb_reset |
PORT Bus_Struct_Reset = sys_bus_reset |
PORT Peripheral_Reset = sys_periph_reset |
END |
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BEGIN opb_usblite |
PARAMETER INSTANCE = opb_usblite_0 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE SOPB = opb_v20_0 |
PORT txdp = opb_usblite_0_txdp |
PORT txdn = opb_usblite_0_txdn |
PORT txoe = opb_usblite_0_txoe |
PORT rxd = opb_usblite_0_rxd |
PORT rxdp = opb_usblite_0_rxdp |
PORT rxdn = opb_usblite_0_rxdn |
PORT USB_Clk = clk_48_0000MHz |
END |
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BEGIN opb_v20 |
PARAMETER INSTANCE = opb_v20_0 |
PARAMETER HW_VER = 1.10.c |
PORT OPB_Clk = clk_50_0000MHz |
PORT SYS_Rst = sys_bus_reset |
END |
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BEGIN plbv46_opb_bridge |
PARAMETER INSTANCE = plbv46_opb_bridge_0 |
PARAMETER HW_VER = 1.01.a |
PARAMETER C_RNG0_BASEADDR = 0xFFFF0000 |
PARAMETER C_RNG0_HIGHADDR = 0xFFFF7FFF |
BUS_INTERFACE SPLB = mb_plb |
BUS_INTERFACE MOPB = opb_v20_0 |
END |
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