Subversion Repositories opb_vga_char_display_nodac

/trunk/microblaze_functions.txt File deleted \ No newline at end of file

/trunk/s3e_vga_char_dev_v1_00_a/gpl.txt File deleted

/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/SVGA_DEFINES.v File deleted

/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v File deleted \ No newline at end of file

/trunk/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd File deleted

/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.pao File deleted

/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.mpd File deleted

/trunk/s3e_vga_char_dev_v1_00_a/data/_s3e_vga_char_dev_xst.prj File deleted

/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.scr File deleted

/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.prj File deleted

/trunk/s3e_vga_char_dev_v1_00_a/devl/README.txt File deleted

/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup

trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli (nonexistent) @@ -1,103 +0,0 @@ -NewProject(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise) -SetProperty(Device Family, virtex2p) -SetProperty(Device, xc2vp7) -SetProperty(Package, fg456) -SetProperty(Speed Grade, -6) -SetProperty(Top-Level Module Type, HDL) -SetProperty(Synthesis Tool, XST (VHDL/Verilog)) -SetProperty(Simulator, Modelsim-SE Mixed) -SetPreference(PathType, Absolute) -AddLibrary(s3e_vga_char_dev_v1_00_a, D:/custom_pulse_generator/standalone_pulse_generator/pcores, TRUE) -AddSource(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd, VHDL Module) -MoveToLibrary(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd, s3e_vga_char_dev_v1_00_a) -AddSource(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v, Verilog Module) -AddLibrary(proc_common_v2_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, proc_common_v2_00_a) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, proc_common_v2_00_a) -AddLibrary(interrupt_control_v1_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, interrupt_control_v1_00_a) -AddLibrary(wrpfifo_v1_01_b, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, wrpfifo_v1_01_b) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, wrpfifo_v1_01_b) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, wrpfifo_v1_01_b) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, wrpfifo_v1_01_b) -AddLibrary(rdpfifo_v1_01_b, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, rdpfifo_v1_01_b) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, rdpfifo_v1_01_b) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, rdpfifo_v1_01_b) -AddLibrary(opb_ipif_v3_01_c, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, opb_ipif_v3_01_c) -AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, VHDL Module) -MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, opb_ipif_v3_01_c) -CloseProject() Index: trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise (nonexistent)

trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore (nonexistent) @@ -1,1345 +0,0 @@ -# Project Navigator Project Restoration Script -# -# WARNING: Do not modify this file. Any alteration of this file is not -# supported and will likely cause project restoration to fail. The -# format and the contents will be modified without further notice. -# -# This script can be used to recreate the associated project. To use this script, -# source it in a Xilinx Tcl shell, such as xtclsh or the Project Navigator Tcl -# Shell tab, and call the 'restore' proc. Restore takes the project directory as -# an optional argument. Pass in the project directory if it is different than the -# current working directory, otherwise don't pass in anything. -# -# Example: -# In this example the project is in the directory "./projects/m_project_dir". -# -# source ./projects/m_project_dir/my_project.restore -# restore ./projects/m_project_dir -# -# Example: -# In this example the project is in the current working directory. -# -# source my_project.restore -# restore -# -# Note that restoring a project this way has the following limitations: -# - Process status will not be restored. -# - A root-level source will be set as "Top", even if a lower-level source had -# previously been set as "Top". -# - Sources with non-default Design View associations will revert to the default -# association. -# - Snapshots will not be restored. -# -# The project which failed to load will be backed up as .fail. -# Please open a Technical Support WebCase at -# www.xilinx.com/support/clearexpress/websupport.htm and submit this file, along -# with the project source files, for evaluation. -# -# Copyright 2007, Xilinx, Inc. - - -proc ERR { msg } { - puts "ERROR: $msg" -} - -proc WARN { msg } { - puts "WARNING: $msg" -} - -proc INFO { msg } { - puts "$msg" -} - -# Helper that returns 1 if the string is blank, otherwise 0. -proc IsBlank { str } { - if { [string length $str] == 0 } { - return 1 - } - return 0 -} - -# Helper for determining whether a value is 'NULL'. -# Returns 1 if the value is 0; returns 0 if the value is anything else. -proc IsNull { val } { - if { $val == 0 } { - return 1 - } - return 0 -} - -proc HandleException { script { msg "" } } { - set catch_result [catch { - uplevel 1 $script - } RESULT] - if {$catch_result} { - if {![IsBlank $msg]} { - ERR $msg - } - INFO "$RESULT" - INFO "$::errorInfo" - } -} - -# These two procs help to load shared libraries in a platform -# independent way. -proc _LoadLibrary {name} { - set libExt [info sharedlibextension] - set libFullName "$name$libExt" - HandleException { - load $libFullName - } "A problem occured loading library $libFullName." -} - -proc _LoadFactoryLibrary {Factory} { - HandleException { - Xilinx::Cit::FactoryLoad $Factory - } "A problem occured loading library $Factory." -} - -_LoadLibrary libCit_CoreStub -_LoadLibrary libPrjrep_CommonStub -_LoadFactoryLibrary libPrjrep_Common -_LoadLibrary libDpm_SupportStub -_LoadLibrary libDpm_PnfStub -_LoadLibrary libDpm_DefnDataStub -_LoadLibrary libDpm_DesignDataStub -_LoadLibrary libDpm_HdlStub -_LoadLibrary libPrjrep_RepositoryStub -_LoadLibrary libCitI_CoreStub -_LoadLibrary libHdcI_HdcHDProjectStub -_LoadLibrary libTcltaskI_TaskStub -_LoadLibrary libCommonI_CommonStub -_LoadFactoryLibrary libTcltask_Helpers -_LoadFactoryLibrary libHdcC_HDProject -_LoadLibrary libHdcI_HdcContainerStub - -# Helper to exectute code only when the (pointer) variable name is valid. -proc OnOkPtr { var_name script } { - if { [ uplevel info exists $var_name ] } { - upvar $var_name var - if { $var != 0 } { return [ uplevel $script ] } - } -} - -# Helper to exectute code only when the (pointer) variable name is 0. -proc OnNullPtr { var_name script } { - if { [ uplevel info exists $var_name ] } { - upvar $var_name var - if { $var == 0 } { return [ uplevel $script ] } - } -} - -# Helper to exectute code only when the value of variable name is 1. -proc OnSuccess { var_name script } { - if { $val != 0 } { return [ uplevel $script ] } -} - -# Helper to exectute code only when the value of variable name is 0. -proc OnFail { val script } { - if { $val != 1 } { return [ uplevel $script ] } -} - -# Helper to get a component interface. -proc GetInterface { iUnk id { name "" } } { - if {$iUnk == 0} { return 0 } - set iIface [ $iUnk GetInterface $id ] - OnNullPtr iIface { - if {![IsBlank $name]} { - ERR " Could not get the \"$name\" interface." - } - } - return $iIface -} - -# Helper to create a component and return one of its interfaces. -proc CreateComponent { compId ifaceId { name "" } } { - set iUnk [ ::Xilinx::Cit::FactoryCreate $compId ] - set iIface [ GetInterface $iUnk $ifaceId ] - OnNullPtr iIface { - if {![IsBlank $name]} { ERR "Could not create a \"$name\" component." } - } - return $iIface -} - -# Helper to release an object -proc Release { args } { - foreach iUnk $args { - set i_refcount [ GetInterface $iUnk $::xilinx::Prjrep::IRefCountID ] - OnNullPtr i_refcount { set i_refcount [ GetInterface $iUnk $::xilinx::CommonI::IRefCountID ] } - OnOkPtr i_refcount { $i_refcount Release } - } -} - -# Helper to loop over IIterator based pointers. -proc ForEachIterEle { _ele_var_name _iter script } { - if {$_iter == 0} { return 0 } - upvar $_ele_var_name ele - for { $_iter First } { ![ $_iter IsEnd ] } { $_iter Next } { - set ele [ $_iter CurrentItem ] - set returned_val [ uplevel $script ] - } -} - -# Helper to get the Tcl Project Manager, if possible. -proc GetTclProjectMgr { } { - set TclProjectMgrId "{7d528480-1196-4635-aba9-639446e4aa59}" - set iUnk [ Xilinx::CitP::CreateComponent $TclProjectMgrId ] - if {$iUnk == 0} { return 0 } - set iTclProjectMgr [ $iUnk GetInterface $::xilinx::TcltaskI::ITclProjectMgrID ] - OnNullPtr iTclProjectMgr { - ERR "Could not create a \"TclProjectMgr\" component." - } - return $iTclProjectMgr -} - -# Helper to get the current Tcl Project, if one is open. -proc GetCurrentTclProject { } { - set iTclProject 0 - set iTclProjectMgr [GetTclProjectMgr] - OnOkPtr iTclProjectMgr { - set errmsg "" - $iTclProjectMgr GetCurrentTclProject iTclProject errmsg - } - return $iTclProject -} - -# Helper to get the current HDProject, if one is open. -proc GetCurrentHDProject { } { - set iHDProject 0 - set iTclProjectMgr [GetTclProjectMgr] - set errmsg "" - OnOkPtr iTclProjectMgr { $iTclProjectMgr GetCurrentHDProject iHDProject errmsg } - OnNullPtr iHDProject { - ERR "Could not get the current HDProject." - } - return $iHDProject -} - -# Helper to create a Project Helper. -proc GetProjectHelper { } { - set ProjectHelperID "{0725c3d2-5e9b-4383-a7b6-a80c932eac21}" - set iProjHelper [CreateComponent $ProjectHelperID $::xilinx::Dpm::IProjectHelperID "Project Helper"] - return $iProjHelper -} - -# Helper to find out if a project is currently open. -# Returns 1 if a project is open, otherwise 0. -proc IsProjectOpen { } { - set iTclProject [GetCurrentTclProject] - set isOpen [expr {$iTclProject != 0}] - Release $iTclProject - return $isOpen -} - -# Helper to return the lock file for the specified project if there is one. -# Returns an empty string if there is no lock file on the specified project. -# This assumes that the project_file is in the current directory. -# It also assumes project_file does not have a path. -proc GetProjectLockFile { project_file } { - INFO "Checking for a lock file for \"$project_file\"." - set lock_file "__ISE_repository_${project_file}_.lock" - if { [ file isfile "$lock_file" ] } { - return $lock_file - } - return -} - -# Helper to move aside the project file. -# This assumes that the project_file is in the current directory. -proc MoveProject { project_file backup_file } { - INFO "Moving aside the project \"$project_file\" so that it can be recreated." - INFO "The project will be backed up as \"$backup_file\"." - if { ![ file isfile "$project_file" ] } { - WARN "Could not move \"$project_file\"; it does not exist or is not a file." - return 1 - } - file rename -force "$project_file" "$backup_file" - # We will need to bail if the project still exists. - if { [ file isfile "$project_file" ] } { - ERR "Could not remove \"$project_file\"; unable to recreate the project.." - return 0 - } - return 1 -} - -# Helper to open a project and return a project facilitator (pointer). -proc OpenFacilProject { project_name } { - # first make sure the tcl project mgr singleton exists - GetTclProjectMgr - # get a Project Helper and open the project. - set iProjHelper [GetProjectHelper] - if {$iProjHelper == 0} { return 0 } - set result [$iProjHelper Open $project_name] - OnFail $result { - if {$result == 576460769483292673} { - ERR "Could not open the project \"$project_name\" because it is locked." - } else { - ERR "Could not open the \"$project_name\" project." - } - Release $iProjHelper - set iProjHelper 0 - } - return $iProjHelper -} - -# Helper to close and release a project. -proc CloseFacilProject { iProjHelper } { - if {$iProjHelper == 0} { return } - $iProjHelper Close - Release $iProjHelper -} - -# Helper to get the Project from the Project Helper. -# Clients must release this. -proc GetProject { iProjHelper } { - if {$iProjHelper == 0} { return 0 } - set dpm_project 0 - $iProjHelper GetDpmProject dpm_project - set iProject [ GetInterface $dpm_project $xilinx::Dpm::IProjectID ] - OnNullPtr iProject { - ERR "Could not get the Project from the Project Helper." - } - return $iProject -} - -# Helper to get the File Manager from the Project Helper. -# Clients must release this. -proc GetFileManager { iProjHelper } { - set iProject [GetProject $iProjHelper] - set iFileMgr [ GetInterface $iProject $xilinx::Dpm::IFileManagerID ] - OnNullPtr iFileMgr { - ERR "Could not get the File Manager from the Project Helper." - } - # Don't release the project here, clients will release it - # when they release its IFileManager interface. - return $iFileMgr -} - -# Helper to get the Source Library Manager from the Project Helper. -# Clients must release this. -proc GetSourceLibraryManager { iProjHelper } { - set iProject [GetProject $iProjHelper] - set iSourceLibraryMgr [ GetInterface $iProject $xilinx::Dpm::ISourceLibraryManagerID ] - OnNullPtr iSourceLibraryMgr { - ERR "Could not get the Source Library Manager from the Project Helper." - } - # Don't release the project here, clients will release it - # when they release its IFileManager interface. - return $iSourceLibraryMgr -} - -# Helper to get the ProjSrcHelper from the Project Helper. -# Clients must NOT release this. -proc GetProjSrcHelper { iProjHelper } { - set iSrcHelper [ GetInterface $iProjHelper $::xilinx::Dpm::IProjSrcHelperID IProjSrcHelper ] - OnNullPtr iSrcHelper { - ERR "Could not get the ProjSrcHelper from the Project Helper." - } - return $iSrcHelper -} - -# Helper to get the ScratchPropertyManager from the Project Helper. -# Clients must NOT release this. -proc GetScratchPropertyManager { iProjHelper } { - set iPropTableFetch [ GetInterface $iProjHelper $xilinx::Dpm::IPropTableFetchID IPropTableFetch ] - set prop_table_comp 0 - OnOkPtr iPropTableFetch { - $iPropTableFetch GetPropTable prop_table_comp - } - set iScratch [ GetInterface $prop_table_comp $xilinx::Dpm::IScratchPropertyManagerID ] - OnNullPtr iScratch { - ERR "Could not get the Scratch Property Manager from the Project Helper." - } - return $iScratch -} - -# Helper to get the Design from the Project Helper. -# Clients must release this. -proc GetDesign { iProjHelper } { - set iProject [GetProject $iProjHelper] - set iDesign 0 - OnOkPtr iProject { $iProject GetDesign iDesign } - OnNullPtr iDesign { - ERR "Could not get the Design from the Project Helper." - } - Release $iProject - return $iDesign -} - -# Helper to get the Data Store from the Project Helper. -# Clients must NOT release this. -proc GetDataStore { iProjHelper } { - set iDesign [ GetDesign $iProjHelper] - set iDataStore 0 - OnOkPtr iDesign { $iDesign GetDataStore iDataStore } - OnNullPtr iDataStore { - ERR "Could not get the Data Store from the Project Helper." - } - Release $iDesign - return $iDataStore -} - -# Helper to get the View Manager from the Project Helper. -# Clients must NOT release this. -proc GetViewManager { iProjHelper } { - set iDesign [ GetDesign $iProjHelper] - set iViewMgr [ GetInterface $iDesign $xilinx::Dpm::IViewManagerID ] - OnNullPtr iViewMgr { - ERR "Could not get the View Manager from the Project Helper." - } - # Don't release the design here, clients will release it - # when they release its IViewManager interface. - return $iViewMgr -} - -# Helper to get the Property Manager from the Project Helper. -# Clients must release this. -proc GetPropertyManager { iProjHelper } { - set iDesign [ GetDesign $iProjHelper] - set iPropMgr 0 - OnOkPtr iDesign { $iDesign GetPropertyManager iPropMgr } - OnNullPtr iPropMgr { - ERR "Could not get the Property Manager from the Project Helper." - } - Release $iDesign - return $iPropMgr -} - -# Helper to find a property template, based on prop_name -# Clients must NOT release this. -proc GetPropertyTemplate { iProjHelper prop_name } { - set iPropTempl 0 - set iUnk 0 - set iDefdataId 0 - set iPropTemplStore 0 - set iDataStore [GetDataStore $iProjHelper] - OnOkPtr iDataStore { $iDataStore GetComponentByName $prop_name iUnk } - OnOkPtr iUnk { set iDefdataId [ GetInterface $iUnk $xilinx::Dpm::IDefDataIdID IDefDataId ] } - OnOkPtr iDefdataId { - set iPropTemplStore [ GetInterface $iDataStore $xilinx::Dpm::IPropertyTemplateStoreID IPropertyTemplateStore ] - } - OnOkPtr iPropTemplStore { $iPropTemplStore GetPropertyTemplate $iDefdataId iPropTempl } - OnNullPtr iPropTempl { - WARN "Could not get the property template for \"$prop_name\"." - } - return $iPropTempl -} - -# Helper to get a component's name. -proc GetName { iUnk } { - set name "" - set iName [ GetInterface $iUnk $xilinx::Prjrep::INameID IName ] - OnOkPtr iName { $iName GetName name } - return $name -} - -# Helper to get the name of a view's type. -proc GetViewTypeName { iView } { - set typeName "" - set iType 0 - set iDefdataType 0 - OnOkPtr iView { $iView GetType iType } - OnOkPtr iType { - set iDefdataType [ GetInterface $iType $xilinx::Dpm::IDefDataIdID IDefDataId ] - } - OnOkPtr iDefdataType { $iDefdataType GetID typeName } - return $typeName -} - -# Helper to find a view and return its context. -# Must clients release this? -proc GetViewContext { iProjHelper view_id view_name } { - # Simply return if the view_id or view_name is empty. - if { [IsBlank $view_id] || [IsBlank $view_name] } { return 0 } - set foundview 0 - set viewiter 0 - set iViewMgr [GetViewManager $iProjHelper] - OnOkPtr iViewMgr { $iViewMgr GetViews viewiter } - ForEachIterEle view $viewiter { - set typeName [GetViewTypeName $view] - set name [GetName $view] - if { [ string equal $name $view_name ] && [ string equal $view_id $typeName ] } { - set foundview $view - } - } - set context [ GetInterface $foundview $xilinx::Dpm::IPropertyContextID ] - OnNullPtr context { - WARN "Could not get the context for view \"$view_id\":\"$view_name\"." - } - return $context -} - -# Helper to get a string property instance from the property manager. -proc GetStringPropertyInstance { iProjHelper simple_id } { - set iPropMgr [GetPropertyManager $iProjHelper] - if {$iPropMgr == 0} { return 0 } - set iPropInst 0 - $iPropMgr GetStringProperty $simple_id iPropInst - OnNullPtr iPropInst { WARN "Could not get the string property instance $simple_id." } - Release $iPropMgr - return $iPropInst -} - -# Helper to get a property instance from the property manager. -proc GetPropertyInstance { iProjHelper view_name view_id prop_name } { - set iPropInst 0 - set iPropTempl [ GetPropertyTemplate $iProjHelper $prop_name ] - if {$iPropTempl == 0} { return 0 } - set context [ GetViewContext $iProjHelper $view_id $view_name ] - set iPropMgr [GetPropertyManager $iProjHelper] - if {$iPropMgr == 0} { return 0 } - $iPropMgr GetPropertyInstance $iPropTempl $context iPropInst - OnNullPtr iPropInst { - if { ![IsBlank $view_id] && ![IsBlank $view_name] } { - WARN "Could not get the context sensitive property instance $prop_name." - } else { - WARN "Could not get the property instance $prop_name." - } - } - Release $iPropMgr - return $iPropInst -} - -# Helper to store properties back into the property manager. -proc RestoreProcessProperties { iProjHelper process_props } { - INFO "Restoring process properties" - foreach { unused view_name view_id simple_id prop_name prop_val } $process_props { - set iPropInst 0 - if {![IsBlank $simple_id]} { - set iPropInst [ GetStringPropertyInstance $iProjHelper $simple_id ] - } else { - set iPropInst [ GetPropertyInstance $iProjHelper $view_name $view_id $prop_name ] - } - OnOkPtr iPropInst { - OnFail [ $iPropInst SetStringValue "$prop_val" ] { - WARN "Could not set the value of the $prop_name property to \"$prop_val\"." - } - } - Release $iPropInst - } -} - -# Helper to recreate partitions from the variable name with -# a list of instance names. -proc RestorePartitions { namelist } { - INFO "Restoring partitions." - set iHDProject [ GetCurrentHDProject ] - OnOkPtr iHDProject { - foreach name $namelist { - set iPartition [ $iHDProject CreatePartition "$name" ] - } - } -} - -# Helper to create and populate a library -# -proc CreateLibrary { iProjHelper libname filelist } { - - set iLibMgr [ GetSourceLibraryManager $iProjHelper ] - set iFileMgr [ GetFileManager $iProjHelper ] - - if {$iLibMgr == 0} { return 0 } - if {$iFileMgr == 0} { return 0 } - - $iLibMgr CreateSourceLibrary "libname" ilib - - OnOkPtr ilib { - foreach filename $filelist { - set argfile [ file normalize "$filename" ] - set found 0 - set fileiter 0 - $iFileMgr GetFiles fileiter - ForEachIterEle ifile $fileiter { - set path "" - set file "" - $ifile getPath path file - set currentfile [ file normalize [ file join "$path" "$file" ] ] - if { $currentfile == $argfile } { - set found 1 - $ilib AddFile ifile - break - } - } - OnNullPtr found { - WARN "Could not add the file \"$filename\" to the library \"$libname\"." - } - } - } -} - -# Helper to create source libraries and populate them. -proc RestoreSourceLibraries { iProjHelper libraries } { - INFO "Restoring source libraries." - foreach { libname filelist } $libraries { - CreateLibrary $iProjHelper "$libname" $filelist - } -} - -# Helper to add user files to the project using the PnF. -proc AddUserFiles { iProjHelper files } { - INFO "Adding User files." - set iconflict 0 - set iSrcHelper [ GetProjSrcHelper $iProjHelper ] - if {$iSrcHelper == 0} { return 0 } - foreach filename $files { - INFO "Adding the file \"$filename\" to the project." - set result [$iSrcHelper AddSourceFile "$filename" iconflict] - OnFail $result { - if {$result == 6} { - INFO "The file \"$filename\" is already in the project." - } else { - ERR "A problem occurred adding the file \"$filename\" to the project." - } - } - } -} - -# Helper to add files to the project and set their origination. -# Valid origination values are: -# 0 - User -# 1 - Generated -# 2 - Imported -# Files of origination "User" are added through the facilitator, -# otherwise they are added directly to the File Manager. -proc AddImportedFiles { iProjHelper files origination } { - switch $origination { - 0 { INFO "Adding User files." } - 1 { INFO "Adding Generated files." } - 2 { INFO "Adding Imported files." } - default { - ERR "Invalid parameter: origination was set to \"$origination\", but may only be 0, 1, or 2." - return 0 - } - } - set iFileMgr [ GetFileManager $iProjHelper ] - if {$iFileMgr == 0} { return 0 } - foreach filename $files { - set file_type 0 - set hdl_file 0 - set result [$iFileMgr AddFile "$filename" $file_type hdl_file] - OnFail $result { - if {$result == 6} { - INFO "The file \"$filename\" is already in the project." - } elseif { $hdl_file == 0 } { - ERR "A problem occurred adding the file \"$filename\" to the project." - } - } - OnOkPtr hdl_file { - set ifile [ GetInterface $hdl_file $xilinx::Dpm::IFileID IFile ] - OnOkPtr ifile { - set result [ $ifile SetOrigination $origination ] - if {$result != 1} { - ERR "A problem occurred setting the origination of \"$filename\" to \"$origination\"." - } - Release $ifile - } - } - } - return 1 -} - -proc RestoreProjectSettings { iProjHelper project_settings } { - INFO "Restoring device settings" - set iScratch [GetScratchPropertyManager $iProjHelper] - set iPropIter 0 - set iPropSet [ GetInterface $iScratch $xilinx::Dpm::IPropertyNodeSetID IPropertyNodeSet ] - OnOkPtr iPropSet { - $iPropSet GetIterator iPropIter - } - set index 0 - set lastindex [llength $project_settings] - ForEachIterEle prop_node $iPropIter { - set prop_instance 0 - $prop_node GetPropertyInstance prop_instance - if { $index < $lastindex } { - set argname [ lindex $project_settings $index ] - set argvalue [ lindex $project_settings [ expr $index + 1 ] ] - } else { - set argname {} - set argvalue {} - } - if { $prop_instance != 0 } { - set name {} - $prop_instance GetName name - if { [string equal $name $argname ] } { - $prop_instance SetStringValue $argvalue - incr index - incr index - } - } - Release $prop_instance - } - $iScratch Commit - # initialize - $iProjHelper Init -} - -# Helper to load a source control configuration from a stream -# and then store it back into an ise file. -proc RestoreSourceControlOptions { prjfile istream } { - INFO "Restoring source control options" - set config_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlConfigurationCompID ] - OnOkPtr config_comp { set ipersist [ $config_comp GetInterface $xilinx::Prjrep::IPersistID ] } - OnOkPtr config_comp { set igetopts [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IGetOptionsID ] } - set helper_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlHelpCompID ] - OnOkPtr helper_comp { set ihelper [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IHelperID ] } - OnOkPtr ipersist { $ipersist Load istream } - OnOkPtr ihelper { OnOkPtr igetopts { $ihelper SaveOptions $prjfile $igetopts } } - Release $helper_comp $config_comp -} - -# Call this proc to restore the ISE project. -proc restore { { project_dir "" } } { - set script_file "s3e_vga_char_dev.restore" - set project_file "s3e_vga_char_dev.ise" - set backup_file "s3e_vga_char_dev.fail" - set old_working_dir [pwd] - # Make sure a project isn't already open. - if {[IsProjectOpen]} { - ERR "The project must be closed before performing this operation." - cd $old_working_dir - return - } - # If a project directory was supplied, cd into it. - if {![IsBlank $project_dir]} { - cd $project_dir - } - # Make sure the project file exists. - if { ![ file isfile "$project_file" ] } { - ERR "Could not find the project file \"$project_file\". You must be in the project directory to perform this operation." - cd $old_working_dir - return - } - # Make sure the project isn't locked. - set lock_file [GetProjectLockFile $project_file] - if { ![IsBlank "$lock_file" ] } { - ERR "Could not restore the project \"$project_name\" because it is locked." - INFO "Please remove the lock file \"$lock_file\" and try again." - cd $old_working_dir - return - } - # Backup this script because it will be overwritten the next time - # the project is saved, which happens right after it is created! - file copy -force "$script_file" "${script_file}.last" - # Back up the project and remove the project file, since it can't be opened. - OnFail [ MoveProject "$project_file" "$backup_file" ] { - cd $old_working_dir - return - } - - # Open the project. - HandleException { - set iProjHelper [ OpenFacilProject "$project_file"] - } "A problem occurred while creating the project \"$project_file\"." - if {$iProjHelper == 0} { - cd $old_working_dir - return - } - INFO "Recreating project \"$project_file\"." - set project_settings { - "PROP_DevFamily" "Virtex2P" - "PROP_DevDevice" "xc2vp7" - "PROP_DevPackage" "fg456" - "PROP_DevSpeed" "-6" - "PROP_Top_Level_Module_Type" "HDL" - "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" - "PROP_Simulator" "Modelsim-SE Mixed" - "PROP_PreferredLanguage" "Verilog" - "PROP_Enable_Message_Capture" "true" - "PROP_Enable_Message_Filtering" "false" - "PROP_Enable_Incremental_Messaging" "false" - } - - HandleException { - RestoreProjectSettings $iProjHelper $project_settings - } "A problem occured while restoring project settings." - - set user_files { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" - "../../hdl/verilog/user_logic.v" - "../../hdl/vhdl/s3e_vga_char_dev.vhd"} - - HandleException { - AddUserFiles $iProjHelper $user_files - } "A problem occured while restoring user files." - - set imported_files {} - - set origination 2 - - HandleException { - AddImportedFiles $iProjHelper $imported_files $origination - } "A problem occured while restoring imported files." - - set process_props { - "A" "" "" "" "PROPEXT_SynthMultStyle_virtex2" "Auto" - "A" "" "" "" "PROPEXT_xilxBitgCfg_DCIUpdateMode_virtex2p" "As Required" - "A" "" "" "" "PROPEXT_xilxBitgCfg_TDO_virtex2p" "Float" - "A" "" "" "" "PROPEXT_xilxBitgStart_Clk_Done_virtex2p" "Default (4)" - "A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex2" "4" - "A" "" "" "" "PROPEXT_xilxSynthAddBufg_virtex2" "16" - "A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex2" "500" - "A" "" "" "" "PROP_CPLDFitkeepio" "false" - "A" "" "" "" "PROP_CompxlibAbelLib" "true" - "A" "" "" "" "PROP_CompxlibCPLDDetLib" "true" - "A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" "" - "A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX//" - "A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite" - "A" "" "" "" "PROP_CompxlibSimPath" "Search in Path" - "A" "" "" "" "PROP_CompxlibSimPrimatives" "true" - "A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true" - "A" "" "" "" "PROP_CurrentFloorplanFile" "" - "A" "" "" "" "PROP_DesignName" "s3e_vga_char_dev" - "A" "" "" "" "PROP_Dummy" "dum1" - "A" "" "" "" "PROP_EnableWYSIWYG" "None" - "A" "" "" "" "PROP_Enable_Incremental_Messaging" "false" - "A" "" "" "" "PROP_Enable_Message_Capture" "true" - "A" "" "" "" "PROP_Enable_Message_Filtering" "false" - "A" "" "" "" "PROP_FunctionBlockInputLimit" "38" - "A" "" "" "" "PROP_ISimLibSearchOrderFile" "" - "A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time" - "A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false" - "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false" - "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false" - "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false" - "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false" - "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false" - "A" "" "" "" "PROP_ISimUutInstName" "UUT" - "A" "" "" "" "PROP_ImpactProjectFile" "" - "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time" - "A" "" "" "" "PROP_ModelSimUseConfigName" "false" - "A" "" "" "" "PROP_Parse_Target" "synthesis" - "A" "" "" "" "PROP_PartitionCreateDelete" "" - "A" "" "" "" "PROP_PartitionForcePlacement" "" - "A" "" "" "" "PROP_PartitionForceSynth" "" - "A" "" "" "" "PROP_PartitionForceTranslate" "" - "A" "" "" "" "PROP_PlsClockEnable" "true" - "A" "" "" "" "PROP_PostTrceFastPath" "false" - "A" "" "" "" "PROP_PreTrceFastPath" "false" - "A" "" "" "" "PROP_SimDo" "true" - "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false" - "A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false" - "A" "" "" "" "PROP_SimModelOtherNetgenOpts" "" - "A" "" "" "" "PROP_SimModelRetainHierarchy" "true" - "A" "" "" "" "PROP_SimUseCustom_behav" "false" - "A" "" "" "" "PROP_SimUseCustom_postMap" "false" - "A" "" "" "" "PROP_SimUseCustom_postPar" "false" - "A" "" "" "" "PROP_SimUseCustom_postXlate" "false" - "A" "" "" "" "PROP_SynthCaseImplStyle" "None" - "A" "" "" "" "PROP_SynthDecoderExtract" "true" - "A" "" "" "" "PROP_SynthEncoderExtract" "Yes" - "A" "" "" "" "PROP_SynthExtractMux" "Yes" - "A" "" "" "" "PROP_SynthExtractRAM" "true" - "A" "" "" "" "PROP_SynthExtractROM" "true" - "A" "" "" "" "PROP_SynthFsmEncode" "Auto" - "A" "" "" "" "PROP_SynthLogicalShifterExtract" "true" - "A" "" "" "" "PROP_SynthOpt" "Speed" - "A" "" "" "" "PROP_SynthOptEffort" "Normal" - "A" "" "" "" "PROP_SynthResSharing" "true" - "A" "" "" "" "PROP_SynthShiftRegExtract" "true" - "A" "" "" "" "PROP_SynthXORCollapse" "true" - "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL" - "A" "" "" "" "PROP_UseDataGate" "true" - "A" "" "" "" "PROP_XPowerOptInputTclScript" "" - "A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default" - "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default" - "A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default" - "A" "" "" "" "PROP_XPowerOptOutputFile" "Default" - "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false" - "A" "" "" "" "PROP_XPowerOtherXPowerOpts" "" - "A" "" "" "" "PROP_XplorerMode" "Off" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq0" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq1" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq2" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq3" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq4" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_keySeq5" "None" - "A" "" "" "" "PROP_bitgen_Encrypt_startCBC" "" - "A" "" "" "" "PROP_bitgen_Encrypt_startKey" "None" - "A" "" "" "" "PROP_bitgen_otherCmdLineOptions" "" - "A" "" "" "" "PROP_cpldBestFit" "false" - "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source" - "A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" "" - "A" "" "" "" "PROP_fitGenSimModel" "false" - "A" "" "" "" "PROP_hprep6_autosig" "false" - "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" "" - "A" "" "" "" "PROP_ibiswriterEnableMultiLingualModel" "false" - "A" "" "" "" "PROP_ibiswriterShowAllModels" "false" - "A" "" "" "" "PROP_impactConfigFileName_CPLD" "" - "A" "" "" "" "PROP_mapUseRLOCConstraints" "true" - "A" "" "" "" "PROP_map_otherCmdLineOptions" "" - "A" "" "" "" "PROP_mpprRsltToCopy" "" - "A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true" - "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" "" - "A" "" "" "" "PROP_parUseTimingConstraints" "true" - "A" "" "" "" "PROP_par_otherCmdLineOptions" "" - "A" "" "" "" "PROP_primeCorrelateOutput" "false" - "A" "" "" "" "PROP_primeFlatternOutputNetlist" "false" - "A" "" "" "" "PROP_primeTopLevelModule" "" - "A" "" "" "" "PROP_primetimeBlockRamData" "" - "A" "" "" "" "PROP_taengine_otherCmdLineOptions" "" - "A" "" "" "" "PROP_xcpldFitDesInit" "Low" - "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32" - "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true" - "A" "" "" "" "PROP_xcpldFitDesSlew" "Fast" - "A" "" "" "" "PROP_xcpldFitDesTimingCst" "true" - "A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper" - "A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper" - "A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18" - "A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density" - "A" "" "" "" "PROP_xcpldFittimRptOption" "Summary" - "A" "" "" "" "PROP_xcpldUseGlobalClocks" "true" - "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true" - "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true" - "A" "" "" "" "PROP_xcpldUseLocConst" "Always" - "A" "" "" "" "PROP_xilxBitgCfg_Clk" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF" - "A" "" "" "" "PROP_xilxBitgCfg_DCMBandgap" "false" - "A" "" "" "" "PROP_xilxBitgCfg_DCMShutdown" "false" - "A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "false" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC" "true" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File" "false" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false" - "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false" - "A" "" "" "" "PROP_xilxBitgCfg_M0" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_M1" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_M2" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_PwrDown" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_Rate" "4" - "A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up" - "A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down" - "A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration" - "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK" - "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" - "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" - "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle" "Auto" - "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" - "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)" - "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" - "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" - "A" "" "" "" "PROP_xilxMapCoverMode" "Area" - "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false" - "A" "" "" "" "PROP_xilxMapPackRegInto" "For Inputs and Outputs" - "A" "" "" "" "PROP_xilxMapReplicateLogic" "true" - "A" "" "" "" "PROP_xilxMapReportDetail" "false" - "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false" - "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false" - "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true" - "A" "" "" "" "PROP_xilxNgdbldIOPads" "false" - "A" "" "" "" "PROP_xilxNgdbldMacro" "" - "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp" - "A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false" - "A" "" "" "" "PROP_xilxNgdbldUR" "" - "A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false" - "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" - "A" "" "" "" "PROP_xilxPARplacerCostTable" "1" - "A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None" - "A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None" - "A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route" - "A" "" "" "" "PROP_xilxPARuseBondedIO" "false" - "A" "" "" "" "PROP_xilxPostTrceAdvAna" "false" - "A" "" "" "" "PROP_xilxPostTrceRpt" "Error Report" - "A" "" "" "" "PROP_xilxPostTrceRptLimit" "3" - "A" "" "" "" "PROP_xilxPostTrceStamp" "" - "A" "" "" "" "PROP_xilxPostTrceTSIFile" "" - "A" "" "" "" "PROP_xilxPostTrceUncovPath" "" - "A" "" "" "" "PROP_xilxPreTrceAdvAna" "false" - "A" "" "" "" "PROP_xilxPreTrceRpt" "Error Report" - "A" "" "" "" "PROP_xilxPreTrceRptLimit" "3" - "A" "" "" "" "PROP_xilxPreTrceUncovPath" "" - "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" - "A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets" - "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No" - "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" - "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" - "A" "" "" "" "PROP_xilxSynthRegBalancing" "No" - "A" "" "" "" "PROP_xilxSynthRegDuplication" "true" - "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" - "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "Off" - "A" "" "" "" "PROP_xstAsynToSync" "false" - "A" "" "" "" "PROP_xstAutoBRAMPacking" "false" - "A" "" "" "" "PROP_xstBRAMUtilRatio" "100" - "A" "" "" "" "PROP_xstBusDelimiter" "<>" - "A" "" "" "" "PROP_xstCase" "Maintain" - "A" "" "" "" "PROP_xstCoresSearchDir" "" - "A" "" "" "" "PROP_xstCrossClockAnalysis" "false" - "A" "" "" "" "PROP_xstEquivRegRemoval" "true" - "A" "" "" "" "PROP_xstFsmStyle" "LUT" - "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" - "A" "" "" "" "PROP_xstGenericsParameters" "" - "A" "" "" "" "PROP_xstHierarchySeparator" "/" - "A" "" "" "" "PROP_xstIniFile" "" - "A" "" "" "" "PROP_xstLibSearchOrder" "" - "A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false" - "A" "" "" "" "PROP_xstPackIORegister" "Auto" - "A" "" "" "" "PROP_xstReadCores" "true" - "A" "" "" "" "PROP_xstSlicePacking" "true" - "A" "" "" "" "PROP_xstSliceUtilRatio" "100" - "A" "" "" "" "PROP_xstTristate2Logic" "Yes" - "A" "" "" "" "PROP_xstUseClockEnable" "Yes" - "A" "" "" "" "PROP_xstUseSyncReset" "Yes" - "A" "" "" "" "PROP_xstUseSyncSet" "Yes" - "A" "" "" "" "PROP_xstUseSynthConstFile" "true" - "A" "" "" "" "PROP_xstUserCompileList" "" - "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" - "A" "" "" "" "PROP_xstVerilog2001" "true" - "A" "" "" "" "PROP_xstVerilogMacros" "" - "A" "" "" "" "PROP_xstWorkDir" "./xst" - "A" "" "" "" "PROP_xstWriteTimingConstraints" "false" - "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" - "A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" - "A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimIncreCompilation" "true" - "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" - "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" - "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimValueRangeCheck" "false" - "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_AnnotatedResultsModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_BehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false" - "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" - "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Post-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimIncreCompilation" "true" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDir" "" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimValueRangeCheck" "false" - "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Structural" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPost-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimIncreCompilation" "true" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimValueRangeCheck" "false" - "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false" - "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_UpdatedBitstream" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false" - "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" - "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" - "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" - "A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" - "B" "" "" "" "PROP_AutoGenFile" "false" - "B" "" "" "" "PROP_DevFamily" "Virtex2P" - "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" - "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" "" - "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" "" - "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" "" - "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" "" - "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" "" - "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" "" - "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false" - "B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false" - "B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true" - "B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true" - "B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true" - "B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true" - "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tb" "false" - "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tbw" "false" - "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tb" "false" - "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tbw" "false" - "B" "" "" "" "PROP_MapEffortLevel" "Medium" - "B" "" "" "" "PROP_MapLogicOptimization" "false" - "B" "" "" "" "PROP_MapPlacerCostTable" "1" - "B" "" "" "" "PROP_MapRegDuplication" "false" - "B" "" "" "" "PROP_ModelSimConfigName" "Default" - "B" "" "" "" "PROP_ModelSimDataWin" "false" - "B" "" "" "" "PROP_ModelSimListWin" "false" - "B" "" "" "" "PROP_ModelSimProcWin" "false" - "B" "" "" "" "PROP_ModelSimSignalWin" "true" - "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" - "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" - "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" - "B" "" "" "" "PROP_ModelSimSourceWin" "false" - "B" "" "" "" "PROP_ModelSimStructWin" "true" - "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT" - "B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT" - "B" "" "" "" "PROP_ModelSimVarsWin" "false" - "B" "" "" "" "PROP_ModelSimWaveWin" "true" - "B" "" "" "" "PROP_SimCustom_behav" "" - "B" "" "" "" "PROP_SimCustom_postMap" "" - "B" "" "" "" "PROP_SimCustom_postPar" "" - "B" "" "" "" "PROP_SimCustom_postXlate" "" - "B" "" "" "" "PROP_SimGenVcdFile" "false" - "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" - "B" "" "" "" "PROP_SimSyntax" "93" - "B" "" "" "" "PROP_SimUseExpDeclOnly" "true" - "B" "" "" "" "PROP_SimUserCompileList_behav" "" - "B" "" "" "" "PROP_Simulator" "Modelsim-SE Mixed" - "B" "" "" "" "PROP_SynthConstraintsFile" "" - "B" "" "" "" "PROP_SynthMuxStyle" "Auto" - "B" "" "" "" "PROP_SynthRAMStyle" "Auto" - "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false" - "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" - "B" "" "" "" "PROP_XPowerOptUseTimeBased" "false" - "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt" "false" - "B" "" "" "" "PROP_impactBaud" "None" - "B" "" "" "" "PROP_impactConfigMode" "None" - "B" "" "" "" "PROP_impactPort" "None" - "B" "" "" "" "PROP_parGenAsyDlyRpt" "false" - "B" "" "" "" "PROP_parGenClkRegionRpt" "false" - "B" "" "" "" "PROP_parGenSimModel" "false" - "B" "" "" "" "PROP_parGenTimingRpt" "true" - "B" "" "" "" "PROP_parMpprNodelistFile" "" - "B" "" "" "" "PROP_parMpprParIterations" "3" - "B" "" "" "" "PROP_parMpprResultsDirectory" "" - "B" "" "" "" "PROP_parMpprResultsToSave" "" - "B" "" "" "" "PROP_parPowerReduction" "false" - "B" "" "" "" "PROP_vcom_otherCmdLineOptions" "" - "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" - "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" - "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" - "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" - "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false" - "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false" - "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false" - "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false" - "B" "" "" "" "PROP_xilxMapPackfactor" "100" - "B" "" "" "" "PROP_xilxPAReffortLevel" "Standard" - "B" "" "" "" "PROP_xstMoveFirstFfStage" "true" - "B" "" "" "" "PROP_xstMoveLastFfStage" "true" - "B" "" "" "" "PROP_xstROMStyle" "Auto" - "B" "" "" "" "PROP_xstSafeImplement" "No" - "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "" - "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "" - "C" "" "" "" "PROP_AceActiveName" "" - "C" "" "" "" "PROP_CompxlibLang" "All" - "C" "" "" "" "PROP_CompxlibSmartModels" "true" - "C" "" "" "" "PROP_CompxlibUpdateIniForSmartModel" "false" - "C" "" "" "" "PROP_DevDevice" "xc2vp7" - "C" "" "" "" "PROP_DevFamilyPMName" "virtex2p" - "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns" - "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns" - "C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns" - "C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns" - "C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd" - "C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd" - "C" "" "" "" "PROP_MapExtraEffort" "None" - "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" - "C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps" - "C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1" - "C" "" "" "" "PROP_bitgen_Encrypt_key0" "" - "C" "" "" "" "PROP_bitgen_Encrypt_key1" "" - "C" "" "" "" "PROP_bitgen_Encrypt_key2" "" - "C" "" "" "" "PROP_bitgen_Encrypt_key3" "" - "C" "" "" "" "PROP_bitgen_Encrypt_key4" "" - "C" "" "" "" "PROP_bitgen_Encrypt_key5" "" - "C" "" "" "" "PROP_bitgen_Encrypt_keyFile" "" - "C" "" "" "" "PROP_impactConfigFileName" "" - "C" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" "false" - "C" "" "" "" "PROP_xilxPARextraEffortLevel" "None" - "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" - "D" "" "" "" "PROP_CompxlibUniSimLib" "true" - "D" "" "" "" "PROP_DevPackage" "fg456" - "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" - "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2" "false" - "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" "false" - "D" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex2" "false" - "E" "" "" "" "PROP_DevSpeed" "-6" - "E" "" "" "" "PROP_PreferredLanguage" "Verilog" - "F" "" "" "" "PROP_ChangeDevSpeed" "-6" - "F" "" "" "" "PROP_SimModelTarget" "Verilog" - "F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog" - "F" "" "" "" "PROP_xilxPostTrceSpeed" "-6" - "F" "" "" "" "PROP_xilxPreTrceSpeed" "-6" - "G" "" "" "" "PROP_PostSynthSimModelName" "_synthesis.v" - "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" - "G" "" "" "" "PROP_SimModelGenArchOnly" "false" - "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" - "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" - "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false" - "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" - "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" - "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" - "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" - "G" "" "" "" "PROP_SimModelRenTopLevMod" "" - "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "_map.v" - "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "_timesim.v" - "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_tbwPostMapTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_tbwPostParTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_tbwPostXlateTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "_translate.v" - "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" - "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false" - "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" - "H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "" - "H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "" - "H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "" - "H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "" - "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" - "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT" - "I" "" "" "" "PROP_SimModelRocPulseWidth" "100" - "I" "" "" "" "PROP_SimModelTocPulseWidth" "0"} - - HandleException { - RestoreProcessProperties $iProjHelper $process_props - } "A problem occured while restoring process properties." - - # library names and their members - set libraries { - "interrupt_control_v1_00_a" - { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" - } - "opb_ipif_v3_01_c" - { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" - } - "proc_common_v2_00_a" - { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" - } - "rdpfifo_v1_01_b" - { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" - } - "s3e_vga_char_dev_v1_00_a" - { - "../../hdl/vhdl/s3e_vga_char_dev.vhd" - } - "wrpfifo_v1_01_b" - { - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" - "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" - } - } - - HandleException { - RestoreSourceLibraries $iProjHelper $libraries - } "A problem occured while restoring source libraries." - - # Close the facilitator project. - CloseFacilProject $iProjHelper - - # Open the restored project in the user's client application, - # which will either be the Projnav GUI or xtclsh. - project open $project_file - - # Let the user know about the backed up project file. - INFO "The project \"$project_file\" was backed up as \"$backup_file\"." - INFO "Please open a Technical Support WebCase at" - INFO "www.xilinx.com/support/clearexpress/websupport.htm" - INFO "and submit this file, along with the project source files, for evaluation." -} - Index: trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log (nonexistent) @@ -1,346 +0,0 @@ - ----------------------------------------------------------------------------- --- Design Analysis -- ----------------------------------------------------------------------------- -Analyze pcore s3e_vga_char_dev ... - - ----------------------------------------------------------------------------- --- File Generation -- ----------------------------------------------------------------------------- -Creating HDL source directory ... -Generating top peripheral VHDL template ... -Generating stub user logic Verilog template ... -HDL templates successfully generated ... -Creating data directory ... -Generating XPS inteface files ... -WARNING:HDLParsers:3497 - Ignoring Verilog File - "D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev - _v1_00_a/data/../hdl/verilog/user_logic.v" -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut -4.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_b -it.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit -.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.v -hd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count -er.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_ -pkg.vhd" in Library proc_common_v2_00_a. -Package compiled. -Package body compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count -er_top.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_t -op.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd -" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit. -vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd -" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" -in Library proc_common_v2_00_a. -Package compiled. -Package body compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" -in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" -in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vh -d" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_sel -ect.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.v -hd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" -in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd -" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg -.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.v -hd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter -.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd -" in Library proc_common_v2_00_a. -Package compiled. -Package body compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.v -hd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_ -cntr_ai.vhd" in Library proc_common_v2_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" -in Library wrpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd. -vhd" in Library rdpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl. -vhd" in Library rdpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr. -vhd" in Library wrpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl. -vhd" in Library wrpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_c -ntr.vhd" in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" -in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vh -d" in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" -in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr. -vhd" in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_ -reg.vhd" in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" -in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interr -upt_control.vhd" in Library interrupt_control_v1_00_a. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" -in Library wrpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" -in Library rdpfifo_v1_01_b. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" in -Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" -in Library opb_ipif_v3_01_c. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file -"D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1 -_00_a/data/../hdl/vhdl/s3e_vga_char_dev.vhd" in Library -s3e_vga_char_dev_v1_00_a. -Entity compiled. -Entity (Architecture ) compiled. - - -Analyzing HDL attributes ... -INFO:MDT - IPTYPE set to value : PERIPHERAL -INFO:MDT - IMP_NETLIST set to value : TRUE -INFO:MDT - HDL set to value : VHDL -WARNING:MDT - Unable to delete temparary XST project file - D:\custom_pulse_generator\standalone_pulse_generator\pcores\s3e_vga_char_dev_ - v1_00_a\data\_s3e_vga_char_dev_xst.prj : 13 -XPS interface files successfully generated ... -Creating development directory ... -Generating command option file ... -Generating readme file ... -Development misc files successfully generated ... -Creating projnav directory ... -Generating ProjNav support files ... -ProjNav support files successfully generated ... -Creating synthesis directory ... -Generating XST synthesis support files ... -XST synthesis support files successfully generated ... -No BFM simulation files will be generated at this time ... -Creating software driver data directory ... -Generating software driver XPS interface (mdd/tcl) files ... -Software driver data definition file (.mdd) successfully generated ... -Software driver data generation file (.tcl) successfully generated ... -Creating software driver src directory ... -Generating software driver template files ... -Software driver compile file (Makefile) successfully generated ... -output user slave register(s) offset to software driver header ... -output IPIF software reset/module identification register(s) offset to software -driver header ... -Software driver header file (.h) successfully generated ... -Software driver source file (.c) successfully generated ... -Software driver SelfTest file (.c) successfully generated ... -Software driver template files successfully generated ... - ----------------------------------------------------------------------------- --- Final Report -- ----------------------------------------------------------------------------- -Thank you for using Create and Import Peripheral Wizard! Please find your -peripheral hardware templates under -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a and peripheral software templates under -D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 -_00_a respectively. - -Peripheral Summary: - - top name : s3e_vga_char_dev - version : 1.00.a - type : OPB slave - features : slave attachement - mir/rst register - user s/w registers - -Address Block Summary: - - user logic slv : C_BASEADDR + 0x00000000 - : C_BASEADDR + 0x000000FF - mir/reset reg : C_BASEADDR + 0x00000100 - : C_BASEADDR + 0x000001FF - -File Summary - - - HDL source - -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a/hdl - top entity : vhdl/s3e_vga_char_dev.vhd - user logic : verilog/user_logic.v - - - XPS interface - -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a/data - mpd : s3e_vga_char_dev_v2_1_0.mpd - pao : s3e_vga_char_dev_v2_1_0.pao - - - ISE project - -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a/devl/projnav - ise project : s3e_vga_char_dev.npl - cli command : s3e_vga_char_dev.cli - - - - XST synthesis - -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a/devl/synthesis - xst script : s3e_vga_char_dev_xst.scr - xst project : s3e_vga_char_dev_xst.prj - - - Misc file - -D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ -00_a/devl - help : README.txt - option : ipwiz.opt - log : ipwiz.log - - - Driver source - -D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 -_00_a/src - makefile : Makefile - header : s3e_vga_char_dev.h - source : s3e_vga_char_dev.c - selftest : s3e_vga_char_dev_selftest.c - - - Driver interface - -D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 -_00_a/data - mdd : s3e_vga_char_dev_v2_1_0.mdd - tcl : s3e_vga_char_dev_v2_1_0.tcl - - Index: trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt (nonexistent) @@ -1,11 +0,0 @@ --batch --create s3e_vga_char_dev --ver 1.00.a --dir "D:\custom_pulse_generator\standalone_pulse_generator" --lang verilog --bus opb s --rstmir --regn 2 32 --xps --ise --driver Index: trunk/s3e_vga_char_dev_v1_00_a.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/s3e_vga_char_dev_v1_00_a.zip =================================================================== --- trunk/s3e_vga_char_dev_v1_00_a.zip (revision 3) +++ trunk/s3e_vga_char_dev_v1_00_a.zip (nonexistent)

trunk/s3e_vga_char_dev_v1_00_a.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: opb_vga_char_display_nodac/trunk/microblaze_functions.txt =================================================================== --- opb_vga_char_display_nodac/trunk/microblaze_functions.txt (nonexistent) +++ opb_vga_char_display_nodac/trunk/microblaze_functions.txt (revision 4) @@ -0,0 +1,55 @@ + #define VGA_LINES_PER_ROW 75 + unsigned char vga_current_line = 0; + unsigned char vga_current_row = 0; + unsigned char VGAcolor; + + PutVGAChar(unsigned char CH, char color) + { + VGAcolor = color; + WriteVGAData(CH); + } + + WriteVGAData(Data) + { + Xuint32 VGAAddress; + + VGAAddress = (((vga_current_row * VGA_LINES_PER_ROW) + vga_current_line) << 18); // Character location + VGAAddress = VGAAddress + (VGAcolor << 14); // 7 is the foreground color white + VGAAddress = VGAAddress + (Data << 6); // The character to write + WriteREG (XPAR_S3E_VGA_CHAR_DEV_0_BASEADDR,USER,0x0,VGAAddress); + + vga_current_line = vga_current_line + 1; + if (vga_current_line > VGA_LINES_PER_ROW) { + vga_current_line = 0; + vga_current_row = vga_current_row + 1; + } + } + + WriteVGAString(char*STR, char color) + { + int i=0; + Xuint32 VGAAddress; + + while (STR[i]!='\0') + { + VGAcolor = color; + WriteVGAData(STR[i]); + i++; + } + VGAcolor = color; + WriteVGAData(0x20); + } + + //---------------------------------------------------------------------------------- + // + // Colors are controlled through the lower four bits of the color parameter. + // Bit zero (the LSB) controls the red portion of the color (on or off). + // Bit one controls green, bit two controls blue. + // Bit three, if set, inverts the character. + // + //---------------------------------------------------------------------------------- + + // Example Call: + vga_current_row = 0; + vga_current_line = 0; + WriteVGAString("Testing VGA Generator Core",0x7); // White, noninverted \ No newline at end of file Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/gpl.txt =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/gpl.txt (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/gpl.txt (revision 4) @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v (revision 4) @@ -0,0 +1,2488 @@ +`include "SVGA_DEFINES.v" + +//---------------------------------------------------------------------------- +// user_logic.v - module +//---------------------------------------------------------------------------- +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +//---------------------------------------------------------------------------- +// Filename: user_logic.v +// Version: 1.00.a +// Description: User logic module. +// Date: Wed Sep 12 16:22:49 2007 (by Create and Import Peripheral Wizard) +// Verilog Standard: Verilog-2001 +//---------------------------------------------------------------------------- +// Naming Conventions: +// active low signals: "*_n" +// clock signals: "clk", "clk_div#", "clk_#x" +// reset signals: "rst", "rst_n" +// generics: "C_*" +// user defined types: "*_TYPE" +// state machine next state: "*_ns" +// state machine current state: "*_cs" +// combinatorial signals: "*_com" +// pipelined or register delay signals: "*_d#" +// counter signals: "*cnt*" +// clock enable signals: "*_ce" +// internal version of output port: "*_i" +// device pins: "*_pin" +// ports: "- Names begin with Uppercase" +// processes: "*_PROCESS" +// component instantiations: "I_<#|FUNC>" +//---------------------------------------------------------------------------- + +module user_logic +( + // -- ADD USER PORTS BELOW THIS LINE --------------- + // --USER ports added here + fifty_clock_in, + VGA_HSYNCH, + VGA_VSYNCH, + VGA_OUT_RED, + VGA_OUT_GREEN, + VGA_OUT_BLUE, + // -- ADD USER PORTS ABOVE THIS LINE --------------- + + // -- DO NOT EDIT BELOW THIS LINE ------------------ + // -- Bus protocol ports, do not add to or delete + Bus2IP_Clk, // Bus to IP clock + Bus2IP_Reset, // Bus to IP reset + Bus2IP_Data, // Bus to IP data bus for user logic + Bus2IP_BE, // Bus to IP byte enables for user logic + Bus2IP_RdCE, // Bus to IP read chip enable for user logic + Bus2IP_WrCE, // Bus to IP write chip enable for user logic + IP2Bus_Data, // IP to Bus data bus for user logic + IP2Bus_Ack, // IP to Bus acknowledgement + IP2Bus_Retry, // IP to Bus retry response + IP2Bus_Error, // IP to Bus error response + IP2Bus_ToutSup // IP to Bus timeout suppress + // -- DO NOT EDIT ABOVE THIS LINE ------------------ +); // user_logic + +// -- ADD USER PARAMETERS BELOW THIS LINE ------------ +// --USER parameters added here +// -- ADD USER PARAMETERS ABOVE THIS LINE ------------ + +// -- DO NOT EDIT BELOW THIS LINE -------------------- +// -- Bus protocol parameters, do not add to or delete +parameter C_DWIDTH = 32; +parameter C_NUM_CE = 2; +// -- DO NOT EDIT ABOVE THIS LINE -------------------- + +// -- ADD USER PORTS BELOW THIS LINE ----------------- +// --USER ports added here +input fifty_clock_in; +output VGA_HSYNCH; +output VGA_VSYNCH; +output VGA_OUT_RED; +output VGA_OUT_GREEN; +output VGA_OUT_BLUE; +// -- ADD USER PORTS ABOVE THIS LINE ----------------- + +// -- DO NOT EDIT BELOW THIS LINE -------------------- +// -- Bus protocol ports, do not add to or delete +input Bus2IP_Clk; +input Bus2IP_Reset; +input [0 : C_DWIDTH-1] Bus2IP_Data; +input [0 : C_DWIDTH/8-1] Bus2IP_BE; +input [0 : C_NUM_CE-1] Bus2IP_RdCE; +input [0 : C_NUM_CE-1] Bus2IP_WrCE; +output [0 : C_DWIDTH-1] IP2Bus_Data; +output IP2Bus_Ack; +output IP2Bus_Retry; +output IP2Bus_Error; +output IP2Bus_ToutSup; +// -- DO NOT EDIT ABOVE THIS LINE -------------------- + +//---------------------------------------------------------------------------- +// Implementation +//---------------------------------------------------------------------------- + + // --USER nets declarations added here, as needed for user logic + + // Nets for user logic slave model s/w accessible register example + reg [0 : C_DWIDTH-1] slv_reg0; + reg [0 : C_DWIDTH-1] slv_reg1; + wire [0 : 1] slv_reg_write_select; + wire [0 : 1] slv_reg_read_select; + reg [0 : C_DWIDTH-1] slv_ip2bus_data; + wire slv_read_ack; + wire slv_write_ack; + integer byte_index, bit_index; + + // --USER logic implementation added here + + // ------------------------------------------------------ + // Example code to read/write user logic slave model s/w accessible registers + // + // Note: + // The example code presented here is to show you one way of reading/writing + // software accessible registers implemented in the user logic slave model. + // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond + // to one software accessible register by the top level template. For example, + // if you have four 32 bit software accessible registers in the user logic, you + // are basically operating on the following memory mapped registers: + // + // Bus2IP_WrCE or Memory Mapped + // Bus2IP_RdCE Register + // "1000" C_BASEADDR + 0x0 + // "0100" C_BASEADDR + 0x4 + // "0010" C_BASEADDR + 0x8 + // "0001" C_BASEADDR + 0xC + // + // ------------------------------------------------------ + + assign + slv_reg_write_select = Bus2IP_WrCE[0:1], + slv_reg_read_select = Bus2IP_RdCE[0:1], + slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1], + slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1]; + + // implement slave model register(s) + always @( posedge Bus2IP_Clk ) + begin: SLAVE_REG_WRITE_PROC + + if ( Bus2IP_Reset == 1 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + end + else + case ( slv_reg_write_select ) + 2'b10 : + for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 ) + if ( Bus2IP_BE[byte_index] == 1 ) + for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) + slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; + 2'b01 : + for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 ) + if ( Bus2IP_BE[byte_index] == 1 ) + for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) + slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; + default : ; + endcase + + end // SLAVE_REG_WRITE_PROC + + // implement slave model register read mux + always @( slv_reg_read_select or slv_reg0 or slv_reg1 ) + begin: SLAVE_REG_READ_PROC + + case ( slv_reg_read_select ) + 2'b10 : slv_ip2bus_data <= slv_reg0; + 2'b01 : slv_ip2bus_data <= slv_reg1; + default : slv_ip2bus_data <= 0; + endcase + + end // SLAVE_REG_READ_PROC + + // ------------------------------------------------------------ + // Example code to drive IP to Bus signals + // ------------------------------------------------------------ + + assign IP2Bus_Data = slv_ip2bus_data; + assign IP2Bus_Ack = slv_write_ack || slv_read_ack; + assign IP2Bus_Error = 0; + assign IP2Bus_Retry = 0; + assign IP2Bus_ToutSup = 0; + + S3E_VGA_CHAR_DEVICE S3E_VGA_CHAR_DEVICE(.SYSTEM_CLOCK(fifty_clock_in), .VGA_HSYNCH(VGA_HSYNCH), + .VGA_VSYNCH(VGA_VSYNCH), .VGA_OUT_RED(VGA_OUT_RED), .VGA_OUT_GREEN(VGA_OUT_GREEN), + .VGA_OUT_BLUE(VGA_OUT_BLUE), .address(slv_reg0[0:13]), .character(slv_reg0[14:25]), .loadit(1)); + +endmodule + +//------------------------------------------------------------------------ + +module S3E_VGA_CHAR_DEVICE +( +SYSTEM_CLOCK, + +VGA_HSYNCH, +VGA_VSYNCH, +VGA_OUT_RED, +VGA_OUT_GREEN, +VGA_OUT_BLUE, + +address, +character, +loadit +); + +input SYSTEM_CLOCK; // 100MHz LVTTL SYSTEM CLOCK + +output VGA_HSYNCH; // horizontal sync for the VGA output connector +output VGA_VSYNCH; // vertical sync for the VGA output connector +output VGA_OUT_RED; // RED DAC data +output VGA_OUT_GREEN; // GREEN DAC data +output VGA_OUT_BLUE; // BLUE DAC data + +input [13:0] address; +input [11:0] character; +input loadit; + +wire system_clock_buffered; // buffered SYSTEM CLOCK +wire pixel_clock; // generated from SYSTEM CLOCK +wire reset; // reset asserted when DCMs are NOT LOCKED + +wire vga_red_data; // red video data +wire vga_green_data; // green video data +wire vga_blue_data; // blue video data + +// internal video timing signals +wire h_synch; // horizontal synch for VGA connector +wire v_synch; // vertical synch for VGA connector +wire blank; // composite blanking +wire [10:0] pixel_count; // bit mapped pixel position within the line +wire [9:0] line_count; // bit mapped line number in a frame lines within the frame +wire [2:0] subchar_pixel; // pixel position within the character +wire [2:0] subchar_line; // identifies the line number within a character block +wire [6:0] char_column; // character number on the current line +wire [6:0] char_line; // line number on the screen + +// instantiate the character generator +CHAR_DISPLAY CHAR_DISPLAY +( +char_column, +char_line, +subchar_line, +subchar_pixel, +pixel_clock, +reset, +vga_red_data, +vga_green_data, +vga_blue_data, +address, +character, +loadit +); + +// instantiate the clock generation module +CLOCK_GEN CLOCK_GEN +( +SYSTEM_CLOCK, +system_clock_buffered, +pixel_clock, +reset +); + +// instantiate the video timing generator +SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION +( +pixel_clock, +reset, +h_synch, +v_synch, +blank, +pixel_count, +line_count, +subchar_pixel, +subchar_line, +char_column, +char_line +); + +// instantiate the video output mux +VIDEO_OUT VIDEO_OUT +( +pixel_clock, +reset, +vga_red_data, +vga_green_data, +vga_blue_data, +h_synch, +v_synch, +blank, + +VGA_HSYNCH, +VGA_VSYNCH, +VGA_OUT_RED, +VGA_OUT_GREEN, +VGA_OUT_BLUE +); + +endmodule // MAIN + +//--------------------------------------------------------- + +module CHAR_DISPLAY +( +char_column, +char_line, +subchar_line, +subchar_pixel, +pixel_clock, +reset, +vga_red_data, +vga_green_data, +vga_blue_data, +address, +character, +loadit +); + +input [6:0] char_column; // character number on the current line +input [6:0] char_line; // line number on the screen +input [2:0] subchar_line; // the line number within a character block 0-8 +input [2:0] subchar_pixel; // the pixel number within a character block 0-8 +input pixel_clock; +input reset; +output vga_red_data; +output vga_green_data; +output vga_blue_data; + +input [13:0] address; +input [11:0] character; +input loadit; + +//// Label Definitions //// + +// Note: all labels must match their defined length--shorter labels will be padded with solid blocks, +// and longer labels will be truncated + +wire write_enable; // character memory is written to on a clock rise when high +assign write_enable = loadit; + +// The character write address +reg [13:0] char_addr; + +//wire [13:0] my_char_read_addr = {char_line[6:0], char_column[6:0]}; +//wire [13:0] my_char_read_addr = {char_line[6:0], char_column[5:0]}; +wire [13:0] my_char_read_addr = (char_line[6:0] * 75) + char_column[6:0]; + +wire pixel_on; // high => output foreground color, low => output background color +reg [13:0] char_write_data; // the data that will be written to character memory at the clock rise +reg char_addr_is_0; + +reg [3:0] hex; // the 4 bit value to be converted into ASCII +wire [7:0] ascii; // the result of the conversion to ASCII +integer i, ii; // iterators + +wire fore_red; +wire fore_green; +wire fore_blue; +wire back_red; +wire back_green; +wire back_blue; + +// write the appropriate character data to memory +always @ (char_line or char_column) begin + char_write_data <= character; + char_addr <= address[13:0]; +end + + +wire background_red; // the red component of the background color +wire background_green; // the green component of the background color +wire background_blue; // the blue component of the background color +wire foreground_red; // the red component of the foreground color +wire foreground_green; // the green component of the foreground color +wire foreground_blue; // the blue component of the foreground color + +// use the result of the character generator module to choose between the foreground and background color +assign vga_red_data = (pixel_on) ? foreground_red : background_red; +assign vga_green_data = (pixel_on) ? foreground_green : background_green; +assign vga_blue_data = (pixel_on) ? foreground_blue : background_blue; + +assign foreground_red = (back_red) ? 0 : fore_red; // If the invert signal is 1, then foreground is 0 +assign foreground_green = (back_red) ? 0 : fore_green; +assign foreground_blue = (back_red) ? 0 : fore_blue; + +assign background_red = (back_red) ? fore_red : 0; // If invert is 1, then the background is the values passed +assign background_green = (back_red) ? fore_green : 0; +assign background_blue = (back_red) ? fore_blue : 0; + +// the character generator block includes the character RAM +// and the character generator ROM +CHAR_GEN CHAR_GEN +( +reset, // reset signal +char_addr, // write address +char_write_data, // write data +write_enable, // write enable +pixel_clock, // write clock +my_char_read_addr,// read address of current character +subchar_line, // current line of pixels within current character +subchar_pixel, // current column of pixels withing current character +pixel_clock, // read clock +pixel_on, // read data +fore_red, +fore_green, +fore_blue, +back_red, +back_green, +back_blue +); + +endmodule //CHAR_DISPLAY + +//------------------------------------------------------- + +module CHAR_GEN( +// control +reset, +// write side +char_write_addr, +char_write_data, +char_write_enable, +char_write_clock, +// read side +char_address, +subchar_line, +subchar_pixel, +pixel_clock, +pixel_on, + +fore_red, +fore_green, +fore_blue, +back_red, +back_green, +back_blue +); + +input pixel_clock; +input reset; +input [2:0] subchar_line; // line number within 8 line block +input [13:0] char_address; // character address "0" is upper left character +input [2:0] subchar_pixel; // pixel position within 8 pixel block +input [13:0] char_write_addr; +input [11:0] char_write_data; +input char_write_enable; +input char_write_clock; +output pixel_on; + +output fore_red; +output fore_green; +output fore_blue; +output back_red; +output back_green; +output back_blue; + +reg latch_data; +reg latch_low_data; +reg shift_high; +reg shift_low; +reg [3:0] latched_low_char_data; +reg [7:0] latched_char_data; +reg pixel_on; + +wire [11:0] ascii_code; +wire [10:0] chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]}; +wire [7:0] char_gen_rom_data; + +// instantiate the CHARACTER RAM +CHAR_RAM CHAR_RAM +( +char_write_clock, +char_write_enable, +char_write_addr, +char_write_data, + +pixel_clock, +char_address, +ascii_code +); + +//assign back_red = ascii_code[10]; +//assign back_green = ascii_code[9]; +//assign back_blue = ascii_code[8]; + +//assign back_red = 0; +assign back_green = 0; +assign back_blue = 0; + +assign fore_red = ascii_code[8]; +assign fore_green = ascii_code[9]; +assign fore_blue = ascii_code[10]; +assign back_red = ascii_code[11]; + +// instantiate the character generator ROM +CHAR_GEN_ROM CHAR_GEN_ROM +( +pixel_clock, +chargen_rom_address, +char_gen_rom_data +); + +// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM +always @ (posedge pixel_clock or posedge reset)begin + if (reset) begin + latch_data <= 1'b0; + end + else if (subchar_pixel == 3'b110) begin + latch_data <= 1'b1; + end + else if (subchar_pixel == 3'b111) begin + latch_data <= 1'b0; + end + end + +always @ (posedge pixel_clock or posedge reset)begin + if (reset) begin + latch_low_data <= 1'b0; + end + else if (subchar_pixel == 3'b010) begin + latch_low_data <= 1'b1; + end + else if (subchar_pixel == 3'b011) begin + latch_low_data <= 1'b0; + end + end + +always @ (posedge pixel_clock or posedge reset)begin + if (reset) begin + shift_high <= 1'b1; + end + else if (subchar_pixel == 3'b011) begin + shift_high <= 1'b0; + end + else if (subchar_pixel == 3'b111) begin + shift_high <= 1'b1; + end + end + +always @ (posedge pixel_clock or posedge reset)begin + if (reset) begin + shift_low <= 1'b0; + end + else if (subchar_pixel == 3'b011) begin + shift_low <= 1'b1; + end + else if (subchar_pixel == 3'b111) begin + shift_low <= 1'b0; + end + end + +// serialize the CHARACTER MODE data +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + begin + pixel_on = 1'b0; + latched_low_char_data = 4'h0; + latched_char_data = 8'h00; + end + + else if (shift_high) + begin + pixel_on = latched_char_data [7]; + latched_char_data [7] = latched_char_data [6]; + latched_char_data [6] = latched_char_data [5]; + latched_char_data [5] = latched_char_data [4]; + latched_char_data [4] = latched_char_data [7]; + if(latch_low_data) begin + latched_low_char_data [3:0] = latched_char_data [3:0]; + end + else begin + latched_low_char_data [3:0] = latched_low_char_data [3:0]; + end + end + + else if (shift_low) + begin + pixel_on = latched_low_char_data [3]; + latched_low_char_data [3] = latched_low_char_data [2]; + latched_low_char_data [2] = latched_low_char_data [1]; + latched_low_char_data [1] = latched_low_char_data [0]; + latched_low_char_data [0] = latched_low_char_data [3]; + if (latch_data) begin + latched_char_data [7:0] = char_gen_rom_data[7:0]; + end + else begin + latched_char_data [7:0] = latched_char_data [7:0]; + end + end + else + begin + latched_low_char_data [3:0] = latched_low_char_data [3:0]; + latched_char_data [7:0] = latched_char_data [7:0]; + pixel_on = pixel_on; + end + end + +endmodule //CHAR_GEN + +//-------------------------------------------------------------- + +/* +------------------------------------------- +Code 00h defines a solid block +Codes 01h-04h define block graphics +Codes 05h-1Fh define line graphics +Codes 20h-7Eh define the ASCII characters +Code 7Fh defines a hash pattern +Codes 80h-FFh user defined characters +------------------------------------------- +*/ + +module CHAR_GEN_ROM +( +pixel_clock, +address, +data +); + +input pixel_clock; +input [10:0] address; +output reg [7:0] data; + +always @(posedge pixel_clock) begin + case(address) + + //// Solid Block //// + + // 00h: solid block + 11'h000: data <= 8'hFF; + 11'h001: data <= 8'hFF; + 11'h002: data <= 8'hFF; + 11'h003: data <= 8'hFF; + 11'h004: data <= 8'hFF; + 11'h005: data <= 8'hFF; + 11'h006: data <= 8'hFF; + 11'h007: data <= 8'hFF; + + //// Block graphics //// + + // 01h: Left block up, right block down + 11'h008: data <= 8'hF0; + 11'h009: data <= 8'hF0; + 11'h00A: data <= 8'hF0; + 11'h00B: data <= 8'hF0; + 11'h00C: data <= 8'h0F; + 11'h00D: data <= 8'h0F; + 11'h00E: data <= 8'h0F; + 11'h00F: data <= 8'h0F; + // 02h: Left block down, right block up + 11'h010: data <= 8'h0F; + 11'h011: data <= 8'h0F; + 11'h012: data <= 8'h0F; + 11'h013: data <= 8'h0F; + 11'h014: data <= 8'hF0; + 11'h015: data <= 8'hF0; + 11'h016: data <= 8'hF0; + 11'h017: data <= 8'hF0; + // 03h: Both blocks down + 11'h018: data <= 8'h00; + 11'h019: data <= 8'h00; + 11'h01A: data <= 8'h00; + 11'h01B: data <= 8'h00; + 11'h01C: data <= 8'hFF; + 11'h01D: data <= 8'hFF; + 11'h01E: data <= 8'hFF; + 11'h01F: data <= 8'hFF; + // 04h: Both blocks up + 11'h020: data <= 8'hFF; + 11'h021: data <= 8'hFF; + 11'h022: data <= 8'hFF; + 11'h023: data <= 8'hFF; + 11'h024: data <= 8'h00; + 11'h025: data <= 8'h00; + 11'h026: data <= 8'h00; + 11'h027: data <= 8'h00; + + //// Line Graphics //// + + // 05h: corner upper left + 11'h028: data <= 8'hFF; + 11'h029: data <= 8'h80; + 11'h02A: data <= 8'h80; + 11'h02B: data <= 8'h80; + 11'h02C: data <= 8'h80; + 11'h02D: data <= 8'h80; + 11'h02E: data <= 8'h80; + 11'h02F: data <= 8'h80; + // 06h: corner upper right + 11'h030: data <= 8'hFF; + 11'h031: data <= 8'h01; + 11'h032: data <= 8'h01; + 11'h033: data <= 8'h01; + 11'h034: data <= 8'h01; + 11'h035: data <= 8'h01; + 11'h036: data <= 8'h01; + 11'h037: data <= 8'h01; + // 07h: corner lower left + 11'h038: data <= 8'h80; + 11'h039: data <= 8'h80; + 11'h03A: data <= 8'h80; + 11'h03B: data <= 8'h80; + 11'h03C: data <= 8'h80; + 11'h03D: data <= 8'h80; + 11'h03E: data <= 8'h80; + 11'h03F: data <= 8'hFF; + // 08h: corner lower right + 11'h040: data <= 8'h01; + 11'h041: data <= 8'h01; + 11'h042: data <= 8'h01; + 11'h043: data <= 8'h01; + 11'h044: data <= 8'h01; + 11'h045: data <= 8'h01; + 11'h046: data <= 8'h01; + 11'h047: data <= 8'hFF; + // 09h: cross junction + 11'h048: data <= 8'h10; + 11'h049: data <= 8'h10; + 11'h04A: data <= 8'h10; + 11'h04B: data <= 8'hFF; + 11'h04C: data <= 8'h10; + 11'h04D: data <= 8'h10; + 11'h04E: data <= 8'h10; + 11'h04F: data <= 8'h10; + // 0Ah: "T" junction + 11'h050: data <= 8'hFF; + 11'h051: data <= 8'h10; + 11'h052: data <= 8'h10; + 11'h053: data <= 8'h10; + 11'h054: data <= 8'h10; + 11'h055: data <= 8'h10; + 11'h056: data <= 8'h10; + 11'h057: data <= 8'h10; + // 0Bh: "T" juntion rotated 90 clockwise + 11'h058: data <= 8'h01; + 11'h059: data <= 8'h01; + 11'h05A: data <= 8'h01; + 11'h05B: data <= 8'hFF; + 11'h05C: data <= 8'h01; + 11'h05D: data <= 8'h01; + 11'h05E: data <= 8'h01; + 11'h05F: data <= 8'h01; + // 0Ch: "T" juntion rotated 180 + 11'h060: data <= 8'h10; + 11'h061: data <= 8'h10; + 11'h062: data <= 8'h10; + 11'h063: data <= 8'h10; + 11'h064: data <= 8'h10; + 11'h065: data <= 8'h10; + 11'h066: data <= 8'h10; + 11'h067: data <= 8'hFF; + // 0Dh: "T" junction rotated 270 clockwise + 11'h068: data <= 8'h80; + 11'h069: data <= 8'h80; + 11'h06A: data <= 8'h80; + 11'h06B: data <= 8'hFF; + 11'h06C: data <= 8'h80; + 11'h06D: data <= 8'h80; + 11'h06E: data <= 8'h80; + 11'h06F: data <= 8'h80; + // 0Eh: arrow pointing right + 11'h070: data <= 8'h08; + 11'h071: data <= 8'h04; + 11'h072: data <= 8'h02; + 11'h073: data <= 8'hFF; + 11'h074: data <= 8'h02; + 11'h075: data <= 8'h04; + 11'h076: data <= 8'h08; + 11'h077: data <= 8'h00; + // 0Fh: arrow pointing left + 11'h078: data <= 8'h10; + 11'h079: data <= 8'h20; + 11'h07A: data <= 8'h40; + 11'h07B: data <= 8'hFF; + 11'h07C: data <= 8'h40; + 11'h07D: data <= 8'h20; + 11'h07E: data <= 8'h10; + 11'h07F: data <= 8'h00; + // 10h: first (top) horizontal line + 11'h080: data <= 8'hFF; + 11'h081: data <= 8'h00; + 11'h082: data <= 8'h00; + 11'h083: data <= 8'h00; + 11'h084: data <= 8'h00; + 11'h085: data <= 8'h00; + 11'h086: data <= 8'h00; + 11'h087: data <= 8'h00; + // 11h: second horizontal line + 11'h088: data <= 8'h00; + 11'h089: data <= 8'hFF; + 11'h08A: data <= 8'h00; + 11'h08B: data <= 8'h00; + 11'h08C: data <= 8'h00; + 11'h08D: data <= 8'h00; + 11'h08E: data <= 8'h00; + 11'h08F: data <= 8'h00; + // 12h: third horizontal line + 11'h090: data <= 8'h00; + 11'h091: data <= 8'h00; + 11'h092: data <= 8'hFF; + 11'h093: data <= 8'h00; + 11'h094: data <= 8'h00; + 11'h095: data <= 8'h00; + 11'h096: data <= 8'h00; + 11'h097: data <= 8'h00; + // 13h: fourth horizontal line + 11'h098: data <= 8'h00; + 11'h099: data <= 8'h00; + 11'h09A: data <= 8'h00; + 11'h09B: data <= 8'hFF; + 11'h09C: data <= 8'h00; + 11'h09D: data <= 8'h00; + 11'h09E: data <= 8'h00; + 11'h09F: data <= 8'h00; + // 14h: fifth horizontal line + 11'h0A0: data <= 8'h00; + 11'h0A1: data <= 8'h00; + 11'h0A2: data <= 8'h00; + 11'h0A3: data <= 8'h00; + 11'h0A4: data <= 8'hFF; + 11'h0A5: data <= 8'h00; + 11'h0A6: data <= 8'h00; + // 15h: sixth horizontal line + 11'h0A7: data <= 8'h00; + 11'h0A8: data <= 8'h00; + 11'h0A9: data <= 8'h00; + 11'h0AA: data <= 8'h00; + 11'h0AB: data <= 8'h00; + 11'h0AC: data <= 8'h00; + 11'h0AD: data <= 8'hFF; + 11'h0AE: data <= 8'h00; + 11'h0AF: data <= 8'h00; + // 16h: seventh horizontal line + 11'h0B0: data <= 8'h00; + 11'h0B1: data <= 8'h00; + 11'h0B2: data <= 8'h00; + 11'h0B3: data <= 8'h00; + 11'h0B4: data <= 8'h00; + 11'h0B5: data <= 8'h00; + 11'h0B6: data <= 8'hFF; + 11'h0B7: data <= 8'h00; + // 17h: eighth (bottom) horizontal line + 11'h0B8: data <= 8'h00; + 11'h0B9: data <= 8'h00; + 11'h0BA: data <= 8'h00; + 11'h0BB: data <= 8'h00; + 11'h0BC: data <= 8'h00; + 11'h0BD: data <= 8'h00; + 11'h0BE: data <= 8'h00; + 11'h0BF: data <= 8'hFF; + // 18h: first (left) vertical line + 11'h0C0: data <= 8'h80; + 11'h0C1: data <= 8'h80; + 11'h0C2: data <= 8'h80; + 11'h0C3: data <= 8'h80; + 11'h0C4: data <= 8'h80; + 11'h0C5: data <= 8'h80; + 11'h0C6: data <= 8'h80; + 11'h0C7: data <= 8'h80; + // 19h: second vertical line + 11'h0C8: data <= 8'h40; + 11'h0C9: data <= 8'h40; + 11'h0CA: data <= 8'h40; + 11'h0CB: data <= 8'h40; + 11'h0CC: data <= 8'h40; + 11'h0CD: data <= 8'h40; + 11'h0CE: data <= 8'h40; + 11'h0CF: data <= 8'h40; + // 1Ah: third vertical line + 11'h0D0: data <= 8'h20; + 11'h0D1: data <= 8'h20; + 11'h0D2: data <= 8'h20; + 11'h0D3: data <= 8'h20; + 11'h0D4: data <= 8'h20; + 11'h0D5: data <= 8'h20; + 11'h0D6: data <= 8'h20; + 11'h0D7: data <= 8'h20; + // 1Bh: fourth vertical line + 11'h0D8: data <= 8'h10; + 11'h0D9: data <= 8'h10; + 11'h0DA: data <= 8'h10; + 11'h0DB: data <= 8'h10; + 11'h0DC: data <= 8'h10; + 11'h0DD: data <= 8'h10; + 11'h0DE: data <= 8'h10; + 11'h0DF: data <= 8'h10; + // 1Ch: fifth vertical line + 11'h0E0: data <= 8'h08; + 11'h0E1: data <= 8'h08; + 11'h0E2: data <= 8'h08; + 11'h0E3: data <= 8'h08; + 11'h0E4: data <= 8'h08; + 11'h0E5: data <= 8'h08; + 11'h0E6: data <= 8'h08; + 11'h0E7: data <= 8'h08; + // 1Dh: sixth vertical line + 11'h0E8: data <= 8'h04; + 11'h0E9: data <= 8'h04; + 11'h0EA: data <= 8'h04; + 11'h0EB: data <= 8'h04; + 11'h0EC: data <= 8'h04; + 11'h0ED: data <= 8'h04; + 11'h0EE: data <= 8'h04; + 11'h0EF: data <= 8'h04; + // 1Eh: seventh vertical line + 11'h0F0: data <= 8'h02; + 11'h0F1: data <= 8'h02; + 11'h0F2: data <= 8'h02; + 11'h0F3: data <= 8'h02; + 11'h0F4: data <= 8'h02; + 11'h0F5: data <= 8'h02; + 11'h0F6: data <= 8'h02; + 11'h0F7: data <= 8'h02; + // 1Fh: eighth (right) vertical line + 11'h0F8: data <= 8'h01; + 11'h0F9: data <= 8'h01; + 11'h0FA: data <= 8'h01; + 11'h0FB: data <= 8'h01; + 11'h0FC: data <= 8'h01; + 11'h0FD: data <= 8'h01; + 11'h0FE: data <= 8'h01; + 11'h0FF: data <= 8'h01; + + //// ASCII Characters //// + + // 20h: space + 11'h100: data <= 8'h00; + 11'h101: data <= 8'h00; + 11'h102: data <= 8'h00; + 11'h103: data <= 8'h00; + 11'h104: data <= 8'h00; + 11'h105: data <= 8'h00; + 11'h106: data <= 8'h00; + 11'h107: data <= 8'h00; + // 21h: ! + 11'h108: data <= 8'h10; + 11'h109: data <= 8'h10; + 11'h10A: data <= 8'h10; + 11'h10B: data <= 8'h10; + 11'h10C: data <= 8'h00; + 11'h10D: data <= 8'h00; + 11'h10E: data <= 8'h10; + 11'h10F: data <= 8'h00; + // 22h: " + 11'h110: data <= 8'h28; + 11'h111: data <= 8'h28; + 11'h112: data <= 8'h28; + 11'h113: data <= 8'h00; + 11'h114: data <= 8'h00; + 11'h115: data <= 8'h00; + 11'h116: data <= 8'h00; + 11'h117: data <= 8'h00; + // 23h: # + 11'h118: data <= 8'h28; + 11'h119: data <= 8'h28; + 11'h11A: data <= 8'h7C; + 11'h11B: data <= 8'h28; + 11'h11C: data <= 8'h7C; + 11'h11D: data <= 8'h28; + 11'h11E: data <= 8'h28; + 11'h11F: data <= 8'h00; + // 24h: $ + 11'h120: data <= 8'h10; + 11'h121: data <= 8'h3C; + 11'h122: data <= 8'h50; + 11'h123: data <= 8'h38; + 11'h124: data <= 8'h14; + 11'h125: data <= 8'h78; + 11'h126: data <= 8'h10; + 11'h127: data <= 8'h00; + // 25h: % + 11'h128: data <= 8'h60; + 11'h129: data <= 8'h64; + 11'h12A: data <= 8'h08; + 11'h12B: data <= 8'h10; + 11'h12C: data <= 8'h20; + 11'h12D: data <= 8'h46; + 11'h12E: data <= 8'h06; + 11'h12F: data <= 8'h00; + // 26h: & + 11'h130: data <= 8'h30; + 11'h131: data <= 8'h48; + 11'h132: data <= 8'h50; + 11'h133: data <= 8'h20; + 11'h134: data <= 8'h54; + 11'h135: data <= 8'h48; + 11'h136: data <= 8'h34; + 11'h137: data <= 8'h00; + // 27h: ' + 11'h138: data <= 8'h30; + 11'h139: data <= 8'h10; + 11'h13A: data <= 8'h20; + 11'h13B: data <= 8'h00; + 11'h13C: data <= 8'h00; + 11'h13D: data <= 8'h00; + 11'h13E: data <= 8'h00; + 11'h13F: data <= 8'h00; + // 28h: ( + 11'h140: data <= 8'h08; + 11'h141: data <= 8'h10; + 11'h142: data <= 8'h20; + 11'h143: data <= 8'h20; + 11'h144: data <= 8'h20; + 11'h145: data <= 8'h10; + 11'h146: data <= 8'h08; + 11'h147: data <= 8'h00; + // 29h: ) + 11'h148: data <= 8'h20; + 11'h149: data <= 8'h10; + 11'h14A: data <= 8'h08; + 11'h14B: data <= 8'h08; + 11'h14C: data <= 8'h08; + 11'h14D: data <= 8'h10; + 11'h14E: data <= 8'h20; + 11'h14F: data <= 8'h00; + // 2Ah: * + 11'h150: data <= 8'h00; + 11'h151: data <= 8'h10; + 11'h152: data <= 8'h54; + 11'h153: data <= 8'h38; + 11'h154: data <= 8'h54; + 11'h155: data <= 8'h10; + 11'h156: data <= 8'h00; + 11'h157: data <= 8'h00; + // 2Bh: + + 11'h158: data <= 8'h00; + 11'h159: data <= 8'h10; + 11'h15A: data <= 8'h10; + 11'h15B: data <= 8'h7C; + 11'h15C: data <= 8'h10; + 11'h15D: data <= 8'h10; + 11'h15E: data <= 8'h00; + 11'h15F: data <= 8'h00; + // 2Ch: , + 11'h160: data <= 8'h00; + 11'h161: data <= 8'h00; + 11'h162: data <= 8'h00; + 11'h163: data <= 8'h00; + 11'h164: data <= 8'h00; + 11'h165: data <= 8'h30; + 11'h166: data <= 8'h10; + 11'h167: data <= 8'h20; + // 2Dh: - + 11'h168: data <= 8'h00; + 11'h169: data <= 8'h00; + 11'h16A: data <= 8'h00; + 11'h16B: data <= 8'h7C; + 11'h16C: data <= 8'h00; + 11'h16D: data <= 8'h00; + 11'h16E: data <= 8'h00; + 11'h16F: data <= 8'h00; + // 2Eh: . + 11'h170: data <= 8'h00; + 11'h171: data <= 8'h00; + 11'h172: data <= 8'h00; + 11'h173: data <= 8'h00; + 11'h174: data <= 8'h00; + 11'h175: data <= 8'h30; + 11'h176: data <= 8'h30; + 11'h177: data <= 8'h00; + // 2Fh: / + 11'h178: data <= 8'h00; + 11'h179: data <= 8'h04; + 11'h17A: data <= 8'h08; + 11'h17B: data <= 8'h10; + 11'h17C: data <= 8'h20; + 11'h17D: data <= 8'h40; + 11'h17E: data <= 8'h00; + 11'h17F: data <= 8'h00; + // 30h: 0 + 11'h180: data <= 8'h38; + 11'h181: data <= 8'h44; + 11'h182: data <= 8'h4C; + 11'h183: data <= 8'h54; + 11'h184: data <= 8'h64; + 11'h185: data <= 8'h44; + 11'h186: data <= 8'h38; + 11'h187: data <= 8'h00; + // 31h: 1 + 11'h188: data <= 8'h10; + 11'h189: data <= 8'h30; + 11'h18A: data <= 8'h10; + 11'h18B: data <= 8'h10; + 11'h18C: data <= 8'h10; + 11'h18D: data <= 8'h10; + 11'h18E: data <= 8'h38; + 11'h18F: data <= 8'h00; + // 32h: 2 + 11'h190: data <= 8'h38; + 11'h191: data <= 8'h44; + 11'h192: data <= 8'h04; + 11'h193: data <= 8'h08; + 11'h194: data <= 8'h10; + 11'h195: data <= 8'h20; + 11'h196: data <= 8'h7C; + 11'h197: data <= 8'h00; + // 33h: 3 + 11'h198: data <= 8'h7C; + 11'h199: data <= 8'h08; + 11'h19A: data <= 8'h10; + 11'h19B: data <= 8'h08; + 11'h19C: data <= 8'h04; + 11'h19D: data <= 8'h44; + 11'h19E: data <= 8'h38; + 11'h19F: data <= 8'h00; + // 34h: 4 + 11'h1A0: data <= 8'h08; + 11'h1A1: data <= 8'h18; + 11'h1A2: data <= 8'h28; + 11'h1A3: data <= 8'h48; + 11'h1A4: data <= 8'h7C; + 11'h1A5: data <= 8'h08; + 11'h1A6: data <= 8'h08; + 11'h1A7: data <= 8'h00; + // 35h: 5 + 11'h1A8: data <= 8'h7C; + 11'h1A9: data <= 8'h40; + 11'h1AA: data <= 8'h78; + 11'h1AB: data <= 8'h04; + 11'h1AC: data <= 8'h04; + 11'h1AD: data <= 8'h44; + 11'h1AE: data <= 8'h38; + 11'h1AF: data <= 8'h00; + // 36h: 6 + 11'h1B0: data <= 8'h18; + 11'h1B1: data <= 8'h20; + 11'h1B2: data <= 8'h40; + 11'h1B3: data <= 8'h78; + 11'h1B4: data <= 8'h44; + 11'h1B5: data <= 8'h44; + 11'h1B6: data <= 8'h38; + 11'h1B7: data <= 8'h00; + // 37h: 7 + 11'h1B8: data <= 8'h7C; + 11'h1B9: data <= 8'h04; + 11'h1BA: data <= 8'h08; + 11'h1BB: data <= 8'h10; + 11'h1BC: data <= 8'h20; + 11'h1BD: data <= 8'h20; + 11'h1BE: data <= 8'h20; + 11'h1BF: data <= 8'h00; + // 38h: 8 + 11'h1C0: data <= 8'h38; + 11'h1C1: data <= 8'h44; + 11'h1C2: data <= 8'h44; + 11'h1C3: data <= 8'h38; + 11'h1C4: data <= 8'h44; + 11'h1C5: data <= 8'h44; + 11'h1C6: data <= 8'h38; + 11'h1C7: data <= 8'h00; + // 39h: 9 + 11'h1C8: data <= 8'h38; + 11'h1C9: data <= 8'h44; + 11'h1CA: data <= 8'h44; + 11'h1CB: data <= 8'h3C; + 11'h1CC: data <= 8'h04; + 11'h1CD: data <= 8'h08; + 11'h1CE: data <= 8'h30; + 11'h1CF: data <= 8'h00; + // 3Ah: : + 11'h1D0: data <= 8'h00; + 11'h1D1: data <= 8'h30; + 11'h1D2: data <= 8'h30; + 11'h1D3: data <= 8'h00; + 11'h1D4: data <= 8'h00; + 11'h1D5: data <= 8'h30; + 11'h1D6: data <= 8'h30; + 11'h1D7: data <= 8'h00; + // 3Bh: ; + 11'h1D8: data <= 8'h00; + 11'h1D9: data <= 8'h30; + 11'h1DA: data <= 8'h30; + 11'h1DB: data <= 8'h00; + 11'h1DC: data <= 8'h00; + 11'h1DD: data <= 8'h30; + 11'h1DE: data <= 8'h10; + 11'h1DF: data <= 8'h20; + // 3Ch: < + 11'h1E0: data <= 8'h08; + 11'h1E1: data <= 8'h10; + 11'h1E2: data <= 8'h20; + 11'h1E3: data <= 8'h40; + 11'h1E4: data <= 8'h20; + 11'h1E5: data <= 8'h10; + 11'h1E6: data <= 8'h08; + 11'h1E7: data <= 8'h00; + // 3Dh: = + 11'h1E8: data <= 8'h00; + 11'h1E9: data <= 8'h00; + 11'h1EA: data <= 8'h7C; + 11'h1EB: data <= 8'h00; + 11'h1EC: data <= 8'h7C; + 11'h1ED: data <= 8'h00; + 11'h1EE: data <= 8'h00; + 11'h1EF: data <= 8'h00; + // 3Eh: > + 11'h1F0: data <= 8'h20; + 11'h1F1: data <= 8'h10; + 11'h1F2: data <= 8'h08; + 11'h1F3: data <= 8'h04; + 11'h1F4: data <= 8'h08; + 11'h1F5: data <= 8'h10; + 11'h1F6: data <= 8'h20; + 11'h1F7: data <= 8'h00; + // 3Fh: ? + 11'h1F8: data <= 8'h38; + 11'h1F9: data <= 8'h44; + 11'h1FA: data <= 8'h04; + 11'h1FB: data <= 8'h08; + 11'h1FC: data <= 8'h10; + 11'h1FD: data <= 8'h00; + 11'h1FE: data <= 8'h10; + 11'h1FF: data <= 8'h00; + // 40h: @ + 11'h200: data <= 8'h38; + 11'h201: data <= 8'h44; + 11'h202: data <= 8'h04; + 11'h203: data <= 8'h34; + 11'h204: data <= 8'h54; + 11'h205: data <= 8'h54; + 11'h206: data <= 8'h38; + 11'h207: data <= 8'h00; + // 41h: A + 11'h208: data <= 8'h38; + 11'h209: data <= 8'h44; + 11'h20A: data <= 8'h44; + 11'h20B: data <= 8'h44; + 11'h20C: data <= 8'h7C; + 11'h20D: data <= 8'h44; + 11'h20E: data <= 8'h44; + 11'h20F: data <= 8'h00; + // 42h: B + 11'h210: data <= 8'h78; + 11'h211: data <= 8'h44; + 11'h212: data <= 8'h44; + 11'h213: data <= 8'h78; + 11'h214: data <= 8'h44; + 11'h215: data <= 8'h44; + 11'h216: data <= 8'h78; + 11'h217: data <= 8'h00; + // 43h: C + 11'h218: data <= 8'h38; + 11'h219: data <= 8'h44; + 11'h21A: data <= 8'h40; + 11'h21B: data <= 8'h40; + 11'h21C: data <= 8'h40; + 11'h21D: data <= 8'h44; + 11'h21E: data <= 8'h38; + 11'h21F: data <= 8'h00; + // 44h: D + 11'h220: data <= 8'h70; + 11'h221: data <= 8'h48; + 11'h222: data <= 8'h44; + 11'h223: data <= 8'h44; + 11'h224: data <= 8'h44; + 11'h225: data <= 8'h48; + 11'h226: data <= 8'h70; + 11'h227: data <= 8'h00; + // 45h: E + 11'h228: data <= 8'h7C; + 11'h229: data <= 8'h40; + 11'h22A: data <= 8'h40; + 11'h22B: data <= 8'h78; + 11'h22C: data <= 8'h40; + 11'h22D: data <= 8'h40; + 11'h22E: data <= 8'h7C; + 11'h22F: data <= 8'h00; + // 46h: F + 11'h230: data <= 8'h7C; + 11'h231: data <= 8'h40; + 11'h232: data <= 8'h40; + 11'h233: data <= 8'h78; + 11'h234: data <= 8'h40; + 11'h235: data <= 8'h40; + 11'h236: data <= 8'h40; + 11'h237: data <= 8'h00; + // 47h: G + 11'h238: data <= 8'h38; + 11'h239: data <= 8'h44; + 11'h23A: data <= 8'h40; + 11'h23B: data <= 8'h5C; + 11'h23C: data <= 8'h44; + 11'h23D: data <= 8'h44; + 11'h23E: data <= 8'h3C; + 11'h23F: data <= 8'h00; + // 48h: H + 11'h240: data <= 8'h44; + 11'h241: data <= 8'h44; + 11'h242: data <= 8'h44; + 11'h243: data <= 8'h7C; + 11'h244: data <= 8'h44; + 11'h245: data <= 8'h44; + 11'h246: data <= 8'h44; + 11'h247: data <= 8'h00; + // 49h: I + 11'h248: data <= 8'h38; + 11'h249: data <= 8'h10; + 11'h24A: data <= 8'h10; + 11'h24B: data <= 8'h10; + 11'h24C: data <= 8'h10; + 11'h24D: data <= 8'h10; + 11'h24E: data <= 8'h38; + 11'h24F: data <= 8'h00; + // 4Ah: J + 11'h250: data <= 8'h1C; + 11'h251: data <= 8'h08; + 11'h252: data <= 8'h08; + 11'h253: data <= 8'h08; + 11'h254: data <= 8'h08; + 11'h255: data <= 8'h48; + 11'h256: data <= 8'h30; + 11'h257: data <= 8'h00; + // 4Bh: K + 11'h258: data <= 8'h44; + 11'h259: data <= 8'h48; + 11'h25A: data <= 8'h50; + 11'h25B: data <= 8'h60; + 11'h25C: data <= 8'h50; + 11'h25D: data <= 8'h48; + 11'h25E: data <= 8'h44; + 11'h25F: data <= 8'h00; + // 4Ch: L + 11'h260: data <= 8'h40; + 11'h261: data <= 8'h40; + 11'h262: data <= 8'h40; + 11'h263: data <= 8'h40; + 11'h264: data <= 8'h40; + 11'h265: data <= 8'h40; + 11'h266: data <= 8'h7C; + 11'h267: data <= 8'h00; + // 4Dh: M + 11'h268: data <= 8'h44; + 11'h269: data <= 8'h6C; + 11'h26A: data <= 8'h54; + 11'h26B: data <= 8'h54; + 11'h26C: data <= 8'h44; + 11'h26D: data <= 8'h44; + 11'h26E: data <= 8'h44; + 11'h26F: data <= 8'h00; + // 4Eh: N + 11'h270: data <= 8'h44; + 11'h271: data <= 8'h44; + 11'h272: data <= 8'h64; + 11'h273: data <= 8'h54; + 11'h274: data <= 8'h4C; + 11'h275: data <= 8'h44; + 11'h276: data <= 8'h44; + 11'h277: data <= 8'h00; + // 4Fh: O + 11'h278: data <= 8'h38; + 11'h279: data <= 8'h44; + 11'h27A: data <= 8'h44; + 11'h27B: data <= 8'h44; + 11'h27C: data <= 8'h44; + 11'h27D: data <= 8'h44; + 11'h27E: data <= 8'h38; + 11'h27F: data <= 8'h00; + // 50h: P + 11'h280: data <= 8'h78; + 11'h281: data <= 8'h44; + 11'h282: data <= 8'h44; + 11'h283: data <= 8'h78; + 11'h284: data <= 8'h40; + 11'h285: data <= 8'h40; + 11'h286: data <= 8'h40; + 11'h287: data <= 8'h00; + // 51h: Q + 11'h288: data <= 8'h38; + 11'h289: data <= 8'h44; + 11'h28A: data <= 8'h44; + 11'h28B: data <= 8'h44; + 11'h28C: data <= 8'h54; + 11'h28D: data <= 8'h48; + 11'h28E: data <= 8'h34; + 11'h28F: data <= 8'h00; + // 52h: R + 11'h290: data <= 8'h78; + 11'h291: data <= 8'h44; + 11'h292: data <= 8'h44; + 11'h293: data <= 8'h78; + 11'h294: data <= 8'h50; + 11'h295: data <= 8'h48; + 11'h296: data <= 8'h44; + 11'h297: data <= 8'h00; + // 53h: S + 11'h298: data <= 8'h3C; + 11'h299: data <= 8'h40; + 11'h29A: data <= 8'h40; + 11'h29B: data <= 8'h38; + 11'h29C: data <= 8'h04; + 11'h29D: data <= 8'h04; + 11'h29E: data <= 8'h78; + 11'h29F: data <= 8'h00; + // 54h: T + 11'h2A0: data <= 8'h7C; + 11'h2A1: data <= 8'h10; + 11'h2A2: data <= 8'h10; + 11'h2A3: data <= 8'h10; + 11'h2A4: data <= 8'h10; + 11'h2A5: data <= 8'h10; + 11'h2A6: data <= 8'h10; + 11'h2A7: data <= 8'h00; + // 55h: U + 11'h2A8: data <= 8'h44; + 11'h2A9: data <= 8'h44; + 11'h2AA: data <= 8'h44; + 11'h2AB: data <= 8'h44; + 11'h2AC: data <= 8'h44; + 11'h2AD: data <= 8'h44; + 11'h2AE: data <= 8'h38; + 11'h2AF: data <= 8'h00; + // 56h: V + 11'h2B0: data <= 8'h44; + 11'h2B1: data <= 8'h44; + 11'h2B2: data <= 8'h44; + 11'h2B3: data <= 8'h44; + 11'h2B4: data <= 8'h44; + 11'h2B5: data <= 8'h28; + 11'h2B6: data <= 8'h10; + 11'h2B7: data <= 8'h00; + // 57h: W + 11'h2B8: data <= 8'h44; + 11'h2B9: data <= 8'h44; + 11'h2BA: data <= 8'h44; + 11'h2BB: data <= 8'h54; + 11'h2BC: data <= 8'h54; + 11'h2BD: data <= 8'h54; + 11'h2BE: data <= 8'h28; + 11'h2BF: data <= 8'h00; + // 58h: X + 11'h2C0: data <= 8'h44; + 11'h2C1: data <= 8'h44; + 11'h2C2: data <= 8'h28; + 11'h2C3: data <= 8'h10; + 11'h2C4: data <= 8'h28; + 11'h2C5: data <= 8'h44; + 11'h2C6: data <= 8'h44; + 11'h2C7: data <= 8'h00; + // 59h: Y + 11'h2C8: data <= 8'h44; + 11'h2C9: data <= 8'h44; + 11'h2CA: data <= 8'h44; + 11'h2CB: data <= 8'h28; + 11'h2CC: data <= 8'h10; + 11'h2CD: data <= 8'h10; + 11'h2CE: data <= 8'h10; + 11'h2CF: data <= 8'h00; + // 5Ah: Z + 11'h2D0: data <= 8'h7C; + 11'h2D1: data <= 8'h04; + 11'h2D2: data <= 8'h08; + 11'h2D3: data <= 8'h10; + 11'h2D4: data <= 8'h20; + 11'h2D5: data <= 8'h40; + 11'h2D6: data <= 8'h7C; + 11'h2D7: data <= 8'h00; + // 5Bh: [ + 11'h2D8: data <= 8'h38; + 11'h2D9: data <= 8'h20; + 11'h2DA: data <= 8'h20; + 11'h2DB: data <= 8'h20; + 11'h2DC: data <= 8'h20; + 11'h2DD: data <= 8'h20; + 11'h2DE: data <= 8'h38; + 11'h2DF: data <= 8'h00; + // 5Ch: \ + 11'h2E0: data <= 8'h00; + 11'h2E1: data <= 8'h40; + 11'h2E2: data <= 8'h20; + 11'h2E3: data <= 8'h10; + 11'h2E4: data <= 8'h08; + 11'h2E5: data <= 8'h04; + 11'h2E6: data <= 8'h00; + 11'h2E7: data <= 8'h00; + // 5Dh: ] + 11'h2E8: data <= 8'h38; + 11'h2E9: data <= 8'h08; + 11'h2EA: data <= 8'h08; + 11'h2EB: data <= 8'h08; + 11'h2EC: data <= 8'h08; + 11'h2ED: data <= 8'h08; + 11'h2EE: data <= 8'h38; + 11'h2EF: data <= 8'h00; + // 5Eh: ^ + 11'h2F0: data <= 8'h10; + 11'h2F1: data <= 8'h28; + 11'h2F2: data <= 8'h44; + 11'h2F3: data <= 8'h00; + 11'h2F4: data <= 8'h00; + 11'h2F5: data <= 8'h00; + 11'h2F6: data <= 8'h00; + 11'h2F7: data <= 8'h00; + // 5Fh: _ + 11'h2F8: data <= 8'h00; + 11'h2F9: data <= 8'h00; + 11'h2FA: data <= 8'h00; + 11'h2FB: data <= 8'h00; + 11'h2FC: data <= 8'h00; + 11'h2FD: data <= 8'h00; + 11'h2FE: data <= 8'h7C; + 11'h2FF: data <= 8'h00; + // 60h: ` + 11'h300: data <= 8'h20; + 11'h301: data <= 8'h10; + 11'h302: data <= 8'h08; + 11'h303: data <= 8'h00; + 11'h304: data <= 8'h00; + 11'h305: data <= 8'h00; + 11'h306: data <= 8'h00; + 11'h307: data <= 8'h00; + // 61h: a + 11'h308: data <= 8'h00; + 11'h309: data <= 8'h00; + 11'h30A: data <= 8'h38; + 11'h30B: data <= 8'h04; + 11'h30C: data <= 8'h3C; + 11'h30D: data <= 8'h44; + 11'h30E: data <= 8'h3C; + 11'h30F: data <= 8'h00; + // 62h: b + 11'h310: data <= 8'h40; + 11'h311: data <= 8'h40; + 11'h312: data <= 8'h58; + 11'h313: data <= 8'h64; + 11'h314: data <= 8'h44; + 11'h315: data <= 8'h44; + 11'h316: data <= 8'h78; + 11'h317: data <= 8'h00; + // 63h: c + 11'h318: data <= 8'h00; + 11'h319: data <= 8'h00; + 11'h31A: data <= 8'h38; + 11'h31B: data <= 8'h40; + 11'h31C: data <= 8'h40; + 11'h31D: data <= 8'h44; + 11'h31E: data <= 8'h38; + 11'h31F: data <= 8'h00; + // 64h: d + 11'h320: data <= 8'h04; + 11'h321: data <= 8'h04; + 11'h322: data <= 8'h34; + 11'h323: data <= 8'h4C; + 11'h324: data <= 8'h44; + 11'h325: data <= 8'h44; + 11'h326: data <= 8'h3C; + 11'h327: data <= 8'h00; + // 65h: e + 11'h328: data <= 8'h00; + 11'h329: data <= 8'h00; + 11'h32A: data <= 8'h38; + 11'h32B: data <= 8'h44; + 11'h32C: data <= 8'h7C; + 11'h32D: data <= 8'h40; + 11'h32E: data <= 8'h38; + 11'h32F: data <= 8'h00; + // 66h: f + 11'h330: data <= 8'h18; + 11'h331: data <= 8'h24; + 11'h332: data <= 8'h20; + 11'h333: data <= 8'h70; + 11'h334: data <= 8'h20; + 11'h335: data <= 8'h20; + 11'h336: data <= 8'h20; + 11'h337: data <= 8'h00; + // 67h: g + 11'h338: data <= 8'h00; + 11'h339: data <= 8'h00; + 11'h33A: data <= 8'h3C; + 11'h33B: data <= 8'h44; + 11'h33C: data <= 8'h44; + 11'h33D: data <= 8'h3C; + 11'h33E: data <= 8'h04; + 11'h33F: data <= 8'h38; + // 68h: h + 11'h340: data <= 8'h40; + 11'h341: data <= 8'h40; + 11'h342: data <= 8'h58; + 11'h343: data <= 8'h64; + 11'h344: data <= 8'h44; + 11'h345: data <= 8'h44; + 11'h346: data <= 8'h44; + 11'h347: data <= 8'h00; + // 69h: i + 11'h348: data <= 8'h10; + 11'h349: data <= 8'h10; + 11'h34A: data <= 8'h30; + 11'h34B: data <= 8'h10; + 11'h34C: data <= 8'h10; + 11'h34D: data <= 8'h10; + 11'h34E: data <= 8'h38; + 11'h34F: data <= 8'h00; + // 6Ah: j + 11'h350: data <= 8'h00; + 11'h351: data <= 8'h08; + 11'h352: data <= 8'h00; + 11'h353: data <= 8'h18; + 11'h354: data <= 8'h08; + 11'h355: data <= 8'h08; + 11'h356: data <= 8'h48; + 11'h357: data <= 8'h30; + // 6Bh: k + 11'h358: data <= 8'h40; + 11'h359: data <= 8'h40; + 11'h35A: data <= 8'h48; + 11'h35B: data <= 8'h50; + 11'h35C: data <= 8'h60; + 11'h35D: data <= 8'h50; + 11'h35E: data <= 8'h48; + 11'h35F: data <= 8'h00; + // 6Ch: l + 11'h360: data <= 8'h30; + 11'h361: data <= 8'h10; + 11'h362: data <= 8'h10; + 11'h363: data <= 8'h10; + 11'h364: data <= 8'h10; + 11'h365: data <= 8'h10; + 11'h366: data <= 8'h38; + 11'h367: data <= 8'h00; + // 6Dh: m + 11'h368: data <= 8'h00; + 11'h369: data <= 8'h00; + 11'h36A: data <= 8'h68; + 11'h36B: data <= 8'h54; + 11'h36C: data <= 8'h54; + 11'h36D: data <= 8'h44; + 11'h36E: data <= 8'h44; + 11'h36F: data <= 8'h00; + // 6Eh: n + 11'h370: data <= 8'h00; + 11'h371: data <= 8'h00; + 11'h372: data <= 8'h58; + 11'h373: data <= 8'h64; + 11'h374: data <= 8'h44; + 11'h375: data <= 8'h44; + 11'h376: data <= 8'h44; + 11'h377: data <= 8'h00; + // 6Fh: o + 11'h378: data <= 8'h00; + 11'h379: data <= 8'h00; + 11'h37A: data <= 8'h38; + 11'h37B: data <= 8'h44; + 11'h37C: data <= 8'h44; + 11'h37D: data <= 8'h44; + 11'h37E: data <= 8'h38; + 11'h37F: data <= 8'h00; + // 70h: p + 11'h380: data <= 8'h00; + 11'h381: data <= 8'h00; + 11'h382: data <= 8'h78; + 11'h383: data <= 8'h44; + 11'h384: data <= 8'h78; + 11'h385: data <= 8'h40; + 11'h386: data <= 8'h40; + 11'h387: data <= 8'h40; + // 71h: q + 11'h388: data <= 8'h00; + 11'h389: data <= 8'h00; + 11'h38A: data <= 8'h00; + 11'h38B: data <= 8'h34; + 11'h38C: data <= 8'h4C; + 11'h38D: data <= 8'h3C; + 11'h38E: data <= 8'h04; + 11'h38F: data <= 8'h04; + // 72h: r + 11'h390: data <= 8'h00; + 11'h391: data <= 8'h00; + 11'h392: data <= 8'h58; + 11'h393: data <= 8'h64; + 11'h394: data <= 8'h40; + 11'h395: data <= 8'h40; + 11'h396: data <= 8'h40; + 11'h397: data <= 8'h00; + // 73h: s + 11'h398: data <= 8'h00; + 11'h399: data <= 8'h00; + 11'h39A: data <= 8'h38; + 11'h39B: data <= 8'h40; + 11'h39C: data <= 8'h38; + 11'h39D: data <= 8'h04; + 11'h39E: data <= 8'h78; + 11'h39F: data <= 8'h00; + // 74h: t + 11'h3A0: data <= 8'h00; + 11'h3A1: data <= 8'h20; + 11'h3A2: data <= 8'h20; + 11'h3A3: data <= 8'h70; + 11'h3A4: data <= 8'h20; + 11'h3A5: data <= 8'h20; + 11'h3A6: data <= 8'h24; + 11'h3A7: data <= 8'h18; + // 75h: u + 11'h3A8: data <= 8'h00; + 11'h3A9: data <= 8'h00; + 11'h3AA: data <= 8'h44; + 11'h3AB: data <= 8'h44; + 11'h3AC: data <= 8'h44; + 11'h3AD: data <= 8'h4C; + 11'h3AE: data <= 8'h34; + 11'h3AF: data <= 8'h00; + // 76h: v + 11'h3B0: data <= 8'h00; + 11'h3B1: data <= 8'h00; + 11'h3B2: data <= 8'h44; + 11'h3B3: data <= 8'h44; + 11'h3B4: data <= 8'h44; + 11'h3B5: data <= 8'h28; + 11'h3B6: data <= 8'h10; + 11'h3B7: data <= 8'h00; + // 77h: w + 11'h3B8: data <= 8'h00; + 11'h3B9: data <= 8'h00; + 11'h3BA: data <= 8'h44; + 11'h3BB: data <= 8'h44; + 11'h3BC: data <= 8'h54; + 11'h3BD: data <= 8'h54; + 11'h3BE: data <= 8'h28; + 11'h3BF: data <= 8'h00; + // 78h: x + 11'h3C0: data <= 8'h00; + 11'h3C1: data <= 8'h00; + 11'h3C2: data <= 8'h44; + 11'h3C3: data <= 8'h28; + 11'h3C4: data <= 8'h10; + 11'h3C5: data <= 8'h28; + 11'h3C6: data <= 8'h44; + 11'h3C7: data <= 8'h00; + // 79h: y + 11'h3C8: data <= 8'h00; + 11'h3C9: data <= 8'h00; + 11'h3CA: data <= 8'h00; + 11'h3CB: data <= 8'h44; + 11'h3CC: data <= 8'h44; + 11'h3CD: data <= 8'h3C; + 11'h3CE: data <= 8'h04; + 11'h3CF: data <= 8'h38; + // 7Ah: z + 11'h3D0: data <= 8'h00; + 11'h3D1: data <= 8'h00; + 11'h3D2: data <= 8'h7C; + 11'h3D3: data <= 8'h08; + 11'h3D4: data <= 8'h10; + 11'h3D5: data <= 8'h20; + 11'h3D6: data <= 8'h7C; + 11'h3D7: data <= 8'h00; + // 7Bh: { + 11'h3D8: data <= 8'h08; + 11'h3D9: data <= 8'h10; + 11'h3DA: data <= 8'h10; + 11'h3DB: data <= 8'h20; + 11'h3DC: data <= 8'h10; + 11'h3DD: data <= 8'h10; + 11'h3DE: data <= 8'h08; + 11'h3DF: data <= 8'h00; + // 7Ch: | + 11'h3E0: data <= 8'h10; + 11'h3E1: data <= 8'h10; + 11'h3E2: data <= 8'h10; + 11'h3E3: data <= 8'h10; + 11'h3E4: data <= 8'h10; + 11'h3E5: data <= 8'h10; + 11'h3E6: data <= 8'h10; + 11'h3E7: data <= 8'h00; + // 7Dh: } + 11'h3E8: data <= 8'h20; + 11'h3E9: data <= 8'h10; + 11'h3EA: data <= 8'h10; + 11'h3EB: data <= 8'h08; + 11'h3EC: data <= 8'h10; + 11'h3ED: data <= 8'h10; + 11'h3EE: data <= 8'h20; + 11'h3EF: data <= 8'h00; + // 7Eh: ~ + 11'h3F0: data <= 8'h00; + 11'h3F1: data <= 8'h00; + 11'h3F2: data <= 8'h60; + 11'h3F3: data <= 8'h92; + 11'h3F4: data <= 8'h0C; + 11'h3F5: data <= 8'h00; + 11'h3F6: data <= 8'h00; + 11'h3F7: data <= 8'h00; + + //// Hash Pattern //// + + // 7Fh: hash pattern + 11'h3F8: data <= 8'h55; + 11'h3F9: data <= 8'hAA; + 11'h3FA: data <= 8'h55; + 11'h3FB: data <= 8'hAA; + 11'h3FC: data <= 8'h55; + 11'h3FD: data <= 8'hAA; + 11'h3FE: data <= 8'h55; + 11'h3FF: data <= 8'hAA; + + //// User Defined Characters //// + + // 80h: vertical to the left + 11'h400: data <= 8'hF0; + 11'h401: data <= 8'hF0; + 11'h402: data <= 8'hF0; + 11'h403: data <= 8'hF0; + 11'h404: data <= 8'hF0; + 11'h405: data <= 8'hF0; + 11'h406: data <= 8'hF0; + 11'h407: data <= 8'hF0; + + // 81h: vertical to the right + 11'h408: data <= 8'h0F; + 11'h409: data <= 8'h0F; + 11'h40A: data <= 8'h0F; + 11'h40B: data <= 8'h0F; + 11'h40C: data <= 8'h0F; + 11'h40D: data <= 8'h0F; + 11'h40E: data <= 8'h0F; + 11'h40F: data <= 8'h0F; + + // 82h: circle + 11'h410: data <= 8'h00; + 11'h411: data <= 8'h18; + 11'h412: data <= 8'h3C; + 11'h413: data <= 8'h7E; + 11'h414: data <= 8'h7E; + 11'h415: data <= 8'h3C; + 11'h416: data <= 8'h18; + 11'h417: data <= 8'h00; + + // 83h: Upper left block only + 11'h418: data <= 8'hF0; + 11'h419: data <= 8'hF0; + 11'h41A: data <= 8'hF0; + 11'h41B: data <= 8'hF0; + 11'h41C: data <= 8'h00; + 11'h41D: data <= 8'h00; + 11'h41E: data <= 8'h00; + 11'h41F: data <= 8'h00; + + // 84h: Upper right block only + 11'h420: data <= 8'h0F; + 11'h421: data <= 8'h0F; + 11'h422: data <= 8'h0F; + 11'h423: data <= 8'h0F; + 11'h424: data <= 8'h00; + 11'h425: data <= 8'h00; + 11'h426: data <= 8'h00; + 11'h427: data <= 8'h00; + + // 85h: Lower left block only + 11'h428: data <= 8'h00; + 11'h429: data <= 8'h00; + 11'h42A: data <= 8'h00; + 11'h42B: data <= 8'h00; + 11'h42C: data <= 8'hF0; + 11'h42D: data <= 8'hF0; + 11'h42E: data <= 8'hF0; + 11'h42F: data <= 8'hF0; + + // 86h: Lower right block only + 11'h430: data <= 8'h00; + 11'h431: data <= 8'h00; + 11'h432: data <= 8'h00; + 11'h433: data <= 8'h00; + 11'h434: data <= 8'h0F; + 11'h435: data <= 8'h0F; + 11'h436: data <= 8'h0F; + 11'h437: data <= 8'h0F; + + // 87h: One horizontal line + 11'h438: data <= 8'h00; + 11'h439: data <= 8'h00; + 11'h43A: data <= 8'h00; + 11'h43B: data <= 8'h00; + 11'h43C: data <= 8'h00; + 11'h43D: data <= 8'h00; + 11'h43E: data <= 8'h00; + 11'h43F: data <= 8'hFF; + + // 88h: Two horizontal lines + 11'h440: data <= 8'h00; + 11'h441: data <= 8'h00; + 11'h442: data <= 8'h00; + 11'h443: data <= 8'h00; + 11'h444: data <= 8'h00; + 11'h445: data <= 8'h00; + 11'h446: data <= 8'hFF; + 11'h447: data <= 8'hFF; + + // 89h: Three horizontal lines + 11'h448: data <= 8'h00; + 11'h449: data <= 8'h00; + 11'h44A: data <= 8'h00; + 11'h44B: data <= 8'h00; + 11'h44C: data <= 8'h00; + 11'h44D: data <= 8'hFF; + 11'h44E: data <= 8'hFF; + 11'h44F: data <= 8'hFF; + + // 8Ah: Four horizontal lines + 11'h450: data <= 8'h00; + 11'h451: data <= 8'h00; + 11'h452: data <= 8'h00; + 11'h453: data <= 8'h00; + 11'h454: data <= 8'hFF; + 11'h455: data <= 8'hFF; + 11'h456: data <= 8'hFF; + 11'h457: data <= 8'hFF; + + // 8Bh: Five horizontal lines + 11'h458: data <= 8'h00; + 11'h459: data <= 8'h00; + 11'h45A: data <= 8'h00; + 11'h45B: data <= 8'hFF; + 11'h45C: data <= 8'hFF; + 11'h45D: data <= 8'hFF; + 11'h45E: data <= 8'hFF; + 11'h45F: data <= 8'hFF; + + // 8Ch: Six horizontal lines + 11'h460: data <= 8'h00; + 11'h461: data <= 8'h00; + 11'h462: data <= 8'hFF; + 11'h463: data <= 8'hFF; + 11'h464: data <= 8'hFF; + 11'h465: data <= 8'hFF; + 11'h466: data <= 8'hFF; + 11'h467: data <= 8'hFF; + + // 8Dh: Seven horizontal lines + 11'h468: data <= 8'h00; + 11'h469: data <= 8'hFF; + 11'h46A: data <= 8'hFF; + 11'h46B: data <= 8'hFF; + 11'h46C: data <= 8'hFF; + 11'h46D: data <= 8'hFF; + 11'h46E: data <= 8'hFF; + 11'h46F: data <= 8'hFF; + + // 8Eh: One vertical line + 11'h470: data <= 8'h80; + 11'h471: data <= 8'h80; + 11'h472: data <= 8'h80; + 11'h473: data <= 8'h80; + 11'h474: data <= 8'h80; + 11'h475: data <= 8'h80; + 11'h476: data <= 8'h80; + 11'h477: data <= 8'h80; + + // 8Fh: Two vertical lines + /*11'h478: data <= 8'hc0; + 11'h479: data <= 8'hc0; + 11'h47A: data <= 8'hc0; + 11'h47B: data <= 8'hc0; + 11'h47C: data <= 8'hc0; + 11'h47D: data <= 8'hc0; + 11'h47E: data <= 8'hc0; + 11'h47F: data <= 8'hc0;*/ + endcase +end + +endmodule //CHAR_GEN_ROM + +//------------------------------------------ + +module CHAR_RAM +( +clka, +wea, +addra, +dia, + +clkb, +addrb, +dob +); + +input clka; +input wea; +input [13:0] addra; +input [11:0] dia; + +input clkb; +input [13:0] addrb; +output [11:0] dob; + +//reg [11:0] ram [16383:0]; +//reg [11:0] ram [8191:0]; +reg [11:0] ram [4095:0]; +reg [13:0] read_addrb; + +always @(posedge clka) begin + if (wea) + ram[addra] <= dia; +end + +always @(posedge clkb) begin + read_addrb <= addrb; +end + +assign dob = ram[read_addrb]; + +// fill the character RAM with spaces +integer index; +initial begin +// for (index = 0; index <= 16383; index = index + 1) begin + for (index = 0; index <= 4095; index = index + 1) begin + ram[index] = 8'h20; // ASCII space + end + + //for (index = 9998; index <= 16383; index = index + 1) begin + // ram[index] = 8'h20; // ASCII space + //end +end + +endmodule //CHAR_RAM + +//------------------------------------ + +module CLOCK_GEN +( +SYSTEM_CLOCK, + +system_clock_buffered, +pixel_clock, +reset +); + +input SYSTEM_CLOCK; // 100MHz LVTTL SYSTEM CLOCK + +output system_clock_buffered; // buffered SYSTEM_CLOCK +output pixel_clock; // adjusted SYSTEM_CLOCK +output reset; // reset asserted when DCMs are NOT LOCKED + +wire low = 1'b0; +wire high = 1'b1; + +// signals associated with the system clock DCM +wire system_dcm_reset; +wire system_dcm_locked; +wire system_clock_in; +wire system_clock_unbuffered; +wire pixel_clock_unbuffered; +wire system_clock_buffered; +wire pixel_clock; + +//IBUFG SYSTEM_CLOCK_BUF ( +//.O (system_clock_in), +//.I (SYSTEM_CLOCK) +//); + +BUFG SYSTEM_CLOCK_BUF ( +.O (system_clock_in), +.I (SYSTEM_CLOCK) +); + +//assign system_clock_in = SYSTEM_CLOCK; + +// instantiate the clock input buffers for the internal clocks +BUFG SYS_CLOCK_BUF ( +.O (system_clock_buffered), +.I (system_clock_unbuffered) +); + +//assign system_clock_buffered = system_clock_unbuffered; + +BUFG PIXEL_CLOCK_BUF ( +.O (pixel_clock), +.I (pixel_clock_unbuffered) +); + +//assign pixel_clock = pixel_clock_unbuffered; + +assign reset = !system_dcm_locked; + +DCM SYSTEM_DCM ( +.CLKFB (system_clock_buffered), +.CLKIN (system_clock_in), +.DSSEN (low), +.PSCLK (low), +.PSEN (low), +.PSINCDEC (low), +.RST (system_dcm_reset), +.CLK0 (system_clock_unbuffered), +.CLK90 (), +.CLK180 (), +.CLK270 (), +.CLK2X (), +.CLK2X180 (), +.CLKDV (), +.CLKFX (pixel_clock_unbuffered), +.CLKFX180 (), +.LOCKED (system_dcm_locked), +.PSDONE (), +.STATUS () +); +defparam SYSTEM_DCM.CLKDV_DIVIDE = 2.0; // divide the system clock (50 MHz) by 2.0 to determine CLKDV (25 MHz) +defparam SYSTEM_DCM.CLKFX_DIVIDE = `CLK_DIVIDE; // the denominator of the clock multiplier used to determine CLKFX +defparam SYSTEM_DCM.CLKFX_MULTIPLY = `CLK_MULTIPLY; // the numerator of the clock multiplier used to determine CLKFX +defparam SYSTEM_DCM.CLKIN_DIVIDE_BY_2 = "FALSE"; +defparam SYSTEM_DCM.CLKIN_PERIOD = 20.0; // period of input clock in ns +defparam SYSTEM_DCM.CLKOUT_PHASE_SHIFT = "NONE"; // phase shift of NONE +defparam SYSTEM_DCM.CLK_FEEDBACK = "1X"; // feedback of NONE, 1X +defparam SYSTEM_DCM.DFS_FREQUENCY_MODE = "LOW"; // LOW frequency mode for frequency synthesis +defparam SYSTEM_DCM.DLL_FREQUENCY_MODE = "LOW"; // LOW frequency mode for DLL +defparam SYSTEM_DCM.DUTY_CYCLE_CORRECTION = "TRUE"; // Duty cycle correction, TRUE +defparam SYSTEM_DCM.PHASE_SHIFT = 0; // Amount of fixed phase shift from -255 to 255 +defparam SYSTEM_DCM.STARTUP_WAIT = "FALSE"; // Delay configuration DONE until DCM LOCK FALSE + +SRL16 RESET_SYSTEM_DCM ( +.Q (system_dcm_reset), +.CLK (system_clock_in), +.D (low), +.A0 (high), +.A1 (high), +.A2 (high), +.A3 (high) +); +defparam RESET_SYSTEM_DCM.INIT = "000F"; + +endmodule //CLOCK_GEN + +//--------------------------------------------------- + +module SVGA_TIMING_GENERATION +( +pixel_clock, +reset, +h_synch, +v_synch, +blank, +pixel_count, +line_count, +subchar_pixel, +subchar_line, +char_column, +char_line +); + +input pixel_clock; // pixel clock +input reset; // reset +output h_synch; // horizontal synch for VGA connector +output v_synch; // vertical synch for VGA connector +output blank; // composite blanking +output [10:0] pixel_count; // counts the pixels in a line +output [9:0] line_count; // counts the display lines +output [2:0] subchar_pixel; // pixel position within the character +output [2:0] subchar_line; // identifies the line number within a character block +output [6:0] char_column; // character number on the current line +output [6:0] char_line; // line number on the screen + +reg [9:0] line_count; // counts the display lines +reg [10:0] pixel_count; // counts the pixels in a line +reg h_synch; // horizontal synch +reg v_synch; // vertical synch + +reg h_blank; // horizontal blanking +reg v_blank; // vertical blanking +reg blank; // composite blanking + +reg [2:0] subchar_line; // identifies the line number within a character block +reg [9:0] char_column_count; // a counter used to define the character column number +reg [9:0] char_line_count; // a counter used to define the character line number +reg reset_char_line; // flag to reset the character line during VBI +reg reset_char_column; // flag to reset the character column during HBI +reg [2:0] subchar_pixel; // pixel position within the character +reg [6:0] char_column; // character number on the current line +reg [6:0] char_line; // line number on the screen + +// CREATE THE HORIZONTAL LINE PIXEL COUNTER +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset set pixel counter to 0 + pixel_count <= 11'd0; + + else if (pixel_count == (`H_TOTAL - 1)) + // last pixel in the line, so reset pixel counter + pixel_count <= 11'd0; + + else + pixel_count <= pixel_count + 1; +end + +// CREATE THE HORIZONTAL SYNCH PULSE +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset remove h_synch + h_synch <= 1'b0; + + else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1)) + // start of h_synch + h_synch <= 1'b1; + + else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1)) + // end of h_synch + h_synch <= 1'b0; +end + +// CREATE THE VERTICAL FRAME LINE COUNTER +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset set line counter to 0 + line_count <= 10'd0; + + else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1))) + // last pixel in last line of frame, so reset line counter + line_count <= 10'd0; + + else if ((pixel_count == (`H_TOTAL - 1))) + // last pixel but not last line, so increment line counter + line_count <= line_count + 1; +end + +// CREATE THE VERTICAL SYNCH PULSE +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset remove v_synch + v_synch = 1'b0; + + else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) & + (pixel_count == `H_TOTAL - 1))) + // start of v_synch + v_synch = 1'b1; + + else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) & + (pixel_count == (`H_TOTAL - 1))) + // end of v_synch + v_synch = 1'b0; +end + + +// CREATE THE HORIZONTAL BLANKING SIGNAL +// the "-2" is used instead of "-1" because of the extra register delay +// for the composite blanking signal +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset remove the h_blank + h_blank <= 1'b0; + + else if (pixel_count == (`H_ACTIVE -2)) + // start of HBI + h_blank <= 1'b1; + + else if (pixel_count == (`H_TOTAL -2)) + // end of HBI + h_blank <= 1'b0; +end + + +// CREATE THE VERTICAL BLANKING SIGNAL +// the "-2" is used instead of "-1" in the horizontal factor because of the extra +// register delay for the composite blanking signal +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset remove v_blank + v_blank <= 1'b0; + + else if ((line_count == (`V_ACTIVE - 1) & + (pixel_count == `H_TOTAL - 2))) + // start of VBI + v_blank <= 1'b1; + + else if ((line_count == (`V_TOTAL - 1)) & + (pixel_count == (`H_TOTAL - 2))) + // end of VBI + v_blank <= 1'b0; +end + + +// CREATE THE COMPOSITE BANKING SIGNAL +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset remove blank + blank <= 1'b0; + + // blank during HBI or VBI + else if (h_blank || v_blank) + blank <= 1'b1; + + else + // active video do not blank + blank <= 1'b0; +end + + +/* + CREATE THE CHARACTER COUNTER. + CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK. + + A 640 x 480 video mode will display 80 characters on 60 lines. + A 800 x 600 video mode will display 100 characters on 75 lines. + A 1024 x 768 video mode will display 128 characters on 96 lines. + + "subchar_line" identifies the row in the 8 x 8 block. + "subchar_pixel" identifies the column in the 8 x 8 block. +*/ + +// CREATE THE VERTICAL FRAME LINE COUNTER +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // on reset set line counter to 0 + subchar_line <= 3'b000; + + else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)) + // reset line counter + subchar_line <= 3'b000; + + else if (pixel_count == (`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY) + // increment line counter + subchar_line <= line_count + 1; +end + +// subchar_pixel defines the pixel within the character line +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + // reset to 5 so that the first character data can be latched + subchar_pixel <= 3'b101; + + else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)) + // reset to 5 so that the first character data can be latched + subchar_pixel <= 3'b101; + + else + subchar_pixel <= subchar_pixel + 1; +end + + +wire [9:0] char_column_count_iter = char_column_count + 1; + +always @ (posedge pixel_clock or posedge reset) begin + if (reset) begin + char_column_count <= 10'd0; + char_column <= 7'd0; + end + + else if (reset_char_column) begin + // reset the char column count during the HBI + char_column_count <= 10'd0; + char_column <= 7'd0; + end + + else begin + char_column_count <= char_column_count_iter; + char_column <= char_column_count_iter[9:3]; + end +end + +wire [9:0] char_line_count_iter = char_line_count + 1; + +always @ (posedge pixel_clock or posedge reset) begin + if (reset) begin + char_line_count <= 10'd0; + char_line <= 7'd0; + end + + else if (reset_char_line) begin + // reset the char line count during the VBI + char_line_count <= 10'd0; + char_line <= 7'd0; + end + + else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)) begin + // last pixel but not last line, so increment line counter + char_line_count <= char_line_count_iter; + char_line <= char_line_count_iter[9:3]; + end +end + +// CREATE THE CONTROL SIGNALS FOR THE CHARACTER ADDRESS COUNTERS +/* + The HOLD and RESET signals are advanced from the beginning and end + of HBI and VBI to compensate for the internal character generation + pipeline. +*/ +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + reset_char_column <= 1'b0; + + else if (pixel_count == ((`H_ACTIVE - 1) - `CHARACTER_DECODE_DELAY)) + // start of HBI + reset_char_column <= 1'b1; + + else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)) + // end of HBI + reset_char_column <= 1'b0; +end + +always @ (posedge pixel_clock or posedge reset) begin + if (reset) + reset_char_line <= 1'b0; + + else if ((line_count == (`V_ACTIVE - 1)) & + (pixel_count == ((`H_ACTIVE - 1) - `CHARACTER_DECODE_DELAY))) + // start of VBI + reset_char_line <= 1'b1; + + else if ((line_count == (`V_TOTAL - 1)) & + (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY))) + // end of VBI + reset_char_line <= 1'b0; +end +endmodule //SVGA_TIMING_GENERATION + +//---------------------------------------------- + +module VIDEO_OUT +( +pixel_clock, +reset, +vga_red_data, +vga_green_data, +vga_blue_data, +h_synch, +v_synch, +blank, + +VGA_HSYNCH, +VGA_VSYNCH, +VGA_OUT_RED, +VGA_OUT_GREEN, +VGA_OUT_BLUE +); + +input pixel_clock; +input reset; +input vga_red_data; +input vga_green_data; +input vga_blue_data; +input h_synch; +input v_synch; +input blank; + +output VGA_HSYNCH; +output VGA_VSYNCH; +output VGA_OUT_RED; +output VGA_OUT_GREEN; +output VGA_OUT_BLUE; + +reg VGA_HSYNCH; +reg VGA_VSYNCH; +reg VGA_OUT_RED; +reg VGA_OUT_GREEN; +reg VGA_OUT_BLUE; + +// make the external video connections +always @ (posedge pixel_clock or posedge reset) begin + if (reset) begin + // shut down the video output during reset + VGA_HSYNCH <= 1'b1; + VGA_VSYNCH <= 1'b1; + VGA_OUT_RED <= 1'b0; + VGA_OUT_GREEN <= 1'b0; + VGA_OUT_BLUE <= 1'b0; + end + + else if (blank) begin + // output black during the blank signal + VGA_HSYNCH <= h_synch; + VGA_VSYNCH <= v_synch; + VGA_OUT_RED <= 1'b0; + VGA_OUT_GREEN <= 1'b0; + VGA_OUT_BLUE <= 1'b0; + end + + else begin + // output color data otherwise + VGA_HSYNCH <= h_synch; + VGA_VSYNCH <= v_synch; + VGA_OUT_RED <= vga_red_data; + VGA_OUT_GREEN <= vga_green_data; + VGA_OUT_BLUE <= vga_blue_data; + end +end + +endmodule // VIDEO_OUT \ No newline at end of file Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/SVGA_DEFINES.v =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/SVGA_DEFINES.v (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/verilog/SVGA_DEFINES.v (revision 4) @@ -0,0 +1,48 @@ +/* +--------------------------------------------------------------------------------- +To select a resolution and refresh rate, remove the comments around the desired +block in this file. The pixel clock output by the DCM module should approximately +equal the rate specified above the timing block that is uncommented. +--------------------------------------------------------------------------------- +*/ + +// DEFINE THE VARIOUS PIPELINE DELAYS + +`define CHARACTER_DECODE_DELAY 4 + + +// 640 X 480 @ 60Hz with a 25.175MHz pixel clock +`define H_ACTIVE 600 // pixels +`define H_FRONT_PORCH 16 // pixels +`define H_SYNCH 96 // pixels +`define H_BACK_PORCH 48 // pixels +`define H_TOTAL 800 // pixels + +`define V_ACTIVE 432 // lines +`define V_FRONT_PORCH 11 // lines +`define V_SYNCH 2 // lines +`define V_BACK_PORCH 31 // lines +`define V_TOTAL 524 // lines + +`define CLK_MULTIPLY 2 // 50 * 2/4 = 25.000 MHz +`define CLK_DIVIDE 4 + + +/* +// 640 X 480 @ 60Hz with a 25.175MHz pixel clock +`define H_ACTIVE 640 // pixels +`define H_FRONT_PORCH 16 // pixels +`define H_SYNCH 96 // pixels +`define H_BACK_PORCH 48 // pixels +`define H_TOTAL 800 // pixels + +`define V_ACTIVE 480 // lines +`define V_FRONT_PORCH 11 // lines +`define V_SYNCH 2 // lines +`define V_BACK_PORCH 31 // lines +`define V_TOTAL 524 // lines + +`define CLK_MULTIPLY 2 // 50 * 2/4 = 25.000 MHz +`define CLK_DIVIDE 4 +*/ + Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd (revision 4) @@ -0,0 +1,473 @@ +------------------------------------------------------------------------------ +-- s3e_vga_char_dev.vhd - entity/architecture pair +------------------------------------------------------------------------------ +-- IMPORTANT: +-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. +-- +-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. +-- +-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW +-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION +-- OF THE USER_LOGIC ENTITY. +------------------------------------------------------------------------------ +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------ +-- Filename: s3e_vga_char_dev.vhd +-- Version: 1.00.a +-- Description: Top level design, instantiates IPIF and user logic. +-- Date: Wed Sep 12 16:22:49 2007 (by Create and Import Peripheral Wizard) +-- VHDL Standard: VHDL'93 +------------------------------------------------------------------------------ +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port: "*_i" +-- device pins: "*_pin" +-- ports: "- Names begin with Uppercase" +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC>" +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library proc_common_v2_00_a; +use proc_common_v2_00_a.proc_common_pkg.all; +use proc_common_v2_00_a.ipif_pkg.all; +library opb_ipif_v3_01_c; +use opb_ipif_v3_01_c.all; + +library s3e_vga_char_dev_v1_00_a; +use s3e_vga_char_dev_v1_00_a.all; + +------------------------------------------------------------------------------ +-- Entity section +------------------------------------------------------------------------------ +-- Definition of Generics: +-- C_BASEADDR -- User logic base address +-- C_HIGHADDR -- User logic high address +-- C_OPB_AWIDTH -- OPB address bus width +-- C_OPB_DWIDTH -- OPB data bus width +-- C_USER_ID_CODE -- User ID to place in MIR/Reset register +-- C_FAMILY -- Target FPGA architecture +-- +-- Definition of Ports: +-- OPB_Clk -- OPB Clock +-- OPB_Rst -- OPB Reset +-- Sl_DBus -- Slave data bus +-- Sl_errAck -- Slave error acknowledge +-- Sl_retry -- Slave retry +-- Sl_toutSup -- Slave timeout suppress +-- Sl_xferAck -- Slave transfer acknowledge +-- OPB_ABus -- OPB address bus +-- OPB_BE -- OPB byte enable +-- OPB_DBus -- OPB data bus +-- OPB_RNW -- OPB read/not write +-- OPB_select -- OPB select +-- OPB_seqAddr -- OPB sequential address +------------------------------------------------------------------------------ + +entity s3e_vga_char_dev is + generic + ( + -- ADD USER GENERICS BELOW THIS LINE --------------- + --USER generics added here + -- ADD USER GENERICS ABOVE THIS LINE --------------- + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol parameters, do not add to or delete + C_BASEADDR : std_logic_vector := X"00000000"; + C_HIGHADDR : std_logic_vector := X"0000FFFF"; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_USER_ID_CODE : integer := 3; + C_FAMILY : string := "virtex2p" + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + port + ( + -- ADD USER PORTS BELOW THIS LINE ------------------ + fifty_clock_in : in std_logic; + VGA_HSYNCH : out std_logic; + VGA_VSYNCH : out std_logic; + VGA_OUT_RED : out std_logic; + VGA_OUT_GREEN : out std_logic; + VGA_OUT_BLUE : out std_logic; + -- ADD USER PORTS ABOVE THIS LINE ------------------ + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol ports, do not add to or delete + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sl_errAck : out std_logic; + Sl_retry : out std_logic; + Sl_toutSup : out std_logic; + Sl_xferAck : out std_logic; + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + + attribute SIGIS : string; + attribute SIGIS of OPB_Clk : signal is "Clk"; + attribute SIGIS of OPB_Rst : signal is "Rst"; + +end entity s3e_vga_char_dev; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture IMP of s3e_vga_char_dev is + + ------------------------------------------ + -- Constant: array of address range identifiers + ------------------------------------------ + constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := + ( + 0 => USER_00, -- user logic S/W register address space + 1 => IPIF_RST -- include IPIF S/W Reset/MIR service + ); + + ------------------------------------------ + -- Constant: array of address pairs for each address range + ------------------------------------------ + constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0'); + + constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; + constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; + + constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; + constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; + + constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := + ( + ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address + ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address + ZERO_ADDR_PAD & RST_BASEADDR, -- MIR/Reset register base address + ZERO_ADDR_PAD & RST_HIGHADDR -- MIR/Reset register high address + ); + + ------------------------------------------ + -- Constant: array of data widths for each target address range + ------------------------------------------ + constant USER_DWIDTH : integer := 32; + + constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := + ( + 0 => USER_DWIDTH, -- user logic data width + 1 => C_OPB_DWIDTH -- MIR/Reset register data width + ); + + ------------------------------------------ + -- Constant: array of desired number of chip enables for each address range + ------------------------------------------ + constant USER_NUM_CE : integer := 2; + + constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 0 => pad_power2(USER_NUM_CE), -- user logic number of CEs + 1 => 1 -- MIR/Reset register - 1 CE + ); + + ------------------------------------------ + -- Constant: array of unique properties for each address range + ------------------------------------------ + constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := + ( + 0 => (others => 0), -- user logic slave space dependent properties (none defined) + 1 => (others => 0) -- IPIF reset/mir dependent properties (none defined) + ); + + ------------------------------------------ + -- Constant: pipeline mode + -- 1 = include OPB-In pipeline registers + -- 2 = include IP pipeline registers + -- 3 = include OPB-In and IP pipeline registers + -- 4 = include OPB-Out pipeline registers + -- 5 = include OPB-In and OPB-Out pipeline registers + -- 6 = include IP and OPB-Out pipeline registers + -- 7 = include OPB-In, IP, and OPB-Out pipeline registers + -- Note: + -- only mode 4, 5, 7 are supported for this release + ------------------------------------------ + constant PIPELINE_MODEL : integer := 5; + + ------------------------------------------ + -- Constant: user core ID code + ------------------------------------------ + constant DEV_BLK_ID : integer := C_USER_ID_CODE; + + ------------------------------------------ + -- Constant: enable MIR/Reset register + ------------------------------------------ + constant DEV_MIR_ENABLE : integer := 1; + + ------------------------------------------ + -- Constant: array of IP interrupt mode + -- 1 = Active-high interrupt condition + -- 2 = Active-low interrupt condition + -- 3 = Active-high pulse interrupt event + -- 4 = Active-low pulse interrupt event + -- 5 = Positive-edge interrupt event + -- 6 = Negative-edge interrupt event + ------------------------------------------ + constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 0 => 0 -- not used + ); + + ------------------------------------------ + -- Constant: enable device burst + ------------------------------------------ + constant DEV_BURST_ENABLE : integer := 0; + + ------------------------------------------ + -- Constant: include address counter for burst transfers + ------------------------------------------ + constant INCLUDE_ADDR_CNTR : integer := 0; + + ------------------------------------------ + -- Constant: include write buffer that decouples OPB and IPIC write transactions + ------------------------------------------ + constant INCLUDE_WR_BUF : integer := 0; + + ------------------------------------------ + -- Constant: index for CS/CE + ------------------------------------------ + constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00); + + constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX); + + ------------------------------------------ + -- IP Interconnect (IPIC) signal declarations -- do not delete + -- prefix 'i' stands for IPIF while prefix 'u' stands for user logic + -- typically user logic will be hooked up to IPIF directly via i + -- unless signal slicing and muxing are needed via u + ------------------------------------------ + signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); + signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); + signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); + signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0'); + signal iIP2Bus_Ack : std_logic := '0'; + signal iIP2Bus_Error : std_logic := '0'; + signal iIP2Bus_Retry : std_logic := '0'; + signal iIP2Bus_ToutSup : std_logic := '0'; + signal ENABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- enable posted write behavior + signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping + signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping + signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping + signal iBus2IP_Clk : std_logic; + signal iBus2IP_Reset : std_logic; + signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); + signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); + signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); + signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); + signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); + + ------------------------------------------ + -- Component declaration for verilog user logic + ------------------------------------------ + component user_logic is + generic + ( + -- ADD USER GENERICS BELOW THIS LINE --------------- + --USER generics added here + -- ADD USER GENERICS ABOVE THIS LINE --------------- + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol parameters, do not add to or delete + C_DWIDTH : integer := 32; + C_NUM_CE : integer := 2 + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + port + ( + -- ADD USER PORTS BELOW THIS LINE ------------------ + --USER ports added here + fifty_clock_in : in std_logic; + VGA_HSYNCH : out std_logic; + VGA_VSYNCH : out std_logic; + VGA_OUT_RED : out std_logic; + VGA_OUT_GREEN : out std_logic; + VGA_OUT_BLUE : out std_logic; + -- ADD USER PORTS ABOVE THIS LINE ------------------ + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol ports, do not add to or delete + Bus2IP_Clk : in std_logic; + Bus2IP_Reset : in std_logic; + Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); + Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); + Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); + Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); + IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); + IP2Bus_Ack : out std_logic; + IP2Bus_Retry : out std_logic; + IP2Bus_Error : out std_logic; + IP2Bus_ToutSup : out std_logic + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + end component user_logic; + +begin + + ------------------------------------------ + -- instantiate the OPB IPIF + ------------------------------------------ + OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif + generic map + ( + C_ARD_ID_ARRAY => ARD_ID_ARRAY, + C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, + C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY, + C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, + C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY, + C_PIPELINE_MODEL => PIPELINE_MODEL, + C_DEV_BLK_ID => DEV_BLK_ID, + C_DEV_MIR_ENABLE => DEV_MIR_ENABLE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, + C_DEV_BURST_ENABLE => DEV_BURST_ENABLE, + C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR, + C_INCLUDE_WR_BUF => INCLUDE_WR_BUF + ) + port map + ( + OPB_select => OPB_select, + OPB_DBus => OPB_DBus, + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_RNW => OPB_RNW, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sl_DBus, + Sln_xferAck => Sl_xferAck, + Sln_errAck => Sl_errAck, + Sln_retry => Sl_retry, + Sln_toutSup => Sl_toutSup, + Bus2IP_CS => open, + Bus2IP_CE => open, + Bus2IP_RdCE => iBus2IP_RdCE, + Bus2IP_WrCE => iBus2IP_WrCE, + Bus2IP_Data => iBus2IP_Data, + Bus2IP_Addr => open, + Bus2IP_AddrValid => open, + Bus2IP_BE => iBus2IP_BE, + Bus2IP_RNW => open, + Bus2IP_Burst => open, + IP2Bus_Data => iIP2Bus_Data, + IP2Bus_Ack => iIP2Bus_Ack, + IP2Bus_AddrAck => '0', + IP2Bus_Error => iIP2Bus_Error, + IP2Bus_Retry => iIP2Bus_Retry, + IP2Bus_ToutSup => iIP2Bus_ToutSup, + IP2Bus_PostedWrInh => ENABLE_POSTED_WRITE, + IP2RFIFO_Data => ZERO_IP2RFIFO_Data, + IP2RFIFO_WrMark => '0', + IP2RFIFO_WrRelease => '0', + IP2RFIFO_WrReq => '0', + IP2RFIFO_WrRestore => '0', + RFIFO2IP_AlmostFull => open, + RFIFO2IP_Full => open, + RFIFO2IP_Vacancy => open, + RFIFO2IP_WrAck => open, + IP2WFIFO_RdMark => '0', + IP2WFIFO_RdRelease => '0', + IP2WFIFO_RdReq => '0', + IP2WFIFO_RdRestore => '0', + WFIFO2IP_AlmostEmpty => open, + WFIFO2IP_Data => ZERO_WFIFO2IP_Data, + WFIFO2IP_Empty => open, + WFIFO2IP_Occupancy => open, + WFIFO2IP_RdAck => open, + IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent, + IP2INTC_Irpt => open, + Freeze => '0', + Bus2IP_Freeze => open, + OPB_Clk => OPB_Clk, + Bus2IP_Clk => iBus2IP_Clk, + IP2Bus_Clk => '0', + Reset => OPB_Rst, + Bus2IP_Reset => iBus2IP_Reset + ); + + ------------------------------------------ + -- instantiate the User Logic + ------------------------------------------ + USER_LOGIC_I : component user_logic + generic map + ( + -- MAP USER GENERICS BELOW THIS LINE --------------- + --USER generics mapped here + -- MAP USER GENERICS ABOVE THIS LINE --------------- + + C_DWIDTH => USER_DWIDTH, + C_NUM_CE => USER_NUM_CE + ) + port map + ( + -- MAP USER PORTS BELOW THIS LINE ------------------ + --USER ports mapped here + fifty_clock_in => fifty_clock_in, + VGA_HSYNCH => VGA_HSYNCH, + VGA_VSYNCH => VGA_VSYNCH, + VGA_OUT_RED => VGA_OUT_RED, + VGA_OUT_GREEN => VGA_OUT_GREEN, + VGA_OUT_BLUE => VGA_OUT_BLUE, + -- MAP USER PORTS ABOVE THIS LINE ------------------ + + Bus2IP_Clk => iBus2IP_Clk, + Bus2IP_Reset => iBus2IP_Reset, + Bus2IP_Data => uBus2IP_Data, + Bus2IP_BE => uBus2IP_BE, + Bus2IP_RdCE => uBus2IP_RdCE, + Bus2IP_WrCE => uBus2IP_WrCE, + IP2Bus_Data => uIP2Bus_Data, + IP2Bus_Ack => iIP2Bus_Ack, + IP2Bus_Retry => iIP2Bus_Retry, + IP2Bus_Error => iIP2Bus_Error, + IP2Bus_ToutSup => iIP2Bus_ToutSup + ); + + ------------------------------------------ + -- hooking up signal slicing + ------------------------------------------ + uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); + uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); + uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); + uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1); + iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; + +end IMP; Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.pao =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.pao (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.pao (revision 4) @@ -0,0 +1,50 @@ +############################################################################## +## Filename: D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Wed Sep 12 16:22:49 2007 (by Create and Import Peripheral Wizard) +############################################################################## + +lib proc_common_v2_00_a proc_common_pkg vhdl +lib proc_common_v2_00_a family vhdl +lib proc_common_v2_00_a or_muxcy vhdl +lib proc_common_v2_00_a or_gate vhdl +lib proc_common_v2_00_a counter_bit vhdl +lib proc_common_v2_00_a counter vhdl +lib proc_common_v2_00_a inferred_lut4 vhdl +lib proc_common_v2_00_a srl_fifo2 vhdl +lib proc_common_v2_00_a pf_counter_bit vhdl +lib proc_common_v2_00_a pf_counter vhdl +lib proc_common_v2_00_a pf_counter_top vhdl +lib proc_common_v2_00_a pf_occ_counter vhdl +lib proc_common_v2_00_a pf_occ_counter_top vhdl +lib proc_common_v2_00_a pf_adder_bit vhdl +lib proc_common_v2_00_a pf_adder vhdl +lib proc_common_v2_00_a pf_dpram_select vhdl +lib proc_common_v2_00_a srl16_fifo vhdl +lib proc_common_v2_00_a pselect vhdl +lib proc_common_v2_00_a valid_be vhdl +lib proc_common_v2_00_a ld_arith_reg vhdl +lib proc_common_v2_00_a mux_onehot vhdl +lib proc_common_v2_00_a down_counter vhdl +lib proc_common_v2_00_a ipif_pkg vhdl +lib proc_common_v2_00_a ipif_steer vhdl +lib proc_common_v2_00_a direct_path_cntr_ai vhdl +lib interrupt_control_v1_00_a interrupt_control vhdl +lib wrpfifo_v1_01_b pf_dly1_mux vhdl +lib wrpfifo_v1_01_b ipif_control_wr vhdl +lib wrpfifo_v1_01_b wrpfifo_dp_cntl vhdl +lib wrpfifo_v1_01_b wrpfifo_top vhdl +lib rdpfifo_v1_01_b ipif_control_rd vhdl +lib rdpfifo_v1_01_b rdpfifo_dp_cntl vhdl +lib rdpfifo_v1_01_b rdpfifo_top vhdl +lib opb_ipif_v3_01_c reset_mir vhdl +lib opb_ipif_v3_01_c brst_addr_cntr vhdl +lib opb_ipif_v3_01_c opb_flex_addr_cntr vhdl +lib opb_ipif_v3_01_c brst_addr_cntr_reg vhdl +lib opb_ipif_v3_01_c opb_be_gen vhdl +lib opb_ipif_v3_01_c srl_fifo3 vhdl +lib opb_ipif_v3_01_c write_buffer vhdl +lib opb_ipif_v3_01_c opb_bam vhdl +lib opb_ipif_v3_01_c opb_ipif vhdl +lib s3e_vga_char_dev_v1_00_a user_logic verilog +lib s3e_vga_char_dev_v1_00_a s3e_vga_char_dev vhdl Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.mpd =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.mpd (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/s3e_vga_char_dev_v2_1_0.mpd (revision 4) @@ -0,0 +1,51 @@ +################################################################### +## +## Name : s3e_vga_char_dev +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN s3e_vga_char_dev + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = MIXED +OPTION IP_GROUP = MICROBLAZE:PPC:USER +OPTION DESC = S3E_VGA_CHAR_DEV + + +## Bus Interfaces +BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR +PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR +PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB, ASSIGNMENT = CONSTANT +PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB, RANGE = (8, 16, 32) +PARAMETER C_USER_ID_CODE = 3, DT = INTEGER, RANGE = (0:255) +PARAMETER C_FAMILY = virtex2p, DT = STRING + +## Ports +PORT fifty_clock_in = "", DIR = I, SIGIS = Clk +PORT VGA_HSYNCH = "", DIR = O +PORT VGA_VSYNCH = "", DIR = O +PORT VGA_OUT_RED = "", DIR = O +PORT VGA_OUT_GREEN = "", DIR = O +PORT VGA_OUT_BLUE = "", DIR = O +PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB +PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB +PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB +PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB +PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB +PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB +PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB +PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB +PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB +PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB +PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB +PORT OPB_select = OPB_select, DIR = I, BUS = SOPB +PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB + +END Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/_s3e_vga_char_dev_xst.prj =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/_s3e_vga_char_dev_xst.prj (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/data/_s3e_vga_char_dev_xst.prj (revision 4) @@ -0,0 +1,54 @@ +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" +vhdl interrupt_control_v1_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/user_logic.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/CHAR_DISPLAY.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/CHAR_GEN.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/CHAR_GEN_ROM.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/CHAR_RAM.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/CLOCK_GEN.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/HEX_2_ASCII.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/MAIN.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/SVGA_DEFINES.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/SVGA_TIMING_GENERATION.v" +verilog s3e_vga_char_dev_v1_00_a "../hdl/verilog/VIDEO_OUT.v" +vhdl s3e_vga_char_dev_v1_00_a "../hdl/vhdl/s3e_vga_char_dev.vhd" Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise (revision 4)

opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.restore (revision 4) @@ -0,0 +1,1345 @@ +# Project Navigator Project Restoration Script +# +# WARNING: Do not modify this file. Any alteration of this file is not +# supported and will likely cause project restoration to fail. The +# format and the contents will be modified without further notice. +# +# This script can be used to recreate the associated project. To use this script, +# source it in a Xilinx Tcl shell, such as xtclsh or the Project Navigator Tcl +# Shell tab, and call the 'restore' proc. Restore takes the project directory as +# an optional argument. Pass in the project directory if it is different than the +# current working directory, otherwise don't pass in anything. +# +# Example: +# In this example the project is in the directory "./projects/m_project_dir". +# +# source ./projects/m_project_dir/my_project.restore +# restore ./projects/m_project_dir +# +# Example: +# In this example the project is in the current working directory. +# +# source my_project.restore +# restore +# +# Note that restoring a project this way has the following limitations: +# - Process status will not be restored. +# - A root-level source will be set as "Top", even if a lower-level source had +# previously been set as "Top". +# - Sources with non-default Design View associations will revert to the default +# association. +# - Snapshots will not be restored. +# +# The project which failed to load will be backed up as .fail. +# Please open a Technical Support WebCase at +# www.xilinx.com/support/clearexpress/websupport.htm and submit this file, along +# with the project source files, for evaluation. +# +# Copyright 2007, Xilinx, Inc. + + +proc ERR { msg } { + puts "ERROR: $msg" +} + +proc WARN { msg } { + puts "WARNING: $msg" +} + +proc INFO { msg } { + puts "$msg" +} + +# Helper that returns 1 if the string is blank, otherwise 0. +proc IsBlank { str } { + if { [string length $str] == 0 } { + return 1 + } + return 0 +} + +# Helper for determining whether a value is 'NULL'. +# Returns 1 if the value is 0; returns 0 if the value is anything else. +proc IsNull { val } { + if { $val == 0 } { + return 1 + } + return 0 +} + +proc HandleException { script { msg "" } } { + set catch_result [catch { + uplevel 1 $script + } RESULT] + if {$catch_result} { + if {![IsBlank $msg]} { + ERR $msg + } + INFO "$RESULT" + INFO "$::errorInfo" + } +} + +# These two procs help to load shared libraries in a platform +# independent way. +proc _LoadLibrary {name} { + set libExt [info sharedlibextension] + set libFullName "$name$libExt" + HandleException { + load $libFullName + } "A problem occured loading library $libFullName." +} + +proc _LoadFactoryLibrary {Factory} { + HandleException { + Xilinx::Cit::FactoryLoad $Factory + } "A problem occured loading library $Factory." +} + +_LoadLibrary libCit_CoreStub +_LoadLibrary libPrjrep_CommonStub +_LoadFactoryLibrary libPrjrep_Common +_LoadLibrary libDpm_SupportStub +_LoadLibrary libDpm_PnfStub +_LoadLibrary libDpm_DefnDataStub +_LoadLibrary libDpm_DesignDataStub +_LoadLibrary libDpm_HdlStub +_LoadLibrary libPrjrep_RepositoryStub +_LoadLibrary libCitI_CoreStub +_LoadLibrary libHdcI_HdcHDProjectStub +_LoadLibrary libTcltaskI_TaskStub +_LoadLibrary libCommonI_CommonStub +_LoadFactoryLibrary libTcltask_Helpers +_LoadFactoryLibrary libHdcC_HDProject +_LoadLibrary libHdcI_HdcContainerStub + +# Helper to exectute code only when the (pointer) variable name is valid. +proc OnOkPtr { var_name script } { + if { [ uplevel info exists $var_name ] } { + upvar $var_name var + if { $var != 0 } { return [ uplevel $script ] } + } +} + +# Helper to exectute code only when the (pointer) variable name is 0. +proc OnNullPtr { var_name script } { + if { [ uplevel info exists $var_name ] } { + upvar $var_name var + if { $var == 0 } { return [ uplevel $script ] } + } +} + +# Helper to exectute code only when the value of variable name is 1. +proc OnSuccess { var_name script } { + if { $val != 0 } { return [ uplevel $script ] } +} + +# Helper to exectute code only when the value of variable name is 0. +proc OnFail { val script } { + if { $val != 1 } { return [ uplevel $script ] } +} + +# Helper to get a component interface. +proc GetInterface { iUnk id { name "" } } { + if {$iUnk == 0} { return 0 } + set iIface [ $iUnk GetInterface $id ] + OnNullPtr iIface { + if {![IsBlank $name]} { + ERR " Could not get the \"$name\" interface." + } + } + return $iIface +} + +# Helper to create a component and return one of its interfaces. +proc CreateComponent { compId ifaceId { name "" } } { + set iUnk [ ::Xilinx::Cit::FactoryCreate $compId ] + set iIface [ GetInterface $iUnk $ifaceId ] + OnNullPtr iIface { + if {![IsBlank $name]} { ERR "Could not create a \"$name\" component." } + } + return $iIface +} + +# Helper to release an object +proc Release { args } { + foreach iUnk $args { + set i_refcount [ GetInterface $iUnk $::xilinx::Prjrep::IRefCountID ] + OnNullPtr i_refcount { set i_refcount [ GetInterface $iUnk $::xilinx::CommonI::IRefCountID ] } + OnOkPtr i_refcount { $i_refcount Release } + } +} + +# Helper to loop over IIterator based pointers. +proc ForEachIterEle { _ele_var_name _iter script } { + if {$_iter == 0} { return 0 } + upvar $_ele_var_name ele + for { $_iter First } { ![ $_iter IsEnd ] } { $_iter Next } { + set ele [ $_iter CurrentItem ] + set returned_val [ uplevel $script ] + } +} + +# Helper to get the Tcl Project Manager, if possible. +proc GetTclProjectMgr { } { + set TclProjectMgrId "{7d528480-1196-4635-aba9-639446e4aa59}" + set iUnk [ Xilinx::CitP::CreateComponent $TclProjectMgrId ] + if {$iUnk == 0} { return 0 } + set iTclProjectMgr [ $iUnk GetInterface $::xilinx::TcltaskI::ITclProjectMgrID ] + OnNullPtr iTclProjectMgr { + ERR "Could not create a \"TclProjectMgr\" component." + } + return $iTclProjectMgr +} + +# Helper to get the current Tcl Project, if one is open. +proc GetCurrentTclProject { } { + set iTclProject 0 + set iTclProjectMgr [GetTclProjectMgr] + OnOkPtr iTclProjectMgr { + set errmsg "" + $iTclProjectMgr GetCurrentTclProject iTclProject errmsg + } + return $iTclProject +} + +# Helper to get the current HDProject, if one is open. +proc GetCurrentHDProject { } { + set iHDProject 0 + set iTclProjectMgr [GetTclProjectMgr] + set errmsg "" + OnOkPtr iTclProjectMgr { $iTclProjectMgr GetCurrentHDProject iHDProject errmsg } + OnNullPtr iHDProject { + ERR "Could not get the current HDProject." + } + return $iHDProject +} + +# Helper to create a Project Helper. +proc GetProjectHelper { } { + set ProjectHelperID "{0725c3d2-5e9b-4383-a7b6-a80c932eac21}" + set iProjHelper [CreateComponent $ProjectHelperID $::xilinx::Dpm::IProjectHelperID "Project Helper"] + return $iProjHelper +} + +# Helper to find out if a project is currently open. +# Returns 1 if a project is open, otherwise 0. +proc IsProjectOpen { } { + set iTclProject [GetCurrentTclProject] + set isOpen [expr {$iTclProject != 0}] + Release $iTclProject + return $isOpen +} + +# Helper to return the lock file for the specified project if there is one. +# Returns an empty string if there is no lock file on the specified project. +# This assumes that the project_file is in the current directory. +# It also assumes project_file does not have a path. +proc GetProjectLockFile { project_file } { + INFO "Checking for a lock file for \"$project_file\"." + set lock_file "__ISE_repository_${project_file}_.lock" + if { [ file isfile "$lock_file" ] } { + return $lock_file + } + return +} + +# Helper to move aside the project file. +# This assumes that the project_file is in the current directory. +proc MoveProject { project_file backup_file } { + INFO "Moving aside the project \"$project_file\" so that it can be recreated." + INFO "The project will be backed up as \"$backup_file\"." + if { ![ file isfile "$project_file" ] } { + WARN "Could not move \"$project_file\"; it does not exist or is not a file." + return 1 + } + file rename -force "$project_file" "$backup_file" + # We will need to bail if the project still exists. + if { [ file isfile "$project_file" ] } { + ERR "Could not remove \"$project_file\"; unable to recreate the project.." + return 0 + } + return 1 +} + +# Helper to open a project and return a project facilitator (pointer). +proc OpenFacilProject { project_name } { + # first make sure the tcl project mgr singleton exists + GetTclProjectMgr + # get a Project Helper and open the project. + set iProjHelper [GetProjectHelper] + if {$iProjHelper == 0} { return 0 } + set result [$iProjHelper Open $project_name] + OnFail $result { + if {$result == 576460769483292673} { + ERR "Could not open the project \"$project_name\" because it is locked." + } else { + ERR "Could not open the \"$project_name\" project." + } + Release $iProjHelper + set iProjHelper 0 + } + return $iProjHelper +} + +# Helper to close and release a project. +proc CloseFacilProject { iProjHelper } { + if {$iProjHelper == 0} { return } + $iProjHelper Close + Release $iProjHelper +} + +# Helper to get the Project from the Project Helper. +# Clients must release this. +proc GetProject { iProjHelper } { + if {$iProjHelper == 0} { return 0 } + set dpm_project 0 + $iProjHelper GetDpmProject dpm_project + set iProject [ GetInterface $dpm_project $xilinx::Dpm::IProjectID ] + OnNullPtr iProject { + ERR "Could not get the Project from the Project Helper." + } + return $iProject +} + +# Helper to get the File Manager from the Project Helper. +# Clients must release this. +proc GetFileManager { iProjHelper } { + set iProject [GetProject $iProjHelper] + set iFileMgr [ GetInterface $iProject $xilinx::Dpm::IFileManagerID ] + OnNullPtr iFileMgr { + ERR "Could not get the File Manager from the Project Helper." + } + # Don't release the project here, clients will release it + # when they release its IFileManager interface. + return $iFileMgr +} + +# Helper to get the Source Library Manager from the Project Helper. +# Clients must release this. +proc GetSourceLibraryManager { iProjHelper } { + set iProject [GetProject $iProjHelper] + set iSourceLibraryMgr [ GetInterface $iProject $xilinx::Dpm::ISourceLibraryManagerID ] + OnNullPtr iSourceLibraryMgr { + ERR "Could not get the Source Library Manager from the Project Helper." + } + # Don't release the project here, clients will release it + # when they release its IFileManager interface. + return $iSourceLibraryMgr +} + +# Helper to get the ProjSrcHelper from the Project Helper. +# Clients must NOT release this. +proc GetProjSrcHelper { iProjHelper } { + set iSrcHelper [ GetInterface $iProjHelper $::xilinx::Dpm::IProjSrcHelperID IProjSrcHelper ] + OnNullPtr iSrcHelper { + ERR "Could not get the ProjSrcHelper from the Project Helper." + } + return $iSrcHelper +} + +# Helper to get the ScratchPropertyManager from the Project Helper. +# Clients must NOT release this. +proc GetScratchPropertyManager { iProjHelper } { + set iPropTableFetch [ GetInterface $iProjHelper $xilinx::Dpm::IPropTableFetchID IPropTableFetch ] + set prop_table_comp 0 + OnOkPtr iPropTableFetch { + $iPropTableFetch GetPropTable prop_table_comp + } + set iScratch [ GetInterface $prop_table_comp $xilinx::Dpm::IScratchPropertyManagerID ] + OnNullPtr iScratch { + ERR "Could not get the Scratch Property Manager from the Project Helper." + } + return $iScratch +} + +# Helper to get the Design from the Project Helper. +# Clients must release this. +proc GetDesign { iProjHelper } { + set iProject [GetProject $iProjHelper] + set iDesign 0 + OnOkPtr iProject { $iProject GetDesign iDesign } + OnNullPtr iDesign { + ERR "Could not get the Design from the Project Helper." + } + Release $iProject + return $iDesign +} + +# Helper to get the Data Store from the Project Helper. +# Clients must NOT release this. +proc GetDataStore { iProjHelper } { + set iDesign [ GetDesign $iProjHelper] + set iDataStore 0 + OnOkPtr iDesign { $iDesign GetDataStore iDataStore } + OnNullPtr iDataStore { + ERR "Could not get the Data Store from the Project Helper." + } + Release $iDesign + return $iDataStore +} + +# Helper to get the View Manager from the Project Helper. +# Clients must NOT release this. +proc GetViewManager { iProjHelper } { + set iDesign [ GetDesign $iProjHelper] + set iViewMgr [ GetInterface $iDesign $xilinx::Dpm::IViewManagerID ] + OnNullPtr iViewMgr { + ERR "Could not get the View Manager from the Project Helper." + } + # Don't release the design here, clients will release it + # when they release its IViewManager interface. + return $iViewMgr +} + +# Helper to get the Property Manager from the Project Helper. +# Clients must release this. +proc GetPropertyManager { iProjHelper } { + set iDesign [ GetDesign $iProjHelper] + set iPropMgr 0 + OnOkPtr iDesign { $iDesign GetPropertyManager iPropMgr } + OnNullPtr iPropMgr { + ERR "Could not get the Property Manager from the Project Helper." + } + Release $iDesign + return $iPropMgr +} + +# Helper to find a property template, based on prop_name +# Clients must NOT release this. +proc GetPropertyTemplate { iProjHelper prop_name } { + set iPropTempl 0 + set iUnk 0 + set iDefdataId 0 + set iPropTemplStore 0 + set iDataStore [GetDataStore $iProjHelper] + OnOkPtr iDataStore { $iDataStore GetComponentByName $prop_name iUnk } + OnOkPtr iUnk { set iDefdataId [ GetInterface $iUnk $xilinx::Dpm::IDefDataIdID IDefDataId ] } + OnOkPtr iDefdataId { + set iPropTemplStore [ GetInterface $iDataStore $xilinx::Dpm::IPropertyTemplateStoreID IPropertyTemplateStore ] + } + OnOkPtr iPropTemplStore { $iPropTemplStore GetPropertyTemplate $iDefdataId iPropTempl } + OnNullPtr iPropTempl { + WARN "Could not get the property template for \"$prop_name\"." + } + return $iPropTempl +} + +# Helper to get a component's name. +proc GetName { iUnk } { + set name "" + set iName [ GetInterface $iUnk $xilinx::Prjrep::INameID IName ] + OnOkPtr iName { $iName GetName name } + return $name +} + +# Helper to get the name of a view's type. +proc GetViewTypeName { iView } { + set typeName "" + set iType 0 + set iDefdataType 0 + OnOkPtr iView { $iView GetType iType } + OnOkPtr iType { + set iDefdataType [ GetInterface $iType $xilinx::Dpm::IDefDataIdID IDefDataId ] + } + OnOkPtr iDefdataType { $iDefdataType GetID typeName } + return $typeName +} + +# Helper to find a view and return its context. +# Must clients release this? +proc GetViewContext { iProjHelper view_id view_name } { + # Simply return if the view_id or view_name is empty. + if { [IsBlank $view_id] || [IsBlank $view_name] } { return 0 } + set foundview 0 + set viewiter 0 + set iViewMgr [GetViewManager $iProjHelper] + OnOkPtr iViewMgr { $iViewMgr GetViews viewiter } + ForEachIterEle view $viewiter { + set typeName [GetViewTypeName $view] + set name [GetName $view] + if { [ string equal $name $view_name ] && [ string equal $view_id $typeName ] } { + set foundview $view + } + } + set context [ GetInterface $foundview $xilinx::Dpm::IPropertyContextID ] + OnNullPtr context { + WARN "Could not get the context for view \"$view_id\":\"$view_name\"." + } + return $context +} + +# Helper to get a string property instance from the property manager. +proc GetStringPropertyInstance { iProjHelper simple_id } { + set iPropMgr [GetPropertyManager $iProjHelper] + if {$iPropMgr == 0} { return 0 } + set iPropInst 0 + $iPropMgr GetStringProperty $simple_id iPropInst + OnNullPtr iPropInst { WARN "Could not get the string property instance $simple_id." } + Release $iPropMgr + return $iPropInst +} + +# Helper to get a property instance from the property manager. +proc GetPropertyInstance { iProjHelper view_name view_id prop_name } { + set iPropInst 0 + set iPropTempl [ GetPropertyTemplate $iProjHelper $prop_name ] + if {$iPropTempl == 0} { return 0 } + set context [ GetViewContext $iProjHelper $view_id $view_name ] + set iPropMgr [GetPropertyManager $iProjHelper] + if {$iPropMgr == 0} { return 0 } + $iPropMgr GetPropertyInstance $iPropTempl $context iPropInst + OnNullPtr iPropInst { + if { ![IsBlank $view_id] && ![IsBlank $view_name] } { + WARN "Could not get the context sensitive property instance $prop_name." + } else { + WARN "Could not get the property instance $prop_name." + } + } + Release $iPropMgr + return $iPropInst +} + +# Helper to store properties back into the property manager. +proc RestoreProcessProperties { iProjHelper process_props } { + INFO "Restoring process properties" + foreach { unused view_name view_id simple_id prop_name prop_val } $process_props { + set iPropInst 0 + if {![IsBlank $simple_id]} { + set iPropInst [ GetStringPropertyInstance $iProjHelper $simple_id ] + } else { + set iPropInst [ GetPropertyInstance $iProjHelper $view_name $view_id $prop_name ] + } + OnOkPtr iPropInst { + OnFail [ $iPropInst SetStringValue "$prop_val" ] { + WARN "Could not set the value of the $prop_name property to \"$prop_val\"." + } + } + Release $iPropInst + } +} + +# Helper to recreate partitions from the variable name with +# a list of instance names. +proc RestorePartitions { namelist } { + INFO "Restoring partitions." + set iHDProject [ GetCurrentHDProject ] + OnOkPtr iHDProject { + foreach name $namelist { + set iPartition [ $iHDProject CreatePartition "$name" ] + } + } +} + +# Helper to create and populate a library +# +proc CreateLibrary { iProjHelper libname filelist } { + + set iLibMgr [ GetSourceLibraryManager $iProjHelper ] + set iFileMgr [ GetFileManager $iProjHelper ] + + if {$iLibMgr == 0} { return 0 } + if {$iFileMgr == 0} { return 0 } + + $iLibMgr CreateSourceLibrary "libname" ilib + + OnOkPtr ilib { + foreach filename $filelist { + set argfile [ file normalize "$filename" ] + set found 0 + set fileiter 0 + $iFileMgr GetFiles fileiter + ForEachIterEle ifile $fileiter { + set path "" + set file "" + $ifile getPath path file + set currentfile [ file normalize [ file join "$path" "$file" ] ] + if { $currentfile == $argfile } { + set found 1 + $ilib AddFile ifile + break + } + } + OnNullPtr found { + WARN "Could not add the file \"$filename\" to the library \"$libname\"." + } + } + } +} + +# Helper to create source libraries and populate them. +proc RestoreSourceLibraries { iProjHelper libraries } { + INFO "Restoring source libraries." + foreach { libname filelist } $libraries { + CreateLibrary $iProjHelper "$libname" $filelist + } +} + +# Helper to add user files to the project using the PnF. +proc AddUserFiles { iProjHelper files } { + INFO "Adding User files." + set iconflict 0 + set iSrcHelper [ GetProjSrcHelper $iProjHelper ] + if {$iSrcHelper == 0} { return 0 } + foreach filename $files { + INFO "Adding the file \"$filename\" to the project." + set result [$iSrcHelper AddSourceFile "$filename" iconflict] + OnFail $result { + if {$result == 6} { + INFO "The file \"$filename\" is already in the project." + } else { + ERR "A problem occurred adding the file \"$filename\" to the project." + } + } + } +} + +# Helper to add files to the project and set their origination. +# Valid origination values are: +# 0 - User +# 1 - Generated +# 2 - Imported +# Files of origination "User" are added through the facilitator, +# otherwise they are added directly to the File Manager. +proc AddImportedFiles { iProjHelper files origination } { + switch $origination { + 0 { INFO "Adding User files." } + 1 { INFO "Adding Generated files." } + 2 { INFO "Adding Imported files." } + default { + ERR "Invalid parameter: origination was set to \"$origination\", but may only be 0, 1, or 2." + return 0 + } + } + set iFileMgr [ GetFileManager $iProjHelper ] + if {$iFileMgr == 0} { return 0 } + foreach filename $files { + set file_type 0 + set hdl_file 0 + set result [$iFileMgr AddFile "$filename" $file_type hdl_file] + OnFail $result { + if {$result == 6} { + INFO "The file \"$filename\" is already in the project." + } elseif { $hdl_file == 0 } { + ERR "A problem occurred adding the file \"$filename\" to the project." + } + } + OnOkPtr hdl_file { + set ifile [ GetInterface $hdl_file $xilinx::Dpm::IFileID IFile ] + OnOkPtr ifile { + set result [ $ifile SetOrigination $origination ] + if {$result != 1} { + ERR "A problem occurred setting the origination of \"$filename\" to \"$origination\"." + } + Release $ifile + } + } + } + return 1 +} + +proc RestoreProjectSettings { iProjHelper project_settings } { + INFO "Restoring device settings" + set iScratch [GetScratchPropertyManager $iProjHelper] + set iPropIter 0 + set iPropSet [ GetInterface $iScratch $xilinx::Dpm::IPropertyNodeSetID IPropertyNodeSet ] + OnOkPtr iPropSet { + $iPropSet GetIterator iPropIter + } + set index 0 + set lastindex [llength $project_settings] + ForEachIterEle prop_node $iPropIter { + set prop_instance 0 + $prop_node GetPropertyInstance prop_instance + if { $index < $lastindex } { + set argname [ lindex $project_settings $index ] + set argvalue [ lindex $project_settings [ expr $index + 1 ] ] + } else { + set argname {} + set argvalue {} + } + if { $prop_instance != 0 } { + set name {} + $prop_instance GetName name + if { [string equal $name $argname ] } { + $prop_instance SetStringValue $argvalue + incr index + incr index + } + } + Release $prop_instance + } + $iScratch Commit + # initialize + $iProjHelper Init +} + +# Helper to load a source control configuration from a stream +# and then store it back into an ise file. +proc RestoreSourceControlOptions { prjfile istream } { + INFO "Restoring source control options" + set config_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlConfigurationCompID ] + OnOkPtr config_comp { set ipersist [ $config_comp GetInterface $xilinx::Prjrep::IPersistID ] } + OnOkPtr config_comp { set igetopts [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IGetOptionsID ] } + set helper_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlHelpCompID ] + OnOkPtr helper_comp { set ihelper [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IHelperID ] } + OnOkPtr ipersist { $ipersist Load istream } + OnOkPtr ihelper { OnOkPtr igetopts { $ihelper SaveOptions $prjfile $igetopts } } + Release $helper_comp $config_comp +} + +# Call this proc to restore the ISE project. +proc restore { { project_dir "" } } { + set script_file "s3e_vga_char_dev.restore" + set project_file "s3e_vga_char_dev.ise" + set backup_file "s3e_vga_char_dev.fail" + set old_working_dir [pwd] + # Make sure a project isn't already open. + if {[IsProjectOpen]} { + ERR "The project must be closed before performing this operation." + cd $old_working_dir + return + } + # If a project directory was supplied, cd into it. + if {![IsBlank $project_dir]} { + cd $project_dir + } + # Make sure the project file exists. + if { ![ file isfile "$project_file" ] } { + ERR "Could not find the project file \"$project_file\". You must be in the project directory to perform this operation." + cd $old_working_dir + return + } + # Make sure the project isn't locked. + set lock_file [GetProjectLockFile $project_file] + if { ![IsBlank "$lock_file" ] } { + ERR "Could not restore the project \"$project_name\" because it is locked." + INFO "Please remove the lock file \"$lock_file\" and try again." + cd $old_working_dir + return + } + # Backup this script because it will be overwritten the next time + # the project is saved, which happens right after it is created! + file copy -force "$script_file" "${script_file}.last" + # Back up the project and remove the project file, since it can't be opened. + OnFail [ MoveProject "$project_file" "$backup_file" ] { + cd $old_working_dir + return + } + + # Open the project. + HandleException { + set iProjHelper [ OpenFacilProject "$project_file"] + } "A problem occurred while creating the project \"$project_file\"." + if {$iProjHelper == 0} { + cd $old_working_dir + return + } + INFO "Recreating project \"$project_file\"." + set project_settings { + "PROP_DevFamily" "Virtex2P" + "PROP_DevDevice" "xc2vp7" + "PROP_DevPackage" "fg456" + "PROP_DevSpeed" "-6" + "PROP_Top_Level_Module_Type" "HDL" + "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" + "PROP_Simulator" "Modelsim-SE Mixed" + "PROP_PreferredLanguage" "Verilog" + "PROP_Enable_Message_Capture" "true" + "PROP_Enable_Message_Filtering" "false" + "PROP_Enable_Incremental_Messaging" "false" + } + + HandleException { + RestoreProjectSettings $iProjHelper $project_settings + } "A problem occured while restoring project settings." + + set user_files { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" + "../../hdl/verilog/user_logic.v" + "../../hdl/vhdl/s3e_vga_char_dev.vhd"} + + HandleException { + AddUserFiles $iProjHelper $user_files + } "A problem occured while restoring user files." + + set imported_files {} + + set origination 2 + + HandleException { + AddImportedFiles $iProjHelper $imported_files $origination + } "A problem occured while restoring imported files." + + set process_props { + "A" "" "" "" "PROPEXT_SynthMultStyle_virtex2" "Auto" + "A" "" "" "" "PROPEXT_xilxBitgCfg_DCIUpdateMode_virtex2p" "As Required" + "A" "" "" "" "PROPEXT_xilxBitgCfg_TDO_virtex2p" "Float" + "A" "" "" "" "PROPEXT_xilxBitgStart_Clk_Done_virtex2p" "Default (4)" + "A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex2" "4" + "A" "" "" "" "PROPEXT_xilxSynthAddBufg_virtex2" "16" + "A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex2" "500" + "A" "" "" "" "PROP_CPLDFitkeepio" "false" + "A" "" "" "" "PROP_CompxlibAbelLib" "true" + "A" "" "" "" "PROP_CompxlibCPLDDetLib" "true" + "A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" "" + "A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX//" + "A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite" + "A" "" "" "" "PROP_CompxlibSimPath" "Search in Path" + "A" "" "" "" "PROP_CompxlibSimPrimatives" "true" + "A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true" + "A" "" "" "" "PROP_CurrentFloorplanFile" "" + "A" "" "" "" "PROP_DesignName" "s3e_vga_char_dev" + "A" "" "" "" "PROP_Dummy" "dum1" + "A" "" "" "" "PROP_EnableWYSIWYG" "None" + "A" "" "" "" "PROP_Enable_Incremental_Messaging" "false" + "A" "" "" "" "PROP_Enable_Message_Capture" "true" + "A" "" "" "" "PROP_Enable_Message_Filtering" "false" + "A" "" "" "" "PROP_FunctionBlockInputLimit" "38" + "A" "" "" "" "PROP_ISimLibSearchOrderFile" "" + "A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time" + "A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false" + "A" "" "" "" "PROP_ISimUutInstName" "UUT" + "A" "" "" "" "PROP_ImpactProjectFile" "" + "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time" + "A" "" "" "" "PROP_ModelSimUseConfigName" "false" + "A" "" "" "" "PROP_Parse_Target" "synthesis" + "A" "" "" "" "PROP_PartitionCreateDelete" "" + "A" "" "" "" "PROP_PartitionForcePlacement" "" + "A" "" "" "" "PROP_PartitionForceSynth" "" + "A" "" "" "" "PROP_PartitionForceTranslate" "" + "A" "" "" "" "PROP_PlsClockEnable" "true" + "A" "" "" "" "PROP_PostTrceFastPath" "false" + "A" "" "" "" "PROP_PreTrceFastPath" "false" + "A" "" "" "" "PROP_SimDo" "true" + "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false" + "A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false" + "A" "" "" "" "PROP_SimModelOtherNetgenOpts" "" + "A" "" "" "" "PROP_SimModelRetainHierarchy" "true" + "A" "" "" "" "PROP_SimUseCustom_behav" "false" + "A" "" "" "" "PROP_SimUseCustom_postMap" "false" + "A" "" "" "" "PROP_SimUseCustom_postPar" "false" + "A" "" "" "" "PROP_SimUseCustom_postXlate" "false" + "A" "" "" "" "PROP_SynthCaseImplStyle" "None" + "A" "" "" "" "PROP_SynthDecoderExtract" "true" + "A" "" "" "" "PROP_SynthEncoderExtract" "Yes" + "A" "" "" "" "PROP_SynthExtractMux" "Yes" + "A" "" "" "" "PROP_SynthExtractRAM" "true" + "A" "" "" "" "PROP_SynthExtractROM" "true" + "A" "" "" "" "PROP_SynthFsmEncode" "Auto" + "A" "" "" "" "PROP_SynthLogicalShifterExtract" "true" + "A" "" "" "" "PROP_SynthOpt" "Speed" + "A" "" "" "" "PROP_SynthOptEffort" "Normal" + "A" "" "" "" "PROP_SynthResSharing" "true" + "A" "" "" "" "PROP_SynthShiftRegExtract" "true" + "A" "" "" "" "PROP_SynthXORCollapse" "true" + "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL" + "A" "" "" "" "PROP_UseDataGate" "true" + "A" "" "" "" "PROP_XPowerOptInputTclScript" "" + "A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default" + "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default" + "A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default" + "A" "" "" "" "PROP_XPowerOptOutputFile" "Default" + "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false" + "A" "" "" "" "PROP_XPowerOtherXPowerOpts" "" + "A" "" "" "" "PROP_XplorerMode" "Off" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq0" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq1" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq2" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq3" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq4" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq5" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_startCBC" "" + "A" "" "" "" "PROP_bitgen_Encrypt_startKey" "None" + "A" "" "" "" "PROP_bitgen_otherCmdLineOptions" "" + "A" "" "" "" "PROP_cpldBestFit" "false" + "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source" + "A" "" "" "" "PROP_cpldfit_otherCmdLineOptions" "" + "A" "" "" "" "PROP_fitGenSimModel" "false" + "A" "" "" "" "PROP_hprep6_autosig" "false" + "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" "" + "A" "" "" "" "PROP_ibiswriterEnableMultiLingualModel" "false" + "A" "" "" "" "PROP_ibiswriterShowAllModels" "false" + "A" "" "" "" "PROP_impactConfigFileName_CPLD" "" + "A" "" "" "" "PROP_mapUseRLOCConstraints" "true" + "A" "" "" "" "PROP_map_otherCmdLineOptions" "" + "A" "" "" "" "PROP_mpprRsltToCopy" "" + "A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true" + "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" "" + "A" "" "" "" "PROP_parUseTimingConstraints" "true" + "A" "" "" "" "PROP_par_otherCmdLineOptions" "" + "A" "" "" "" "PROP_primeCorrelateOutput" "false" + "A" "" "" "" "PROP_primeFlatternOutputNetlist" "false" + "A" "" "" "" "PROP_primeTopLevelModule" "" + "A" "" "" "" "PROP_primetimeBlockRamData" "" + "A" "" "" "" "PROP_taengine_otherCmdLineOptions" "" + "A" "" "" "" "PROP_xcpldFitDesInit" "Low" + "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32" + "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true" + "A" "" "" "" "PROP_xcpldFitDesSlew" "Fast" + "A" "" "" "" "PROP_xcpldFitDesTimingCst" "true" + "A" "" "" "" "PROP_xcpldFitDesTriMode" "Keeper" + "A" "" "" "" "PROP_xcpldFitDesUnused" "Keeper" + "A" "" "" "" "PROP_xcpldFitDesVolt" "LVCMOS18" + "A" "" "" "" "PROP_xcpldFitTemplate_xpla3" "Optimize Density" + "A" "" "" "" "PROP_xcpldFittimRptOption" "Summary" + "A" "" "" "" "PROP_xcpldUseGlobalClocks" "true" + "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true" + "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true" + "A" "" "" "" "PROP_xcpldUseLocConst" "Always" + "A" "" "" "" "PROP_xilxBitgCfg_Clk" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF" + "A" "" "" "" "PROP_xilxBitgCfg_DCMBandgap" "false" + "A" "" "" "" "PROP_xilxBitgCfg_DCMShutdown" "false" + "A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "false" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC" "true" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File" "false" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false" + "A" "" "" "" "PROP_xilxBitgCfg_M0" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_M1" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_M2" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_PwrDown" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_Rate" "4" + "A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down" + "A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration" + "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK" + "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" + "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" + "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle" "Auto" + "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" + "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)" + "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" + "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" + "A" "" "" "" "PROP_xilxMapCoverMode" "Area" + "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false" + "A" "" "" "" "PROP_xilxMapPackRegInto" "For Inputs and Outputs" + "A" "" "" "" "PROP_xilxMapReplicateLogic" "true" + "A" "" "" "" "PROP_xilxMapReportDetail" "false" + "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false" + "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false" + "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true" + "A" "" "" "" "PROP_xilxNgdbldIOPads" "false" + "A" "" "" "" "PROP_xilxNgdbldMacro" "" + "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp" + "A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false" + "A" "" "" "" "PROP_xilxNgdbldUR" "" + "A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false" + "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" + "A" "" "" "" "PROP_xilxPARplacerCostTable" "1" + "A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None" + "A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None" + "A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route" + "A" "" "" "" "PROP_xilxPARuseBondedIO" "false" + "A" "" "" "" "PROP_xilxPostTrceAdvAna" "false" + "A" "" "" "" "PROP_xilxPostTrceRpt" "Error Report" + "A" "" "" "" "PROP_xilxPostTrceRptLimit" "3" + "A" "" "" "" "PROP_xilxPostTrceStamp" "" + "A" "" "" "" "PROP_xilxPostTrceTSIFile" "" + "A" "" "" "" "PROP_xilxPostTrceUncovPath" "" + "A" "" "" "" "PROP_xilxPreTrceAdvAna" "false" + "A" "" "" "" "PROP_xilxPreTrceRpt" "Error Report" + "A" "" "" "" "PROP_xilxPreTrceRptLimit" "3" + "A" "" "" "" "PROP_xilxPreTrceUncovPath" "" + "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" + "A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets" + "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No" + "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" + "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" + "A" "" "" "" "PROP_xilxSynthRegBalancing" "No" + "A" "" "" "" "PROP_xilxSynthRegDuplication" "true" + "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" + "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "Off" + "A" "" "" "" "PROP_xstAsynToSync" "false" + "A" "" "" "" "PROP_xstAutoBRAMPacking" "false" + "A" "" "" "" "PROP_xstBRAMUtilRatio" "100" + "A" "" "" "" "PROP_xstBusDelimiter" "<>" + "A" "" "" "" "PROP_xstCase" "Maintain" + "A" "" "" "" "PROP_xstCoresSearchDir" "" + "A" "" "" "" "PROP_xstCrossClockAnalysis" "false" + "A" "" "" "" "PROP_xstEquivRegRemoval" "true" + "A" "" "" "" "PROP_xstFsmStyle" "LUT" + "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" + "A" "" "" "" "PROP_xstGenericsParameters" "" + "A" "" "" "" "PROP_xstHierarchySeparator" "/" + "A" "" "" "" "PROP_xstIniFile" "" + "A" "" "" "" "PROP_xstLibSearchOrder" "" + "A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false" + "A" "" "" "" "PROP_xstPackIORegister" "Auto" + "A" "" "" "" "PROP_xstReadCores" "true" + "A" "" "" "" "PROP_xstSlicePacking" "true" + "A" "" "" "" "PROP_xstSliceUtilRatio" "100" + "A" "" "" "" "PROP_xstTristate2Logic" "Yes" + "A" "" "" "" "PROP_xstUseClockEnable" "Yes" + "A" "" "" "" "PROP_xstUseSyncReset" "Yes" + "A" "" "" "" "PROP_xstUseSyncSet" "Yes" + "A" "" "" "" "PROP_xstUseSynthConstFile" "true" + "A" "" "" "" "PROP_xstUserCompileList" "" + "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" + "A" "" "" "" "PROP_xstVerilog2001" "true" + "A" "" "" "" "PROP_xstVerilogMacros" "" + "A" "" "" "" "PROP_xstWorkDir" "./xst" + "A" "" "" "" "PROP_xstWriteTimingConstraints" "false" + "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" + "A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" + "A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimIncreCompilation" "true" + "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" + "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" + "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimValueRangeCheck" "false" + "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_AnnotatedResultsModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_BehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false" + "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" + "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Post-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimIncreCompilation" "true" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDir" "" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimValueRangeCheck" "false" + "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Structural" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPost-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimIncreCompilation" "true" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimValueRangeCheck" "false" + "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false" + "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_UpdatedBitstream" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false" + "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" + "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" + "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" + "A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "Architecture|s3e_vga_char_dev|IMP" + "B" "" "" "" "PROP_AutoGenFile" "false" + "B" "" "" "" "PROP_DevFamily" "Virtex2P" + "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" + "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" "" + "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false" + "B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false" + "B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true" + "B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true" + "B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true" + "B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true" + "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tb" "false" + "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tbw" "false" + "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tb" "false" + "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tbw" "false" + "B" "" "" "" "PROP_MapEffortLevel" "Medium" + "B" "" "" "" "PROP_MapLogicOptimization" "false" + "B" "" "" "" "PROP_MapPlacerCostTable" "1" + "B" "" "" "" "PROP_MapRegDuplication" "false" + "B" "" "" "" "PROP_ModelSimConfigName" "Default" + "B" "" "" "" "PROP_ModelSimDataWin" "false" + "B" "" "" "" "PROP_ModelSimListWin" "false" + "B" "" "" "" "PROP_ModelSimProcWin" "false" + "B" "" "" "" "PROP_ModelSimSignalWin" "true" + "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" + "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" + "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" + "B" "" "" "" "PROP_ModelSimSourceWin" "false" + "B" "" "" "" "PROP_ModelSimStructWin" "true" + "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT" + "B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT" + "B" "" "" "" "PROP_ModelSimVarsWin" "false" + "B" "" "" "" "PROP_ModelSimWaveWin" "true" + "B" "" "" "" "PROP_SimCustom_behav" "" + "B" "" "" "" "PROP_SimCustom_postMap" "" + "B" "" "" "" "PROP_SimCustom_postPar" "" + "B" "" "" "" "PROP_SimCustom_postXlate" "" + "B" "" "" "" "PROP_SimGenVcdFile" "false" + "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" + "B" "" "" "" "PROP_SimSyntax" "93" + "B" "" "" "" "PROP_SimUseExpDeclOnly" "true" + "B" "" "" "" "PROP_SimUserCompileList_behav" "" + "B" "" "" "" "PROP_Simulator" "Modelsim-SE Mixed" + "B" "" "" "" "PROP_SynthConstraintsFile" "" + "B" "" "" "" "PROP_SynthMuxStyle" "Auto" + "B" "" "" "" "PROP_SynthRAMStyle" "Auto" + "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false" + "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" + "B" "" "" "" "PROP_XPowerOptUseTimeBased" "false" + "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt" "false" + "B" "" "" "" "PROP_impactBaud" "None" + "B" "" "" "" "PROP_impactConfigMode" "None" + "B" "" "" "" "PROP_impactPort" "None" + "B" "" "" "" "PROP_parGenAsyDlyRpt" "false" + "B" "" "" "" "PROP_parGenClkRegionRpt" "false" + "B" "" "" "" "PROP_parGenSimModel" "false" + "B" "" "" "" "PROP_parGenTimingRpt" "true" + "B" "" "" "" "PROP_parMpprNodelistFile" "" + "B" "" "" "" "PROP_parMpprParIterations" "3" + "B" "" "" "" "PROP_parMpprResultsDirectory" "" + "B" "" "" "" "PROP_parMpprResultsToSave" "" + "B" "" "" "" "PROP_parPowerReduction" "false" + "B" "" "" "" "PROP_vcom_otherCmdLineOptions" "" + "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" + "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" + "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" + "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" + "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false" + "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false" + "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false" + "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false" + "B" "" "" "" "PROP_xilxMapPackfactor" "100" + "B" "" "" "" "PROP_xilxPAReffortLevel" "Standard" + "B" "" "" "" "PROP_xstMoveFirstFfStage" "true" + "B" "" "" "" "PROP_xstMoveLastFfStage" "true" + "B" "" "" "" "PROP_xstROMStyle" "Auto" + "B" "" "" "" "PROP_xstSafeImplement" "No" + "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "" + "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "" + "C" "" "" "" "PROP_AceActiveName" "" + "C" "" "" "" "PROP_CompxlibLang" "All" + "C" "" "" "" "PROP_CompxlibSmartModels" "true" + "C" "" "" "" "PROP_CompxlibUpdateIniForSmartModel" "false" + "C" "" "" "" "PROP_DevDevice" "xc2vp7" + "C" "" "" "" "PROP_DevFamilyPMName" "virtex2p" + "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns" + "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns" + "C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns" + "C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns" + "C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd" + "C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd" + "C" "" "" "" "PROP_MapExtraEffort" "None" + "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" + "C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps" + "C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1" + "C" "" "" "" "PROP_bitgen_Encrypt_key0" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key1" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key2" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key3" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key4" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key5" "" + "C" "" "" "" "PROP_bitgen_Encrypt_keyFile" "" + "C" "" "" "" "PROP_impactConfigFileName" "" + "C" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" "false" + "C" "" "" "" "PROP_xilxPARextraEffortLevel" "None" + "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" + "D" "" "" "" "PROP_CompxlibUniSimLib" "true" + "D" "" "" "" "PROP_DevPackage" "fg456" + "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" + "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2" "false" + "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" "false" + "D" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex2" "false" + "E" "" "" "" "PROP_DevSpeed" "-6" + "E" "" "" "" "PROP_PreferredLanguage" "Verilog" + "F" "" "" "" "PROP_ChangeDevSpeed" "-6" + "F" "" "" "" "PROP_SimModelTarget" "Verilog" + "F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog" + "F" "" "" "" "PROP_xilxPostTrceSpeed" "-6" + "F" "" "" "" "PROP_xilxPreTrceSpeed" "-6" + "G" "" "" "" "PROP_PostSynthSimModelName" "_synthesis.v" + "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" + "G" "" "" "" "PROP_SimModelGenArchOnly" "false" + "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" + "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" + "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false" + "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" + "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" + "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" + "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" + "G" "" "" "" "PROP_SimModelRenTopLevMod" "" + "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "_map.v" + "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "_timesim.v" + "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_tbwPostMapTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_tbwPostParTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_tbwPostXlateTestbenchName" "" + "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "_translate.v" + "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" + "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false" + "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" + "H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "" + "H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "" + "H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "" + "H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "" + "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" + "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT" + "I" "" "" "" "PROP_SimModelRocPulseWidth" "100" + "I" "" "" "" "PROP_SimModelTocPulseWidth" "0"} + + HandleException { + RestoreProcessProperties $iProjHelper $process_props + } "A problem occured while restoring process properties." + + # library names and their members + set libraries { + "interrupt_control_v1_00_a" + { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" + } + "opb_ipif_v3_01_c" + { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" + } + "proc_common_v2_00_a" + { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" + } + "rdpfifo_v1_01_b" + { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" + } + "s3e_vga_char_dev_v1_00_a" + { + "../../hdl/vhdl/s3e_vga_char_dev.vhd" + } + "wrpfifo_v1_01_b" + { + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" + "../../../../../../EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" + } + } + + HandleException { + RestoreSourceLibraries $iProjHelper $libraries + } "A problem occured while restoring source libraries." + + # Close the facilitator project. + CloseFacilProject $iProjHelper + + # Open the restored project in the user's client application, + # which will either be the Projnav GUI or xtclsh. + project open $project_file + + # Let the user know about the backed up project file. + INFO "The project \"$project_file\" was backed up as \"$backup_file\"." + INFO "Please open a Technical Support WebCase at" + INFO "www.xilinx.com/support/clearexpress/websupport.htm" + INFO "and submit this file, along with the project source files, for evaluation." +} + Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/automake.log =================================================================== Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup (revision 4)

opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise_ISE_Backup Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.cli (revision 4) @@ -0,0 +1,103 @@ +NewProject(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/devl/projnav/s3e_vga_char_dev.ise) +SetProperty(Device Family, virtex2p) +SetProperty(Device, xc2vp7) +SetProperty(Package, fg456) +SetProperty(Speed Grade, -6) +SetProperty(Top-Level Module Type, HDL) +SetProperty(Synthesis Tool, XST (VHDL/Verilog)) +SetProperty(Simulator, Modelsim-SE Mixed) +SetPreference(PathType, Absolute) +AddLibrary(s3e_vga_char_dev_v1_00_a, D:/custom_pulse_generator/standalone_pulse_generator/pcores, TRUE) +AddSource(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd, VHDL Module) +MoveToLibrary(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/vhdl/s3e_vga_char_dev.vhd, s3e_vga_char_dev_v1_00_a) +AddSource(D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl/verilog/user_logic.v, Verilog Module) +AddLibrary(proc_common_v2_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, proc_common_v2_00_a) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, proc_common_v2_00_a) +AddLibrary(interrupt_control_v1_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, interrupt_control_v1_00_a) +AddLibrary(wrpfifo_v1_01_b, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, wrpfifo_v1_01_b) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, wrpfifo_v1_01_b) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, wrpfifo_v1_01_b) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, wrpfifo_v1_01_b) +AddLibrary(rdpfifo_v1_01_b, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, rdpfifo_v1_01_b) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, rdpfifo_v1_01_b) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, rdpfifo_v1_01_b) +AddLibrary(opb_ipif_v3_01_c, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, opb_ipif_v3_01_c) +AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, VHDL Module) +MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, opb_ipif_v3_01_c) +CloseProject() Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/projnav/__projnav.log =================================================================== Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.log (revision 4) @@ -0,0 +1,346 @@ + +---------------------------------------------------------------------------- +-- Design Analysis -- +---------------------------------------------------------------------------- +Analyze pcore s3e_vga_char_dev ... + + +---------------------------------------------------------------------------- +-- File Generation -- +---------------------------------------------------------------------------- +Creating HDL source directory ... +Generating top peripheral VHDL template ... +Generating stub user logic Verilog template ... +HDL templates successfully generated ... +Creating data directory ... +Generating XPS inteface files ... +WARNING:HDLParsers:3497 - Ignoring Verilog File + "D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev + _v1_00_a/data/../hdl/verilog/user_logic.v" +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut +4.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_b +it.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit +.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.v +hd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count +er.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_ +pkg.vhd" in Library proc_common_v2_00_a. +Package compiled. +Package body compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count +er_top.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_t +op.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd +" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit. +vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd +" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" +in Library proc_common_v2_00_a. +Package compiled. +Package body compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" +in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" +in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vh +d" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_sel +ect.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.v +hd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" +in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd +" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg +.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.v +hd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter +.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd +" in Library proc_common_v2_00_a. +Package compiled. +Package body compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.v +hd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_ +cntr_ai.vhd" in Library proc_common_v2_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" +in Library wrpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd. +vhd" in Library rdpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl. +vhd" in Library rdpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr. +vhd" in Library wrpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl. +vhd" in Library wrpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_c +ntr.vhd" in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" +in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vh +d" in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" +in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr. +vhd" in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_ +reg.vhd" in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" +in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interr +upt_control.vhd" in Library interrupt_control_v1_00_a. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" +in Library wrpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" +in Library rdpfifo_v1_01_b. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" in +Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" +in Library opb_ipif_v3_01_c. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file +"D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_vga_char_dev_v1 +_00_a/data/../hdl/vhdl/s3e_vga_char_dev.vhd" in Library +s3e_vga_char_dev_v1_00_a. +Entity compiled. +Entity (Architecture ) compiled. + + +Analyzing HDL attributes ... +INFO:MDT - IPTYPE set to value : PERIPHERAL +INFO:MDT - IMP_NETLIST set to value : TRUE +INFO:MDT - HDL set to value : VHDL +WARNING:MDT - Unable to delete temparary XST project file + D:\custom_pulse_generator\standalone_pulse_generator\pcores\s3e_vga_char_dev_ + v1_00_a\data\_s3e_vga_char_dev_xst.prj : 13 +XPS interface files successfully generated ... +Creating development directory ... +Generating command option file ... +Generating readme file ... +Development misc files successfully generated ... +Creating projnav directory ... +Generating ProjNav support files ... +ProjNav support files successfully generated ... +Creating synthesis directory ... +Generating XST synthesis support files ... +XST synthesis support files successfully generated ... +No BFM simulation files will be generated at this time ... +Creating software driver data directory ... +Generating software driver XPS interface (mdd/tcl) files ... +Software driver data definition file (.mdd) successfully generated ... +Software driver data generation file (.tcl) successfully generated ... +Creating software driver src directory ... +Generating software driver template files ... +Software driver compile file (Makefile) successfully generated ... +output user slave register(s) offset to software driver header ... +output IPIF software reset/module identification register(s) offset to software +driver header ... +Software driver header file (.h) successfully generated ... +Software driver source file (.c) successfully generated ... +Software driver SelfTest file (.c) successfully generated ... +Software driver template files successfully generated ... + +---------------------------------------------------------------------------- +-- Final Report -- +---------------------------------------------------------------------------- +Thank you for using Create and Import Peripheral Wizard! Please find your +peripheral hardware templates under +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a and peripheral software templates under +D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 +_00_a respectively. + +Peripheral Summary: + + top name : s3e_vga_char_dev + version : 1.00.a + type : OPB slave + features : slave attachement + mir/rst register + user s/w registers + +Address Block Summary: + + user logic slv : C_BASEADDR + 0x00000000 + : C_BASEADDR + 0x000000FF + mir/reset reg : C_BASEADDR + 0x00000100 + : C_BASEADDR + 0x000001FF + +File Summary + + - HDL source - +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a/hdl + top entity : vhdl/s3e_vga_char_dev.vhd + user logic : verilog/user_logic.v + + - XPS interface - +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a/data + mpd : s3e_vga_char_dev_v2_1_0.mpd + pao : s3e_vga_char_dev_v2_1_0.pao + + - ISE project - +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a/devl/projnav + ise project : s3e_vga_char_dev.npl + cli command : s3e_vga_char_dev.cli + + + - XST synthesis - +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a/devl/synthesis + xst script : s3e_vga_char_dev_xst.scr + xst project : s3e_vga_char_dev_xst.prj + + - Misc file - +D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_ +00_a/devl + help : README.txt + option : ipwiz.opt + log : ipwiz.log + + - Driver source - +D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 +_00_a/src + makefile : Makefile + header : s3e_vga_char_dev.h + source : s3e_vga_char_dev.c + selftest : s3e_vga_char_dev_selftest.c + + - Driver interface - +D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1 +_00_a/data + mdd : s3e_vga_char_dev_v2_1_0.mdd + tcl : s3e_vga_char_dev_v2_1_0.tcl + + Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/ipwiz.opt (revision 4) @@ -0,0 +1,11 @@ +-batch +-create s3e_vga_char_dev +-ver 1.00.a +-dir "D:\custom_pulse_generator\standalone_pulse_generator" +-lang verilog +-bus opb s +-rstmir +-regn 2 32 +-xps +-ise +-driver Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.scr =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.scr (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.scr (revision 4) @@ -0,0 +1,12 @@ +run +-opt_level 2 +-opt_mode speed +-ifmt mixed +-ifn "D:\custom_pulse_generator\standalone_pulse_generator\pcores\s3e_vga_char_dev_v1_00_a\devl\synthesis\s3e_vga_char_dev_xst.prj" +-top s3e_vga_char_dev +-p virtex2p +-ofn "D:\custom_pulse_generator\standalone_pulse_generator\pcores\s3e_vga_char_dev_v1_00_a\devl\synthesis\s3e_vga_char_dev_xst.ngc" +-iobuf NO +-rtlview YES +-hierarchy_separator / +-work_lib s3e_vga_char_dev_v1_00_a Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.prj =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.prj (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/synthesis/s3e_vga_char_dev_xst.prj (revision 4) @@ -0,0 +1,44 @@ +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" +vhdl proc_common_v2_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" +vhdl interrupt_control_v1_00_a "D:\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" +vhdl wrpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" +vhdl rdpfifo_v1_01_b "D:\EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" +vhdl opb_ipif_v3_01_c "D:\EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd" +verilog s3e_vga_char_dev_v1_00_a "../../hdl/verilog/user_logic.v" +vhdl s3e_vga_char_dev_v1_00_a "../../hdl/vhdl/s3e_vga_char_dev.vhd" Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/README.txt =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/README.txt (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a/devl/README.txt (revision 4) @@ -0,0 +1,245 @@ +TABLE OF CONTENTS + 1) Peripheral Summary + 2) Description of Generated Files + 3) Description of Used IPIC Signals + 4) Description of Top Level Generics + + +================================================================================ +* 1) Peripheral Summary * +================================================================================ +Peripheral Summary: + + XPS project / EDK repository : D:\custom_pulse_generator\standalone_pulse_generator + logical library name : s3e_vga_char_dev_v1_00_a + top name : s3e_vga_char_dev + version : 1.00.a + type : OPB slave + features : slave attachement + mir/rst register + user s/w registers + +Address Block for User Logic and IPIF Predefined Services + + User logic slave space service : C_BASEADDR + 0x00000000 + : C_BASEADDR + 0x000000FF + IPIF Reset/MIR service : C_BASEADDR + 0x00000100 + : C_BASEADDR + 0x000001FF + + +================================================================================ +* 2) Description of Generated Files * +================================================================================ +- HDL source file(s) + D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/hdl + + vhdl/s3e_vga_char_dev.vhd + + This is the template file for your peripheral's top design entity. It + configures and instantiates the corresponding IPIF unit in the way you + indicated in the wizard GUI and hooks it up to the stub user logic where + the actual functionalites should get implemented. You are not expected to + modify this template file except certain marked places for adding user + specific generics and ports. + + verilog/user_logic.v + + This is the template file for the stub user logic design entity, either in + VHDL or Verilog, where the actual functionalities should get implemented. + Some sample code snippet may be provided for demonstration purpose. + + +- XPS interface file(s) + D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/data + + s3e_vga_char_dev_v2_1_0.mpd + + This Microprocessor Peripheral Description file contains information of the + interface of your peripheral, so that other EDK tools can recognize your + peripheral. + + s3e_vga_char_dev_v2_1_0.pao + + This Peripheral Analysis Order file defines the analysis order of all the HDL + source files that are used to compile your peripheral. + + +- ISE project file(s) + D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/devl/projnav + + s3e_vga_char_dev.npl + + This is the ProjNavigator project file. It sets up the needed logical + libraries and dependent library files for you to help you develop your + peripheral using ProjNavigator. + + s3e_vga_char_dev.cli + + This is the TCL command line file used to generate the .npl file. + + +- XST synthesis file(s) + D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/devl/synthesis + + s3e_vga_char_dev_xst.scr + + This is the XST synthesis script file to compile your peripheral. + Note: you may want to modify the device part option for your target. + + s3e_vga_char_dev_xst.prj + + This is the XST synthesis project file used by the above script file to + compile your peripheral. + + +- Driver source file(s) + D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1_00_a/src + + s3e_vga_char_dev.h + + This is the software driver header template file, which contains address offset of + software addressable registers in your peripheral, as well as some common masks and + simple register access macros or function declaration. + + s3e_vga_char_dev.c + + This is the software driver source template file, to define all applicable driver + functions. + + s3e_vga_char_dev_selftest.c + + This is the software driver self test example file, which contain self test example + code to test various hardware features of your peripheral. + + Makefile + + This is the software driver makefile to compile drivers. + + +- Driver interface file(s) + D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_vga_char_dev_v1_00_a/data + + s3e_vga_char_dev_v2_1_0.mdd + + This is the Microprocessor Driver Definition file. + + s3e_vga_char_dev_v2_1_0.tcl + + This is the Microprocessor Driver Command file. + + +- Other misc file(s) + D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_vga_char_dev_v1_00_a/devl + + ipwiz.opt + + This is the option setting file for the wizard batch mode, which should + generate the same result as the wizard GUI mode. + + README.txt + + This README file for your peripheral. + + ipwiz.log + + This is the log file by operating on this wizard. + + +================================================================================ +* 3) Description of Used IPIC Signals * +================================================================================ +For more information (usage, timing diagrams, etc.) regarding the IPIC signals +used in the templates, please refer to the following specifications (under +%XILINX_EDK%\doc for windows or $XILINX_EDK/doc for solaris and linux): +proc_ip_ref_guide.pdf - Processor IP Reference Guide (chapter 4 IPIF) +user_core_templates_ref_guide.pdf - User Core Templates Reference Guide + +Bus2IP_Clk + This is the clock input to the user logic. All IPIC signals are synchronous + to this clock. It is identical to the _Clk signal that is an input to + the user core. In an OPB core, Bus2IP_Clk is the same as OPB_Clk, and in a + PLB core, it is the same as PLB_Clk. No additional buffering is provided on + the clock; it is passed through as is. + +Bus2IP_Reset + Signal to reset the User Logic; asserts whenever the _Rst signal does + and, if the Reset block is included, whenever there is a software-programmed + reset. + +Bus2IP_Data + This is the data bus from the IPIF to the user logic; it is used for both + master and slave transactions. It is used to access user logic registers. + +Bus2IP_BE + The Bus2IP_BE is a bus of Byte Enable qualifiers from the IPIF to the user + logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte + lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates + that byte lanes 2 and 3 contains valid data. + +Bus2IP_RdCE + The Bus2IP_RdCE bus is an input to the user logic. It is Bus2IP_CE qualified + by a read transaction. + +Bus2IP_WrCE + The Bus2IP_WrCE bus is an input to the user logic. It is Bus2IP_CE qualified + by a write transaction. + +IP2Bus_Data + This is the data bus from the user logic to the IPIF; it is used for both + master and slave transactions. It is used to access user logic registers. + +IP2Bus_Ack + The IP2Bus_Ack signal provide the read/write acknowledgement from the user + logic to the IPIF. For writes, it indicates the data has been taken by the + user logic. For reads, it indicates that valid data is available. For + immediate acknowledgement (such as for a register read/write), this signal + can be tied to '1'. Wait states can be inserted in the transaction by + delaying the assertion of the acknowledgement. If the IP2Bus_Ack for OPB + cores will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout + suppress) signal must also be asserted to prevent a timeout on the host bus. + +IP2Bus_Retry + IP2Bus_Retry is a response from the user logic to the IPIF that indicates + the currently requested transaction cannot be completed at this time and + that the requesting master should retry the operation. If the IP2Bus_Retry + signal will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout + suppress) signal must also be asserted to prevent a timeout on the host bus. + Note: this signal is unused by PLB IPIF. + +IP2Bus_Error + This signal from the user logic to the IPIF indicates an error has occurred + during the current transaction. It is valid when IP2Bus_Ack is asserted. + +IP2Bus_ToutSup + The IP2Bus_ToutSup must be asserted by the user logic whenever its + acknowledgement or retry response will take longer than 8 clock cycles. + +================================================================================ +* 4) Description of Top Level Generics * +================================================================================ +C_BASEADDR/C_HIGHADDR + These two generics are used to define the memory mapped address space for + the peripheral registers, including Reset/MIR register, Interrupt Source + Controller registers, Read/Write FIFO control/data registers, user logic + software accessible registers and etc., but excluding those user logic + address ranges if ever used. When instantiation, the address space size + determined by these two generics must be a power of 2 (e.g. 2^k = + C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the + minimum size as indicated in the template. + +C_OPB_DWIDTH + This is the data bus width for On-chip Peripheral Bus (OPB). It should + always be set to 32 as of today. + +C_OPB_AWIDTH + This is the address bus width for On-chip Peripheral Bus (OPB). It should + always be set to 32 as of today. + +C_USER_ID_CODE + This is the ID that will be put into the MIR register, it's mainly used + for debug purpose to identify the peripheral under test if multiple + instances exist in the system. + +C_FAMILY + This is to set the target FPGA architecture, s.t. virtex2, virtex2p, etc. + Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a.zip =================================================================== --- opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a.zip (nonexistent) +++ opb_vga_char_display_nodac/trunk/s3e_vga_char_dev_v1_00_a.zip (revision 4)

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