URL
https://opencores.org/ocsvn/pit/pit/trunk
Subversion Repositories pit
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/pit/trunk/sim/verilog/run/how_to
0,0 → 1,4
./run_iverilog |
vvp pit_compiled -lxt2 |
gtkwave pit_wave_dump.lxt & |
|
/pit/trunk/sim/verilog/run/run_iverilog
0,0 → 1,32
#!/bin/csh |
|
set pit = ../../.. |
set bench = $pit/bench |
set wave_dir = $pit/sim/rtl_sim/pit_verilog/waves |
|
iverilog \ |
\ |
-I $bench/verilog \ |
-I $pit/rtl/verilog \ |
\ |
-o pit_compiled \ |
-D WAVES_V \ |
\ |
$pit/rtl/verilog/pit_top.v \ |
$pit/rtl/verilog/pit_wb_bus.v \ |
$pit/rtl/verilog/pit_regs.v \ |
$pit/rtl/verilog/pit_prescale.v \ |
$pit/rtl/verilog/pit_count.v \ |
\ |
$bench/verilog/wb_master_model.v \ |
$bench/verilog/tst_bench_top.v |
|
@ good_compile = $status |
|
if ($good_compile == 0) then |
echo "Compile was Good" |
vvp pit_compiled -lxt2 |
else |
echo "Compile Failed" |
endif |
|
pit/trunk/sim/verilog/run/run_iverilog
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: pit/trunk/sim/verilog/run/pit_waves.sav
===================================================================
--- pit/trunk/sim/verilog/run/pit_waves.sav (nonexistent)
+++ pit/trunk/sim/verilog/run/pit_waves.sav (revision 4)
@@ -0,0 +1,62 @@
+[size] 1197 666
+[pos] -1 -1
+*-16.338505 72000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tst_bench_top.
+[treeopen] tst_bench_top.pit_1.
+[treeopen] tst_bench_top.pit_2.
+[treeopen] tst_bench_top.pit_3.
+[treeopen] tst_bench_top.pit_4.
+@22
+tst_bench_top.test_num[7:0]
+@28
+tst_bench_top.pit_1.wb_clk_i
+@22
+tst_bench_top.pit_1.wb_dat_i[15:0]
+tst_bench_top.pit_1.wb_dat_o[15:0]
+@28
+tst_bench_top.sync_reset
+tst_bench_top.pit_1.arst_i
+tst_bench_top.pit_1.wb_stb_i
+@22
+tst_bench_top.mstr_psx_modx.cntrl_val[15:0]
+@200
+-Control Register
+@22
+tst_bench_top.pit_1.regs.mod_value[15:0]
+tst_bench_top.pit_1.regs.pit_pre_scl[3:0]
+tst_bench_top.pit_1.regs.write_bus[15:0]
+@28
+tst_bench_top.pit_1.regs.pit_slave
+@200
+-Modulo Counter
+@22
+tst_bench_top.pit_1.counter.mod_value[15:0]
+@28
+tst_bench_top.pit_1.counter.rollover
+@22
+tst_bench_top.pit_1.counter.cnt_n[15:0]
+@28
+tst_bench_top.pit_1.counter.counter_sync
+tst_bench_top.pit_1.counter.prescale_out
+tst_bench_top.pit_1.pit_o
+@200
+-Prescaler
+@22
+tst_bench_top.pit_1.prescale.cnt_n[14:0]
+tst_bench_top.pit_1.prescale.end_count[14:0]
+@28
+tst_bench_top.pit_1.prescale.rollover
+@200
+-Slave PIT
+@22
+tst_bench_top.pit_2.prescale.cnt_n[14:0]
+tst_bench_top.pit_2.counter.cnt_n[15:0]
+@200
+-Slave 1
+@28
+tst_bench_top.pit_3.cnt_flag_o
+tst_bench_top.pit_3.pit_o
+@200
+-Byte Mode Slave
+@22
+tst_bench_top.pit_4.counter.cnt_n[15:0]