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/trunk/source/generate_pci32tlite/gen_pci32tlite.pl

trunk/source/generate_pci32tlite/gen_pci32tlite.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (nonexistent) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part1 (revision 4) @@ -0,0 +1,75 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pci32tlite.vhd | +--| | +--| Components: pcidec_new.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: TARGET PCI : | +--| | +--| * PCI Target 32 Bits | +--| * BAR0 32MByte address space | +--| * Whisbone compatible: D16, 32MB address space | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| 2006-01-05 R00B00 MS inverted reset nres | +--| and added debug signals debug_init and debug_access | | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci32tlite is +generic ( + + vendorID : std_logic_vector(15 downto 0) := x"10EE"; + deviceID : std_logic_vector(15 downto 0) := x"0100"; + revisionID : std_logic_vector(7 downto 0) := x"37"; + subsystemID : std_logic_vector(15 downto 0) := x"1558"; + subsystemvID : std_logic_vector(15 downto 0) := x"0480"; Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (nonexistent) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part2 (revision 4) @@ -0,0 +1,142 @@ + +); +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + +); +end pci32tlite; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture rtl of pci32tlite is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + + + component pcidec_new + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + ad_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + idsel_i : in std_logic; + bar0_i : in std_logic_vector(31 downto 25); + memEN_i : in std_logic; + pciadrLD_i : in std_logic; + adrcfg_o : out std_logic; + adrmem_o : out std_logic; + adr_o : out std_logic_vector(24 downto 1); + cmd_o : out std_logic_vector(3 downto 0) + + ); + end component; + + + component pciwbsequ + port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- pci + cmd_i : in std_logic_vector(3 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + frame_i : in std_logic; + irdy_i : in std_logic; + devsel_o : out std_logic; + trdy_o : out std_logic; + -- control + adrcfg_i : in std_logic; + adrmem_i : in std_logic; + pciadrLD_o : out std_logic; + pcidOE_o : out std_logic; + parOE_o : out std_logic; + wbdatLD_o : out std_logic; + wbrgdMX_o : out std_logic; + wbd16MX_o : out std_logic; + wrcfg_o : out std_logic; + rdcfg_o : out std_logic; + -- whisbone + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + ); + end component; + + + component pcidmux + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + d_io : inout std_logic_vector(31 downto 0); + pcidatout_o : out std_logic_vector(31 downto 0); + pcidOE_i : in std_logic; + wbdatLD_i : in std_logic; + wbrgdMX_i : in std_logic; + wbd16MX_i : in std_logic; + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + rg_dat_i : in std_logic_vector(31 downto 0); + rg_dat_o : out std_logic_vector(31 downto 0) + + ); + end component; + + + component pciregs + generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (nonexistent) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part3 (revision 4) @@ -0,0 +1,176 @@ + + ); + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(7 downto 2); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + + ); + end component; + + + component pcipargen + port ( + + clk_i : in std_logic; + pcidatout_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + parOE_i : in std_logic; + par_o : out std_logic + + ); + end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal bar0 : std_logic_vector(31 downto 25); + signal memEN : std_logic; + signal pciadrLD : std_logic; + signal adrcfg : std_logic; + signal adrmem : std_logic; + signal adr : std_logic_vector(24 downto 1); + signal cmd : std_logic_vector(3 downto 0); + signal pcidOE : std_logic; + signal parOE : std_logic; + signal wbdatLD : std_logic; + signal wbrgdMX : std_logic; + signal wbd16MX : std_logic; + signal wrcfg : std_logic; + signal rdcfg : std_logic; + signal pcidatread : std_logic_vector(31 downto 0); + signal pcidatwrite : std_logic_vector(31 downto 0); + signal pcidatout : std_logic_vector(31 downto 0); + signal parerr : std_logic; + signal syserr : std_logic; + signal tabort : std_logic; + signal perrEN : std_logic; + signal serrEN : std_logic; + +begin + + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| PCI decoder | + --+-----------------------------------------+ + + u1: component pcidec_new + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + ad_i => ad, + cbe_i => cbe, + idsel_i => idsel, + bar0_i => bar0, + memEN_i => memEN, + pciadrLD_i => pciadrLD, + adrcfg_o => adrcfg, + adrmem_o => adrmem, + adr_o => adr, + cmd_o => cmd + + ); + + + --+-----------------------------------------+ + --| PCI-WB Sequencer | + --+-----------------------------------------+ + + u2: component pciwbsequ + port map ( + + -- General + clk_i => clk33, + nrst_i => nrst, + -- pci + cmd_i => cmd, + cbe_i => cbe, + frame_i => frame, + irdy_i => irdy, + devsel_o => devsel, + trdy_o => trdy, + -- control + adrcfg_i => adrcfg, + adrmem_i => adrmem, + pciadrLD_o => pciadrLD, + pcidOE_o => pcidOE, + parOE_o => parOE, + wbdatLD_o => wbdatLD, + wbrgdMX_o => wbrgdMX, + wbd16MX_o => wbd16MX, + wrcfg_o => wrcfg, + rdcfg_o => rdcfg, + -- whisbone + wb_sel_o => wb_sel_o, + wb_we_o => wb_we_o, + wb_stb_o => wb_stb_o, + wb_cyc_o => wb_cyc_o, + wb_ack_i => wb_ack_i, + wb_err_i => wb_err_i, + -- debug signals + debug_init => debug_init, + debug_access => debug_access + ); + + + --+-----------------------------------------+ + --| PCI-wb datamultiplexer | + --+-----------------------------------------+ + + u3: component pcidmux + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + d_io => ad, + pcidatout_o => pcidatout, + pcidOE_i => pcidOE, + wbdatLD_i => wbdatLD, + wbrgdMX_i => wbrgdMX, + wbd16MX_i => wbd16MX, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o, + rg_dat_i => pcidatread, + rg_dat_o => pcidatwrite + + ); + + + --+-----------------------------------------+ + --| PCI registers | + --+-----------------------------------------+ + + u4: component pciregs + generic map ( + + vendorID => vendorID, + deviceID => deviceID, + revisionID => revisionID, + subsystemID => subsystemID, + subsystemvID => subsystemvID, Index: trunk/source/generate_pci32tlite/new_pci32tlite.vhd =================================================================== --- trunk/source/generate_pci32tlite/new_pci32tlite.vhd (nonexistent) +++ trunk/source/generate_pci32tlite/new_pci32tlite.vhd (revision 4) @@ -0,0 +1,590 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pci32tlite.vhd | +--| | +--| Components: pcidec_new.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: TARGET PCI : | +--| | +--| * PCI Target 32 Bits | +--| * BAR0 32MByte address space | +--| * Whisbone compatible: D16, 32MB address space | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| 2006-01-05 R00B00 MS inverted reset nres | +--| and added debug signals debug_init and debug_access | | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci32tlite is +generic ( + + vendorID : std_logic_vector(15 downto 0) := x"10EE"; + deviceID : std_logic_vector(15 downto 0) := x"0100"; + revisionID : std_logic_vector(7 downto 0) := x"37"; + subsystemID : std_logic_vector(15 downto 0) := x"1558"; + subsystemvID : std_logic_vector(15 downto 0) := x"0480"; + jcarr1ID : std_logic_vector(31 downto 0) := x"12345671"; + jcarr2ID : std_logic_vector(31 downto 0) := x"12345672"; + jcarr3ID : std_logic_vector(31 downto 0) := x"12345673"; + jcarr4ID : std_logic_vector(31 downto 0) := x"12345674"; + jcarr5ID : std_logic_vector(31 downto 0) := x"12345675"; + jcarr6ID : std_logic_vector(31 downto 0) := x"12345676"; + jcarr7ID : std_logic_vector(31 downto 0) := x"12345677"; + jcarr8ID : std_logic_vector(31 downto 0) := x"12345678"; + jcarr9ID : std_logic_vector(31 downto 0) := x"12345679"; + jcarr10ID : std_logic_vector(31 downto 0) := x"12345680"; + jcarr11ID : std_logic_vector(31 downto 0) := x"12345681"; + jcarr12ID : std_logic_vector(31 downto 0) := x"12345682"; + jcarr13ID : std_logic_vector(31 downto 0) := x"12345683"; + jcarr14ID : std_logic_vector(31 downto 0) := x"12345684"; + jcarr15ID : std_logic_vector(31 downto 0) := x"12345685"; + jcarr16ID : std_logic_vector(31 downto 0) := x"12345686"; + jcarr17ID : std_logic_vector(31 downto 0) := x"12345687"; + jcarr18ID : std_logic_vector(31 downto 0) := x"12345688"; + jcarr19ID : std_logic_vector(31 downto 0) := x"12345689"; + jcarr20ID : std_logic_vector(31 downto 0) := x"12345690"; + jcarr21ID : std_logic_vector(31 downto 0) := x"12345691"; + jcarr22ID : std_logic_vector(31 downto 0) := x"12345692"; + jcarr23ID : std_logic_vector(31 downto 0) := x"12345693"; + jcarr24ID : std_logic_vector(31 downto 0) := x"12345694"; + jcarr25ID : std_logic_vector(31 downto 0) := x"12345695"; + jcarr26ID : std_logic_vector(31 downto 0) := x"12345696"; + jcarr27ID : std_logic_vector(31 downto 0) := x"12345697"; + jcarr28ID : std_logic_vector(31 downto 0) := x"12345698"; + jcarr29ID : std_logic_vector(31 downto 0) := x"12345699"; + jcarr30ID : std_logic_vector(31 downto 0) := x"12345700"; + jcarr31ID : std_logic_vector(31 downto 0) := x"12345701"; + jcarr32ID : std_logic_vector(31 downto 0) := x"12345702"; + jcarr33ID : std_logic_vector(31 downto 0) := x"12345703"; + jcarr34ID : std_logic_vector(31 downto 0) := x"12345704"; + jcarr35ID : std_logic_vector(31 downto 0) := x"12345705"; + jcarr36ID : std_logic_vector(31 downto 0) := x"12345706"; + jcarr37ID : std_logic_vector(31 downto 0) := x"12345707"; + jcarr38ID : std_logic_vector(31 downto 0) := x"12345708"; + jcarr39ID : std_logic_vector(31 downto 0) := x"12345709"; + jcarr40ID : std_logic_vector(31 downto 0) := x"12345710"; + jcarr41ID : std_logic_vector(31 downto 0) := x"12345711"; + jcarr42ID : std_logic_vector(31 downto 0) := x"12345712" + +); +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + +); +end pci32tlite; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture rtl of pci32tlite is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + + + component pcidec_new + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + ad_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + idsel_i : in std_logic; + bar0_i : in std_logic_vector(31 downto 25); + memEN_i : in std_logic; + pciadrLD_i : in std_logic; + adrcfg_o : out std_logic; + adrmem_o : out std_logic; + adr_o : out std_logic_vector(24 downto 1); + cmd_o : out std_logic_vector(3 downto 0) + + ); + end component; + + + component pciwbsequ + port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- pci + cmd_i : in std_logic_vector(3 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + frame_i : in std_logic; + irdy_i : in std_logic; + devsel_o : out std_logic; + trdy_o : out std_logic; + -- control + adrcfg_i : in std_logic; + adrmem_i : in std_logic; + pciadrLD_o : out std_logic; + pcidOE_o : out std_logic; + parOE_o : out std_logic; + wbdatLD_o : out std_logic; + wbrgdMX_o : out std_logic; + wbd16MX_o : out std_logic; + wrcfg_o : out std_logic; + rdcfg_o : out std_logic; + -- whisbone + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : inout std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + ); + end component; + + + component pcidmux + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + d_io : inout std_logic_vector(31 downto 0); + pcidatout_o : out std_logic_vector(31 downto 0); + pcidOE_i : in std_logic; + wbdatLD_i : in std_logic; + wbrgdMX_i : in std_logic; + wbd16MX_i : in std_logic; + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + rg_dat_i : in std_logic_vector(31 downto 0); + rg_dat_o : out std_logic_vector(31 downto 0) + + ); + end component; + + + component pciregs + generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); + jcarr1ID : std_logic_vector(31 downto 0); + jcarr2ID : std_logic_vector(31 downto 0); + jcarr3ID : std_logic_vector(31 downto 0); + jcarr4ID : std_logic_vector(31 downto 0); + jcarr5ID : std_logic_vector(31 downto 0); + jcarr6ID : std_logic_vector(31 downto 0); + jcarr7ID : std_logic_vector(31 downto 0); + jcarr8ID : std_logic_vector(31 downto 0); + jcarr9ID : std_logic_vector(31 downto 0); + jcarr10ID : std_logic_vector(31 downto 0); + jcarr11ID : std_logic_vector(31 downto 0); + jcarr12ID : std_logic_vector(31 downto 0); + jcarr13ID : std_logic_vector(31 downto 0); + jcarr14ID : std_logic_vector(31 downto 0); + jcarr15ID : std_logic_vector(31 downto 0); + jcarr16ID : std_logic_vector(31 downto 0); + jcarr17ID : std_logic_vector(31 downto 0); + jcarr18ID : std_logic_vector(31 downto 0); + jcarr19ID : std_logic_vector(31 downto 0); + jcarr20ID : std_logic_vector(31 downto 0); + jcarr21ID : std_logic_vector(31 downto 0); + jcarr22ID : std_logic_vector(31 downto 0); + jcarr23ID : std_logic_vector(31 downto 0); + jcarr24ID : std_logic_vector(31 downto 0); + jcarr25ID : std_logic_vector(31 downto 0); + jcarr26ID : std_logic_vector(31 downto 0); + jcarr27ID : std_logic_vector(31 downto 0); + jcarr28ID : std_logic_vector(31 downto 0); + jcarr29ID : std_logic_vector(31 downto 0); + jcarr30ID : std_logic_vector(31 downto 0); + jcarr31ID : std_logic_vector(31 downto 0); + jcarr32ID : std_logic_vector(31 downto 0); + jcarr33ID : std_logic_vector(31 downto 0); + jcarr34ID : std_logic_vector(31 downto 0); + jcarr35ID : std_logic_vector(31 downto 0); + jcarr36ID : std_logic_vector(31 downto 0); + jcarr37ID : std_logic_vector(31 downto 0); + jcarr38ID : std_logic_vector(31 downto 0); + jcarr39ID : std_logic_vector(31 downto 0); + jcarr40ID : std_logic_vector(31 downto 0); + jcarr41ID : std_logic_vector(31 downto 0); + jcarr42ID : std_logic_vector(31 downto 0) + + ); + port ( + + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(7 downto 2); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + + ); + end component; + + + component pcipargen + port ( + + clk_i : in std_logic; + pcidatout_i : in std_logic_vector(31 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + parOE_i : in std_logic; + par_o : out std_logic + + ); + end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal bar0 : std_logic_vector(31 downto 25); + signal memEN : std_logic; + signal pciadrLD : std_logic; + signal adrcfg : std_logic; + signal adrmem : std_logic; + signal adr : std_logic_vector(24 downto 1); + signal cmd : std_logic_vector(3 downto 0); + signal pcidOE : std_logic; + signal parOE : std_logic; + signal wbdatLD : std_logic; + signal wbrgdMX : std_logic; + signal wbd16MX : std_logic; + signal wrcfg : std_logic; + signal rdcfg : std_logic; + signal pcidatread : std_logic_vector(31 downto 0); + signal pcidatwrite : std_logic_vector(31 downto 0); + signal pcidatout : std_logic_vector(31 downto 0); + signal parerr : std_logic; + signal syserr : std_logic; + signal tabort : std_logic; + signal perrEN : std_logic; + signal serrEN : std_logic; + +begin + + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| PCI decoder | + --+-----------------------------------------+ + + u1: component pcidec_new + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + ad_i => ad, + cbe_i => cbe, + idsel_i => idsel, + bar0_i => bar0, + memEN_i => memEN, + pciadrLD_i => pciadrLD, + adrcfg_o => adrcfg, + adrmem_o => adrmem, + adr_o => adr, + cmd_o => cmd + + ); + + + --+-----------------------------------------+ + --| PCI-WB Sequencer | + --+-----------------------------------------+ + + u2: component pciwbsequ + port map ( + + -- General + clk_i => clk33, + nrst_i => nrst, + -- pci + cmd_i => cmd, + cbe_i => cbe, + frame_i => frame, + irdy_i => irdy, + devsel_o => devsel, + trdy_o => trdy, + -- control + adrcfg_i => adrcfg, + adrmem_i => adrmem, + pciadrLD_o => pciadrLD, + pcidOE_o => pcidOE, + parOE_o => parOE, + wbdatLD_o => wbdatLD, + wbrgdMX_o => wbrgdMX, + wbd16MX_o => wbd16MX, + wrcfg_o => wrcfg, + rdcfg_o => rdcfg, + -- whisbone + wb_sel_o => wb_sel_o, + wb_we_o => wb_we_o, + wb_stb_o => wb_stb_o, + wb_cyc_o => wb_cyc_o, + wb_ack_i => wb_ack_i, + wb_err_i => wb_err_i, + -- debug signals + debug_init => debug_init, + debug_access => debug_access + ); + + + --+-----------------------------------------+ + --| PCI-wb datamultiplexer | + --+-----------------------------------------+ + + u3: component pcidmux + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + d_io => ad, + pcidatout_o => pcidatout, + pcidOE_i => pcidOE, + wbdatLD_i => wbdatLD, + wbrgdMX_i => wbrgdMX, + wbd16MX_i => wbd16MX, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o, + rg_dat_i => pcidatread, + rg_dat_o => pcidatwrite + + ); + + + --+-----------------------------------------+ + --| PCI registers | + --+-----------------------------------------+ + + u4: component pciregs + generic map ( + + vendorID => vendorID, + deviceID => deviceID, + revisionID => revisionID, + subsystemID => subsystemID, + subsystemvID => subsystemvID, + jcarr1ID => jcarr1ID, + jcarr2ID => jcarr2ID, + jcarr3ID => jcarr3ID, + jcarr4ID => jcarr4ID, + jcarr5ID => jcarr5ID, + jcarr6ID => jcarr6ID, + jcarr7ID => jcarr7ID, + jcarr8ID => jcarr8ID, + jcarr9ID => jcarr9ID, + jcarr10ID => jcarr10ID, + jcarr11ID => jcarr11ID, + jcarr12ID => jcarr12ID, + jcarr13ID => jcarr13ID, + jcarr14ID => jcarr14ID, + jcarr15ID => jcarr15ID, + jcarr16ID => jcarr16ID, + jcarr17ID => jcarr17ID, + jcarr18ID => jcarr18ID, + jcarr19ID => jcarr19ID, + jcarr20ID => jcarr20ID, + jcarr21ID => jcarr21ID, + jcarr22ID => jcarr22ID, + jcarr23ID => jcarr23ID, + jcarr24ID => jcarr24ID, + jcarr25ID => jcarr25ID, + jcarr26ID => jcarr26ID, + jcarr27ID => jcarr27ID, + jcarr28ID => jcarr28ID, + jcarr29ID => jcarr29ID, + jcarr30ID => jcarr30ID, + jcarr31ID => jcarr31ID, + jcarr32ID => jcarr32ID, + jcarr33ID => jcarr33ID, + jcarr34ID => jcarr34ID, + jcarr35ID => jcarr35ID, + jcarr36ID => jcarr36ID, + jcarr37ID => jcarr37ID, + jcarr38ID => jcarr38ID, + jcarr39ID => jcarr39ID, + jcarr40ID => jcarr40ID, + jcarr41ID => jcarr41ID, + jcarr42ID => jcarr42ID + + ) + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + adr_i => adr(7 downto 2), + cbe_i => cbe, + dat_i => pcidatwrite, + dat_o => pcidatread, + wrcfg_i => wrcfg, + rdcfg_i => rdcfg, + perr_i => parerr, + serr_i => syserr, + tabort_i => tabort, + bar0_o => bar0, + perrEN_o => perrEN, + serrEN_o => serrEN, + memEN_o => memEN + + ); + + --+-----------------------------------------+ + --| PCI Parity Gnerator | + --+-----------------------------------------+ + + u5: component pcipargen + port map ( + + clk_i => clk33, + pcidatout_i => pcidatout, + cbe_i => cbe, + parOE_i => parOE, + par_o => par + + ); + + + --+-----------------------------------------+ + --| Whisbone Address bus | + --+-----------------------------------------+ + + wb_adr_o <= adr; + + + --+-----------------------------------------+ + --| unimplemented | + --+-----------------------------------------+ + + parerr <= '0'; + syserr <= '0'; + tabort <= '0'; + + + --+-----------------------------------------+ + --| unused outputs | + --+-----------------------------------------+ + -- #stop: Curret TARGET indicates to Master stop current transaction + -- #perr: + -- #serr: + + perr <= 'Z'; + serr <= 'Z'; + stop <= 'Z'; + intb <= '0' when ( wb_int_i = '1' ) else 'Z'; + + +end rtl; + + Index: trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 =================================================================== --- trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (nonexistent) +++ trunk/source/generate_pci32tlite/pci32tlite.vhd.part4 (revision 4) @@ -0,0 +1,71 @@ + + ) + port map ( + + clk_i => clk33, + nrst_i => nrst, + -- + adr_i => adr(7 downto 2), + cbe_i => cbe, + dat_i => pcidatwrite, + dat_o => pcidatread, + wrcfg_i => wrcfg, + rdcfg_i => rdcfg, + perr_i => parerr, + serr_i => syserr, + tabort_i => tabort, + bar0_o => bar0, + perrEN_o => perrEN, + serrEN_o => serrEN, + memEN_o => memEN + + ); + + --+-----------------------------------------+ + --| PCI Parity Gnerator | + --+-----------------------------------------+ + + u5: component pcipargen + port map ( + + clk_i => clk33, + pcidatout_i => pcidatout, + cbe_i => cbe, + parOE_i => parOE, + par_o => par + + ); + + + --+-----------------------------------------+ + --| Whisbone Address bus | + --+-----------------------------------------+ + + wb_adr_o <= adr; + + + --+-----------------------------------------+ + --| unimplemented | + --+-----------------------------------------+ + + parerr <= '0'; + syserr <= '0'; + tabort <= '0'; + + + --+-----------------------------------------+ + --| unused outputs | + --+-----------------------------------------+ + -- #stop: Curret TARGET indicates to Master stop current transaction + -- #perr: + -- #serr: + + perr <= 'Z'; + serr <= 'Z'; + stop <= 'Z'; + intb <= '0' when ( wb_int_i = '1' ) else 'Z'; + + +end rtl; + + Index: trunk/source/generate_pci32tlite/Makefile =================================================================== --- trunk/source/generate_pci32tlite/Makefile (nonexistent) +++ trunk/source/generate_pci32tlite/Makefile (revision 4) @@ -0,0 +1,4 @@ +all: + ./gen_pci32tlite.pl > new_pci32tlite.vhd + unix2dos new_pci32tlite.vhd + cp new_pci32tlite.vhd .. Index: trunk/source/pfs.v =================================================================== --- trunk/source/pfs.v (nonexistent) +++ trunk/source/pfs.v (revision 4) @@ -0,0 +1,11 @@ +module pfs2 (clk, a, b); + input clk; + input a; + output b; + reg b; + + always @(posedge clk) + begin + b <= a; + end +endmodule Index: trunk/source/vga_main.vhd =================================================================== --- trunk/source/vga_main.vhd (nonexistent) +++ trunk/source/vga_main.vhd (revision 4) @@ -0,0 +1,103 @@ +--------------------------------------------------------------------- +-- vga_main.vhd Demo VGA configuration module. +--------------------------------------------------------------------- +-- Author: Barron Barnett +-- Copyright 2004 Digilent, Inc. +--------------------------------------------------------------------- +-- +-- This project is compatible with Xilinx ISE or Xilinx WebPack tools. +-- +-- Inputs: +-- mclk - System Clock +-- Outputs: +-- hs - Horizontal Sync +-- vs - Vertical Sync +-- red - Red Output +-- grn - Green Output +-- blu - Blue Output +-- +-- This module creates a three line pattern on a vga display using a +-- a vertical refresh rate of 60Hz. This is done by dividing the +-- system clock in half and using that for the pixel clock. This in +-- turn drives the vertical sync when the horizontal sync has reached +-- its reset point. All data displayed is done by basic value +-- comparisons. +------------------------------------------------------------------------ +-- Revision History: +-- 07/01/2004(BarronB): created +------------------------------------------------------------------------ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity vgaController is + Port ( mclk : in std_logic; + hs : out std_logic; + vs : out std_logic; + red : out std_logic; + grn : out std_logic; + blu : out std_logic); +end vgaController; + +architecture Behavioral of vgaController is + + + constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line + constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display + + constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch + constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch + constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch + constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch + + signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters + signal clkdiv : std_logic; --Clock divider + signal vidon : std_logic; --Tells whether or not its ok to display data + signal vsenable : std_logic; --Enable for the Vertical counter + +begin + --This cuts the 50Mhz clock in half + process(mclk) + begin + if(mclk = '1' and mclk'EVENT) then + clkdiv <= not clkdiv; + end if; + end process; + + --Runs the horizontal counter + process(clkdiv) + begin + if(clkdiv = '1' and clkdiv'EVENT) then + if hc = hpixels then --If the counter has reached the end of pixel count + hc <= "0000000000"; --reset the counter + vsenable <= '1'; --Enable the vertical counter to increment + else + hc <= hc + 1; --Increment the horizontal counter + vsenable <= '0'; --Leave the vsenable off + end if; + end if; + end process; + + hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse + + process(clkdiv) + begin + if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled + if vc = vlines then --Reset when the number of lines is reached + vc <= "0000000000"; + else vc <= vc + 1; --Increment the vertical counter + end if; + end if; + end process; + + vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse + + red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count + grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count + blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count + + vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches + +end Behavioral; Index: trunk/source/wb_7seg.v =================================================================== --- trunk/source/wb_7seg.v (nonexistent) +++ trunk/source/wb_7seg.v (revision 4) @@ -0,0 +1,87 @@ +module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, + wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED); + + input clk_i; + input nrst_i; + input [24:1] wb_adr_i; + output [15:0] wb_dat_o; + input [15:0] wb_dat_i; + input [1:0] wb_sel_i; + input wb_we_i; + input wb_stb_i; + input wb_cyc_i; + output wb_ack_o; + output wb_err_o; + output wb_int_o; + output reg [3:0] DISP_SEL; + output reg [6:0] DISP_LED; + + reg [15:0] data_reg; + reg [6:0] disp_cnt; + reg [3:0] disp_data; + wire [6:0] disp_data_led; + reg [3:0] disp_pos; + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + data_reg <= 16'hABCD; + else + if (wb_stb_i && wb_we_i) + data_reg <= wb_dat_i; + end + + assign wb_ack_o = wb_stb_i; + assign wb_err_o = 1'b0; + assign wb_int_o = 1'b0; + assign wb_dat_o = data_reg; + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_cnt <= 7'b0000000; + else + disp_cnt <= disp_cnt + 1; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_pos <= 4'b0010; + else + if (disp_cnt == 7'b1111111) + disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]}; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + disp_data <= 4'b0000; + else + case (DISP_SEL) + 4'b1000: disp_data <= data_reg[3:0]; + 4'b0100: disp_data <= data_reg[7:4]; + 4'b0010: disp_data <= data_reg[11:8]; + 4'b0001: disp_data <= data_reg[15:12]; + endcase + end + + disp_dec u0 (disp_data, disp_data_led); + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + DISP_LED <= 7'b0000000; + else + DISP_LED <= disp_data_led; + end + + always @(posedge clk_i or negedge nrst_i) + begin + if (nrst_i == 0) + DISP_SEL <= 0; + else + DISP_SEL <= disp_pos; + end + +endmodule Index: trunk/source/top_pci_7seg.vhd =================================================================== --- trunk/source/top_pci_7seg.vhd (nonexistent) +++ trunk/source/top_pci_7seg.vhd (revision 4) @@ -0,0 +1,259 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: top.vhd | +--| | +--| Components: pci32lite.vhd | +--| pciwbsequ.vhd | +--| pcidmux.vhd | +--| pciregs.vhd | +--| pcipargen.vhd | +--| -- Libs -- | +--| ona.vhd | +--| | +--| Description: RS1 PCI Demo : (TOP) Main file. | +--| | +--| | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pci_7seg is +port ( + + -- General + PCI_CLK : in std_logic; + PCI_nRES : in std_logic; + + -- PCI target 32bits + PCI_AD : inout std_logic_vector(31 downto 0); + PCI_CBE : in std_logic_vector(3 downto 0); + PCI_PAR : out std_logic; + PCI_nFRAME : in std_logic; + PCI_nIRDY : in std_logic; + PCI_nTRDY : out std_logic; + PCI_nDEVSEL : out std_logic; + PCI_nSTOP : out std_logic; + PCI_IDSEL : in std_logic; + PCI_nPERR : out std_logic; + PCI_nSERR : out std_logic; + PCI_nINT : out std_logic; + + -- 7seg + DISP_SEL : inout std_logic_vector(3 downto 0); + DISP_LED : out std_logic_vector(6 downto 0); + + -- debug signals + LED_INIT : out std_logic; + LED_ACCESS : out std_logic; + LED_ALIVE : out std_logic; + + -- vga signals + hs : out std_logic; + vs : out std_logic; + red, grn, blu : out std_logic; + mclk : in std_logic + +); +end pci_7seg; + + +--+-----------------------------------------------------------------------------+ +--| ARCHITECTURE | +--+-----------------------------------------------------------------------------+ + +architecture pci_7seg_arch of pci_7seg is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ + +component pci32tlite +port ( + + -- General + clk33 : in std_logic; + nrst : in std_logic; + + -- PCI target 32bits + ad : inout std_logic_vector(31 downto 0); + cbe : in std_logic_vector(3 downto 0); + par : out std_logic; + frame : in std_logic; + irdy : in std_logic; + trdy : out std_logic; + devsel : out std_logic; + stop : out std_logic; + idsel : in std_logic; + perr : out std_logic; + serr : out std_logic; + intb : out std_logic; + + -- Master whisbone + wb_adr_o : out std_logic_vector(24 downto 1); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_sel_o : out std_logic_vector(1 downto 0); + wb_we_o : out std_logic; + wb_stb_o : out std_logic; + wb_cyc_o : out std_logic; + wb_ack_i : in std_logic; + wb_err_i : in std_logic; + wb_int_i : in std_logic; + + -- debug signals + debug_init : out std_logic; + debug_access : out std_logic + + ); +end component; + + +component wb_7seg_new +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + + -- Master whisbone + wb_adr_i : in std_logic_vector(24 downto 1); + wb_dat_o : out std_logic_vector(15 downto 0); + wb_dat_i : in std_logic_vector(15 downto 0); + wb_sel_i : in std_logic_vector(1 downto 0); + wb_we_i : in std_logic; + wb_stb_i : in std_logic; + wb_cyc_i : in std_logic; + wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_int_o : out std_logic; + + -- 7seg + DISP_SEL : inout std_logic_vector(3 downto 0); + DISP_LED : out std_logic_vector(6 downto 0) + + ); +end component; + + +component vgaController is + Port ( mclk : in std_logic; + hs : out std_logic; + vs : out std_logic; + red : out std_logic; + grn : out std_logic; + blu : out std_logic); +end component; + + +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal wb_adr : std_logic_vector(24 downto 1); + signal wb_dat_out : std_logic_vector(15 downto 0); + signal wb_dat_in : std_logic_vector(15 downto 0); + signal wb_sel : std_logic_vector(1 downto 0); + signal wb_we : std_logic; + signal wb_stb : std_logic; + signal wb_cyc : std_logic; + signal wb_ack : std_logic; + signal wb_err : std_logic; + signal wb_int : std_logic; + + +begin + + LED_ALIVE <= '1'; +--+-------------------------------------------------------------------------+ +--| Component instances | +--+-------------------------------------------------------------------------+ + + vga1: vgaController port map (mclk => mclk, + hs => hs, + vs => vs, + red => red, + grn => grn, + blu => blu); + +--+-----------------------------------------+ +--| PCI Target | +--+-----------------------------------------+ + +u_pci: component pci32tlite +port map( + clk33 => PCI_CLK, + nrst => PCI_nRES, + ad => PCI_AD, + cbe => PCI_CBE, + par => PCI_PAR, + frame => PCI_nFRAME, + irdy => PCI_nIRDY, + trdy => PCI_nTRDY, + devsel => PCI_nDEVSEL, + stop => PCI_nSTOP, + idsel => PCI_IDSEL, + perr => PCI_nPERR, + serr => PCI_nSERR, + intb => PCI_nINT, + wb_adr_o => wb_adr, + wb_dat_i => wb_dat_out, + wb_dat_o => wb_dat_in, + wb_sel_o => wb_sel, + wb_we_o => wb_we, + wb_stb_o => wb_stb, + wb_cyc_o => wb_cyc, + wb_ack_i => wb_ack, + wb_err_i => wb_err, + wb_int_i => wb_int, + debug_init => LED_INIT, + debug_access => LED_ACCESS + ); + +--+-----------------------------------------+ +--| WB-7seg | +--+-----------------------------------------+ + +u_wb: component wb_7seg_new +port map( + clk_i => PCI_CLK, + nrst_i => PCI_nRES, + wb_adr_i => wb_adr, + wb_dat_o => wb_dat_out, + wb_dat_i => wb_dat_in, + wb_sel_i => wb_sel, + wb_we_i => wb_we, + wb_stb_i => wb_stb, + wb_cyc_i => wb_cyc, + wb_ack_o => wb_ack, + wb_err_o => wb_err, + wb_int_o => wb_int, + DISP_SEL => DISP_SEL, + DISP_LED => DISP_LED +); + +end pci_7seg_arch; Index: trunk/source/generate_pciregs/gen_pciregs.pl =================================================================== --- trunk/source/generate_pciregs/gen_pciregs.pl (nonexistent) +++ trunk/source/generate_pciregs/gen_pciregs.pl (revision 4) @@ -0,0 +1,44 @@ +#!/usr/bin/perl + +my $TOTAL = 42; +my $START = 0x11; + +%h2b = (0 => "0000", 1 => "0001", 2 => "0010", 3 => "0011", +4 => "0100", 5 => "0101", 6 => "0110", 7 => "0111", +8 => "1000", 9 => "1001", a => "1010", b => "1011", +c => "1100", d => "1101", e => "1110", f => "1111", +); + + +system ("cat pciregs.vhd.part1"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ";"; + $end = "" if $i eq $TOTAL; + print "\t\tjcarr$i" . "ID : std_logic_vector(31 downto 0)$end\n"; +} + +system ("cat pciregs.vhd.part2"); + +foreach $i ( 1 .. $TOTAL ) { + my $end = ";"; + # $end = "" if $i eq $TOTAL; + print "\tconstant JCARR$i" . "IDr : std_logic_vector(31 downto 0) := jcarr$i" . "ID$end\n"; +} + +system ("cat pciregs.vhd.part3"); + +foreach $i ( 1 .. $TOTAL ) { + my $binary, $hex; + $hex = sprintf("%03X", $START); + ($binary = $hex) =~ s/(.)/$h2b{lc $1}/g; + my $out = substr $binary, -6; + print "\t\t when b\"$out\" =>\n"; + my $end = ";"; + # $end = "" if $i eq $TOTAL; + print "\t\t\t\t dataout <= JCARR$i" . "IDr$end\n"; + ++$START; +} + +system ("cat pciregs.vhd.part4"); +

trunk/source/generate_pciregs/gen_pciregs.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/source/generate_pciregs/pciregs.vhd.part1 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part1 (nonexistent) +++ trunk/source/generate_pciregs/pciregs.vhd.part1 (revision 4) @@ -0,0 +1,189 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pciregs.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: Registros PCI | +--| BAR0 is used externally by decoder. | +--| | +--| +-----------------------------------------------------------------------+ | +--| | PCI CONFIGURATION SPACE REGISTERS | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-------------------------------------------------------------------+ | +--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | +--| +-------------------------------------------------------------------+ | +--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | +--| +-------------------------------------------------------------------+ | +--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | INTPIN | 001111 (r) | 3D | 1 | 1 | | +--| +-------------------------------------------------------------------+ | +--| (w*) Reseteable | +--| | +--| +-----------------------------------------------+ | +--| | VENDORID (r) Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies manufacturer of device. | | +--| | VENDORIDr : vendorID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | DEVICEID (r) Device ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the device. | | +--| | DEVICEIDr : deviceID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | CMD (r/w) CoMmanD register | | +--| +-----------------------------------------------+----------------------------+ | +--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | +--| +----------------------------------------------------------------------------+ | +--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | +--| +----------------------------------------------------------------------------+ | +--| | SERRENb : System ERRor ENable (1 = Enabled) | | +--| | PERRENb : Parity ERRor ENable (1 = Enabled) | | +--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | ST (r/w*) STatus register | | +--| +-----------------------------------------------+-------------------------+ | +--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | +--| +-------------------------------------------------------------------------+ | +--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | +--| +-------------------------------------------------------------------------+ | +--| | PERRDTb : Parity ERRor DeTected | | +--| | SERRSIb : System ERRor SIgnaled | | +--| | TABORTSIb : Target ABORT SIgnaled | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | REVISIONID (r) Revision ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies a device revision. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | CLASSCODE (r) CLASS CODE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the generic funtion of the device. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | HEADERTYPE (r) Header Type register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the layout of the second part of the predefined header. | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | BAR0 (r/w) Base AddRess 0 register | | +--| +-----------------------------------------------+-----------------------+ | +--| | BAR032MBb(6..0) | -- | (31-24) | +--| +-----------------------------------------------------------------------+ | +--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies vendor of add-in board or subsystem. | | +--| | SUBSYSTEMVIDr : subsystemvID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMID (r) SUBSYSTEM ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Vendor specific. | | +--| | SUBSYTEMIDr : subsytemID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTLINE (r/w) INTerrupt LINE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | INTLINEr(7..0) | (7..0) | +--| +-----------------------------------------------------------------------+ | +--| | Interrupt Line routing information | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTPIN (r) INTerrupt PIN register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Tells which interrupt pin the device uses: 01=INTA | | +--| +-----------------------------------------------------------------------+ | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pciregs is +generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); Index: trunk/source/generate_pciregs/pciregs.vhd.part2 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part2 (nonexistent) +++ trunk/source/generate_pciregs/pciregs.vhd.part2 (revision 4) @@ -0,0 +1,46 @@ + +); +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(5 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + -- + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + +); +end pciregs; + + +architecture rtl of pciregs is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ + + constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice + constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... + constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; + constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed + constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; + constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; + constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; + constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; Index: trunk/source/generate_pciregs/pciregs.vhd.part3 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part3 (nonexistent) +++ trunk/source/generate_pciregs/pciregs.vhd.part3 (revision 4) @@ -0,0 +1,245 @@ + constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# + + +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal dataout : std_logic_vector(31 downto 0); + signal tabortPFS : std_logic; + signal serrPFS : std_logic; + signal perrPFS : std_logic; + signal adrSTCMD : std_logic; + signal adrBAR0 : std_logic; + signal adrINT : std_logic; + signal we0CMD : std_logic; + signal we1CMD : std_logic; + signal we3ST : std_logic; + signal we3BAR0 : std_logic; + signal we0INT : std_logic; + signal we1INT : std_logic; + signal st11SEN : std_logic; + signal st11REN : std_logic; + signal st14SEN : std_logic; + signal st14REN : std_logic; + signal st15SEN : std_logic; + signal st15REN : std_logic; + + + --+---------------------------------------------------------+ + --| CONFIGURATION SPACE REGISTERS | + --+---------------------------------------------------------+ + + -- INTERRUPT LINE register + signal INTLINEr : std_logic_vector(7 downto 0); + -- COMMAND register bits + signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) + signal PERRENb : std_logic; -- Parity ERRor ENable (bit) + signal SERRENb : std_logic; -- SERR ENable (bit) + -- STATUS register bits + --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) + signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) + signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) + signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) + -- BAR0 register bits + signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) + + +component pfs +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic +); + +end component; + +begin + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); + u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); + u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); + + + --+-------------------------------------------------------------------------+ + --| Registers Address Decoder | + --+-------------------------------------------------------------------------+ + + adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; + adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; + adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; + + + --+-------------------------------------------------------------------------+ + --| WRITE ENABLE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| Write Enable Registers | + --+-----------------------------------------+ + + we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); + we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); + --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); + we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); + --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); + we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); + we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); + --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); + + --+-----------------------------------------+ + --| Set Enable & Reset Enable bits | + --+-----------------------------------------+ + st11SEN <= tabortPFS; + st11REN <= we3ST and dat_i(27); + st14SEN <= serrPFS; + st14REN <= we3ST and dat_i(30); + st15SEN <= perrPFS; + st15REN <= we3ST and dat_i(31); + + + --+-------------------------------------------------------------------------+ + --| WRITE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+---------------------------------------------------------+ + --| COMMAND REGISTER Write | + --+---------------------------------------------------------+ + + REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) + begin + + if( nrst_i = '0' ) then + MEMSPACEENb <= '0'; + PERRENb <= '0'; + SERRENb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0CMD = '1' ) then + MEMSPACEENb <= dat_i(1); + PERRENb <= dat_i(6); + end if; + + -- Byte 1 + if( we1CMD = '1' ) then + SERRENb <= dat_i(8); + end if; + + end if; + + end process REGCMDWR; + + + --+---------------------------------------------------------+ + --| STATUS REGISTER WRITE (Reset only) | + --+---------------------------------------------------------+ + + REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) + begin + + if( nrst_i = '0' ) then + TABORTSIb <= '0'; + SERRSIb <= '0'; + PERRDTb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- TarGet ABORT SIgnaling bit + if( st11SEN = '1' ) then + TABORTSIb <= '1'; + elsif ( st11REN = '1' ) then + TABORTSIb <= '0'; + end if; + + -- System ERRor SIgnaling bit + if( st14SEN = '1' ) then + SERRSIb <= '1'; + elsif ( st14REN = '1' ) then + SERRSIb <= '0'; + end if; + + -- Parity ERRor DEtected bit + if( st15SEN = '1' ) then + PERRDTb <= '1'; + elsif ( st15REN = '1' ) then + PERRDTb <= '0'; + end if; + + end if; + + end process REGSTWR; + + + --+---------------------------------------------------------+ + --| INTERRUPT REGISTER Write | + --+---------------------------------------------------------+ + + REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) + begin + + if( nrst_i = '0' ) then + INTLINEr <= ( others => '0' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0INT = '1' ) then + INTLINEr <= dat_i(7 downto 0); + end if; + + + end if; + + end process REGINTWR; + + + --+---------------------------------------------------------+ + --| BAR0 32MBytes address space (bits 31-25) | + --+---------------------------------------------------------+ + + REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) + begin + + if( nrst_i = '0' ) then + BAR032MBb <= ( others => '1' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 3 + if( we3BAR0 = '1' ) then + BAR032MBb <= dat_i(31 downto 25); + end if; + + end if; + + end process REGBAR0WR; + + + --+-------------------------------------------------------------------------+ + --| Registers MUX (READ) | + --+-------------------------------------------------------------------------+ +--+-------------------------------------------------------------------------------------------------+ + + RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, + INTLINEr, rdcfg_i ) + begin + + if ( rdcfg_i = '1' ) then + + case adr_i is + + when b"000000" => + dataout <= DEVICEIDr & VENDORIDr; + when b"000001" => + dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & + b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; + when b"000010" => + dataout <= CLASSCODEr & REVISIONIDr; + when b"000100" => + dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; + when b"001011" => + dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; + when b"001111" => + dataout <= b"0000000000000000" & INTPINr & INTLINEr; Index: trunk/source/generate_pciregs/new_pciregs.vhd =================================================================== --- trunk/source/generate_pciregs/new_pciregs.vhd (nonexistent) +++ trunk/source/generate_pciregs/new_pciregs.vhd (revision 4) @@ -0,0 +1,675 @@ +--+-------------------------------------------------------------------------------------------------+ +--| | +--| File: pciregs.vhd | +--| | +--| Project: pci32tlite_oc | +--| | +--| Description: Registros PCI | +--| BAR0 is used externally by decoder. | +--| | +--| +-----------------------------------------------------------------------+ | +--| | PCI CONFIGURATION SPACE REGISTERS | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-------------------------------------------------------------------+ | +--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | | +--| +-------------------------------------------------------------------+ | +--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | | +--| +-------------------------------------------------------------------+ | +--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | | +--| +-------------------------------------------------------------------+ | +--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | | +--| +-------------------------------------------------------------------+ | +--| | INTPIN | 001111 (r) | 3D | 1 | 1 | | +--| +-------------------------------------------------------------------+ | +--| (w*) Reseteable | +--| | +--| +-----------------------------------------------+ | +--| | VENDORID (r) Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies manufacturer of device. | | +--| | VENDORIDr : vendorID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | DEVICEID (r) Device ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the device. | | +--| | DEVICEIDr : deviceID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | CMD (r/w) CoMmanD register | | +--| +-----------------------------------------------+----------------------------+ | +--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) | +--| +----------------------------------------------------------------------------+ | +--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) | +--| +----------------------------------------------------------------------------+ | +--| | SERRENb : System ERRor ENable (1 = Enabled) | | +--| | PERRENb : Parity ERRor ENable (1 = Enabled) | | +--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | ST (r/w*) STatus register | | +--| +-----------------------------------------------+-------------------------+ | +--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) | +--| +-------------------------------------------------------------------------+ | +--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) | +--| +-------------------------------------------------------------------------+ | +--| | PERRDTb : Parity ERRor DeTected | | +--| | SERRSIb : System ERRor SIgnaled | | +--| | TABORTSIb : Target ABORT SIgnaled | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | REVISIONID (r) Revision ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies a device revision. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | CLASSCODE (r) CLASS CODE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the generic funtion of the device. | | +--| +-----------------------------------------------------------------------+ | +--| +-----------------------------------------------+ | +--| | HEADERTYPE (r) Header Type register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies the layout of the second part of the predefined header. | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | BAR0 (r/w) Base AddRess 0 register | | +--| +-----------------------------------------------+-----------------------+ | +--| | BAR032MBb(6..0) | -- | (31-24) | +--| +-----------------------------------------------------------------------+ | +--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Identifies vendor of add-in board or subsystem. | | +--| | SUBSYSTEMVIDr : subsystemvID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | SUBSYSTEMID (r) SUBSYSTEM ID register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Vendor specific. | | +--| | SUBSYTEMIDr : subsytemID (generic) | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTLINE (r/w) INTerrupt LINE register | | +--| +-----------------------------------------------+-----------------------+ | +--| | INTLINEr(7..0) | (7..0) | +--| +-----------------------------------------------------------------------+ | +--| | Interrupt Line routing information | | +--| +-----------------------------------------------------------------------+ | +--| | +--| +-----------------------------------------------+ | +--| | INTPIN (r) INTerrupt PIN register | | +--| +-----------------------------------------------+-----------------------+ | +--| | Tells which interrupt pin the device uses: 01=INTA | | +--| +-----------------------------------------------------------------------+ | +--| | +--+-------------------------------------------------------------------------------------------------+ +--| | +--| Revision history : | +--| Date Version Author Description | +--| 2005-05-13 R00A00 PAU First alfa revision (eng) | +--| | +--| To do: | +--| | +--+-------------------------------------------------------------------------------------------------+ +--+-----------------------------------------------------------------+ +--| | +--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | +--| | +--| This source file may be used and distributed without | +--| restriction provided that this copyright statement is not | +--| removed from the file and that any derivative work contains | +--| the original copyright notice and the associated disclaimer. | +--| | +--| This source file is free software; you can redistribute it | +--| and/or modify it under the terms of the GNU Lesser General | +--| Public License as published by the Free Software Foundation; | +--| either version 2.1 of the License, or (at your option) any | +--| later version. | +--| | +--| This source is distributed in the hope that it will be | +--| useful, but WITHOUT ANY WARRANTY; without even the implied | +--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | +--| PURPOSE. See the GNU Lesser General Public License for more | +--| details. | +--| | +--| You should have received a copy of the GNU Lesser General | +--| Public License along with this source; if not, download it | +--| from http://www.opencores.org/lgpl.shtml | +--| | +--+-----------------------------------------------------------------+ + + +--+-----------------------------------------------------------------------------+ +--| LIBRARIES | +--+-----------------------------------------------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + + +--+-----------------------------------------------------------------------------+ +--| ENTITY | +--+-----------------------------------------------------------------------------+ + +entity pciregs is +generic ( + + vendorID : std_logic_vector(15 downto 0); + deviceID : std_logic_vector(15 downto 0); + revisionID : std_logic_vector(7 downto 0); + subsystemID : std_logic_vector(15 downto 0); + subsystemvID : std_logic_vector(15 downto 0); + jcarr1ID : std_logic_vector(31 downto 0); + jcarr2ID : std_logic_vector(31 downto 0); + jcarr3ID : std_logic_vector(31 downto 0); + jcarr4ID : std_logic_vector(31 downto 0); + jcarr5ID : std_logic_vector(31 downto 0); + jcarr6ID : std_logic_vector(31 downto 0); + jcarr7ID : std_logic_vector(31 downto 0); + jcarr8ID : std_logic_vector(31 downto 0); + jcarr9ID : std_logic_vector(31 downto 0); + jcarr10ID : std_logic_vector(31 downto 0); + jcarr11ID : std_logic_vector(31 downto 0); + jcarr12ID : std_logic_vector(31 downto 0); + jcarr13ID : std_logic_vector(31 downto 0); + jcarr14ID : std_logic_vector(31 downto 0); + jcarr15ID : std_logic_vector(31 downto 0); + jcarr16ID : std_logic_vector(31 downto 0); + jcarr17ID : std_logic_vector(31 downto 0); + jcarr18ID : std_logic_vector(31 downto 0); + jcarr19ID : std_logic_vector(31 downto 0); + jcarr20ID : std_logic_vector(31 downto 0); + jcarr21ID : std_logic_vector(31 downto 0); + jcarr22ID : std_logic_vector(31 downto 0); + jcarr23ID : std_logic_vector(31 downto 0); + jcarr24ID : std_logic_vector(31 downto 0); + jcarr25ID : std_logic_vector(31 downto 0); + jcarr26ID : std_logic_vector(31 downto 0); + jcarr27ID : std_logic_vector(31 downto 0); + jcarr28ID : std_logic_vector(31 downto 0); + jcarr29ID : std_logic_vector(31 downto 0); + jcarr30ID : std_logic_vector(31 downto 0); + jcarr31ID : std_logic_vector(31 downto 0); + jcarr32ID : std_logic_vector(31 downto 0); + jcarr33ID : std_logic_vector(31 downto 0); + jcarr34ID : std_logic_vector(31 downto 0); + jcarr35ID : std_logic_vector(31 downto 0); + jcarr36ID : std_logic_vector(31 downto 0); + jcarr37ID : std_logic_vector(31 downto 0); + jcarr38ID : std_logic_vector(31 downto 0); + jcarr39ID : std_logic_vector(31 downto 0); + jcarr40ID : std_logic_vector(31 downto 0); + jcarr41ID : std_logic_vector(31 downto 0); + jcarr42ID : std_logic_vector(31 downto 0) + +); +port ( + + -- General + clk_i : in std_logic; + nrst_i : in std_logic; + -- + adr_i : in std_logic_vector(5 downto 0); + cbe_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- + wrcfg_i : in std_logic; + rdcfg_i : in std_logic; + perr_i : in std_logic; + serr_i : in std_logic; + tabort_i : in std_logic; + -- + bar0_o : out std_logic_vector(31 downto 25); + perrEN_o : out std_logic; + serrEN_o : out std_logic; + memEN_o : out std_logic + +); +end pciregs; + + +architecture rtl of pciregs is + + +--+-----------------------------------------------------------------------------+ +--| COMPONENTS | +--+-----------------------------------------------------------------------------+ +--+-----------------------------------------------------------------------------+ +--| CONSTANTS | +--+-----------------------------------------------------------------------------+ + + constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice + constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81... + constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; + constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed + constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; + constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; + constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; + constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; + constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID; + constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID; + constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID; + constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID; + constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID; + constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID; + constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID; + constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID; + constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID; + constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID; + constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID; + constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID; + constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID; + constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID; + constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID; + constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID; + constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID; + constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID; + constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID; + constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID; + constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID; + constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID; + constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID; + constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID; + constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID; + constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID; + constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID; + constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID; + constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID; + constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID; + constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID; + constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID; + constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID; + constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID; + constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID; + constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID; + constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID; + constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID; + constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID; + constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID; + constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID; + constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID; + constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA# + + +--+-----------------------------------------------------------------------------+ +--| SIGNALS | +--+-----------------------------------------------------------------------------+ + + signal dataout : std_logic_vector(31 downto 0); + signal tabortPFS : std_logic; + signal serrPFS : std_logic; + signal perrPFS : std_logic; + signal adrSTCMD : std_logic; + signal adrBAR0 : std_logic; + signal adrINT : std_logic; + signal we0CMD : std_logic; + signal we1CMD : std_logic; + signal we3ST : std_logic; + signal we3BAR0 : std_logic; + signal we0INT : std_logic; + signal we1INT : std_logic; + signal st11SEN : std_logic; + signal st11REN : std_logic; + signal st14SEN : std_logic; + signal st14REN : std_logic; + signal st15SEN : std_logic; + signal st15REN : std_logic; + + + --+---------------------------------------------------------+ + --| CONFIGURATION SPACE REGISTERS | + --+---------------------------------------------------------+ + + -- INTERRUPT LINE register + signal INTLINEr : std_logic_vector(7 downto 0); + -- COMMAND register bits + signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit) + signal PERRENb : std_logic; -- Parity ERRor ENable (bit) + signal SERRENb : std_logic; -- SERR ENable (bit) + -- STATUS register bits + --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits) + signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit) + signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit) + signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit) + -- BAR0 register bits + signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits) + + +component pfs +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic +); + +end component; + +begin + + --+-------------------------------------------------------------------------+ + --| Component instances | + --+-------------------------------------------------------------------------+ + + u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS ); + u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS ); + u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS ); + + + --+-------------------------------------------------------------------------+ + --| Registers Address Decoder | + --+-------------------------------------------------------------------------+ + + adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0'; + adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0'; + adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0'; + + + --+-------------------------------------------------------------------------+ + --| WRITE ENABLE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+-----------------------------------------+ + --| Write Enable Registers | + --+-----------------------------------------+ + + we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0)); + we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1)); + --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2)); + we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3)); + --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2)); + we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3)); + we0INT <= adrINT and wrcfg_i and (not cbe_i(0)); + --we1INT <= adrINT and wrcfg_i and (not cbe_i(1)); + + --+-----------------------------------------+ + --| Set Enable & Reset Enable bits | + --+-----------------------------------------+ + st11SEN <= tabortPFS; + st11REN <= we3ST and dat_i(27); + st14SEN <= serrPFS; + st14REN <= we3ST and dat_i(30); + st15SEN <= perrPFS; + st15REN <= we3ST and dat_i(31); + + + --+-------------------------------------------------------------------------+ + --| WRITE REGISTERS | + --+-------------------------------------------------------------------------+ + + --+---------------------------------------------------------+ + --| COMMAND REGISTER Write | + --+---------------------------------------------------------+ + + REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i ) + begin + + if( nrst_i = '0' ) then + MEMSPACEENb <= '0'; + PERRENb <= '0'; + SERRENb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0CMD = '1' ) then + MEMSPACEENb <= dat_i(1); + PERRENb <= dat_i(6); + end if; + + -- Byte 1 + if( we1CMD = '1' ) then + SERRENb <= dat_i(8); + end if; + + end if; + + end process REGCMDWR; + + + --+---------------------------------------------------------+ + --| STATUS REGISTER WRITE (Reset only) | + --+---------------------------------------------------------+ + + REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN ) + begin + + if( nrst_i = '0' ) then + TABORTSIb <= '0'; + SERRSIb <= '0'; + PERRDTb <= '0'; + elsif( rising_edge( clk_i ) ) then + + -- TarGet ABORT SIgnaling bit + if( st11SEN = '1' ) then + TABORTSIb <= '1'; + elsif ( st11REN = '1' ) then + TABORTSIb <= '0'; + end if; + + -- System ERRor SIgnaling bit + if( st14SEN = '1' ) then + SERRSIb <= '1'; + elsif ( st14REN = '1' ) then + SERRSIb <= '0'; + end if; + + -- Parity ERRor DEtected bit + if( st15SEN = '1' ) then + PERRDTb <= '1'; + elsif ( st15REN = '1' ) then + PERRDTb <= '0'; + end if; + + end if; + + end process REGSTWR; + + + --+---------------------------------------------------------+ + --| INTERRUPT REGISTER Write | + --+---------------------------------------------------------+ + + REGINTWR: process( clk_i, nrst_i, we0INT, dat_i ) + begin + + if( nrst_i = '0' ) then + INTLINEr <= ( others => '0' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 0 + if( we0INT = '1' ) then + INTLINEr <= dat_i(7 downto 0); + end if; + + + end if; + + end process REGINTWR; + + + --+---------------------------------------------------------+ + --| BAR0 32MBytes address space (bits 31-25) | + --+---------------------------------------------------------+ + + REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i ) + begin + + if( nrst_i = '0' ) then + BAR032MBb <= ( others => '1' ); + elsif( rising_edge( clk_i ) ) then + + -- Byte 3 + if( we3BAR0 = '1' ) then + BAR032MBb <= dat_i(31 downto 25); + end if; + + end if; + + end process REGBAR0WR; + + + --+-------------------------------------------------------------------------+ + --| Registers MUX (READ) | + --+-------------------------------------------------------------------------+ +--+-------------------------------------------------------------------------------------------------+ + + RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, + INTLINEr, rdcfg_i ) + begin + + if ( rdcfg_i = '1' ) then + + case adr_i is + + when b"000000" => + dataout <= DEVICEIDr & VENDORIDr; + when b"000001" => + dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" & + b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0"; + when b"000010" => + dataout <= CLASSCODEr & REVISIONIDr; + when b"000100" => + dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000"; + when b"001011" => + dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr; + when b"001111" => + dataout <= b"0000000000000000" & INTPINr & INTLINEr; + when b"010001" => + dataout <= JCARR1IDr; + when b"010010" => + dataout <= JCARR2IDr; + when b"010011" => + dataout <= JCARR3IDr; + when b"010100" => + dataout <= JCARR4IDr; + when b"010101" => + dataout <= JCARR5IDr; + when b"010110" => + dataout <= JCARR6IDr; + when b"010111" => + dataout <= JCARR7IDr; + when b"011000" => + dataout <= JCARR8IDr; + when b"011001" => + dataout <= JCARR9IDr; + when b"011010" => + dataout <= JCARR10IDr; + when b"011011" => + dataout <= JCARR11IDr; + when b"011100" => + dataout <= JCARR12IDr; + when b"011101" => + dataout <= JCARR13IDr; + when b"011110" => + dataout <= JCARR14IDr; + when b"011111" => + dataout <= JCARR15IDr; + when b"100000" => + dataout <= JCARR16IDr; + when b"100001" => + dataout <= JCARR17IDr; + when b"100010" => + dataout <= JCARR18IDr; + when b"100011" => + dataout <= JCARR19IDr; + when b"100100" => + dataout <= JCARR20IDr; + when b"100101" => + dataout <= JCARR21IDr; + when b"100110" => + dataout <= JCARR22IDr; + when b"100111" => + dataout <= JCARR23IDr; + when b"101000" => + dataout <= JCARR24IDr; + when b"101001" => + dataout <= JCARR25IDr; + when b"101010" => + dataout <= JCARR26IDr; + when b"101011" => + dataout <= JCARR27IDr; + when b"101100" => + dataout <= JCARR28IDr; + when b"101101" => + dataout <= JCARR29IDr; + when b"101110" => + dataout <= JCARR30IDr; + when b"101111" => + dataout <= JCARR31IDr; + when b"110000" => + dataout <= JCARR32IDr; + when b"110001" => + dataout <= JCARR33IDr; + when b"110010" => + dataout <= JCARR34IDr; + when b"110011" => + dataout <= JCARR35IDr; + when b"110100" => + dataout <= JCARR36IDr; + when b"110101" => + dataout <= JCARR37IDr; + when b"110110" => + dataout <= JCARR38IDr; + when b"110111" => + dataout <= JCARR39IDr; + when b"111000" => + dataout <= JCARR40IDr; + when b"111001" => + dataout <= JCARR41IDr; + when b"111010" => + dataout <= JCARR42IDr; + when others => + dataout <= ( others => '0' ); + + end case; + + else + + dataout <= ( others => '0' ); + + end if; + + end process RRMUX; + + dat_o <= dataout; + + + --+-------------------------------------------------------------------------+ + --| BAR0 & COMMAND REGS bits outputs | + --+-------------------------------------------------------------------------+ + + bar0_o <= BAR032MBb; + perrEN_o <= PERRENb; + serrEN_o <= SERRENb; + memEN_o <= MEMSPACEENb; + + +end rtl; Index: trunk/source/generate_pciregs/pciregs.vhd.part4 =================================================================== --- trunk/source/generate_pciregs/pciregs.vhd.part4 (nonexistent) +++ trunk/source/generate_pciregs/pciregs.vhd.part4 (revision 4) @@ -0,0 +1,27 @@ + when others => + dataout <= ( others => '0' ); + + end case; + + else + + dataout <= ( others => '0' ); + + end if; + + end process RRMUX; + + dat_o <= dataout; + + + --+-------------------------------------------------------------------------+ + --| BAR0 & COMMAND REGS bits outputs | + --+-------------------------------------------------------------------------+ + + bar0_o <= BAR032MBb; + perrEN_o <= PERRENb; + serrEN_o <= SERRENb; + memEN_o <= MEMSPACEENb; + + +end rtl; Index: trunk/source/generate_pciregs/Makefile =================================================================== --- trunk/source/generate_pciregs/Makefile (nonexistent) +++ trunk/source/generate_pciregs/Makefile (revision 4) @@ -0,0 +1,4 @@ +all: + ./gen_pciregs.pl > new_pciregs.vhd + unix2dos new_pciregs.vhd + cp new_pciregs.vhd .. Index: trunk/source/pciwbsequ.v =================================================================== --- trunk/source/pciwbsequ.v (nonexistent) +++ trunk/source/pciwbsequ.v (revision 4) @@ -0,0 +1,295 @@ +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// + +(* signal_encoding = "user" *) +(* safe_implementation = "yes" *) + +module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o, + trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o, + wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o, + wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access ); + + // General + input clk_i; + input nrst_i; + // pci + // adr_i + input [3:0] cmd_i; + input [3:0] cbe_i; + input frame_i; + input irdy_i; + output devsel_o; + output trdy_o; + // control + input adrcfg_i; + input adrmem_i; + output pciadrLD_o; + output pcidOE_o; + output reg parOE_o; + output wbdatLD_o; + output wbrgdMX_o; + output wbd16MX_o; + output wrcfg_o; + output rdcfg_o; + // whisbone + output [1:0] wb_sel_o; + output wb_we_o; + inout wb_stb_o; + output wb_cyc_o; + input wb_ack_i; + input wb_err_i; + // debug signals + output reg debug_init; + output reg debug_access; + + //type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR ); + //wire pst_pci : PciFSM; + //wire nxt_pci : PciFSM; + + // typedef enum reg [2:0] { + // RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW + // } color_t; + // + // color_t my_color = GREEN; + + // parameter PCIIDLE = 2'b00; + // parameter B_BUSY = 2'b01; + // parameter S_DATA1 = 2'b10; + // parameter S_DATA2 = 2'b11; + // parameter TURN_AR = 3'b100; + + reg [2:0] pst_pci; + reg [2:0] nxt_pci; + + parameter [2:0] + PCIIDLE = 3'b000, + B_BUSY = 3'b001, + S_DATA1 = 3'b010, + S_DATA2 = 3'b011, + TURN_AR = 3'b100; + + + initial begin + pst_pci = 3'b000; + end + + initial begin + nxt_pci = 3'b000; + end + + wire sdata1; + wire sdata2; + wire idleNX; + wire sdata1NX; + wire sdata2NX; + wire turnarNX; + wire idle; + reg devselNX_n; + reg trdyNX_n; + reg devsel; + reg trdy; + wire adrpci; + wire acking; + wire rdcfg; + reg targOE; + reg pcidOE; + + // always @(nrst_i or clk_i or nxt_pci) + always @(negedge nrst_i or posedge clk_i) + begin + if( nrst_i == 0 ) + pst_pci <= PCIIDLE; + else + pst_pci <= nxt_pci; + end + + // always @(negedge nrst_i or posedge clk_i) + always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking ) + begin + devselNX_n <= 1'b1; + trdyNX_n <= 1'b1; + case (pst_pci) + PCIIDLE : + begin + if ( frame_i == 0 ) + nxt_pci <= B_BUSY; + else + nxt_pci <= PCIIDLE; + end + B_BUSY: + if ( adrpci == 0 ) + nxt_pci <= TURN_AR; + else + begin + nxt_pci <= S_DATA1; + devselNX_n <= 0; + end + S_DATA1: + if ( acking == 1 ) + begin + nxt_pci <= S_DATA2; + devselNX_n <= 0; + trdyNX_n <= 0; + end + else + begin + nxt_pci <= S_DATA1; + devselNX_n <= 0; + end + S_DATA2: + if ( frame_i == 1 && irdy_i == 0 ) + nxt_pci <= TURN_AR; + else + begin + nxt_pci <= S_DATA2; + devselNX_n <= 0; + trdyNX_n <= 0; + end + TURN_AR: + if ( frame_i == 1 ) + nxt_pci <= PCIIDLE; + else + nxt_pci <= TURN_AR; + endcase + end + + // FSM control signals + assign adrpci = adrmem_i; + + assign acking = ( + ( wb_ack_i == 1 || wb_err_i == 1 ) || + ( adrcfg_i == 1 && irdy_i == 0) + ) ? 1'b1 : 1'b0; + + // FSM derived Control signals + assign idle = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0; + assign sdata1 = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0; + assign sdata2 = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0; + assign idleNX = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0; + assign sdata1NX = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0; + assign sdata2NX = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0; + assign turnarNX = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0; + + // PCI Data Output Enable + // always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + pcidOE <= 0; + else + if ( sdata1NX == 1 && cmd_i [0] == 0 ) + pcidOE <= 1; + else + if ( turnarNX == 1 ) + pcidOE <= 0; + end + + assign pcidOE_o = pcidOE; + + // PAR Output Enable + // PCI Read data phase + // PAR is valid 1 cicle after data is valid + // always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + parOE_o <= 0; + else + if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 ) + parOE_o <= 1; + else + parOE_o <= 0; + end + + // Target s/t/s signals OE control + // targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0'; + // always @( nrst_i or clk_i or sdata1NX or idleNX ) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + targOE <= 0; + else + if ( sdata1NX == 1 ) + targOE <= 1; + else + if ( idleNX == 1 ) + targOE <= 0; + end + + // WHISBONE outs + assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0; + assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0; + + // PCI(Little endian) to WB(Big endian) + assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]); + assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]); + + assign wb_we_o = cmd_i [0]; + + // Syncronized PCI outs + always @(negedge nrst_i or posedge clk_i) + begin + if( nrst_i == 0 ) + begin + devsel <= 1; + trdy <= 1; + end + else + begin + devsel <= devselNX_n; + trdy <= trdyNX_n; + end + end + + assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ; + assign trdy_o = ( targOE == 1 ) ? trdy : 1'bZ; + + // rd/wr Configuration Space Registers + assign wrcfg_o = ( + adrcfg_i == 1 && + cmd_i [0] == 1 && + sdata2 == 1 + ) ? 1'b1 : 1'b0; + + assign rdcfg = ( + adrcfg_i == 1 && + cmd_i [0] == 0 && + (sdata1 == 1 || sdata2 == 1) + ) ? 1'b1 : 1'b0; + + assign rdcfg_o = rdcfg; + + // LoaD enable signals + assign pciadrLD_o = ! frame_i; + assign wbdatLD_o = wb_ack_i; + + // Mux control signals + assign wbrgdMX_o = ! rdcfg; + assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0; + + // debug outs + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + debug_init <= 0; + else + if (devsel == 0) + debug_init <= 1; + end + + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + debug_access <= 0; + else + if (wb_stb_o == 1) + debug_access <= 1; + end + +endmodule Index: trunk/source/pfs.vhd =================================================================== --- trunk/source/pfs.vhd (nonexistent) +++ trunk/source/pfs.vhd (revision 4) @@ -0,0 +1,35 @@ +--+-----------------------------------------+ +--| pfs | +--+-----------------------------------------+ + +library ieee; +use ieee.std_logic_1164.all; + +entity pfs is +port ( + clk : in std_logic; + a : in std_logic; + y : out std_logic + +); +end pfs; + +architecture rtl of pfs is + + signal a_s : std_logic; + +begin + + SYNCP: process( clk, a ) + begin + + if ( rising_edge(clk) ) then + a_s <= a; + end if; + + end process SYNCP; + + y <= a and (not a_s); + +end rtl; + Index: trunk/source/pcipargen.v =================================================================== --- trunk/source/pcipargen.v (nonexistent) +++ trunk/source/pcipargen.v (revision 4) @@ -0,0 +1,80 @@ +// +// PCI Parity Generator. +// +// PCI Target generates PAR in the data phase of a read cycle. +// The 1's sum on AD, CBE and PAR is even. +// +// Date Version Author Description +// 2005-05-13 R00A00 PAU First alfa revision (eng) +// +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// +// This source file is free software; you can redistribute it | +// and/or modify it under the terms of the GNU Lesser General | +// Public License as published by the Free Software Foundation; | +// either version 2.1 of the License, or (at your option) any | +// later version. | + + +module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o); + + input clk_i; + input [31:0] pcidatout_i; + input [3:0] cbe_i; + input parOE_i; + output par_o; + + + wire [31:0] d; + wire pardat; + wire parcbe; + wire par; + wire par_s; + + assign d = pcidatout_i; + + assign pardat = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ + d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ + d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ + d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]; + + assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; + + assign par = pardat ^ parcbe; + + // PAR + assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ; + +endmodule +/* +component sync +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +component sync2 +port ( + clk : in std_logic; + d : in std_logic; + q : out std_logic +); +end component; + +begin + + + + u1: sync2 port map ( + clk => clk_i, + d => par, + q => par_s + ); + + + + +end rtl; +*/ Index: trunk/source/pcidmux.v =================================================================== --- trunk/source/pcidmux.v (nonexistent) +++ trunk/source/pcidmux.v (revision 4) @@ -0,0 +1,55 @@ +// Copyright (C) 2005 Peio Azkarate, peio@opencores.org +// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org +// +// I think what this does is handle 16 vs 32 bit pci accesses + +module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i, + wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o); + + input clk_i; + input nrst_i; + + // d_io : inout std_logic_vector(31 downto 0); + inout [31:0] d_io; + output [31:0] pcidatout_o; + + input pcidOE_i; + input wbdatLD_i; + input wbrgdMX_i; + input wbd16MX_i; + + input [15:0] wb_dat_i; + output [15:0] wb_dat_o; + input [31:0] rg_dat_i; + output [31:0] rg_dat_o; + + wire [31:0] pcidatin; + wire [31:0] pcidatout; + + reg [15:0] wb_dat_is; + + // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i) + always @(negedge nrst_i or posedge clk_i) + begin + if ( nrst_i == 0 ) + wb_dat_is <= 16'b1111_1111_1111_1111; + else + if ( wbdatLD_i == 1 ) + wb_dat_is <= wb_dat_i; + end + + assign pcidatin = d_io; + assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ; + + assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [31:24]; + assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16]; + assign pcidatout [15:8] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [15:8]; + assign pcidatout [7:0] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0]; + + assign pcidatout_o = pcidatout; + assign rg_dat_o = pcidatin; + + assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0]; + assign wb_dat_o [7:0] = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8]; + +endmodule Index: trunk/source/disp_dec.v =================================================================== --- trunk/source/disp_dec.v (nonexistent) +++ trunk/source/disp_dec.v (revision 4) @@ -0,0 +1,29 @@ +module disp_dec(disp_dec_in, disp_dec_out); + input [3:0] disp_dec_in; + output reg [6:0] disp_dec_out; + + always @(disp_dec_in) + begin + case (disp_dec_in) + 4'b0000: disp_dec_out <= 7'b1000000; + 4'b0001: disp_dec_out <= 7'b1111001; + 4'b0010: disp_dec_out <= 7'b0100100; + 4'b0011: disp_dec_out <= 7'b0110000; + + 4'b0100: disp_dec_out <= 7'b0011001; + 4'b0101: disp_dec_out <= 7'b0010010; + 4'b0110: disp_dec_out <= 7'b0000010; + 4'b0111: disp_dec_out <= 7'b1111000; + + 4'b1000: disp_dec_out <= 7'b0000000; + 4'b1001: disp_dec_out <= 7'b0010000; + 4'b1010: disp_dec_out <= 7'b0001000; + 4'b1011: disp_dec_out <= 7'b0000011; + + 4'b1100: disp_dec_out <= 7'b1000110; + 4'b1101: disp_dec_out <= 7'b0100001; + 4'b1110: disp_dec_out <= 7'b0000110; + 4'b1111: disp_dec_out <= 7'b0001110; + endcase + end +endmodule