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URL https://opencores.org/ocsvn/reed_solomon_decoder/reed_solomon_decoder/trunk

Subversion Repositories reed_solomon_decoder

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Rev 3 → Rev 4

/reed_solomon_decoder/trunk/simulation/Makefile
0,0 → 1,18
MODULE=RS_dec
TESTBENCH=${MODULE}_tb.v
SOURCES=$(wildcard ../rtl/*.v)
 
all: sim
 
${MODULE}.vvp: ${TESTBENCH} ${SOURCES}
iverilog ${TESTBENCH} ${SOURCES} -o $@
 
sim: ${MODULE}.vvp
vvp -n ${MODULE}.vvp
 
clean:
rm -f a.out ${MODULE}.vvp
 
all-clean: clean
rm -f *~
 
/reed_solomon_decoder/trunk/synthesis/asic/syn.tcl
0,0 → 1,111
echo -n " Starting Synthesis "
 
set search_path [list . $search_path ../../rtl]
set synthetic_library [list standard.sldb dw_foundation.sldb]
 
set tech_lib "slow"
 
set target_library ${tech_lib}.db
set link_library [concat $target_library $synthetic_library]
 
define_design_lib WORK -path work
 
analyze -work WORK -format verilog ../../rtl/BM_lamda.v
analyze -work WORK -format verilog ../../rtl/GF_mult_add_syndromes.v
analyze -work WORK -format verilog ../../rtl/Omega_Phy.v
analyze -work WORK -format verilog ../../rtl/RS_dec.v
analyze -work WORK -format verilog ../../rtl/error_correction.v
analyze -work WORK -format verilog ../../rtl/input_syndromes.v
analyze -work WORK -format verilog ../../rtl/lamda_roots.v
analyze -work WORK -format verilog ../../rtl/out_stage.v
analyze -work WORK -format verilog ../../rtl/transport_in2out.v
set module RS_dec
 
elaborate -work WORK $module
 
current_design ${module}
 
echo -n " ================================== "
echo -n " Constraining the design "
echo -n " ================================== "
 
# /*------------------------------------------------------------------------
# Creating virtual clock
# ------------------------------------------------------------------------*/
 
create_clock "clk" -period 17.8
 
set_dont_touch_network clk
set_clock_latency 0.8 clk
set_clock_uncertainty 0.5 clk
 
set_dont_touch_network [get_ports clk]
set_dont_touch_network [get_ports reset]
 
set_drive 0 [get_ports clk]
set_fix_hold [get_clocks clk]
 
# /*------------------------------------------------------------------------
# Setting Input/Output delays
# ------------------------------------------------------------------------*/
 
set_input_delay 5.9 -clock clk [all_inputs]
 
set_output_delay 5.9 -clock clk [all_outputs]
 
 
echo " ================================== "
echo " Linking "
echo " ================================== "
link
 
echo " ================================== "
echo " Uniquifying "
echo " ================================== "
set uniquify_naming_style %s_%d
uniquify
 
 
echo -n " ================================== "
echo -n " Compiling the design "
echo -n " ================================== "
 
compile -ungroup_all -map_effort high -scan
 
echo -n " ================================== "
echo -n " Generating reports "
echo -n " ================================== "
report_area > "report/${module}.rpt"
report_timing >> "report/${module}.rpt"
report_design >> "report/${module}.rpt"
report_cell >> "report/${module}.rpt"
report_power -nosplit >> "report/${module}.rpt"
report_constraint >> "report/${module}.rpt"
echo "Loops\n" >> "report/${module}.rpt"
echo "=====\n" >> "report/${module}.rpt"
report_timing -loops >> "report/${module}.rpt"
 
echo "Reporting Hierarchy\n" >> "report/${module}.rpt"
echo "===================\n" >> "report/${module}.rpt"
report_hier >> "report/${module}.rpt"
get_designs -hier "*" >> "report/${module}.rpt"
 
echo "Reporting Fanout\n" >> "report/${module}.rpt"
echo "================\n" >> "report/${module}.rpt"
report_net_fanout -high -nosplit >> "report/${module}.rpt"
 
 
current_design ${module}
 
write -format ddc -hierarchy -o gatenet/$module.ddc
write -format verilog -o gatenet/$module.v
write_sdc gatenet/$module.sdc
 
echo -n " ================================== "
echo -n " Synthesis Over "
echo -n " ================================== "
sh date
 
echo "Done"
quit
 
/reed_solomon_decoder/trunk/synthesis/asic/Makefile
0,0 → 1,26
MODULE=RS_dec
DEPS ?=
 
all: syn
 
syn:
[ -d work ] || mkdir work
[ -d report ] || mkdir report
[ -d gatenet ] || mkdir gatenet
bash -c "dc_shell-t -f syn.tcl > report/syn.log"
 
config:
echo -n > analyze.tcl
for src in ../../rtl/*.v; do \
echo analyze -work WORK -format verilog $$src >> analyze.tcl; \
done;
for src in $(DEPS); do \
echo read_db ../../../$$src/syn/asic/gatenet/$$src.db >> analyze.tcl; \
done;
echo set module $(MODULE) >> analyze.tcl
 
clean:
-${RM} -r work/ gatenet/ *.log default.svf
 
all-clean: clean
-${RM} -r report/ *~
/reed_solomon_decoder/trunk/synthesis/altera/RS_dec.qpf
0,0 → 1,3
# Revisions
 
PROJECT_REVISION = "RS_dec"
/reed_solomon_decoder/trunk/synthesis/altera/RS_dec.qsf
0,0 → 1,43
set_global_assignment -name FAMILY StratixIII
set_global_assignment -name DEVICE EP3SL150F1152C2
set_global_assignment -name TOP_LEVEL_ENTITY RS_dec
set_global_assignment -name VERILOG_FILE "../../rtl/transport_in2out.v"
set_global_assignment -name VERILOG_FILE "../../rtl/RS_dec.v"
set_global_assignment -name VERILOG_FILE "../../rtl/out_stage.v"
set_global_assignment -name VERILOG_FILE "../../rtl/Omega_Phy.v"
set_global_assignment -name VERILOG_FILE "../../rtl/lamda_roots.v"
set_global_assignment -name VERILOG_FILE "../../rtl/input_syndromes.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_mult_add_syndromes.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_dec.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_ascending_binary.v"
set_global_assignment -name VERILOG_FILE "../../rtl/error_correction.v"
set_global_assignment -name VERILOG_FILE "../../rtl/DP_RAM.v"
set_global_assignment -name VERILOG_FILE "../../rtl/BM_lamda.v"
set_global_assignment -name USER_LIBRARIES "../../rtl/;"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name DO_COMBINED_ANALYSIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SDC_FILE RS_dec.sdc
 
 
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
/reed_solomon_decoder/trunk/synthesis/altera/RS_dec.sdc
0,0 → 1,94
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {clk} -period 6.250 -waveform { 0.000 3.125 } [get_ports {clk}]
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.272
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.272
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.272
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.272
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.781 [all_inputs]
set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.000 [all_inputs]
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
set_output_delay -add_delay -max -clock [get_clocks {clk}] 0.332 [all_outputs]
set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.000 [all_outputs]
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
set_false_path -from [get_ports {reset}] -to [get_registers {*}]
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
 
 
#**************************************************************
# Set Load
#**************************************************************
 
/reed_solomon_decoder/trunk/synthesis/altera/Makefile
0,0 → 1,104
MODULE=RS_dec
###################################################################
# Project Configuration:
#
# Specify the name of the design (project), the Quartus II Settings
# File (.qsf), and the list of source files used.
###################################################################
 
PROJECT ?= $(MODULE)
DEPS ?=
SOURCE_FILES ?= $(wildcard ../../rtl/*.v)
 
ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and database
###################################################################
 
all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt $(PROJECT).eda.rpt
 
clean:
rm -rf *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db *.summary *.smsg *.qdf simulation dse incremental_db
 
all-clean: clean
rm -rf *.rpt *.done *~
 
map: smart.log $(PROJECT).map.rpt
fit: smart.log $(PROJECT).fit.rpt
asm: smart.log $(PROJECT).asm.rpt
tan: smart.log $(PROJECT).tan.rpt
sta: smart.log $(PROJECT).sta.rpt
eda: smart.log $(PROJECT).eda.rpt
dse: $(PROJECT).dse.rpt
smart: smart.log
 
###################################################################
# Executable Configuration
###################################################################
 
#MAP_ARGS = --family="StratixII"
#FIT_ARGS = --part=EP2S180F1508C3
FIT_ARGS =
ASM_ARGS =
TAN_ARGS =
STA_ARGS =
DSE_ARGS = -exploration-space "Physical Synthesis with Retiming Space"
###################################################################
# Target implementations
###################################################################
 
STAMP = echo done >
 
$(PROJECT).map.rpt: map.chg $(SOURCE_FILES)
quartus_map $(MAP_ARGS) $(PROJECT)
$(STAMP) fit.chg
 
$(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt
quartus_fit $(FIT_ARGS) $(PROJECT)
$(STAMP) asm.chg
$(STAMP) tan.chg
$(STAMP) sta.chg
 
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
quartus_asm $(ASM_ARGS) $(PROJECT)
 
$(PROJECT).tan.rpt: tan.chg $(PROJECT).fit.rpt
quartus_tan $(TAN_ARGS) $(PROJECT)
 
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
quartus_sta $(STA_ARGS) $(PROJECT)
 
$(PROJECT).eda.rpt: eda.chg $(PROJECT).fit.rpt
quartus_eda $(PROJECT)
 
$(PROJECT).dse.rpt: $(ASSIGNMENT_FILES)
quartus_sh --dse -nogui -project $(PROJECT) $(DSE_ARGS)
 
smart.log: $(ASSIGNMENT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
 
###################################################################
# Project initialization
###################################################################
 
#$(ASSIGNMENT_FILES):
# quartus_sh --prepare $(PROJECT)
 
map.chg:
$(STAMP) map.chg
fit.chg:
$(STAMP) fit.chg
tan.chg:
$(STAMP) tan.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
eda.chg:
$(STAMP) eda.chg
 
.PHONY: dse
/reed_solomon_decoder/trunk/synthesis/xilinx/bitgen.ut
0,0 → 1,30
-w
-g DebugBitstream:No
-g Binary:no
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:6
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g en_porb:Yes
-g drive_awake:No
-g suspend_filter:Yes
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
/reed_solomon_decoder/trunk/synthesis/xilinx/RS_dec.prj
0,0 → 1,12
verilog work ../../rtl/BM_lamda.v
verilog work ../../rtl/DP_RAM.v
verilog work ../../rtl/error_correction.v
verilog work ../../rtl/GF_matrix_ascending_binary.v
verilog work ../../rtl/GF_matrix_dec.v
verilog work ../../rtl/GF_mult_add_syndromes.v
verilog work ../../rtl/input_syndromes.v
verilog work ../../rtl/lamda_roots.v
verilog work ../../rtl/Omega_Phy.v
verilog work ../../rtl/out_stage.v
verilog work ../../rtl/RS_dec.v
verilog work ../../rtl/transport_in2out.v
/reed_solomon_decoder/trunk/synthesis/xilinx/RS_dec.ucf
0,0 → 1,4
 
NET "clk" TNM_NET = clk;
 
NET reset LOC = Y16;
/reed_solomon_decoder/trunk/synthesis/xilinx/RS_dec.xst
0,0 → 1,16
set -tmpdir .
set -xsthdpdir ./xst
run
-ifn RS_dec.prj
-ifmt mixed
-ofn RS_dec
-ofmt NGC
-p xc3sd3400a-4-fg676
-top RS_dec
-opt_mode Speed
-opt_level 1
-work_lib work
-rtlview Yes
-verilog2001 YES
# Set iobuf option to YES if this design is a toplevel design:
-iobuf YES
/reed_solomon_decoder/trunk/synthesis/xilinx/Makefile
0,0 → 1,72
MODULE=RS_dec
DEPS ?=
SOURCE_FILES ?= $(wildcard ../../rtl/*.v)
 
ADEPS ?=$(DEPS)
LIBS = ${ADEPS:%=-sd ../../../%/syn/xilinx}
MAP_OPTIONS ?= -timing
PAR_OPTIONS ?=
 
all: ${MODULE}.bit ${MODULE}.twr ${MODULE}_timesim.v
 
# (Re)generate $(MODULE).prj file:
config:
echo -n > $(MODULE).prj
for src in $(SOURCE_FILES); do \
echo verilog work $$src >> $(MODULE).prj; \
done
$(foreach dir, ${ADEPS}, \
for src in ../../../$(dir)/rtl/*.v; do \
echo verilog work $$src >> $(MODULE).prj; \
done; )
 
# Synthesize the HDL files into an NGC file. This rule is triggered if
# any of the HDL files are changed or the synthesis options are changed.
%.ngc: %.xst
echo "XST start: $$(date)" > time.log
xst -intstyle silent -ifn $*.xst -ofn $*.syr
echo "XST finish: $$(date)" >> time.log
 
# Take the output of the synthesizer and create the NGD file. This rule
# will also be triggered if constraints file is changed.
%.ngd: %.ngc %.ucf
ngdbuild -intstyle silent -dd _ngo $(LIBS) -uc $*.ucf $*.ngc $*.ngd
 
# Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
%_map.ncd %.pcf: %.ngd
echo "Map start: $$(date)" >> time.log
map -intstyle silent $(MAP_OPTIONS) -o $*_map.ncd $*.ngd $*.pcf
echo "Map finish: $$(date)" >> time.log
 
# Place & route the mapped NCD file to create the final NCD file.
%.ncd: %_map.ncd %.pcf
echo "PAR start: $$(date)" >> time.log
par -intstyle silent $(PAR_OPTIONS) $*_map.ncd $*.ncd $*.pcf
echo "PAR finish: $$(date)" >> time.log
 
# Generate BIT file:
%.bit: %.ncd
echo "bitgen start: $$(date)" >> time.log
bitgen -intstyle silent -f ../../../include/syn/bitgen.ut $*.ncd
echo "bitgen finish: $$(date)" >> time.log
 
# Create the FPGA timing report after place & route.
%.twr: %.ncd %.pcf
echo "TRCE start: $$(date)" >> time.log
trce -intstyle silent -v 3 -s 4 $*.ncd -o $*.twr $*.pcf
echo "TRCE finish: $$(date)" >> time.log
 
%_timesim.v %_timesim.sdf: %.pcf %.ncd
echo "netgen start: $$(date)" >> time.log
netgen -intstyle silent -s 4 -pcf $*.pcf -sdf_anno true -insert_glbl true -w -ofmt verilog -sim $*.ncd $*_timesim.v
echo "netgen finish: $$(date)" >> time.log
 
clean:
${RM} *.bld *.map *.ncd *.ng? *.pad *.csv *.pcf *.nlf *.xpi *.bgn *.drc *.ngm *.ngr *.xrpt *.ise *.restore *twx time.log deps.v
rm -rf _ngo xst _xmsgs *_xdb
 
all-clean: clean
${RM} *.mrp *.par *.syr *.txt *.sdf *.twr *.unroutes *.xml *~ *.bit *_timesim.v *_pad.txt
 
# Preserve intermediate files.
.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.vm6 %.jed

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