URL
https://opencores.org/ocsvn/robust_fir/robust_fir/trunk
Subversion Repositories robust_fir
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/robust_fir/trunk/run/run.sh
6,4 → 6,4
|
../../../robust ../src/base/fir.v ../src/base/def_fir_top.txt -od out -I ../src/gen -list firlist.txt -listpath -header |
|
echo Completed RobustVerilog fir run - results in examples/fir/run/out/ |
echo Completed RobustVerilog fir run - results in run/out/ |
/robust_fir/trunk/README.txt
2,6 → 2,10
------------------------------ Remark ---------------------------------------- |
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required. |
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools. |
|
We will be very happy to receive any kind of feedback regarding our tools and cores. |
We will also be willing to support any company intending to integrate our cores into their project. |
For any questions / remarks / suggestions / bugs please contact info@provartec.com. |
------------------------------------------------------------------------------ |
|
RobustVerilog generic FIR filter |
18,4 → 22,3
|
Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.). |
|
For any questions / remarks / suggestions / bugs please contact info@provartec.com. |