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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

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Rev 3 → Rev 4

/trunk/hdl/macrocell/sparc_libs/u1_lib.v
0,0 → 1,3999
//
// OpenSPARC T1 Processor File: u1.behV
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////
//
// basic gates {
//
////////////////////////////////////////////////////////////////////////
 
 
//bw_u1_inv_0p6x
//
//
 
module bw_u1_inv_0p6x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_1x
//
//
 
module bw_u1_inv_1x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_1p4x
//
//
 
module bw_u1_inv_1p4x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_2x
//
//
 
module bw_u1_inv_2x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_3x
//
//
 
module bw_u1_inv_3x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_4x
//
//
 
module bw_u1_inv_4x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
 
//bw_u1_inv_5x
//
//
 
module bw_u1_inv_5x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_8x
//
//
 
module bw_u1_inv_8x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_10x
//
//
 
module bw_u1_inv_10x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_15x
//
//
 
module bw_u1_inv_15x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_20x
//
//
 
module bw_u1_inv_20x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_30x
//
//
 
module bw_u1_inv_30x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_inv_40x
//
//
 
module bw_u1_inv_40x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
//bw_u1_invh_15x
//
//
 
module bw_u1_invh_15x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
//bw_u1_invh_25x
//
//
 
module bw_u1_invh_25x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_invh_30x
//
//
 
module bw_u1_invh_30x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_invh_50x
//
//
 
module bw_u1_invh_50x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_invh_60x
//
//
 
module bw_u1_invh_60x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_nand2_0p4x
//
//
module bw_u1_nand2_0p4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_0p6x
//
//
module bw_u1_nand2_0p6x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_1x
//
//
module bw_u1_nand2_1x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_1p4x
//
//
module bw_u1_nand2_1p4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_2x
//
//
module bw_u1_nand2_2x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_3x
//
//
module bw_u1_nand2_3x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_4x
//
//
module bw_u1_nand2_4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_5x
//
//
module bw_u1_nand2_5x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_7x
//
//
module bw_u1_nand2_7x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_10x
//
//
module bw_u1_nand2_10x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand2_15x
//
//
module bw_u1_nand2_15x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nand3_0p4x
//
//
module bw_u1_nand3_0p4x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
 
 
//bw_u1_nand3_0p6x
//
//
module bw_u1_nand3_0p6x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
 
//bw_u1_nand3_1x
 
//
//
module bw_u1_nand3_1x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_1p4x
 
//
//
module bw_u1_nand3_1p4x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_2x
 
//
//
module bw_u1_nand3_2x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_3x
 
//
//
module bw_u1_nand3_3x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_4x
 
//
//
module bw_u1_nand3_4x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_5x
 
//
//
module bw_u1_nand3_5x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_7x
 
//
//
module bw_u1_nand3_7x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand3_10x
 
//
//
module bw_u1_nand3_10x (
z,
a,
b,
c );
output z;
input a;
input b;
input c;
 
endmodule
 
 
//bw_u1_nand4_0p6x
 
//
//
module bw_u1_nand4_0p6x (
z,
a,
b,
c,
d );
output z;
input a;
input b;
input c;
input d;
 
endmodule
 
 
//bw_u1_nand4_1x
//
//
module bw_u1_nand4_1x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
endmodule
 
 
//bw_u1_nand4_1p4x
//
//
module bw_u1_nand4_1p4x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
endmodule
 
 
//bw_u1_nand4_2x
//
//
module bw_u1_nand4_2x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
endmodule
 
 
//bw_u1_nand4_3x
//
//
module bw_u1_nand4_3x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
endmodule
 
 
//bw_u1_nand4_4x
//
//
module bw_u1_nand4_4x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
endmodule
 
 
//bw_u1_nand4_6x
//
//
 
module bw_u1_nand4_6x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
nand( z, a, b,c,d);
 
endmodule
 
//bw_u1_nand4_8x
//
//
 
module bw_u1_nand4_8x (
z,
a,
b,
c,
d );
 
output z;
input a;
input b;
input c;
input d;
 
 
nand( z, a, b,c,d);
 
endmodule
 
//bw_u1_nor2_0p6x
//
//
 
module bw_u1_nor2_0p6x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_1x
//
//
 
module bw_u1_nor2_1x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_1p4x
//
//
 
module bw_u1_nor2_1p4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_2x
//
//
 
module bw_u1_nor2_2x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_3x
//
//
 
module bw_u1_nor2_3x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_4x
//
//
 
module bw_u1_nor2_4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_6x
//
//
 
module bw_u1_nor2_6x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_8x
//
//
 
module bw_u1_nor2_8x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
//bw_u1_nor2_12x
//
//
 
module bw_u1_nor2_12x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
 
 
 
//bw_u1_nor3_0p6x
//
//
 
module bw_u1_nor3_0p6x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_1x
//
//
 
module bw_u1_nor3_1x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_1p4x
//
//
 
module bw_u1_nor3_1p4x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_2x
//
//
 
module bw_u1_nor3_2x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_3x
//
//
 
module bw_u1_nor3_3x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_4x
//
//
 
module bw_u1_nor3_4x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_6x
//
//
 
module bw_u1_nor3_6x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_nor3_8x
//
//
 
module bw_u1_nor3_8x (
z,
a,
b,
c );
 
output z;
input a;
input b;
input c;
 
 
endmodule
 
 
//bw_u1_aoi21_0p4x
//
//
module bw_u1_aoi21_0p4x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi21_1x
//
//
module bw_u1_aoi21_1x (
 
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi21_2x
//
//
module bw_u1_aoi21_2x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi21_4x
//
//
module bw_u1_aoi21_4x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi21_8x
//
//
module bw_u1_aoi21_8x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi21_12x
//
//
module bw_u1_aoi21_12x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
//bw_u1_aoi22_0p4x
//
//
module bw_u1_aoi22_0p4x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
//bw_u1_aoi22_1x
//
//
module bw_u1_aoi22_1x (
z,
b1,
b2,
a1,
a2 );
 
output z;
input b1;
input b2;
input a1;
input a2;
 
 
 
endmodule
//bw_u1_aoi22_2x
//
//
module bw_u1_aoi22_2x (
 
 
z,
b1,
b2,
a1,
a2 );
 
output z;
input b1;
input b2;
input a1;
input a2;
 
endmodule
//bw_u1_aoi22_4x
//
//
module bw_u1_aoi22_4x (
 
z,
b1,
b2,
a1,
a2 );
 
output z;
input b1;
input b2;
input a1;
input a2;
 
 
endmodule
//bw_u1_aoi22_8x
//
//
module bw_u1_aoi22_8x (
 
z,
b1,
b2,
a1,
a2 );
 
output z;
input b1;
input b2;
input a1;
input a2;
 
 
endmodule
//bw_u1_aoi211_0p3x
//
//
module bw_u1_aoi211_0p3x (
 
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_aoi211_1x
//
//
module bw_u1_aoi211_1x (
 
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_aoi211_2x
//
//
module bw_u1_aoi211_2x (
 
 
 
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_aoi211_4x
//
//
module bw_u1_aoi211_4x (
 
 
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
 
endmodule
 
//bw_u1_aoi211_8x
//
//
module bw_u1_aoi211_8x (
 
 
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
 
endmodule
 
//bw_u1_oai21_0p4x
//
//
module bw_u1_oai21_0p4x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai21_1x
//
//
module bw_u1_oai21_1x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai21_2x
//
//
module bw_u1_oai21_2x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai21_4x
//
//
module bw_u1_oai21_4x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai21_8x
//
//
module bw_u1_oai21_8x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai21_12x
//
//
module bw_u1_oai21_12x (
z,
b1,
b2,
a );
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
//bw_u1_oai22_0p4x
//
module bw_u1_oai22_0p4x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
 
//bw_u1_oai22_1x
//
module bw_u1_oai22_1x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
 
//bw_u1_oai22_2x
//
module bw_u1_oai22_2x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
 
//bw_u1_oai22_4x
//
module bw_u1_oai22_4x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
 
//bw_u1_oai22_8x
//
module bw_u1_oai22_8x (
z,
a1,
a2,
b1,
b2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
 
 
endmodule
 
//bw_u1_oai211_0p3x
//
//
module bw_u1_oai211_0p3x (
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_oai211_1x
//
//
module bw_u1_oai211_1x (
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_oai211_2x
//
//
module bw_u1_oai211_2x (
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_oai211_4x
//
//
module bw_u1_oai211_4x (
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_oai211_8x
//
//
module bw_u1_oai211_8x (
z,
c1,
c2,
b,
a );
 
output z;
input c1;
input c2;
input b;
input a;
 
 
endmodule
 
//bw_u1_aoi31_1x
//
//
module bw_u1_aoi31_1x (
 
 
z,
b1,
b2,
b3,
a );
 
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
//bw_u1_aoi31_2x
//
//
module bw_u1_aoi31_2x (
 
z,
b1,
b2,
b3,
a );
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
//bw_u1_aoi31_4x
//
//
module bw_u1_aoi31_4x (
z,
b1,
b2,
b3,
a );
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
//bw_u1_aoi31_8x
//
//
module bw_u1_aoi31_8x (
 
z,
b1,
b2,
b3,
a );
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
//bw_u1_aoi32_1x
//
//
module bw_u1_aoi32_1x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
//bw_u1_aoi32_2x
//
//
module bw_u1_aoi32_2x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
 
endmodule
 
//bw_u1_aoi32_4x
//
//
module bw_u1_aoi32_4x (
 
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
 
endmodule
 
//bw_u1_aoi32_8x
//
//
module bw_u1_aoi32_8x (
 
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
//bw_u1_aoi33_1x
//
//
module bw_u1_aoi33_1x (
 
 
 
 
z,
b1,
b2,
b3,
a1,
a2,
a3 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_aoi33_2x
//
//
module bw_u1_aoi33_2x (
 
z,
b1,
b2,
b3,
a1,
a2,
a3 );
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_aoi33_4x
//
//
module bw_u1_aoi33_4x (
 
z,
b1,
b2,
b3,
a1,
a2,
a3 );
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
 
endmodule
 
 
//bw_u1_aoi33_8x
//
//
module bw_u1_aoi33_8x (
z,
b1,
b2,
b3,
a1,
a2,
a3 );
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
 
endmodule
 
 
//bw_u1_aoi221_1x
//
//
module bw_u1_aoi221_1x (
 
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
endmodule
 
 
//bw_u1_aoi221_2x
//
//
module bw_u1_aoi221_2x (
 
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
 
endmodule
 
 
//bw_u1_aoi221_4x
//
//
module bw_u1_aoi221_4x (
 
 
 
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
 
endmodule
 
 
//bw_u1_aoi221_8x
//
//
module bw_u1_aoi221_8x (
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
 
endmodule
 
 
//bw_u1_aoi222_1x
//
//
module bw_u1_aoi222_1x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
 
 
endmodule
 
//bw_u1_aoi222_2x
//
//
module bw_u1_aoi222_2x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
 
 
endmodule
 
 
//bw_u1_aoi222_4x
//
//
module bw_u1_aoi222_4x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
 
 
endmodule
 
 
//bw_u1_aoi311_1x
//
//
module bw_u1_aoi311_1x (
 
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_aoi311_2x
//
//
module bw_u1_aoi311_2x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_aoi311_4x
//
//
module bw_u1_aoi311_4x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
 
endmodule
 
 
 
 
//bw_u1_aoi311_8x
//
//
module bw_u1_aoi311_8x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_oai31_1x
//
//
module bw_u1_oai31_1x (
z,
b1,
b2,
b3,
a );
 
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_oai31_2x
//
//
module bw_u1_oai31_2x (
z,
b1,
b2,
b3,
a );
 
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_oai31_4x
//
//
module bw_u1_oai31_4x (
z,
b1,
b2,
b3,
a );
 
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_oai31_8x
//
//
module bw_u1_oai31_8x (
z,
b1,
b2,
b3,
a );
 
output z;
input b1;
input b2;
input b3;
input a;
 
 
endmodule
 
 
 
 
//bw_u1_oai32_1x
//
//
module bw_u1_oai32_1x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
 
 
//bw_u1_oai32_2x
//
//
module bw_u1_oai32_2x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
 
 
//bw_u1_oai32_4x
//
//
module bw_u1_oai32_4x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
 
 
//bw_u1_oai32_8x
//
//
module bw_u1_oai32_8x (
z,
b1,
b2,
b3,
a1,
a2 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
 
 
endmodule
 
 
 
//bw_u1_oai33_1x
//
//
module bw_u1_oai33_1x (
z,
b1,
b2,
b3,
a1,
a2,
a3 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_oai33_2x
//
//
module bw_u1_oai33_2x (
z,
b1,
b2,
b3,
a1,
a2,
a3 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_oai33_4x
//
//
module bw_u1_oai33_4x (
z,
b1,
b2,
b3,
a1,
a2,
a3 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_oai33_8x
//
//
module bw_u1_oai33_8x (
z,
b1,
b2,
b3,
a1,
a2,
a3 );
 
output z;
input b1;
input b2;
input b3;
input a1;
input a2;
input a3;
 
 
endmodule
 
 
//bw_u1_oai221_1x
//
//
module bw_u1_oai221_1x (
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
endmodule
 
//bw_u1_oai221_2x
//
//
module bw_u1_oai221_2x (
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
endmodule
 
//bw_u1_oai221_4x
//
//
module bw_u1_oai221_4x (
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
endmodule
 
//bw_u1_oai221_8x
//
//
module bw_u1_oai221_8x (
z,
c1,
c2,
b1,
b2,
a );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a;
 
 
endmodule
 
//bw_u1_oai222_1x
//
//
module bw_u1_oai222_1x (
z,
c1,
c2,
b1,
b2,
a1,
a2 );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a1;
input a2;
 
 
endmodule
 
 
//bw_u1_oai222_2x
//
//
module bw_u1_oai222_2x (
z,
c1,
c2,
b1,
b2,
a1,
a2 );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a1;
input a2;
 
 
endmodule
 
 
//bw_u1_oai222_4x
//
//
module bw_u1_oai222_4x (
z,
c1,
c2,
b1,
b2,
a1,
a2 );
 
output z;
input c1;
input c2;
input b1;
input b2;
input a1;
input a2;
 
 
endmodule
 
 
//bw_u1_oai311_1x
//
//
module bw_u1_oai311_1x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
//bw_u1_oai311_2x
//
//
module bw_u1_oai311_2x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
//bw_u1_oai311_4x
//
//
module bw_u1_oai311_4x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
//bw_u1_oai311_8x
//
//
module bw_u1_oai311_8x (
z,
c1,
c2,
c3,
b,
a );
 
output z;
input c1;
input c2;
input c3;
input b;
input a;
 
 
endmodule
 
 
//bw_u1_muxi21_0p6x
 
 
 
module bw_u1_muxi21_0p6x (z, d0, d1, s);
output z;
input d0, d1, s;
 
endmodule
 
 
//bw_u1_muxi21_1x
 
 
 
module bw_u1_muxi21_1x (z, d0, d1, s);
output z;
input d0, d1, s;
 
endmodule
 
 
 
 
 
 
 
//bw_u1_muxi21_2x
 
 
 
module bw_u1_muxi21_2x (z, d0, d1, s);
output z;
input d0, d1, s;
 
endmodule
 
 
//bw_u1_muxi21_4x
 
 
 
module bw_u1_muxi21_4x (z, d0, d1, s);
output z;
input d0, d1, s;
 
endmodule
 
 
 
 
//bw_u1_muxi21_6x
 
 
module bw_u1_muxi21_6x (z, d0, d1, s);
output z;
input d0, d1, s;
 
endmodule
 
//bw_u1_muxi31d_4x
//
 
module bw_u1_muxi31d_4x (z, d0, d1, d2, s0, s1, s2);
output z;
input d0, d1, d2, s0, s1, s2;
endmodule
 
//bw_u1_muxi41d_4x
//
 
module bw_u1_muxi41d_4x (z, d0, d1, d2, d3, s0, s1, s2, s3);
output z;
input d0, d1, d2, d3, s0, s1, s2, s3;
endmodule
 
//bw_u1_muxi41d_6x
//
 
module bw_u1_muxi41d_6x (z, d0, d1, d2, d3, s0, s1, s2, s3);
output z;
input d0, d1, d2, d3, s0, s1, s2, s3;
endmodule
 
//bw_u1_xor2_0p6x
//
//
module bw_u1_xor2_0p6x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xor2_1x
//
//
module bw_u1_xor2_1x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xor2_2x
//
//
module bw_u1_xor2_2x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xor2_4x
//
//
module bw_u1_xor2_4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xnor2_0p6x
//
//
module bw_u1_xnor2_0p6x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xnor2_1x
//
//
module bw_u1_xnor2_1x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xnor2_2x
//
//
module bw_u1_xnor2_2x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
//bw_u1_xnor2_4x
//
//
module bw_u1_xnor2_4x (
z,
a,
b );
 
output z;
input a;
input b;
 
 
endmodule
 
//bw_u1_buf_1x
//
 
module bw_u1_buf_1x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
//bw_u1_buf_5x
//
 
module bw_u1_buf_5x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_buf_10x
//
 
module bw_u1_buf_10x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_buf_15x
//
 
module bw_u1_buf_15x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_buf_20x
//
 
module bw_u1_buf_20x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_buf_30x
//
 
module bw_u1_buf_30x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_buf_40x
//
 
module bw_u1_buf_40x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
 
//bw_u1_ao2222_1x
//
//
module bw_u1_ao2222_1x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2,
d1,
d2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
input d1;
input d2;
 
 
endmodule
 
 
//bw_u1_ao2222_2x
//
//
module bw_u1_ao2222_2x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2,
d1,
d2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
input d1;
input d2;
 
 
endmodule
 
//bw_u1_ao2222_4x
//
//
module bw_u1_ao2222_4x (
 
z,
a1,
a2,
b1,
b2,
c1,
c2,
d1,
d2 );
 
output z;
input a1;
input a2;
input b1;
input b2;
input c1;
input c2;
input d1;
input d2;
 
 
endmodule
 
////////////////////////////////////////////////////////////////////////
//
// flipflops {
//
////////////////////////////////////////////////////////////////////////
 
// scanable D-flipflop with scanout
 
module bw_u1_soff_1x (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
endmodule
 
module bw_u1_soff_2x (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
endmodule
 
module bw_u1_soff_4x (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
endmodule
 
module bw_u1_soff_8x (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
endmodule
 
// fast scanable D-flipflop with scanout with inverted Q output
 
module bw_u1_soffi_4x (q_l, so, ck, d, se, sd);
output q_l, so;
input ck, d, se, sd;
endmodule
module bw_u1_soffi_8x (q_l, so, ck, d, se, sd);
output q_l, so;
input ck, d, se, sd;
endmodule
 
// scanable D-flipflop with scanout with 2-to-1 input mux
 
module bw_u1_soffm2_4x (q, so, ck, d0, d1, s, se, sd);
output q, so;
input ck, d0, d1, s, se, sd;
endmodule
 
module bw_u1_soffm2_8x (q, so, ck, d0, d1, s, se, sd);
output q, so;
input ck, d0, d1, s, se, sd;
endmodule
 
// scanable D-flipflop with scanout with sync reset-bar
 
module bw_u1_soffr_2x (q, so, ck, d, se, sd, r_l);
output q, so;
input ck, d, se, sd, r_l;
endmodule
module bw_u1_soffr_4x (q, so, ck, d, se, sd, r_l);
output q, so;
input ck, d, se, sd, r_l;
endmodule
 
module bw_u1_soffr_8x (q, so, ck, d, se, sd, r_l);
output q, so;
input ck, d, se, sd, r_l;
endmodule
 
//bw_u1_soffasr_2x
 
module bw_u1_soffasr_2x (q, so, ck, d, r_l, s_l, se, sd);
output q, so;
input ck, d, r_l, s_l, se, sd;
endmodule
 
 
//bw_u1_ckbuf_1p5x
 
 
module bw_u1_ckbuf_1p5x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
 
//bw_u1_ckbuf_3x
 
 
module bw_u1_ckbuf_3x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
//bw_u1_ckbuf_4p5x
 
 
module bw_u1_ckbuf_4p5x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
 
//bw_u1_ckbuf_6x
 
 
module bw_u1_ckbuf_6x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
//bw_u1_ckbuf_7x
//
 
module bw_u1_ckbuf_7x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
//bw_u1_ckbuf_8x
//
module bw_u1_ckbuf_8x (clk, rclk);
output clk;
input rclk;
buf (clk, rclk);
endmodule
 
 
//bw_u1_ckbuf_11x
//
 
module bw_u1_ckbuf_11x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
//bw_u1_ckbuf_14x
//
 
module bw_u1_ckbuf_14x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
//bw_u1_ckbuf_17x
//
 
module bw_u1_ckbuf_17x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
 
 
 
//bw_u1_ckbuf_19x
//
 
module bw_u1_ckbuf_19x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
 
 
 
//bw_u1_ckbuf_22x
//
 
module bw_u1_ckbuf_22x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
//bw_u1_ckbuf_25x
//
 
module bw_u1_ckbuf_25x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
 
//bw_u1_ckbuf_28x
//
 
module bw_u1_ckbuf_28x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
 
//bw_u1_ckbuf_30x
//
 
module bw_u1_ckbuf_30x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
//bw_u1_ckbuf_33x
//
 
module bw_u1_ckbuf_33x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
//bw_u1_ckbuf_40x
//
 
module bw_u1_ckbuf_40x (clk, rclk);
output clk;
input rclk;
 
 
endmodule
 
 
// gated clock buffers
 
 
module bw_u1_ckenbuf_6x (clk, rclk, en_l, tm_l);
output clk;
input rclk, en_l, tm_l;
endmodule
 
module bw_u1_ckenbuf_14x (clk, rclk, en_l, tm_l);
output clk;
input rclk, en_l, tm_l;
endmodule
 
////////////////////////////////////////////////////////////////////////
//
// half cells
//
////////////////////////////////////////////////////////////////////////
 
 
 
module bw_u1_zhinv_0p6x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
module bw_u1_zhinv_1x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
 
module bw_u1_zhinv_1p4x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
module bw_u1_zhinv_2x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
 
module bw_u1_zhinv_3x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
 
module bw_u1_zhinv_4x (z, a);
output z;
input a;
not (z, a);
endmodule
 
 
 
module bw_u1_zhnand2_0p4x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand2_0p6x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand2_1x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand2_1p4x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand2_2x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand2_3x (z, a, b);
output z;
input a, b;
nand (z, a, b);
endmodule
 
 
module bw_u1_zhnand3_0p6x (z, a, b, c);
output z;
input a, b, c;
nand (z, a, b, c);
endmodule
 
module bw_u1_zhnand3_1x (z, a, b, c);
output z;
input a, b, c;
nand (z, a, b, c);
endmodule
 
module bw_u1_zhnand3_2x (z, a, b, c);
output z;
input a, b, c;
nand (z, a, b, c);
endmodule
 
 
module bw_u1_zhnand4_0p6x (z, a, b, c, d);
output z;
input a, b, c, d;
nand (z, a, b, c, d);
endmodule
 
module bw_u1_zhnand4_1x (z, a, b, c, d);
output z;
input a, b, c, d;
nand (z, a, b, c, d);
endmodule
 
module bw_u1_zhnand4_2x (z, a, b, c, d);
output z;
input a, b, c, d;
nand (z, a, b, c, d);
endmodule
 
 
module bw_u1_zhnor2_0p6x (z, a, b);
output z;
input a, b;
nor (z, a, b);
endmodule
 
module bw_u1_zhnor2_1x (z, a, b);
output z;
input a, b;
nor (z, a, b);
endmodule
 
module bw_u1_zhnor2_2x (z, a, b);
output z;
input a, b;
nor (z, a, b);
endmodule
 
 
 
module bw_u1_zhnor3_0p6x (z, a, b, c);
output z;
input a, b, c;
nor (z, a, b, c);
endmodule
 
 
module bw_u1_zhaoi21_0p4x (z,b1,b2,a);
 
output z;
input b1;
input b2;
input a;
 
endmodule
 
 
 
module bw_u1_zhaoi21_1x (z, a, b1, b2);
 
output z;
input b1;
input b2;
input a;
 
 
endmodule
 
 
 
module bw_u1_zhoai21_1x (z,b1,b2,a );
output z;
input b1;
input b2;
input a;
endmodule
 
 
 
 
module bw_u1_zhoai211_0p3x (z, a, b, c1, c2);
output z;
input c1;
input c2;
input b;
input a;
endmodule
 
 
 
 
 
module bw_u1_zhoai211_1x (z, a, b, c1, c2);
output z;
input a, b, c1, c2;
endmodule
 
 
 
 
 
/////////////// Scan data lock up latch ///////////////
 
module bw_u1_scanlg_2x (so, sd, ck, se);
output so;
input sd, ck, se;
 
 
 
endmodule
 
module bw_u1_scanl_2x (so, sd, ck);
output so;
input sd, ck;
 
 
 
endmodule
 
 
 
////////////////// Synchronizer ////////////////
 
module bw_u1_syncff_4x (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
 
 
endmodule
 
 
 
 
////////////////////////////////////////////////////////////////////////
//
// non library cells
//
////////////////////////////////////////////////////////////////////////
 
// These cells are used only in custom DP macros
// Do not use in any block design without prior permission
 
 
module bw_u1_zzeccxor2_5x (z, a, b);
output z;
input a, b;
 
endmodule
 
 
 
module bw_u1_zzmulcsa42_5x (sum, carry, cout, a, b, c, d, cin);
output sum, carry, cout;
input a, b, c, d, cin;
endmodule
 
 
 
module bw_u1_zzmulcsa32_5x (sum, cout, a, b, c);
output sum, cout;
input a, b, c;
endmodule
 
 
 
module bw_u1_zzmulppmuxi21_2x ( z, d0, d1, s );
output z;
input d0, d1, s;
endmodule
 
 
 
module bw_u1_zzmulnand2_2x ( z, a, b );
output z;
input a;
input b;
endmodule
 
 
 
// Primitives
 
 
 
 
module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2);
output z;
input d0, d1, d2, s0, s1, s2;
// for Blacktie
`ifdef VERPLEX
$constraint dp_1h3 ($one_hot ({s0,s1,s2}));
`endif
endmodule
 
 
 
 
 
 
 
module zmuxi41d_prim (z, d0, d1, d2, d3, s0, s1, s2, s3);
output z;
input d0, d1, d2, d3, s0, s1, s2, s3;
// for Blacktie
`ifdef VERPLEX
$constraint dp_1h4 ($one_hot ({s0,s1,s2,s3}));
`endif
endmodule
 
 
 
module zsoff_prim (q, so, ck, d, se, sd);
output q, so;
input ck, d, se, sd;
endmodule
 
 
module zsoffr_prim (q, so, ck, d, se, sd, r_l);
output q, so;
input ck, d, se, sd, r_l;
endmodule
 
 
module zsoffi_prim (q_l, so, ck, d, se, sd);
output q_l, so;
input ck, d, se, sd;
endmodule
 
 
 
module zsoffm2_prim (q, so, ck, d0, d1, s, se, sd);
output q, so;
input ck, d0, d1, s, se, sd;
endmodule
 
module zsoffasr_prim (q, so, ck, d, r_l, s_l, se, sd);
output q, so;
input ck, d, r_l, s_l, se, sd;
 
// asynchronous reset and asynchronous set
// (priority: r_l > s_l > se > d)
 
 
 
endmodule
 
 
 
module zckenbuf_prim (clk, rclk, en_l, tm_l);
output clk;
input rclk, en_l, tm_l;
endmodule
 
module bw_mckbuf_40x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_33x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_30x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_28x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_25x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_22x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_19x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_17x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_14x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_11x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_8x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_7x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_6x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_4p5x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_3x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
module bw_mckbuf_1p5x (clk, rclk, en);
output clk;
input rclk;
input en;
 
 
endmodule
 
//bw_u1_minbuf_1x
//
 
module bw_u1_minbuf_1x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
//bw_u1_minbuf_4x
//
 
module bw_u1_minbuf_4x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
//bw_u1_minbuf_5x
//
 
module bw_u1_minbuf_5x (
z,
a );
 
output z;
input a;
 
 
endmodule
 
module bw_u1_ckenbuf_4p5x (clk, rclk, en_l, tm_l);
output clk;
input rclk, en_l, tm_l;
endmodule
 
// dummy fill modules to get rid of DFT "CAP" property errors (bug 5487)
 
module bw_u1_fill_1x(\vdd! );
input \vdd! ;
endmodule
 
module bw_u1_fill_2x(\vdd! );
input \vdd! ;
endmodule
 
module bw_u1_fill_3x(\vdd! );
input \vdd! ;
endmodule
 
module bw_u1_fill_4x(\vdd! );
input \vdd! ;
endmodule
/trunk/hdl/macrocell/sparc_libs/m1_lib.v
0,0 → 1,683
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: m1.behV
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// 64 bit nor gate with first 32 bits out
 
module zznor64_32 ( znor64, znor32, a );
input [63:0] a;
output znor64;
output znor32;
 
 
 
endmodule // zznor64_32
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 36 bit or gate
 
module zzor36 ( z, a );
input [35:0] a;
output z;
 
endmodule // zzor36
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 32 bit or gate
 
module zzor32 ( z, a );
input [31:0] a;
output z;
 
 
endmodule // zzor32
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 24 bit nor gate
 
module zznor24 ( z, a );
input [23:0] a;
output z;
 
 
endmodule // zznor24
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 16 bit nor gate
 
module zznor16 ( z, a );
input [15:0] a;
output z;
 
 
endmodule // zznor16
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 8 bit or gate
 
module zzor8 ( z, a );
input [7:0] a;
output z;
 
endmodule // zzor8
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
// Description: This block implements the adder for the sparc FPU.
// It takes two operands and a carry bit. It adds them together
// and sends the output to adder_out.
 
module zzadd13 ( rs1_data, rs2_data, cin, adder_out );
 
input [12:0] rs1_data; // 1st input operand
input [12:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [12:0] adder_out; // result of adder
 
 
endmodule // zzadd13
 
 
 
////////////////////////////////////////////////////////////////////////////////
// Description: This block implements the adder for the sparc FPU.
// It takes two operands and a carry bit. It adds them together
// and sends the output to adder_out.
 
module zzadd56 ( rs1_data, rs2_data, cin, adder_out );
 
input [55:0] rs1_data; // 1st input operand
input [55:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [55:0] adder_out; // result of adder
 
 
endmodule // zzadd56
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzadd48 ( rs1_data, rs2_data, cin, adder_out );
 
input [47:0] rs1_data; // 1st input operand
input [47:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [47:0] adder_out; // result of adder
 
 
endmodule // zzadd48
 
 
 
////////////////////////////////////////////////////////////////////////////////
// This adder is primarily used in the multiplier.
// The cin to out path is optimized.
 
module zzadd34c ( rs1_data, rs2_data, cin, adder_out );
 
input [33:0] rs1_data;
input [33:0] rs2_data;
input cin;
 
output [33:0] adder_out;
 
 
 
endmodule // zzadd34c
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzadd32 ( rs1_data, rs2_data, cin, adder_out, cout );
 
input [31:0] rs1_data; // 1st input operand
input [31:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [31:0] adder_out; // result of adder
output cout; // carry out
 
 
endmodule // zzadd32
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzadd18 ( rs1_data, rs2_data, cin, adder_out, cout );
 
input [17:0] rs1_data; // 1st input operand
input [17:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [17:0] adder_out; // result of adder
output cout; // carry out
 
 
endmodule // zzadd18
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzadd8 ( rs1_data, rs2_data, cin, adder_out, cout );
 
input [7:0] rs1_data; // 1st input operand
input [7:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [7:0] adder_out; // result of add & decrement
output cout; // carry out
 
 
endmodule // zzadd8
 
 
 
////////////////////////////////////////////////////////////////////////////////
// Special 4-operand 32b adder used in spu_shamd5
// Description: This block implements the 4-operand 32-bit adder for SPU
// It takes four 32-bit operands. It add them together and
// output the 32-bit results to adder_out. The overflow of
// 32th bit and higher will be ignored.
 
module zzadd32op4 ( rs1_data, rs2_data, rs3_data, rs4_data, adder_out );
 
input [31:0] rs1_data; // 1st input operand
input [31:0] rs2_data; // 2nd input operand
input [31:0] rs3_data; // 3rd input operand
input [31:0] rs4_data; // 4th input operand
 
output [31:0] adder_out; // result of add
 
 
endmodule // zzadd32op4
 
 
////////////////////////////////////////////////////////////////////////////////
// Description: This block implements the adder for the sparc alu.
// It takes two operands and a carry bit. It adds them together
// and sends the output to adder_out. It outputs the overflow
// and carry condition codes for both 64 bit and 32 bit operations.
 
module zzadd64 ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 );
 
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [63:0] adder_out; // result of adder
output cout32; // carry out from lower 32 bit add
output cout64; // carry out from 64 bit add
 
 
endmodule // zzadd64
 
 
 
///////////////////////////////////////////////////////////////////////
/*
// Description: This is the ffu VIS adder. It can do either
// 2 16 bit adds or 1 32 bit add.
*/
 
module zzadd32v (/*AUTOARG*/
// Outputs
z,
// Inputs
a, b, cin, add32
) ;
input [31:0] a;
input [31:0] b;
input cin;
input add32;
 
output [31:0] z;
 
 
 
 
endmodule // zzadd32v
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 64-bit incrementer
 
module zzinc64 ( in, out );
 
input [63:0] in;
 
output [63:0] out; // result of increment
 
 
endmodule // zzinc64
 
 
////////////////////////////////////////////////////////////////////////////////
// 48-bit incrementer
 
module zzinc48 ( in, out, overflow );
 
input [47:0] in;
 
output [47:0] out; // result of increment
output overflow; // overflow
 
 
endmodule // zzinc48
 
 
////////////////////////////////////////////////////////////////////////////////
// 32-bit incrementer
 
module zzinc32 ( in, out );
 
input [31:0] in;
 
output [31:0] out; // result of increment
 
 
endmodule // zzinc32
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzecc_exu_chkecc2 ( q,ce, ue, ne, d, p, vld );
input [63:0] d;
input [7:0] p;
input vld;
output [6:0] q;
output ce,
ue,
ne;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule // zzecc_exu_chkecc2
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzecc_sctag_24b_gen ( din, dout, parity ) ;
 
// Input Ports
input [23:0] din ;
 
// Output Ports
output [23:0] dout ;
output [5:0] parity ;
 
 
// Local Reg and Wires
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
module zzecc_sctag_30b_cor ( din, parity, dout, corrected_bit ) ;
 
// Input Ports
input [23:0] din ;
input [4:0] parity ;
 
// Output Ports
output [23:0] dout ;
output [4:0] corrected_bit ;
 
 
// Local Reg and Wires
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
 
 
////////////////////////////////////////////////////////////////////////////////
//Module Name: zzecc_sctag_ecc39
//Function: Error Detection and Correction
//
//
 
module zzecc_sctag_ecc39 ( dout, cflag, pflag, parity, din);
 
//Output: 32bit corrected data
output[31:0] dout;
output [5:0] cflag;
output pflag;
//Input: 32bit data din
input [31:0] din;
input [6:0] parity;
 
 
//refer to the comments in parity_gen_32b.v for the position description
 
 
//generate total parity flag
//6 to 32 decoder
 
//correct the error bit, it can only correct one error bit.
 
endmodule // zzecc_sctag_ecc39
 
 
////////////////////////////////////////////////////////////////////////////////
//Module Name: zzecc_sctag_pgen_32b
//Function: Generate 7 parity bits for 32bits input data
//
 
module zzecc_sctag_pgen_32b ( dout, parity, din);
 
//Output: 32bit dout and 7bit parity bit
output[31:0] dout;
output [6:0] parity;
 
//Input: 32bit data din
input [31:0] din;
 
//input data passing through this module
 
//generate parity bits based on the hamming codes
//the method to generate parity bit is shown as follows
//1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
//P1 P2 d0 P4 d1 d2 d3 P8 d4 d5 d6 d7 d8 d9 d10 P16 d11 d12 d13
//
// 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
//d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 P32 d26 d27 d28
//
// 36 37 38
//d29 d30 d31
//For binary numbers B1-B2-B3-B4-B5-B6:
//Parity bit P1,P2,P4,P8,P16,P32 can be generated from the above group of
//bits B1=1,B2=1,B3=1,B4=1,B5=1,B6=1 respectively.
 
//use parity[5:0] to stand for P1,P2,P4,P8,P16,P32
//
//
//
//
//
 
//the last parity bit is the xor of all 38bits
//it can be further simplified as:
//din= d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
//p0 = x x x x x x x x x x
//p1 = x x x x x x x x x
//p2 = x x x x x x x x x
//p3 = x x x x x x x
//p4 = x x x x x
//p5 =
//-------------------------------------------------------------------
//Total 3 3 3 4 3 3 4 3 4 4 5 3 3 4 3 4
//
//din=d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
//p0= x x x x x x x x
//p1= x x x x x x x x x
//p2= x x x x x x x x x
//p3= x x x x x x x x
//p4= x x x x x x x x x x
//p5= x x x x x x
//-------------------------------------------------------------------
//total 4 5 3 4 4 5 4 5 5 6 3 3 4 3 4 4
 
//so total=even number, the corresponding bit will not show up in the
//final xor tree.
endmodule // zzecc_sctag_pgen_32b
 
////////////////////////////////////////////////////////////////////////////////
// 34 bit parity tree
 
module zzpar34 ( z, d );
input [33:0] d;
output z;
 
 
endmodule // zzpar34
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 32 bit parity tree
 
module zzpar32 ( z, d );
input [31:0] d;
output z;
 
 
endmodule // zzpar32
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 28 bit parity tree
 
module zzpar28 ( z, d );
input [27:0] d;
output z;
 
 
endmodule // zzpar28
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 16 bit parity tree
 
module zzpar16 ( z, d );
input [15:0] d;
output z;
 
endmodule // zzpar16
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 8 bit parity tree
 
module zzpar8 ( z, d );
input [7:0] d;
output z;
 
 
endmodule // zzpar8
 
 
 
////////////////////////////////////////////////////////////////////////////////
// 64 -> 6 priority encoder
// Bit 63 has the highest priority
 
module zzpenc64 (/*AUTOARG*/
// Outputs
z,
// Inputs
a
);
 
input [63:0] a;
output [5:0] z;
 
 
 
endmodule // zzpenc64
 
////////////////////////////////////////////////////////////////////////////////
// 4-bit 60x buffers
 
module zzbufh_60x4 (/*AUTOARG*/
// Outputs
z,
// Inputs
a
);
 
input [3:0] a;
output [3:0] z;
 
 
endmodule //zzbufh_60x4
 
// LVT modules added below
 
module zzadd64_lv ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 );
 
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input cin; // carry in
 
output [63:0] adder_out; // result of adder
output cout32; // carry out from lower 32 bit add
output cout64; // carry out from 64 bit add
 
 
endmodule // zzadd64_lv
 
module zzpar8_lv ( z, d );
input [7:0] d;
output z;
 
 
endmodule // zzpar8_lv
 
 
module zzpar32_lv ( z, d );
input [31:0] d;
output z;
 
 
endmodule // zzpar32_lv
 
 
 
module zznor64_32_lv ( znor64, znor32, a );
input [63:0] a;
output znor64;
output znor32;
 
 
 
endmodule // zznor64_32_lv
 
////////////////////////////////////////////////////////////////////////////////
// 64 -> 6 priority encoder
// Bit 63 has the highest priority
// LVT version
 
module zzpenc64_lv (/*AUTOARG*/
// Outputs
z,
// Inputs
a
);
 
input [63:0] a;
output [5:0] z;
 
 
 
endmodule // zzpenc64_lv
 
////////////////////////////////////////////////////////////////////////////////
// 36 bit or gate
// LVT version
 
module zzor36_lv ( z, a );
input [35:0] a;
output z;
 
 
endmodule // zzor36_lv
 
////////////////////////////////////////////////////////////////////////////////
// 34 bit parity tree
// LVT version
 
module zzpar34_lv ( z, d );
input [33:0] d;
output z;
 
 
endmodule // zzpar34_lv
 
 
/trunk/hdl/rtl/s1_top/rst_ctrl.v
0,0 → 1,166
/*
* Reset Controller
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
* The above named program is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* DESCRIPTION:
* This block implements the Reset Controller used by the S1 Core
* to wake up the SPARC Core of the OpenSPARC T1; its behavior was
* reverse-engineered from the OpenSPARC waveforms.
*/
 
`include "s1_defs.h"
 
module rst_ctrl (
sys_clock_i, sys_reset_i,
cluster_cken_o, gclk_o, cmp_grst_o, cmp_arst_o,
ctu_tst_pre_grst_o, adbginit_o, gdbginit_o,
sys_reset_final_o
);
 
/*
* Inputs
*/
 
// System inputs
input sys_clock_i; // System Clock
input sys_reset_i; // System Reset
 
/*
* Registered Outputs
*/
 
output gclk_o;
 
/*
* Registered Outputs
*/
 
// SPARC Core inputs
output cluster_cken_o;
reg cluster_cken_o;
output cmp_grst_o;
reg cmp_grst_o;
output cmp_arst_o;
reg cmp_arst_o;
output ctu_tst_pre_grst_o;
reg ctu_tst_pre_grst_o;
output adbginit_o;
reg adbginit_o;
output gdbginit_o;
reg gdbginit_o;
output sys_reset_final_o;
reg sys_reset_final_o;
 
/*
* Registers
*/
 
// Counter used as a timer to strobe the reset signals
reg[`TIMER_BITS-1:0] cycle_counter;
 
/*
* Procedural blocks
*/
 
// This process handles the timer counter
always @(posedge sys_clock_i)
begin
if(sys_reset_i==1'b1)
begin
cycle_counter = 0;
end
else
begin
if(cycle_counter[`TIMER_BITS-1]==1'b0)
begin
cycle_counter = cycle_counter+1;
end
end
end
 
// This other process assigns the proper values to the outputs
// (that are used as system inputs by the SPARC Core)
always @(posedge sys_clock_i)
begin
if(sys_reset_i==1)
begin
cluster_cken_o <= 0;
cmp_grst_o <= 0;
cmp_arst_o <= 0;
ctu_tst_pre_grst_o <= 0;
adbginit_o <= 0;
gdbginit_o <= 0;
sys_reset_final_o <= 1;
end
else
begin
if(cycle_counter<`RESET_CYCLES_1)
begin
cluster_cken_o <= 0;
cmp_grst_o <= 0;
cmp_arst_o <= 0;
ctu_tst_pre_grst_o <= 0;
adbginit_o <= 0;
gdbginit_o <= 0;
sys_reset_final_o <= 1;
end
else
if(cycle_counter<`RESET_CYCLES_2)
begin
cluster_cken_o <= 0;
cmp_grst_o <= 0;
cmp_arst_o <= 1; // <--
ctu_tst_pre_grst_o <= 0;
adbginit_o <= 1; // <--
gdbginit_o <= 0;
sys_reset_final_o <= 1;
end
else
if(cycle_counter<`RESET_CYCLES_3)
begin
cluster_cken_o <= 1; // <--
cmp_grst_o <= 0;
cmp_arst_o <= 1;
ctu_tst_pre_grst_o <= 1; // <--
adbginit_o <= 1;
gdbginit_o <= 0;
sys_reset_final_o <= 1;
end
else
if(cycle_counter<`RESET_CYCLES_4)
begin
cluster_cken_o <= 1;
cmp_grst_o <= 1; // <--
cmp_arst_o <= 1;
ctu_tst_pre_grst_o <= 1;
adbginit_o <= 1;
gdbginit_o <= 1; // <--
sys_reset_final_o <= 1;
end
else
begin
cluster_cken_o <= 1;
cmp_grst_o <= 1;
cmp_arst_o <= 1;
ctu_tst_pre_grst_o <= 1;
adbginit_o <= 1;
gdbginit_o <= 1;
sys_reset_final_o <= 0; // <--
end
end
end
 
assign gclk_o = (cycle_counter>`GCLK_CYCLES) & sys_clock_i;
 
endmodule
trunk/hdl/rtl/s1_top/rst_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/rtl/s1_top/spc2wbm.v =================================================================== --- trunk/hdl/rtl/s1_top/spc2wbm.v (nonexistent) +++ trunk/hdl/rtl/s1_top/spc2wbm.v (revision 4) @@ -0,0 +1,664 @@ +/* + * Bridge from SPARC Core to Wishbone Master + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements a bridge from one SPARC Core of the + * OpenSPARC T1 to a master interface that makes use of the + * Wishbone interconnect protocol. + * For informations about Sun Microsystems' OpenSPARC T1 + * refer to the web site http://www.opensparc.net + * For informations about OpenCores' Wishbone interconnect + * please refer to the web site http://www.opencores.org + */ + +`include "s1_defs.h" + +module spc2wbm ( + sys_clock_i, sys_reset_i, sys_interrupt_source_i, + spc_req_i, spc_atom_i, spc_packetout_i, + spc_grant_o, spc_ready_o, spc_packetin_o, spc_stallreq_o, + wbm_ack_i, wbm_data_i, + wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o + ); + + /* + * Inputs + */ + + // System inputs + input sys_clock_i; // System Clock + input sys_reset_i; // System Reset + input[5:0] sys_interrupt_source_i; // Interrupt Requests + + // SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core + input[4:0] spc_req_i; // Request + input spc_atom_i; // Atomic Request + input[(`PCX_WIDTH-1):0] spc_packetout_i; // Outgoing Packet + + // Wishbone Master interface inputs + input wbm_ack_i; // Ack + input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In + + /* + * Registered Outputs + */ + + // SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core + output[4:0] spc_grant_o; // Grant + reg[4:0] spc_grant_o; // Grant + output spc_ready_o; // Ready + reg spc_ready_o; // Ready + output[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet + reg[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet + output spc_stallreq_o; // Stall Request + reg spc_stallreq_o; // Stall Request + + // Wishbone Master interface outputs + output wbm_cycle_o; // Cycle Start + reg wbm_cycle_o; // Cycle Start + output wbm_strobe_o; // Strobe Request + reg wbm_strobe_o; // Strobe Request + output wbm_we_o; // Write Enable + reg wbm_we_o; // Write Enable + output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus + reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus + output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out + reg[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out + output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output + reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output + + /* + * Registers + */ + + // Registers to latch requests from SPARC Core to Wishbone Master + reg[3:0] state; + reg[4:0] spc2wbm_region; // Target region number (one-hot encoded) + reg spc2wbm_atom; + reg[(`PCX_WIDTH-1):0] spc2wbm_packet; // Latched Packet + + // Wishbone Master to SPARC Core info used to encode the return packet + reg wbm2spc_valid; // Valid + reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type + reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error + reg wbm2spc_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch + reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread + reg[(`CPX_P_HI-`CPX_P_LO):0] wbm2spc_packet_id; // Packet ID + reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data + reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_interrupt_source; // Interrupt Source + reg wbm2spc_reset_not_int; // Reset and not interrupt packet + reg[4:0] wbm2spc_virtual_cpu_target; // ID of virtual CPU target + reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_intsrc_or_resettype; // Interrupt Source or Reset Type + reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_new_irq; // New Interrupt Request Pending + + /* + * Wires + */ + + // Decoded SPARC Core to Wishbone Master info + wire spc2wbm_req; // Request + wire spc2wbm_valid; // Valid + wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type; // Request type + wire spc2wbm_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch + wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id; // CPU ID + wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread; // Thread + wire[(`PCX_BF_HI-`PCX_BF_LO):0] spc2wbm_buffer; // Buffer + wire[(`PCX_P_HI-`PCX_P_LO):0] spc2wbm_packet_id; // Packet ID + wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size; // Load/Store size + wire[(`PCX_ERR_HI-`PCX_ERR_LO):0] spc2wbm_error; // Error + wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr; // Address + wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data; // Store Data + + // Return packets assembled with various fields + wire[`CPX_WIDTH-1:0] wbm2spc_packet_dat; // Incoming Packet - Data + wire[`CPX_WIDTH-1:0] wbm2spc_packet_int; // Incoming Packet - Interrupt + + /* + * Encode/decode incoming info + * + * Legenda: available constants for some of the PCX/CPX fields. + * + * spc2wbm_size (3 bits) is one of: + * - PCX_SZ_1B + * - PCX_SZ_2B + * - PCX_SZ_4B + * - PCX_SZ_8B + * - PCX_SZ_16B (Read accesses only) + * + * spc2wbm_type (5 bits) is one of: + * { LOAD_RQ, IMISS_RQ, STORE_RQ, CAS1_RQ, CAS2_RQ, SWAP_RQ, STRLOAD_RQ, STRST_RQ, STQ_RQ, + * INT_RQ, FWD_RQ, FWD_RPY, RSVD_RQ } + * + * wbm2spc_type (4 bits) is one of: + * { LOAD_RET, INV_RET, ST_ACK, AT_ACK, INT_RET, TEST_RET, FP_RET, IFILL_RET, EVICT_REQ, + * ERR_RET, STRLOAD_RET, STRST_ACK, FWD_RQ_RET, FWD_RPY_RET, RSVD_RET } + * + */ + + // Decode info arriving from the SPC side + assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] ); + assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD]; + assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO]; + assign spc2wbm_rnwd_or_ncif = spc2wbm_packet[`PCX_R]; + assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO]; + assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO]; + assign spc2wbm_buffer = spc2wbm_packet[`PCX_BF_HI:`PCX_BF_LO]; + assign spc2wbm_packet_id = spc2wbm_packet[`PCX_P_HI:`PCX_P_LO]; + assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO]; + assign spc2wbm_error = spc2wbm_packet[`PCX_ERR_HI:`PCX_ERR_LO]; + assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO]; + assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO]; + + // Encode info going to the SPC side assembling return packets + assign wbm2spc_packet_dat = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, + wbm2spc_rnwd_or_ncif, wbm2spc_thread, 2'b00, wbm2spc_packet_id, + 2'b00, wbm2spc_data }; + assign wbm2spc_packet_int = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, + wbm2spc_rnwd_or_ncif, wbm2spc_thread, wbm2spc_interrupt_source, + 111'b0, wbm2spc_reset_not_int, 3'b0, wbm2spc_virtual_cpu_target, + 2'b0, wbm2spc_intsrc_or_resettype }; + + /* + * State Machine + */ + + always @(posedge sys_clock_i) begin + + // Initialization + if(sys_reset_i==1) begin + + // Clear outputs going to SPARC Core inputs + spc_grant_o = 5'b00000; + spc_ready_o = 0; + spc_packetin_o = 0; + spc_stallreq_o = 0; + + // Clear Wishbone Master interface outputs + wbm_cycle_o = 0; + wbm_strobe_o = 0; + wbm_we_o = 0; + wbm_addr_o = 64'b0; + wbm_data_o = 64'b0; + wbm_sel_o = 8'b0; + + // Prepare wakeup packet for SPARC Core, the resulting output is + // spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001; + wbm2spc_valid = 1; + wbm2spc_type = `INT_RET; + wbm2spc_error = 0; + wbm2spc_rnwd_or_ncif = 0; + wbm2spc_thread = 0; + wbm2spc_packet_id = 0; + wbm2spc_interrupt_source = 0; + wbm2spc_reset_not_int = 1; + wbm2spc_virtual_cpu_target = 0; + wbm2spc_intsrc_or_resettype = 6'b000001; + wbm2spc_new_irq = 0; // Ignored for wakeup packet + + // Clear state machine + state = `STATE_WAKEUP; + + end else begin + + // FSM State 0: STATE_WAKEUP + // Send to the SPARC Core the wakeup packet + if(state==`STATE_WAKEUP) begin + + // Send wakeup packet + spc_ready_o = 1; + spc_packetin_o = wbm2spc_packet_int; + +// synopsys translate_off + // Display comment + $display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting..."); + $display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core"); +// synopsys translate_on + + // Unconditional state change + state = `STATE_IDLE; + + // FSM State 1: STATE_IDLE + // Wait for a request from the SPARC Core + // If available send an interrupt packet to the Core + end else if(state==`STATE_IDLE) begin + + // Check if there's an incoming request + if(spc2wbm_req==1) begin + + // Clear previously modified outputs + spc_ready_o = 0; + spc_packetin_o = 0; + + // Stall other requests from the SPARC Core + spc_stallreq_o = 1; + + // Latch target region and atomicity + spc2wbm_region = spc_req_i; + spc2wbm_atom = spc_atom_i; + + // Jump to next state + state = `STATE_REQUEST_LATCHED; + + // See if the interrupt vector has changed + end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin + + // Set the flag for next cycle + wbm2spc_new_irq = 1; + + // Prepare the interrupt packet for the SPARC Core + wbm2spc_valid = 1; + wbm2spc_type = `INT_RET; + wbm2spc_error = 0; + wbm2spc_rnwd_or_ncif = 0; + wbm2spc_thread = 0; + wbm2spc_packet_id = 0; + wbm2spc_interrupt_source = sys_interrupt_source_i; + wbm2spc_reset_not_int = 0; + wbm2spc_virtual_cpu_target = 0; + wbm2spc_intsrc_or_resettype = sys_interrupt_source_i; + + // Stall other requests from the SPARC Core + spc_stallreq_o = 1; + + // Next cycle see if there's an int to be forwarded to the Core + end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_new_irq) begin + + // Clean the flag + wbm2spc_new_irq = 0; + + // Send the interrupt packet to the Core + spc_ready_o = 1; + spc_packetin_o = wbm2spc_packet_int; + + // Stall other requests from the SPARC Core + spc_stallreq_o = 1; + + // Stay in this state + state = `STATE_IDLE; + + // Nothing to do, stay idle + end else begin + + // Clear previously modified outputs + spc_ready_o = 0; + spc_packetin_o = 0; + spc_stallreq_o = 0; + + // Stay in this state + state = `STATE_IDLE; + + end + + // FSM State 2: STATE_REQUEST_LATCHED + // We've just latched the request + // Now we latch the packet + // Start granting the request + end else if(state==`STATE_REQUEST_LATCHED) begin + + // Latch the incoming packet + spc2wbm_packet = spc_packetout_i; + + // Grant the request to the SPARC Core + spc_grant_o = spc2wbm_region; + +// synopsys translate_off + // Print details of SPARC Core request + $display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***"); + if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0"); + else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1"); + else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2"); + else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3"); + else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block"); + else $display("INFO: SPC2WBM: Request to target region unknown"); + if(spc2wbm_atom==1) $display("INFO: SPC2WBM: Request is ATOMIC"); + else $display("INFO: SPC2WBM: Request is not atomic"); +// synopsys translate_on + + // Unconditional state change + state = `STATE_PACKET_LATCHED; + + // FSM State 3: STATE_PACKET_LATCHED + // The packet has already been latched + // Decode this packet to build the request for the Wishbone bus + // The grant of the request to the SPARC Core has been completed + end else if(state==`STATE_PACKET_LATCHED) begin + + // Clear previously modified outputs + spc_grant_o = 5'b0; + + // Issue a request on the Wishbone bus + wbm_cycle_o = 1; + wbm_strobe_o = 1; + wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:3], 3'b000 }; + wbm_data_o = spc2wbm_data; + + // Handle write enable and byte select + if(spc2wbm_type==`IMISS_RQ) begin + + // For instruction miss always read memory + wbm_we_o = 0; + if(spc2wbm_region==5'b10000) + // For accesses to SSI ROM only 32 bits are required + wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2)); + else + // For accesses to RAM 256 bits are expected (2 ret packets) + wbm_sel_o = 8'b11111111; + + end else begin + + // For data load/store use the provided data + wbm_we_o = !spc2wbm_rnwd_or_ncif; + case(spc2wbm_size) + `PCX_SZ_1B: wbm_sel_o = (1'b1<
trunk/hdl/rtl/s1_top/spc2wbm.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/rtl/s1_top/int_ctrl.v =================================================================== --- trunk/hdl/rtl/s1_top/int_ctrl.v (nonexistent) +++ trunk/hdl/rtl/s1_top/int_ctrl.v (revision 4) @@ -0,0 +1,114 @@ +/* + * Interrupt Controller + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements the Interrupt Controller used by the S1 + * to detect if some peripheral raised an interrupt request. + * A proper interrupt packet is sent to the SPARC Core by the + * bridge with one of the 64 interrupt sources (provided by this + * controller) encoded in the 6-bit Interrupt Source field. + * Please note that IRQ 0 is reserved for Power-On Reset (handled + * directly by the bridge) so up to 63 external peripherals can be + * connected to the S1. + * Note also that currently the interrupt vector is hardwired to + * all zeroes. + */ + +module int_ctrl ( + sys_clock_i, sys_reset_i, sys_irq_i, + sys_interrupt_source_o + ); + + // System inputs + input sys_clock_i; + input sys_reset_i; + + // Incoming Interrupt Requests + input[63:0] sys_irq_i; + + // Encoded Interrupt Source + output[5:0] sys_interrupt_source_o; + reg[5:0] sys_interrupt_source_o; + + // Encoding of the source using priority and ignoring IRQ 0 + always @(posedge sys_clock_i) begin + if(sys_reset_i==1) sys_interrupt_source_o = 0; + else if(sys_irq_i[63]) sys_interrupt_source_o = 63; + else if(sys_irq_i[62]) sys_interrupt_source_o = 62; + else if(sys_irq_i[61]) sys_interrupt_source_o = 61; + else if(sys_irq_i[60]) sys_interrupt_source_o = 60; + else if(sys_irq_i[59]) sys_interrupt_source_o = 59; + else if(sys_irq_i[58]) sys_interrupt_source_o = 58; + else if(sys_irq_i[57]) sys_interrupt_source_o = 57; + else if(sys_irq_i[56]) sys_interrupt_source_o = 56; + else if(sys_irq_i[55]) sys_interrupt_source_o = 55; + else if(sys_irq_i[54]) sys_interrupt_source_o = 54; + else if(sys_irq_i[53]) sys_interrupt_source_o = 53; + else if(sys_irq_i[52]) sys_interrupt_source_o = 52; + else if(sys_irq_i[51]) sys_interrupt_source_o = 51; + else if(sys_irq_i[50]) sys_interrupt_source_o = 50; + else if(sys_irq_i[49]) sys_interrupt_source_o = 49; + else if(sys_irq_i[48]) sys_interrupt_source_o = 48; + else if(sys_irq_i[47]) sys_interrupt_source_o = 47; + else if(sys_irq_i[46]) sys_interrupt_source_o = 46; + else if(sys_irq_i[45]) sys_interrupt_source_o = 45; + else if(sys_irq_i[44]) sys_interrupt_source_o = 44; + else if(sys_irq_i[43]) sys_interrupt_source_o = 43; + else if(sys_irq_i[42]) sys_interrupt_source_o = 42; + else if(sys_irq_i[41]) sys_interrupt_source_o = 41; + else if(sys_irq_i[40]) sys_interrupt_source_o = 40; + else if(sys_irq_i[39]) sys_interrupt_source_o = 39; + else if(sys_irq_i[38]) sys_interrupt_source_o = 38; + else if(sys_irq_i[37]) sys_interrupt_source_o = 37; + else if(sys_irq_i[36]) sys_interrupt_source_o = 36; + else if(sys_irq_i[35]) sys_interrupt_source_o = 35; + else if(sys_irq_i[34]) sys_interrupt_source_o = 34; + else if(sys_irq_i[33]) sys_interrupt_source_o = 33; + else if(sys_irq_i[32]) sys_interrupt_source_o = 32; + else if(sys_irq_i[31]) sys_interrupt_source_o = 31; + else if(sys_irq_i[30]) sys_interrupt_source_o = 30; + else if(sys_irq_i[29]) sys_interrupt_source_o = 29; + else if(sys_irq_i[28]) sys_interrupt_source_o = 28; + else if(sys_irq_i[27]) sys_interrupt_source_o = 27; + else if(sys_irq_i[26]) sys_interrupt_source_o = 26; + else if(sys_irq_i[25]) sys_interrupt_source_o = 25; + else if(sys_irq_i[24]) sys_interrupt_source_o = 24; + else if(sys_irq_i[23]) sys_interrupt_source_o = 23; + else if(sys_irq_i[22]) sys_interrupt_source_o = 22; + else if(sys_irq_i[21]) sys_interrupt_source_o = 21; + else if(sys_irq_i[20]) sys_interrupt_source_o = 20; + else if(sys_irq_i[19]) sys_interrupt_source_o = 19; + else if(sys_irq_i[18]) sys_interrupt_source_o = 18; + else if(sys_irq_i[17]) sys_interrupt_source_o = 17; + else if(sys_irq_i[16]) sys_interrupt_source_o = 16; + else if(sys_irq_i[15]) sys_interrupt_source_o = 15; + else if(sys_irq_i[14]) sys_interrupt_source_o = 14; + else if(sys_irq_i[13]) sys_interrupt_source_o = 13; + else if(sys_irq_i[12]) sys_interrupt_source_o = 12; + else if(sys_irq_i[11]) sys_interrupt_source_o = 11; + else if(sys_irq_i[10]) sys_interrupt_source_o = 10; + else if(sys_irq_i[9]) sys_interrupt_source_o = 9; + else if(sys_irq_i[8]) sys_interrupt_source_o = 8; + else if(sys_irq_i[7]) sys_interrupt_source_o = 7; + else if(sys_irq_i[6]) sys_interrupt_source_o = 6; + else if(sys_irq_i[5]) sys_interrupt_source_o = 5; + else if(sys_irq_i[4]) sys_interrupt_source_o = 4; + else if(sys_irq_i[3]) sys_interrupt_source_o = 3; + else if(sys_irq_i[2]) sys_interrupt_source_o = 2; + else if(sys_irq_i[1]) sys_interrupt_source_o = 1; + else sys_interrupt_source_o = 0; + end + +endmodule
trunk/hdl/rtl/s1_top/int_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/rtl/s1_top/packet.txt =================================================================== --- trunk/hdl/rtl/s1_top/packet.txt (nonexistent) +++ trunk/hdl/rtl/s1_top/packet.txt (revision 4) @@ -0,0 +1,1695 @@ +// ========== Copyright Header Begin ========================================== +// +// OpenSPARC T1 Processor File: lsu_qdp1.v +// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +// +// The above named program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// The above named program is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this work; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +// +// ========== Copyright Header End ============================================ +/////////////////////////////////////////////////////////////////////// +/* +// Description: LSU PCX Datapath - QDP1 +*/ +//////////////////////////////////////////////////////////////////////// +// header file includes +//////////////////////////////////////////////////////////////////////// +`include "sys.h" // system level definition file which contains the + // time scale definition +`include "iop.h" +`include "lsu.h" + +//////////////////////////////////////////////////////////////////////// +// Local header file includes / local defines +//////////////////////////////////////////////////////////////////////// + +module lsu_qdp1 ( /*AUTOARG*/ + // Outputs + so, lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m, lsu_va_wtchpt_addr, spc_pcx_data_pa, + dtag_wdata_m, lmq0_byp_misc_sz, lmq1_byp_misc_sz, + lmq2_byp_misc_sz, lmq3_byp_misc_sz, lsu_byp_misc_sz_e, + lsu_l2fill_sign_extend_m, lsu_l2fill_bendian_m, lmq0_l2fill_fpld, + lmq1_l2fill_fpld, lmq2_l2fill_fpld, lmq3_l2fill_fpld, lmq_ld_rd1, + lmq0_ncache_ld, lmq1_ncache_ld, lmq2_ncache_ld, lmq3_ncache_ld, + lmq0_ld_rq_type, lmq1_ld_rq_type, lmq2_ld_rq_type, + lmq3_ld_rq_type, lmq0_ldd_vld, lmq1_ldd_vld, lmq2_ldd_vld, + lmq3_ldd_vld, ld_sec_hit_thrd0, ld_sec_hit_thrd1, + ld_sec_hit_thrd2, ld_sec_hit_thrd3, lmq0_pcx_pkt_addr, + lmq1_pcx_pkt_addr, lmq2_pcx_pkt_addr, lmq3_pcx_pkt_addr, + lsu_mmu_rs3_data_g, lsu_tlu_rs3_data_g, lsu_diagnstc_wr_data_b0, + lsu_diagnstc_wr_data_e, lsu_ifu_stxa_data, + lsu_ifu_ld_icache_index, lsu_ifu_ld_pcxpkt_tid, lsu_error_pa_m, + lsu_pref_pcx_req, st_rs3_data_g, lsu_ldst_va_way_g, + dcache_alt_data_w0_m, + // Inputs + rclk, si, se, lsu_dcache_iob_rd_w, lsu_ramtest_rd_w, + lsu_pcx_rq_sz_b3, lsu_diagnstc_data_sel, pcx_pkt_src_sel, + lsu_stb_pcx_rvld_d1, imiss_pcx_mx_sel, fwd_int_fp_pcx_mx_sel, + spu_lsu_ldst_pckt, tlu_lsu_pcxpkt, const_cpuid, ifu_pcx_pkt, + lmq_byp_data_en_w2, lmq_byp_data_sel0, lmq_byp_data_sel1, + lmq_byp_data_sel2, lmq_byp_data_sel3, lmq_byp_ldxa_sel0, + lmq_byp_ldxa_sel1, lmq_byp_ldxa_sel2, lmq_byp_ldxa_sel3, + lmq_byp_data_fmx_sel, exu_lsu_rs3_data_e, ifu_lsu_ldxa_data_w2, + tlu_lsu_int_ldxa_data_w2, spu_lsu_ldxa_data_w2, stb_rdata_ramd, + stb_rdata_ramc, lmq_byp_misc_sel, dfq_byp_sel, ld_pcx_rq_sel, + ld_pcx_thrd, lmq_enable, ld_pcx_pkt_g, ffu_lsu_data, + lsu_tlb_st_sel_m, lsu_pcx_fwd_pkt, lsu_pcx_fwd_reply, + lsu_diagnstc_dtagv_prty_invrt_e, lsu_misc_rdata_w2, + lsu_stb_rd_tid, lsu_iobrdge_rply_data_sel, lsu_iobrdge_rd_data, + lsu_atomic_pkt2_bsel_g, lsu_pcx_ld_dtag_perror_w2, + lsu_dcache_rdata_w, lsu_va_wtchpt0_wr_en_l, + lsu_va_wtchpt1_wr_en_l, lsu_va_wtchpt2_wr_en_l, + lsu_va_wtchpt3_wr_en_l, thread0_m, thread1_m, thread2_m, + thread3_m, lsu_thread_g, lsu_ldst_va_m, tlb_pgnum, lsu_bld_pcx_rq, + lsu_bld_rq_addr, lmq0_pcx_pkt_way, lmq1_pcx_pkt_way, + lmq2_pcx_pkt_way, lmq3_pcx_pkt_way, lsu_dfq_ld_vld, + lsu_ifu_asi_data_en_l, lsu_ld0_spec_vld_kill_w2, + lsu_ld1_spec_vld_kill_w2, lsu_ld2_spec_vld_kill_w2, + lsu_ld3_spec_vld_kill_w2, lsu_fwd_rply_sz1_unc, rst_tri_en, + lsu_l2fill_data, l2fill_vld_m, ld_thrd_byp_sel_m, sehold + ) ; + +input rclk ; +input si; +input se; +input sehold; +//input tmb_l; + +output so; +input lsu_dcache_iob_rd_w ; +input lsu_ramtest_rd_w ; + +input lsu_pcx_rq_sz_b3 ; + +input [3:0] lsu_diagnstc_data_sel ; + +input [3:0] pcx_pkt_src_sel ; // sel 1/4 pkt src for pcx. +input lsu_stb_pcx_rvld_d1 ; // stb has been read-delayby1cycle +input imiss_pcx_mx_sel ; // select imiss over spu. +input [2:0] fwd_int_fp_pcx_mx_sel ; // select fwd/intrpt/fpop + +input [`PCX_WIDTH-1:0] spu_lsu_ldst_pckt ; // stream ld/st pkt for pcx. +input [25:0] tlu_lsu_pcxpkt ; // truncated pcx interrupt pkt. +input [2:0] const_cpuid ; // cpu id +input [51:0] ifu_pcx_pkt ; // ifu imiss request. +input [3:0] lmq_byp_data_en_w2 ; +input [3:0] lmq_byp_data_sel0 ; // ldxa/stb/cas bypass data sel. +input [3:0] lmq_byp_data_sel1 ; // ldxa/stb/cas bypass data sel. +input [3:0] lmq_byp_data_sel2 ; // ldxa/stb/cas bypass data sel. +input [3:0] lmq_byp_data_sel3 ; // ldxa/stb/cas bypass data sel. +input [2:0] lmq_byp_ldxa_sel0 ; // ldxa data sel - thread0 +input [2:0] lmq_byp_ldxa_sel1 ; // ldxa data sel - thread1 +input [2:0] lmq_byp_ldxa_sel2 ; // ldxa data sel - thread2 +input [2:0] lmq_byp_ldxa_sel3 ; // ldxa data sel - thread3 +input [3:0] lmq_byp_data_fmx_sel ; // final sel for lmq data. +input [63:0] exu_lsu_rs3_data_e ; // rs3_data for cas pkt 2. +input [63:0] ifu_lsu_ldxa_data_w2 ; // ldxa data from ifu. +//input [63:0] tlu_lsu_ldxa_data_w2 ; // ldxa data from tlu (mmu) +input [63:0] tlu_lsu_int_ldxa_data_w2 ; // ldxa data from tlu (intrpt/scpd) +input [63:0] spu_lsu_ldxa_data_w2 ; // ldxa data from spu +input [75:0] stb_rdata_ramd ; // stb0 data ram output. +input [44:9] stb_rdata_ramc ; // stb0 tag ram output. +input [3:0] lmq_byp_misc_sel ; // select g-stage lmq source +input [3:0] dfq_byp_sel ; +input [3:0] ld_pcx_rq_sel ; +input [1:0] ld_pcx_thrd ; + +input [3:0] lmq_enable ; // 4 enables for lmq. +input [`LMQ_WIDTH-1:40] ld_pcx_pkt_g ; // ld miss pkt for thread. +input [80:0] ffu_lsu_data ; +input [3:0] lsu_tlb_st_sel_m ; +//input [3:0] lsu_tlb_st_sel_g ; +//input lsu_tlb_st_vld_g ; +input [107:0] lsu_pcx_fwd_pkt ; // local fwd reply/req +input lsu_pcx_fwd_reply ; // fwd reply on pcx pkt +input lsu_diagnstc_dtagv_prty_invrt_e ; +//input lsu_diagnstc_wr_src_sel_e ;// dcache/dtag/v write - diag +//input [47:0] lsu_local_ldxa_data_w2 ; // local ldxa data +input [63:0] lsu_misc_rdata_w2 ; // local ldxa data +input [1:0] lsu_stb_rd_tid ; // thread for which stb rd occurs +input [2:0] lsu_iobrdge_rply_data_sel ; +input [43:0] lsu_iobrdge_rd_data ; +input [2:0] lsu_atomic_pkt2_bsel_g ; +input lsu_pcx_ld_dtag_perror_w2 ; +input [63:0] lsu_dcache_rdata_w ; +//input [47:0] tlu_lsu_iobrdge_pc_data ; // NOTE: unused: remove this in sync w/ tlu + +input lsu_va_wtchpt0_wr_en_l; +input lsu_va_wtchpt1_wr_en_l; +input lsu_va_wtchpt2_wr_en_l; +input lsu_va_wtchpt3_wr_en_l; +input thread0_m; +input thread1_m; +input thread2_m; +input thread3_m; + + input [3:0] lsu_thread_g; + + +//input lsu_pa_wtchpt_wr_en_l; +input [47:0] lsu_ldst_va_m; +input [39:13] tlb_pgnum; +input lsu_bld_pcx_rq ; // cycle after request +input [1:0] lsu_bld_rq_addr ; // cycle after request + +//input [1:0] lsu_lmq_pkt_way_g; +input [1:0] lmq0_pcx_pkt_way; +input [1:0] lmq1_pcx_pkt_way; +input [1:0] lmq2_pcx_pkt_way; +input [1:0] lmq3_pcx_pkt_way; + +input lsu_dfq_ld_vld ; +input lsu_ifu_asi_data_en_l ; + +input lsu_ld0_spec_vld_kill_w2 ; +input lsu_ld1_spec_vld_kill_w2 ; +input lsu_ld2_spec_vld_kill_w2 ; +input lsu_ld3_spec_vld_kill_w2 ; + +input lsu_fwd_rply_sz1_unc ; + +input rst_tri_en ; + +output lsu_va_match_b47_b32_m; +output lsu_va_match_b31_b3_m; + +//output lsu_pa_match_b39_13_g; +//output lsu_pa_match_b12_3_m; +output [47:3] lsu_va_wtchpt_addr; +//output [39:3] lsu_pa_wtchpt_addr; + +//output [63:0] ld_stb_bypass_data ; // st to load bypass data. + +output [`PCX_WIDTH-1:0] spc_pcx_data_pa ; +output [29:0] dtag_wdata_m ; // tag to write to dtag. +//output [3:0] lsu_byp_misc_addr_m ; // lower 3bits of addr for ldxa/raw etc +//output [1:0] lsu_byp_misc_sz_m ; // size for ldxa/raw etc +output [1:0] lmq0_byp_misc_sz ; +output [1:0] lmq1_byp_misc_sz ; +output [1:0] lmq2_byp_misc_sz ; +output [1:0] lmq3_byp_misc_sz ; + +output [1:0] lsu_byp_misc_sz_e ; // size for ldxa/raw etc +output lsu_l2fill_sign_extend_m ;// requires sign-extend else zero extend +output lsu_l2fill_bendian_m ; // big endian fill/bypass. +//output lsu_l2fill_fpld_e ; // fp load +output lmq0_l2fill_fpld ; // fp load +output lmq1_l2fill_fpld ; // fp load +output lmq2_l2fill_fpld ; // fp load +output lmq3_l2fill_fpld ; // fp load + +output [4:0] lmq_ld_rd1 ; // rd for all loads +//output lsu_ncache_ld_e ; // non-cacheable ld from dfq +output lmq0_ncache_ld ; // non-cacheable ld from dfq +output lmq1_ncache_ld ; // non-cacheable ld from dfq +output lmq2_ncache_ld ; // non-cacheable ld from dfq +output lmq3_ncache_ld ; // non-cacheable ld from dfq +//output [2:0] lsu_ld_rq_type_e ; // for identifying atomic ld. + +output [2:0] lmq0_ld_rq_type ; // for identifying atomic ld. +output [2:0] lmq1_ld_rq_type ; // for identifying atomic ld. +output [2:0] lmq2_ld_rq_type ; // for identifying atomic ld. +output [2:0] lmq3_ld_rq_type ; // for identifying atomic ld. + +output lmq0_ldd_vld ; // ld double +output lmq1_ldd_vld ; // ld double +output lmq2_ldd_vld ; // ld double +output lmq3_ldd_vld ; // ld double + +output ld_sec_hit_thrd0 ; // ld has sec. hit against th0 +output ld_sec_hit_thrd1 ; // ld has sec. hit against th1 +output ld_sec_hit_thrd2 ; // ld has sec. hit against th2 +output ld_sec_hit_thrd3 ; // ld has sec. hit against th3 +//output [1:0] lmq_pcx_pkt_sz ; +//output [39:0] lmq_pcx_pkt_addr ; +output [10:0] lmq0_pcx_pkt_addr; +output [10:0] lmq1_pcx_pkt_addr; +output [10:0] lmq2_pcx_pkt_addr; +output [10:0] lmq3_pcx_pkt_addr; + +//output [63:0] lsu_tlu_st_rs3_data_g ; +output [63:0] lsu_mmu_rs3_data_g ; +output [63:0] lsu_tlu_rs3_data_g ; + +output lsu_diagnstc_wr_data_b0 ; // diagnostic wr data - bit 0 +output [63:0] lsu_diagnstc_wr_data_e ; + +output [47:0] lsu_ifu_stxa_data ; // stxa related data + +output [11:5] lsu_ifu_ld_icache_index ; +output [1:0] lsu_ifu_ld_pcxpkt_tid ; + +//output [1:0] lmq_ld_way ; // cache set way for ld fill + +output [28:0] lsu_error_pa_m ; // error phy addr +//output [13:0] lsu_spu_rsrv_data_m ; // rs3 data for reserved fields. +output lsu_pref_pcx_req ; // pref sent to pcx + + output [63:0] st_rs3_data_g; + +output [1:0] lsu_ldst_va_way_g ; // 12:11 for direct map +//==================================================================== +//dc_fill CP + + input [63:0] lsu_l2fill_data; //from qdp2 + input l2fill_vld_m; //from dctl + input [3:0] ld_thrd_byp_sel_m;//from dctl + + output [63:0] dcache_alt_data_w0_m; //to d$ +// output [7:0] lsu_l2fill_or_byp_msb_m; //to dctl +//==================================================================== + + +wire [`STB_PCX_WIDTH-1:0] store_pcx_pkt ; +wire [`PCX_WIDTH-1:0] pcx_pkt_data ; +wire [`STB_PCX_WIDTH-1:0] stb_pcx_pkt ; +wire [`PCX_WIDTH-1:0] imiss_strm_pcx_pkt ; +wire [`PCX_WIDTH-1:0] intrpt_full_pcxpkt ; +wire [`PCX_WIDTH-1:0] ifu_full_pcx_pkt_e ; +wire [51:0] ifu_pcx_pkt_e ; +wire [63:0] cas_pkt2_data ; +wire [63:0] lmq0_bypass_data_in,lmq1_bypass_data_in ; +wire [63:0] lmq2_bypass_data_in,lmq3_bypass_data_in ; +wire [63:0] lmq0_bypass_data, lmq1_bypass_data ; +wire [63:0] lmq2_bypass_data, lmq3_bypass_data ; +wire [39:0] lmq_ld_addr ; +wire [`LMQ_WIDTH:0] load_pcx_pkt ; +wire [`LMQ_WIDTH-1:0] lmq0_pcx_pkt, lmq1_pcx_pkt ; +wire [`LMQ_WIDTH-1:0] lmq2_pcx_pkt, lmq3_pcx_pkt ; +wire [`PCX_WIDTH-1:0] fpop_full_pcxpkt ; +wire [63:0] tlb_st_data ; +//wire [63:0] formatted_tte_tag ; +//wire [63:0] formatted_tte_data ; +wire [63:0] lmq0_bypass_ldxa_data ; +wire [63:0] lmq1_bypass_ldxa_data ; +wire [63:0] lmq2_bypass_ldxa_data ; +wire [63:0] lmq3_bypass_ldxa_data ; +wire [`PCX_WIDTH-1:0] fwd_full_pcxpkt ; +wire [47:3] lsu_tlu_st_rs3_data_g ; + + +//=================================================== +// clock buffer +//=================================================== +//wire lsu_qdp1_clk ; +wire clk; +assign clk = rclk; + +wire thread0_g; +wire thread1_g; +wire thread2_g; +wire thread3_g; + + assign thread0_g = lsu_thread_g[0]; + assign thread1_g = lsu_thread_g[1]; + assign thread2_g = lsu_thread_g[2]; + assign thread3_g = lsu_thread_g[3]; + +//================================================================================================= +// LMQ DP +//================================================================================================= + +wire [12:0] ldst_va_g; + +dff #(13) ff_ldst_va_g ( + .din (lsu_ldst_va_m[12:0]), + .q (ldst_va_g[12:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_ldst_va_way_g[1:0] = ldst_va_g[12:11]; + +wire [`LMQ_VLD:0] ld_pcx_pkt_g_tmp; + +assign ld_pcx_pkt_g_tmp[`LMQ_VLD:0] = {ld_pcx_pkt_g[`LMQ_WIDTH-1:44], + 2'b00, // done after the flop + //lsu_lmq_pkt_way_g[1:0], + ld_pcx_pkt_g[41:40], + tlb_pgnum[39:13],ldst_va_g[12:0]}; + +// Unfortunately ld_pcx_pkt_g is now 65 bits wide. Grape-mapper needs to give feedback. +// THREAD 0. +/* +dffe #(`LMQ_WIDTH) lmq0 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq0_pcx_pkt[`LMQ_VLD:0]), + .en (lmq_enable[0]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire lmq0_clk; +clken_buf lmq0_clkbuf ( + .rclk (clk), + .enb_l (~lmq_enable[0]), + .tmb_l (~se), + .clk (lmq0_clk) + ) ; +wire [`LMQ_VLD:0] lmq0_pcx_pkt_tmp ; + +dff #(`LMQ_WIDTH) lmq0 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq0_pcx_pkt_tmp[`LMQ_VLD:0]), + .clk (lmq0_clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - speculative pick in w-cycle +wire lmq0_pcx_pkt_vld ; +assign lmq0_pcx_pkt_vld = lmq0_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld0_spec_vld_kill_w2 ; + +assign lmq0_pcx_pkt[`LMQ_VLD:0] = {lmq0_pcx_pkt_vld, + lmq0_pcx_pkt_tmp[`LMQ_VLD-1:44], + lmq0_pcx_pkt_way[1:0], + lmq0_pcx_pkt_tmp[41:0]}; + +// Needs to be multi-threaded. +//assign lmq_pcx_pkt_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI:`LMQ_SZ_LO] ; + +assign ld_sec_hit_thrd0 = +(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ; + +// THREAD 1. +/* +dffe #(`LMQ_WIDTH) lmq1 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq1_pcx_pkt[`LMQ_VLD:0]), + .en (lmq_enable[1]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire lmq1_clk; +clken_buf lmq1_clkbuf ( + .rclk (clk), + .enb_l (~lmq_enable[1]), + .tmb_l (~se), + .clk (lmq1_clk) + ) ; + +wire [`LMQ_VLD:0] lmq1_pcx_pkt_tmp; + +dff #(`LMQ_WIDTH) lmq1 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq1_pcx_pkt_tmp[`LMQ_VLD:0]), + .clk (lmq1_clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - speculative pick in w-cycle +wire lmq1_pcx_pkt_vld ; +assign lmq1_pcx_pkt_vld = lmq1_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld1_spec_vld_kill_w2 ; + +assign lmq1_pcx_pkt[`LMQ_VLD:0] = {lmq1_pcx_pkt_vld, + lmq1_pcx_pkt_tmp[`LMQ_VLD-1:44], + lmq1_pcx_pkt_way[1:0], + lmq1_pcx_pkt_tmp[41:0]}; + +assign ld_sec_hit_thrd1 = +(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ; + +// THREAD 2. +/* +dffe #(`LMQ_WIDTH) lmq2 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq2_pcx_pkt[`LMQ_VLD:0]), + .en (lmq_enable[2]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire lmq2_clk; +clken_buf lmq2_clkbuf ( + .rclk (clk), + .enb_l (~lmq_enable[2]), + .tmb_l (~se), + .clk (lmq2_clk) + ) ; + +wire [`LMQ_VLD:0] lmq2_pcx_pkt_tmp; + +dff #(`LMQ_WIDTH) lmq2 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq2_pcx_pkt_tmp[`LMQ_VLD:0]), + .clk (lmq2_clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - speculative pick in w-cycle +wire lmq2_pcx_pkt_vld ; +assign lmq2_pcx_pkt_vld = lmq2_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld2_spec_vld_kill_w2 ; + + +assign lmq2_pcx_pkt[`LMQ_VLD:0] = {lmq2_pcx_pkt_vld, + lmq2_pcx_pkt_tmp[`LMQ_VLD-1:44], + lmq2_pcx_pkt_way[1:0], + lmq2_pcx_pkt_tmp[41:0]}; + +assign ld_sec_hit_thrd2 = +(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ; + +// THREAD 3. +/* +dffe #(`LMQ_WIDTH) lmq3 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq3_pcx_pkt[`LMQ_VLD:0]), + .en (lmq_enable[3]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire lmq3_clk; +clken_buf lmq3_clkbuf ( + .rclk (clk), + .enb_l (~lmq_enable[3]), + .tmb_l (~se), + .clk (lmq3_clk) + ) ; + +wire [`LMQ_VLD:0] lmq3_pcx_pkt_tmp; + +dff #(`LMQ_WIDTH) lmq3 ( + .din (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]), + .q (lmq3_pcx_pkt_tmp[`LMQ_VLD:0]), + .clk (lmq3_clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - speculative pick in w-cycle +wire lmq3_pcx_pkt_vld ; +assign lmq3_pcx_pkt_vld = lmq3_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld3_spec_vld_kill_w2 ; + + +assign lmq3_pcx_pkt[`LMQ_VLD:0] = {lmq3_pcx_pkt_vld, + lmq3_pcx_pkt_tmp[`LMQ_VLD-1:44], + lmq3_pcx_pkt_way[1:0], + lmq3_pcx_pkt_tmp[41:0]}; + + +assign ld_sec_hit_thrd3 = +(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ; + +// Select 1 of 4 LMQ Contents. +// selection is based on which thread's load is chosen for pcx. +mux4ds #(`LMQ_WIDTH) lmq_pthrd_sel ( + .in0 (lmq0_pcx_pkt[`LMQ_WIDTH-1:0]), + .in1 (lmq1_pcx_pkt[`LMQ_WIDTH-1:0]), + .in2 (lmq2_pcx_pkt[`LMQ_WIDTH-1:0]), + .in3 (lmq3_pcx_pkt[`LMQ_WIDTH-1:0]), + .sel0 (ld_pcx_rq_sel[0]), + .sel1 (ld_pcx_rq_sel[1]), + .sel2 (ld_pcx_rq_sel[2]), + .sel3 (ld_pcx_rq_sel[3]), + .dout (load_pcx_pkt[`LMQ_WIDTH-1:0]) +); + +assign lsu_pref_pcx_req = load_pcx_pkt[`LMQ_PREF] ; + +// Choose data to src for fill/bypass. +// E-stage muxing : required for fills specifically. + + assign lmq0_ldd_vld = lmq0_pcx_pkt[`LMQ_RD2_VLD]; + assign lmq1_ldd_vld = lmq1_pcx_pkt[`LMQ_RD2_VLD]; + assign lmq2_ldd_vld = lmq2_pcx_pkt[`LMQ_RD2_VLD]; + assign lmq3_ldd_vld = lmq3_pcx_pkt[`LMQ_RD2_VLD]; + + assign lmq0_pcx_pkt_addr[10:0] = lmq0_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO]; + assign lmq1_pcx_pkt_addr[10:0] = lmq1_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO]; + assign lmq2_pcx_pkt_addr[10:0] = lmq2_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO]; + assign lmq3_pcx_pkt_addr[10:0] = lmq3_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO]; + + assign lmq0_ld_rq_type[2:0] = lmq0_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO]; + assign lmq1_ld_rq_type[2:0] = lmq1_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO]; + assign lmq2_ld_rq_type[2:0] = lmq2_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO]; + assign lmq3_ld_rq_type[2:0] = lmq3_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO]; + + assign lmq0_l2fill_fpld = lmq0_pcx_pkt[`LMQ_FPLD]; + assign lmq1_l2fill_fpld = lmq1_pcx_pkt[`LMQ_FPLD]; + assign lmq2_l2fill_fpld = lmq2_pcx_pkt[`LMQ_FPLD]; + assign lmq3_l2fill_fpld = lmq3_pcx_pkt[`LMQ_FPLD]; +/* + wire lsu_l2fill_fpld_e; + +mux4ds #(44) lmq_dthrd_sel1 ( + .in0 ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq0_pcx_pkt[`LMQ_NC], + lmq0_pcx_pkt[`LMQ_FPLD],lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in1 ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq1_pcx_pkt[`LMQ_NC], + lmq1_pcx_pkt[`LMQ_FPLD],lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in2 ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq2_pcx_pkt[`LMQ_NC], + lmq2_pcx_pkt[`LMQ_FPLD],lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in3 ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq3_pcx_pkt[`LMQ_NC], + lmq3_pcx_pkt[`LMQ_FPLD],lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .sel0 (dfq_byp_sel[0]), + .sel1 (dfq_byp_sel[1]), + .sel2 (dfq_byp_sel[2]), + .sel3 (dfq_byp_sel[3]), + .dout ({lmq_ld_addr[39:0], lsu_ncache_ld_e, + lsu_l2fill_fpld_e, lsu_byp_misc_sz_e[1:0]}) +); +*/ + + assign lmq0_ncache_ld = lmq0_pcx_pkt[`LMQ_NC]; + assign lmq1_ncache_ld = lmq1_pcx_pkt[`LMQ_NC]; + assign lmq2_ncache_ld = lmq2_pcx_pkt[`LMQ_NC]; + assign lmq3_ncache_ld = lmq3_pcx_pkt[`LMQ_NC]; + +mux4ds #(42) lmq_dthrd_sel1 ( + .in0 ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], + lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in1 ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], + lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in2 ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], + lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .in3 ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], + lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}), + .sel0 (dfq_byp_sel[0]), + .sel1 (dfq_byp_sel[1]), + .sel2 (dfq_byp_sel[2]), + .sel3 (dfq_byp_sel[3]), + .dout ({lmq_ld_addr[39:0], lsu_byp_misc_sz_e[1:0]}) +); + +// POR +// M-stage muxing : require for alignment and bypassing to exu. +// flopped then used in qctl/dctl G-stage +// lmq_ld_rd1 to lsu_qctl +// others to lsu_dctl + +// M-Stage Muxing +mux4ds #(7) lmq_dthrd_sel2 ( + .in0 ({lmq0_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq0_pcx_pkt[`LMQ_BIGEND], + lmq0_pcx_pkt[`LMQ_SIGNEXT]}), + .in1 ({lmq1_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq1_pcx_pkt[`LMQ_BIGEND], + lmq1_pcx_pkt[`LMQ_SIGNEXT]}), + .in2 ({lmq2_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq2_pcx_pkt[`LMQ_BIGEND], + lmq2_pcx_pkt[`LMQ_SIGNEXT]}), + .in3 ({lmq3_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq3_pcx_pkt[`LMQ_BIGEND], + lmq3_pcx_pkt[`LMQ_SIGNEXT]}), + .sel0 (lmq_byp_misc_sel[0]), + .sel1 (lmq_byp_misc_sel[1]), + .sel2 (lmq_byp_misc_sel[2]), + .sel3 (lmq_byp_misc_sel[3]), + .dout ({lmq_ld_rd1[4:0],lsu_l2fill_bendian_m,lsu_l2fill_sign_extend_m}) +); + + assign lmq0_byp_misc_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]; + assign lmq1_byp_misc_sz[1:0] = lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]; + assign lmq2_byp_misc_sz[1:0] = lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]; + assign lmq3_byp_misc_sz[1:0] = lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]; + + +//assign lmq_pcx_pkt_addr[10:0] = lmq_ld_addr[10:0] ; + + + wire [28:0] dtag_wdata_e; + +assign dtag_wdata_e[28:0] = + ~lsu_dfq_ld_vld ? + lsu_diagnstc_wr_data_e[29:1] : lmq_ld_addr[39:11] ; + +// Parity Generation for Tag. Match with macro. +wire dtag_wr_parity ; +//assign dtag_wr_parity = ^dtag_wdata_e[28:0] ; +//assign dtag_wdata_e[29] = +// ~lsu_dfq_ld_vld ? +// lsu_diagnstc_dtagv_prty_invrt_e^dtag_wr_parity : dtag_wr_parity ; + + wire dtag_wr_parity_7_0, dtag_wr_parity_15_8, + dtag_wr_parity_23_16, dtag_wr_parity_28_24; + + assign dtag_wr_parity_7_0 = ^dtag_wdata_e[7:0]; //zzpar8 + assign dtag_wr_parity_15_8 = ^dtag_wdata_e[15:8]; //zzpar8 + assign dtag_wr_parity_23_16 = ^dtag_wdata_e[23:16]; //zzpar8 + assign dtag_wr_parity_28_24 = ^dtag_wdata_e[28:24]; //zzpar8 + + wire dtag_wr_parity_28_24_with_invrt; + + assign dtag_wr_parity_28_24_with_invrt = + (^dtag_wdata_e[28:24]) ^ lsu_diagnstc_dtagv_prty_invrt_e; //zzpar8 + + + wire dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m, + dtag_wr_parity_23_16_m, dtag_wr_parity_28_24_m; + wire lsu_dfq_ld_vld_m; + wire dtag_wr_parity_28_24_with_invrt_m; + + +// 12/12/03 : Change for Macrotest. I didn't mention +// these 4 bits ! Pls check for a max time violation. +wire dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din ; +wire dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din ; +assign dtag_wr_parity_7_0_din = +sehold ? dtag_wr_parity_7_0_m : dtag_wr_parity_7_0 ; +assign dtag_wr_parity_15_8_din = +sehold ? dtag_wr_parity_15_8_m : dtag_wr_parity_15_8 ; +assign dtag_wr_parity_23_16_din = +sehold ? dtag_wr_parity_23_16_m : dtag_wr_parity_23_16 ; +assign dtag_wr_parity_28_24_din = +sehold ? dtag_wr_parity_28_24_m : dtag_wr_parity_28_24 ; + +dff #(6) tag_parity_m ( + .din ({dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din, + dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din, + lsu_dfq_ld_vld, dtag_wr_parity_28_24_with_invrt}), + .q ({dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m, + dtag_wr_parity_23_16_m, dtag_wr_parity_28_24_m, + lsu_dfq_ld_vld_m, dtag_wr_parity_28_24_with_invrt_m}), + .clk (clk), + .se (1'b0), .si (), .so () +); + +assign dtag_wr_parity = dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^ + dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_m; + + wire dtag_wr_parity_with_invrt; + +assign dtag_wr_parity_with_invrt = + dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^ + dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_with_invrt_m; + +wire [29:0] dtag_wdata_m; + +// 12/12/03 : Change for Macrotest. +assign dtag_wdata_m[29] = + ~(lsu_dfq_ld_vld_m | sehold) ? + dtag_wr_parity_with_invrt : dtag_wr_parity ; + +// 12/12/03 : Change for Macrotest. +wire [28:0] dtag_wdata_e_din ; +assign dtag_wdata_e_din[28:0] = +sehold ? dtag_wdata_m[28:0] : dtag_wdata_e[28:0] ; + +dff #(29) tag_stgm ( + .din (dtag_wdata_e_din[28:0]), + .q (dtag_wdata_m[28:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + assign lsu_error_pa_m[28:0] = dtag_wdata_m[28:0]; + + +//================================================================================================= +// RS3 DATA ALIGNMENT FOR CAS +//================================================================================================= + +wire [7:0] rs3_byte0, rs3_byte1, rs3_byte2, rs3_byte3 ; +wire [7:0] rs3_byte4, rs3_byte5, rs3_byte6, rs3_byte7 ; +wire [63:0] atm_byte_g ; +wire [63:0] st_rs3_data_m,st_rs3_data_g ; + +dff #(64) rs3_stgm ( + .din (exu_lsu_rs3_data_e[63:0]), + .q (st_rs3_data_m[63:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// rm (along with spu). +//assign lsu_spu_rsrv_data_m[13:0] = +// {st_rs3_data_m[27:23],st_rs3_data_m[21:16],st_rs3_data_m[8:6]} ; + +dff #(64) rs3_stgg ( + .din (st_rs3_data_m[63:0]), + .q (st_rs3_data_g[63:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign rs3_byte0[7:0] = st_rs3_data_g[7:0] ; +assign rs3_byte1[7:0] = st_rs3_data_g[15:8] ; +assign rs3_byte2[7:0] = st_rs3_data_g[23:16] ; +assign rs3_byte3[7:0] = st_rs3_data_g[31:24] ; +assign rs3_byte4[7:0] = st_rs3_data_g[39:32] ; +assign rs3_byte5[7:0] = st_rs3_data_g[47:40] ; +assign rs3_byte6[7:0] = st_rs3_data_g[55:48] ; +assign rs3_byte7[7:0] = st_rs3_data_g[63:56] ; + +//assign atm_byte_g[7:0] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte0[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte7[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_7_0 ( + .in0 (rs3_byte0[7:0]), + .in1 (rs3_byte3[7:0]), + .in2 (rs3_byte7[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[7:0])); + + +//assign atm_byte_g[15:8] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte1[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte6[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_15_8 ( + .in0 (rs3_byte1[7:0]), + .in1 (rs3_byte2[7:0]), + .in2 (rs3_byte6[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[15:8])); + +//assign atm_byte_g[23:16] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte2[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte5[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_23_16 ( + .in0 (rs3_byte2[7:0]), + .in1 (rs3_byte1[7:0]), + .in2 (rs3_byte5[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[23:16])); + +//assign atm_byte_g[31:24] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte3[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte4[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_31_24 ( + .in0 (rs3_byte3[7:0]), + .in1 (rs3_byte0[7:0]), + .in2 (rs3_byte4[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[31:24])); + +//assign atm_byte_g[39:32] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte4[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte3[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_39_32 ( + .in0 (rs3_byte4[7:0]), + .in1 (rs3_byte0[7:0]), + .in2 (rs3_byte3[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[39:32])); + +//assign atm_byte_g[47:40] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte5[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte2[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_47_40( + .in0 (rs3_byte5[7:0]), + .in1 (rs3_byte1[7:0]), + .in2 (rs3_byte2[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[47:40])); + +//assign atm_byte_g[55:48] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte6[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte1[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_55_48( + .in0 (rs3_byte6[7:0]), + .in1 (rs3_byte2[7:0]), + .in2 (rs3_byte1[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[55:48])); + +//assign atm_byte_g[63:56] = +//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte7[7:0] : +// lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] : +// lsu_atomic_pkt2_bsel_g[0] ? rs3_byte0[7:0] : 8'bxxxx_xxxx ; + +mux3ds #(8) mx_atm_byte_g_63_56 ( + .in0 (rs3_byte7[7:0]), + .in1 (rs3_byte3[7:0]), + .in2 (rs3_byte0[7:0]), + .sel0(lsu_atomic_pkt2_bsel_g[2]), + .sel1(lsu_atomic_pkt2_bsel_g[1]), + .sel2(lsu_atomic_pkt2_bsel_g[0]), + .dout(atm_byte_g[63:56])); + +//================================================================================================= +// STB/LDXA DATA BYPASSING +//================================================================================================= + +// Add STB to load bypass data flops. +// Attempt is made to bypass data in G-stage for load. If not +// possible then flop data and wait for next available bubble. +// Once bypass occurs then load can be considered resolved. +// Load Full Raw bypassing does not have to use DFQ. + +// ldxa data will reside in bypass flops until an opportunity +// is available to write to irf. ldxa's must write to lmq +// in order to provide information such as rd to irf. + +// ** The two conditions are mutually exclusive. ** + +// lsu_local_ldxa_data_w2 w/ lsu_misc_rdata_w2 for all 4 threads + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [2:0] lmq_byp_ldxa_sel0_1hot ; +assign lmq_byp_ldxa_sel0_1hot[0] = lmq_byp_ldxa_sel0[0] & ~rst_tri_en; +assign lmq_byp_ldxa_sel0_1hot[1] = lmq_byp_ldxa_sel0[1] & ~rst_tri_en; +assign lmq_byp_ldxa_sel0_1hot[2] = lmq_byp_ldxa_sel0[2] | rst_tri_en; + + +// THREAD 0 +mux3ds #(64) ldbyp0_ldxa_mx ( + .in0 (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data + //.in1 (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data + .in1 (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data + .in2 (lsu_misc_rdata_w2[63:0]), // local asi bypass data + .sel0 (lmq_byp_ldxa_sel0_1hot[0]), + //.sel1 (lmq_byp_ldxa_sel0[1]), + .sel1 (lmq_byp_ldxa_sel0_1hot[1]), + .sel2 (lmq_byp_ldxa_sel0_1hot[2]), + .dout (lmq0_bypass_ldxa_data[63:0]) +); + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [3:0] lmq_byp_data_sel0_1hot ; +assign lmq_byp_data_sel0_1hot[0] = lmq_byp_data_sel0[0] ; +assign lmq_byp_data_sel0_1hot[1] = lmq_byp_data_sel0[1] ; +assign lmq_byp_data_sel0_1hot[2] = lmq_byp_data_sel0[2] ; +assign lmq_byp_data_sel0_1hot[3] = lmq_byp_data_sel0[3] ; + +wire [63:0] lmq0_bypass_misc_data ; +mux4ds #(64) ldbyp0_data_mx ( + .in0 (stb_rdata_ramd[63:0]), // stb bypass data + .in1 (exu_lsu_rs3_data_e[63:0]), // rs3 data + .in2 (atm_byte_g[63:0]), // cas formatted data + .in3 (lmq0_bypass_ldxa_data[63:0]), // ldxa bypass data + .sel0 (lmq_byp_data_sel0_1hot[0]), + .sel1 (lmq_byp_data_sel0_1hot[1]), + .sel2 (lmq_byp_data_sel0_1hot[2]), + .sel3 (lmq_byp_data_sel0_1hot[3]), + .dout (lmq0_bypass_misc_data[63:0]) +); + + +// 2:1 mux for additional data bus from tlu. +// Grape : merge into mux-flop. +mux2ds #(64) ldbyp0_fmx ( + .in0 (lmq0_bypass_misc_data[63:0]), + .in1 (tlu_lsu_int_ldxa_data_w2[63:0]), + .sel0 (~lmq_byp_data_fmx_sel[0]), + .sel1 (lmq_byp_data_fmx_sel[0]), + .dout (lmq0_bypass_data_in[63:0]) +); + +/* +dffe #(64) ldbyp0_data_ff ( + .din (lmq0_bypass_data_in[63:0]), + .q (lmq0_bypass_data[63:0]), + .en (lmq_byp_data_en_w2[0]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire ldbyp0_data_clk; +clken_buf ldbyp0_data_clkbuf ( + .rclk (clk), + .enb_l (~lmq_byp_data_en_w2[0]), + .tmb_l (~se), + .clk (ldbyp0_data_clk) + ) ; + +dff #(64) ldbyp0_data_ff ( + .din (lmq0_bypass_data_in[63:0]), + .q (lmq0_bypass_data[63:0]), + .clk (ldbyp0_data_clk), + .se (1'b0), .si (), .so () + ); + + +// THREAD 1 +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [2:0] lmq_byp_ldxa_sel1_1hot ; +assign lmq_byp_ldxa_sel1_1hot[0] = lmq_byp_ldxa_sel1[0] & ~rst_tri_en; +assign lmq_byp_ldxa_sel1_1hot[1] = lmq_byp_ldxa_sel1[1] & ~rst_tri_en; +assign lmq_byp_ldxa_sel1_1hot[2] = lmq_byp_ldxa_sel1[2] | rst_tri_en; + + +mux3ds #(64) ldbyp1_ldxa_mx ( + .in0 (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data + //.in1 (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data + .in1 (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data + .in2 (lsu_misc_rdata_w2[63:0]),// local asi bypass data + .sel0 (lmq_byp_ldxa_sel1_1hot[0]), + //.sel1 (lmq_byp_ldxa_sel1[1]), + .sel1 (lmq_byp_ldxa_sel1_1hot[1]), + .sel2 (lmq_byp_ldxa_sel1_1hot[2]), + .dout (lmq1_bypass_ldxa_data[63:0]) +); + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [3:0] lmq_byp_data_sel1_1hot ; +assign lmq_byp_data_sel1_1hot[0] = lmq_byp_data_sel1[0] ; +assign lmq_byp_data_sel1_1hot[1] = lmq_byp_data_sel1[1] ; +assign lmq_byp_data_sel1_1hot[2] = lmq_byp_data_sel1[2] ; +assign lmq_byp_data_sel1_1hot[3] = lmq_byp_data_sel1[3] ; + + +wire [63:0] lmq1_bypass_misc_data ; +mux4ds #(64) ldbyp1_data_mx ( + .in0 (stb_rdata_ramd[63:0]), // stb bypass data + .in1 (exu_lsu_rs3_data_e[63:0]), // rs3 data + .in2 (atm_byte_g[63:0]), // cas formatted data + .in3 (lmq1_bypass_ldxa_data[63:0]), // ldxa bypass data + .sel0 (lmq_byp_data_sel1_1hot[0]), + .sel1 (lmq_byp_data_sel1_1hot[1]), + .sel2 (lmq_byp_data_sel1_1hot[2]), + .sel3 (lmq_byp_data_sel1_1hot[3]), + .dout (lmq1_bypass_misc_data[63:0]) +); + +// 2:1 mux for additional data bus from tlu. +// Grape : merge into mux-flop. +mux2ds #(64) ldbyp1_fmx ( + .in0 (lmq1_bypass_misc_data[63:0]), + .in1 (tlu_lsu_int_ldxa_data_w2[63:0]), + .sel0 (~lmq_byp_data_fmx_sel[1]), + .sel1 (lmq_byp_data_fmx_sel[1]), + .dout (lmq1_bypass_data_in[63:0]) +); + +/* +dffe #(64) ldbyp1_data_ff ( + .din (lmq1_bypass_data_in[63:0]), + .q (lmq1_bypass_data[63:0]), + .en (lmq_byp_data_en_w2[1]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire ldbyp1_data_clk; +clken_buf ldbyp1_data_clkbuf ( + .rclk (clk), + .enb_l (~lmq_byp_data_en_w2[1]), + .tmb_l (~se), + .clk (ldbyp1_data_clk) + ) ; + +dff #(64) ldbyp1_data_ff ( + .din (lmq1_bypass_data_in[63:0]), + .q (lmq1_bypass_data[63:0]), + .clk (ldbyp1_data_clk), + .se (1'b0), .si (), .so () + ); + +// THREAD 2 +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [2:0] lmq_byp_ldxa_sel2_1hot ; +assign lmq_byp_ldxa_sel2_1hot[0] = lmq_byp_ldxa_sel2[0] & ~rst_tri_en; +assign lmq_byp_ldxa_sel2_1hot[1] = lmq_byp_ldxa_sel2[1] & ~rst_tri_en; +assign lmq_byp_ldxa_sel2_1hot[2] = lmq_byp_ldxa_sel2[2] | rst_tri_en; + + +mux3ds #(64) ldbyp2_data_mx ( + .in0 (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data + //.in1 (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data + .in1 (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data + .in2 (lsu_misc_rdata_w2[63:0]),// local asi bypass data + .sel0 (lmq_byp_ldxa_sel2_1hot[0]), + //.sel1 (lmq_byp_ldxa_sel2[1]), + .sel1 (lmq_byp_ldxa_sel2_1hot[1]), + .sel2 (lmq_byp_ldxa_sel2_1hot[2]), + .dout (lmq2_bypass_ldxa_data[63:0]) +); + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [3:0] lmq_byp_data_sel2_1hot ; +assign lmq_byp_data_sel2_1hot[0] = lmq_byp_data_sel2[0] ; +assign lmq_byp_data_sel2_1hot[1] = lmq_byp_data_sel2[1] ; +assign lmq_byp_data_sel2_1hot[2] = lmq_byp_data_sel2[2] ; +assign lmq_byp_data_sel2_1hot[3] = lmq_byp_data_sel2[3] ; + + +wire [63:0] lmq2_bypass_misc_data ; +mux4ds #(64) ldbyp2_ldxa_mx ( + .in0 (stb_rdata_ramd[63:0]), // stb bypass data + .in1 (exu_lsu_rs3_data_e[63:0]), // rs3 data + .in2 (atm_byte_g[63:0]), // cas formatted data + .in3 (lmq2_bypass_ldxa_data[63:0]), // ldxa bypass data + .sel0 (lmq_byp_data_sel2_1hot[0]), + .sel1 (lmq_byp_data_sel2_1hot[1]), + .sel2 (lmq_byp_data_sel2_1hot[2]), + .sel3 (lmq_byp_data_sel2_1hot[3]), + .dout (lmq2_bypass_misc_data[63:0]) +); + +// 2:1 mux for additional data bus from tlu. +// Grape : merge into mux-flop. +mux2ds #(64) ldbyp2_fmx ( + .in0 (lmq2_bypass_misc_data[63:0]), + .in1 (tlu_lsu_int_ldxa_data_w2[63:0]), + .sel0 (~lmq_byp_data_fmx_sel[2]), + .sel1 (lmq_byp_data_fmx_sel[2]), + .dout (lmq2_bypass_data_in[63:0]) +); + +/* +dffe #(64) ldbyp2_data_ff ( + .din (lmq2_bypass_data_in[63:0]), + .q (lmq2_bypass_data[63:0]), + .en (lmq_byp_data_en_w2[2]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire ldbyp2_data_clk; +clken_buf ldbyp2_data_clkbuf ( + .rclk (clk), + .enb_l (~lmq_byp_data_en_w2[2]), + .tmb_l (~se), + .clk (ldbyp2_data_clk) + ) ; + +dff #(64) ldbyp2_data_ff ( + .din (lmq2_bypass_data_in[63:0]), + .q (lmq2_bypass_data[63:0]), + .clk (ldbyp2_data_clk), + .se (1'b0), .si (), .so () + ); + +// THREAD 3 +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [2:0] lmq_byp_ldxa_sel3_1hot ; +assign lmq_byp_ldxa_sel3_1hot[0] = lmq_byp_ldxa_sel3[0] & ~rst_tri_en; +assign lmq_byp_ldxa_sel3_1hot[1] = lmq_byp_ldxa_sel3[1] & ~rst_tri_en; +assign lmq_byp_ldxa_sel3_1hot[2] = lmq_byp_ldxa_sel3[2] | rst_tri_en; + + +mux3ds #(64) ldbyp3_data_mx ( + .in0 (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data + //.in1 (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data + .in1 (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data + .in2 (lsu_misc_rdata_w2[63:0]),// local asi bypass data + .sel0 (lmq_byp_ldxa_sel3_1hot[0]), + //.sel1 (lmq_byp_ldxa_sel3[1]), + .sel1 (lmq_byp_ldxa_sel3_1hot[1]), + .sel2 (lmq_byp_ldxa_sel3_1hot[2]), + .dout (lmq3_bypass_ldxa_data[63:0]) +); + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [3:0] lmq_byp_data_sel3_1hot ; +assign lmq_byp_data_sel3_1hot[0] = lmq_byp_data_sel3[0] ; +assign lmq_byp_data_sel3_1hot[1] = lmq_byp_data_sel3[1] ; +assign lmq_byp_data_sel3_1hot[2] = lmq_byp_data_sel3[2] ; +assign lmq_byp_data_sel3_1hot[3] = lmq_byp_data_sel3[3] ; + + +wire [63:0] lmq3_bypass_misc_data ; +mux4ds #(64) ldbyp3_ldxa_mx ( + .in0 (stb_rdata_ramd[63:0]), // stb bypass data + .in1 (exu_lsu_rs3_data_e[63:0]), // rs3 data + .in2 (atm_byte_g[63:0]), // cas formatted data + .in3 (lmq3_bypass_ldxa_data[63:0]), // ldxa bypass data + .sel0 (lmq_byp_data_sel3_1hot[0]), + .sel1 (lmq_byp_data_sel3_1hot[1]), + .sel2 (lmq_byp_data_sel3_1hot[2]), + .sel3 (lmq_byp_data_sel3_1hot[3]), + .dout (lmq3_bypass_misc_data[63:0]) +); + +// 2:1 mux for additional data bus from tlu. +// Grape : merge into mux-flop. +mux2ds #(64) ldbyp3_fmx ( + .in0 (lmq3_bypass_misc_data[63:0]), + .in1 (tlu_lsu_int_ldxa_data_w2[63:0]), + .sel0 (~lmq_byp_data_fmx_sel[3]), + .sel1 (lmq_byp_data_fmx_sel[3]), + .dout (lmq3_bypass_data_in[63:0]) +); + +/* +dffe #(64) ldbyp3_data_ff ( + .din (lmq3_bypass_data_in[63:0]), + .q (lmq3_bypass_data[63:0]), + .en (lmq_byp_data_en_w2[3]), .clk (clk), + .se (1'b0), .si (), .so () + ); +*/ +wire ldbyp3_data_clk; +clken_buf ldbyp3_data_clkbuf ( + .rclk (clk), + .enb_l (~lmq_byp_data_en_w2[3]), + .tmb_l (~se), + .clk (ldbyp3_data_clk) + ) ; + +dff #(64) ldbyp3_data_ff ( + .din (lmq3_bypass_data_in[63:0]), + .q (lmq3_bypass_data[63:0]), + .clk (ldbyp3_data_clk), + .se (1'b0), .si (), .so () + ); + + +// This can be merged with above mux !!!! +mux4ds #(64) ld_byp_cas_mx ( + .in0 (lmq0_bypass_data[63:0]), + .in1 (lmq1_bypass_data[63:0]), + .in2 (lmq2_bypass_data[63:0]), + .in3 (lmq3_bypass_data[63:0]), + .sel0 (ld_pcx_rq_sel[0]), + .sel1 (ld_pcx_rq_sel[1]), + .sel2 (ld_pcx_rq_sel[2]), + .sel3 (ld_pcx_rq_sel[3]), + .dout (cas_pkt2_data[63:0]) +); + +// Can this be merged with above muxes ? +mux4ds #(64) tlb_st_mx ( + .in0 (lmq0_bypass_data[63:0]), + .in1 (lmq1_bypass_data[63:0]), + .in2 (lmq2_bypass_data[63:0]), + .in3 (lmq3_bypass_data[63:0]), + .sel0 (lsu_tlb_st_sel_m[0]), + .sel1 (lsu_tlb_st_sel_m[1]), + .sel2 (lsu_tlb_st_sel_m[2]), + .sel3 (lsu_tlb_st_sel_m[3]), + .dout (tlb_st_data[63:0]) +); + +/*mux4ds #(64) tlb_st_mx ( + .in0 (lmq0_bypass_data[63:0]), + .in1 (lmq1_bypass_data[63:0]), + .in2 (lmq2_bypass_data[63:0]), + .in3 (lmq3_bypass_data[63:0]), + .sel0 (lsu_tlb_st_sel_g[0]), + .sel1 (lsu_tlb_st_sel_g[1]), + .sel2 (lsu_tlb_st_sel_g[2]), + .sel3 (lsu_tlb_st_sel_g[3]), + .dout (tlb_st_data[63:0]) +);*/ + +wire [63:0] tlb_st_data_d1 ; +dff #(64) std_d1 ( + .din (tlb_st_data[63:0]), + .q (tlb_st_data_d1[63:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Begin - Bug3487. + + +wire asi_data_clk; +clken_buf asid_clkbuf ( + .rclk (clk), + .enb_l (lsu_ifu_asi_data_en_l), + .tmb_l (~se), + .clk (asi_data_clk) + ) ; + +dff #(48) ifu_std_d1 ( + .din (tlb_st_data[47:0]), + .q (lsu_ifu_stxa_data[47:0]), + .clk (asi_data_clk), + .se (1'b0), .si (), .so () + ); + +// select is now a stage earlier, which should be +// fine as selects stay constant. +//assign lsu_ifu_stxa_data[47:0] = tlb_st_data_d1[47:0] ; + +// End - Bug3487. + + +//wire [3:0] lsu_diag_access_sel_d1 ; + +//dff #(4) diagsel_stgd1 ( +// .din (lsu_diag_access_sel[3:0]), +// .q (lsu_diag_access_sel_d1[3:0]), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +//mux4ds #(64) diag_st_mx ( +// .in0 (lmq0_bypass_data[63:0]), +// .in1 (lmq1_bypass_data[63:0]), +// .in2 (lmq2_bypass_data[63:0]), +// .in3 (lmq3_bypass_data[63:0]), +// .sel0 (lsu_diag_access_sel_d1[0]), +// .sel1 (lsu_diag_access_sel_d1[1]), +// .sel2 (lsu_diag_access_sel_d1[2]), +// .sel3 (lsu_diag_access_sel_d1[3]), +// .dout (lsu_diagnstc_wr_data_e[63:0]) +//); + +// 1-hot fix: 8/1/03 - can be multihot during scan +// grape mapper convert the 1 of the inverter used for the select to the logic below +wire [3:0] lsu_diagnstc_data_sel_1hot ; +assign lsu_diagnstc_data_sel_1hot[0] = lsu_diagnstc_data_sel[0] & ~rst_tri_en; +assign lsu_diagnstc_data_sel_1hot[1] = lsu_diagnstc_data_sel[1] & ~rst_tri_en; +assign lsu_diagnstc_data_sel_1hot[2] = lsu_diagnstc_data_sel[2] & ~rst_tri_en; +assign lsu_diagnstc_data_sel_1hot[3] = lsu_diagnstc_data_sel[3] | rst_tri_en; + + +mux4ds #(64) diag_st_mx ( + .in0 (lmq0_bypass_data[63:0]), + .in1 (lmq1_bypass_data[63:0]), + .in2 (lmq2_bypass_data[63:0]), + .in3 (lmq3_bypass_data[63:0]), + .sel0 (lsu_diagnstc_data_sel_1hot[0]), + .sel1 (lsu_diagnstc_data_sel_1hot[1]), + .sel2 (lsu_diagnstc_data_sel_1hot[2]), + .sel3 (lsu_diagnstc_data_sel_1hot[3]), + .dout (lsu_diagnstc_wr_data_e[63:0]) +); + +// Remove flops +/*dff #(64) dgndt_d1 ( + .din (tlb_st_data[63:0]), + .q (lsu_diagnstc_wr_data_e[63:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); */ + +assign lsu_diagnstc_wr_data_b0 = lsu_diagnstc_wr_data_e[0] ; + +// Move tte format and parity calc to tlbdp + +//assign lsu_tlu_st_rs3_data_g[63:0] = tlb_st_data_d1[63:0]; +assign lsu_tlu_st_rs3_data_g[47:3] = tlb_st_data_d1[47:3]; +assign lsu_mmu_rs3_data_g[63:0] = tlb_st_data_d1[63:0]; +assign lsu_tlu_rs3_data_g[63:0] = tlb_st_data_d1[63:0]; + +// Removed Fast bypass as penalty is negligible. + +//================================================================================================= +// STQ PKT2 DATA +//================================================================================================= + +//** stquad support removed ** + +//================================================================================================= +// IMISS/SPU DP +//================================================================================================= + +// Format of IFU pcx packet (50b) : +// b49 - valid +// b48:44 - req type +// b43:42 - rep way (for "eviction" - maintains directory consistency ) +// b41:40 - mil id +// b39:0 - imiss address + + +// Align ifu pkt with ldst pkt - temporary ! +// Does this need to be enabled ?!!!! No. +assign ifu_pcx_pkt_e[51:0] = ifu_pcx_pkt[51:0] ; + +// Form pcx-wide ifu request packet. +assign ifu_full_pcx_pkt_e[`PCX_VLD] = ifu_pcx_pkt_e[51] ; +assign ifu_full_pcx_pkt_e[`PCX_RQ_HI:`PCX_RQ_LO] = ifu_pcx_pkt_e[48:44]; +assign ifu_full_pcx_pkt_e[`PCX_NC] = ifu_pcx_pkt_e[49] ; +assign ifu_full_pcx_pkt_e[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ; +// thread-id unused - use mil id instead. +assign ifu_full_pcx_pkt_e[`PCX_TH_HI:`PCX_TH_LO] = ifu_pcx_pkt_e[41:40] ; +assign ifu_full_pcx_pkt_e[`PCX_BF_HI] = ifu_pcx_pkt_e[50] ; +assign ifu_full_pcx_pkt_e[`PCX_BF_HI-1:`PCX_BF_LO] = 2'b00; +assign ifu_full_pcx_pkt_e[`PCX_WY_HI:`PCX_WY_LO] = ifu_pcx_pkt_e[43:42] ; +// unused - always infer 32b +assign ifu_full_pcx_pkt_e[`PCX_SZ_HI:`PCX_SZ_LO] = 3'b000 ; +assign ifu_full_pcx_pkt_e[`PCX_AD_HI:`PCX_AD_LO] = ifu_pcx_pkt_e[39:0] ; +// no data +assign ifu_full_pcx_pkt_e[`PCX_DA_HI:`PCX_DA_LO] = 64'd0 ; + +// Form pcx-wide interrupt request packet. +assign intrpt_full_pcxpkt[`PCX_VLD] = tlu_lsu_pcxpkt[25] ; +assign intrpt_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = tlu_lsu_pcxpkt[24:20]; +assign intrpt_full_pcxpkt[`PCX_NC] = 1'b0 ; + +//tlu_lsu_pcxpkt[12:8] is the 5 bit interrupt destination thread id, +//so [12:10] is the cpu id, and [9:8] is the thread id. +assign intrpt_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = tlu_lsu_pcxpkt[12:10]; + +// or should thread-id be 19:18 ? +assign intrpt_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = tlu_lsu_pcxpkt[19:18] ; +// May actually make undriven fields x. +assign intrpt_full_pcxpkt[`PCX_BF_HI:`PCX_BF_LO] = 3'b000; +assign intrpt_full_pcxpkt[`PCX_WY_HI:`PCX_WY_LO] = 2'b00 ; +assign intrpt_full_pcxpkt[`PCX_SZ_HI:`PCX_SZ_LO] = 3'b000 ; +assign intrpt_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] = 40'd0 ; +assign intrpt_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] = {46'd0,tlu_lsu_pcxpkt[17:0]} ; + +// Format fpop_full_pcxpkt. + +assign fpop_full_pcxpkt[`PCX_VLD] = ffu_lsu_data[80] ; +assign fpop_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {4'b0101,ffu_lsu_data[78]} ; +assign fpop_full_pcxpkt[`PCX_NC] = 1'b0 ; +assign fpop_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ; +assign fpop_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = ffu_lsu_data[77:76] ; +assign fpop_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] = 8'd0 ; +assign fpop_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO+16] = 24'd0 ; +assign fpop_full_pcxpkt[`PCX_AD_LO+15:`PCX_AD_LO+8] = ffu_lsu_data[75:68]; // 79:72 +assign fpop_full_pcxpkt[`PCX_AD_LO+7:`PCX_AD_LO+4] = 4'b0000; // 71:68 +assign fpop_full_pcxpkt[`PCX_AD_LO+3:`PCX_AD_LO] = ffu_lsu_data[67:64] ; // 67:64 +assign fpop_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] = ffu_lsu_data[63:0] ; + + +// RAMTest Data Merging. +wire cacherd_clk; +clken_buf cacherd_clkbuf ( + .rclk (clk), + .enb_l (~lsu_ramtest_rd_w), + .tmb_l (~se), + .clk (cacherd_clk) + ) ; + +wire [63:0] cache_rdata_w,cache_rdata_w2 ; + +mux2ds #(64) cacherd_sel ( + .in0 (ifu_lsu_ldxa_data_w2[63:0]), + .in1 (lsu_dcache_rdata_w[63:0]), + .sel0 (~lsu_dcache_iob_rd_w), + .sel1 (lsu_dcache_iob_rd_w), + .dout (cache_rdata_w[63:0]) +); + +dff #(64) cachedata ( + .din (cache_rdata_w[63:0]), + .q (cache_rdata_w2[63:0]), // references dcache rd staging + .clk (cacherd_clk), + .se (1'b0), .si (), .so () + ); + +assign fwd_full_pcxpkt[`PCX_VLD] = 1'b1 ; +assign fwd_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {3'b011,lsu_pcx_fwd_reply,~lsu_pcx_fwd_reply} ; +assign fwd_full_pcxpkt[`PCX_NC] = lsu_pcx_fwd_pkt[107] ; +assign fwd_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = lsu_pcx_fwd_pkt[106:104] ; +assign fwd_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = 2'b00 ; +assign fwd_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] = + {6'b000000,lsu_fwd_rply_sz1_unc,1'b1} ; +// All address bits should not be required !!! +assign fwd_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] = lsu_pcx_fwd_pkt[103:64] ; + +// Mux sources of TAP request data - margin,pc,defeature/debug/bist. +// Be careful about pc - could be a critical path. +// ** Assume read-data stays constant at output latches of dcache ** +//assign fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] = +//lsu_iobrdge_rply_data_sel[0] ? {20'd0,lsu_iobrdge_rd_data[43:0]} : +// lsu_iobrdge_rply_data_sel[1] ? cache_rdata_w2[63:0] : +// lsu_iobrdge_rply_data_sel[2] ? lsu_pcx_fwd_pkt[63:0] : +// 64'hxxxx_xxxx_xxxx_xxxx ; + +mux3ds #(64) mx_fwd_full_pcxpkt ( + .in0 ({20'd0,lsu_iobrdge_rd_data[43:0]}), + .in1 (cache_rdata_w2[63:0]), + .in2 (lsu_pcx_fwd_pkt[63:0]), + .sel0(lsu_iobrdge_rply_data_sel[0]), + .sel1(lsu_iobrdge_rply_data_sel[1]), + .sel2(lsu_iobrdge_rply_data_sel[2]), + .dout(fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO])); + + +wire [`PCX_WIDTH-1:0] spu_lsu_ldst_pckt_d1 ; +dff #(`PCX_WIDTH) ff_spu_lsu_ldst_pckt_d1 ( + .din (spu_lsu_ldst_pckt[`PCX_WIDTH-1:0]), + .q (spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign imiss_strm_pcx_pkt[`PCX_WIDTH-1:0] = imiss_pcx_mx_sel ? + ifu_full_pcx_pkt_e[`PCX_WIDTH-1:0] : spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0] ; + +wire [`PCX_WIDTH-1:0] fwd_int_fp_pcx_pkt ; +mux3ds #(`PCX_WIDTH) mux_fwd_int_fp_pcx_pkt ( + .in0 (fwd_full_pcxpkt[`PCX_WIDTH-1:0]), + .in1 (intrpt_full_pcxpkt[`PCX_WIDTH-1:0]), + .in2 (fpop_full_pcxpkt[`PCX_WIDTH-1:0]), + .sel0 (fwd_int_fp_pcx_mx_sel[0]), + .sel1 (fwd_int_fp_pcx_mx_sel[1]), + .sel2 (fwd_int_fp_pcx_mx_sel[2]), + .dout (fwd_int_fp_pcx_pkt [`PCX_WIDTH-1:0]) +); + +//================================================================================================= +// PCX PKT SELECTION +//================================================================================================= + +assign stb_pcx_pkt[`STB_PCX_VLD] = lsu_stb_pcx_rvld_d1 ; // Valid +// Support stores for now. +assign stb_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO] = stb_rdata_ramd[74:72] ; // Rq-type +assign stb_pcx_pkt[`STB_PCX_NC] = + // Mina the OR gate has been extended to a 3 input gate + stb_rdata_ramd[74] | stb_rdata_ramd[73] | // atomics + stb_rdata_ramd[71] ; // flush inst +// cpu-id will be inserted on way out of core. +assign stb_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO] = lsu_stb_rd_tid[1:0] ; // TID +// bf-id is not required. +// mux will have to be placed elsewhere. (grape) +assign stb_pcx_pkt[`STB_PCX_FLSH] = stb_rdata_ramd[71] ; // flush +assign stb_pcx_pkt[`STB_PCX_FLSH-1] = 1'b0 ; +//assign stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO] = 2'b00 ; + +//bug 2511 +assign stb_pcx_pkt[`STB_PCX_SZ_HI:`STB_PCX_SZ_LO] = + stb_rdata_ramd[69:68]; // Size + +//assign stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] = stb_pcx_pkt[`STB_PCX_FLSH] ? 40'b0 : +// {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr + +assign stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] = + {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr + + +assign stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] = + stb_rdata_ramd[63:0]; // Data + +assign store_pcx_pkt[`STB_PCX_WIDTH-1:0] = stb_pcx_pkt[`STB_PCX_WIDTH-1:0] ; + +// bld addr select. +wire [1:0] bld_addr_b54 ; +assign bld_addr_b54[1:0] = + lsu_bld_pcx_rq ? lsu_bld_rq_addr[1:0] : load_pcx_pkt[`LMQ_AD_LO+5:`LMQ_AD_LO+4] ; + +// Select between load and store outbound pkt. +// *** cpu-id currently hardwired in pkt +// *** Thrd id currently hardwired. +mux4ds #(124) pcx_pkt_src ( + .in0 ({load_pcx_pkt[`LMQ_VLD],2'b00, + load_pcx_pkt[`LMQ_RQ_HI: `LMQ_RQ_LO], + load_pcx_pkt[`LMQ_NC],const_cpuid[2:0], + ld_pcx_thrd[1:0],lsu_pcx_ld_dtag_perror_w2, + load_pcx_pkt[`LMQ_PREF],load_pcx_pkt[`LMQ_DFLUSH], + load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lsu_pcx_rq_sz_b3, + //load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],1'b0, + //load_pcx_pkt[`LMQ_SZ_HI:0],cas_pkt2_data[63:0]}), // load + load_pcx_pkt[`LMQ_SZ_HI:`LMQ_AD_LO+6], bld_addr_b54[1:0], + load_pcx_pkt[`LMQ_AD_LO+3:`LMQ_AD_LO],cas_pkt2_data[63:0]}), // load + .in1 ({store_pcx_pkt[`STB_PCX_VLD],1'b0, + store_pcx_pkt[`STB_PCX_FLSH], // turn into interrupt request. + store_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO], + store_pcx_pkt[`STB_PCX_NC], const_cpuid[2:0], + store_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO], + 1'b0, + stb_rdata_ramd[70], // blk-st : Bug 3395 + stb_rdata_ramd[75], + 2'b00, + //store_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO], + 1'b0,store_pcx_pkt[`STB_PCX_SZ_HI:0]}), // store + .in2 (imiss_strm_pcx_pkt[`PCX_WIDTH-1:0]), // alt src : imiss,stream. + .in3 (fwd_int_fp_pcx_pkt[`PCX_WIDTH-1:0]), // fwd, interrupt, fpop + .sel0 (pcx_pkt_src_sel[0]), + .sel1 (pcx_pkt_src_sel[1]), + .sel2 (pcx_pkt_src_sel[2]), + .sel3 (pcx_pkt_src_sel[3]), + .dout (pcx_pkt_data[`PCX_WIDTH-1:0]) +); + +dff #(124) pcx_xmit_ff ( + .din (pcx_pkt_data[`PCX_WIDTH-1:0]), + .q (spc_pcx_data_pa[`PCX_WIDTH-1:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Stage to avoid critical path +/*assign lsu_ifu_ld_icache_index[11:5] = pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5] ; +assign lsu_ifu_ld_pcxpkt_tid[1:0] = pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO] ;*/ + +dff #(9) stg_icindx ( + .din ({pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5],pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO]}), + .q ({lsu_ifu_ld_icache_index[11:5],lsu_ifu_ld_pcxpkt_tid[1:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//========================================================================================= +// VA Watchpt Reg per thread +//========================================================================================= + +//VA_watchpoint_thread0 + wire va_wtchpt0_clk ; + wire [47:3] va_wtchpt0_addr; + +clken_buf clkbf_va_wtchpt0 ( + .rclk (clk), + .enb_l (lsu_va_wtchpt0_wr_en_l), + .tmb_l (~se), + .clk (va_wtchpt0_clk) + ) ; + +dff #(45) va_wtchpt0_ff ( + .din (lsu_tlu_st_rs3_data_g[47:3]), + .q (va_wtchpt0_addr[47:3]), + .clk (va_wtchpt0_clk), + .se (1'b0), .si (), .so () + ); + +//VA_watchpoint_thread1 + wire va_wtchpt1_clk ; + wire [47:3] va_wtchpt1_addr; + +clken_buf clkbf_va_wtchpt1 ( + .rclk (clk), + .enb_l (lsu_va_wtchpt1_wr_en_l), + .tmb_l (~se), + .clk (va_wtchpt1_clk) + ) ; + +dff #(45) va_wtchpt1_ff ( + .din (lsu_tlu_st_rs3_data_g[47:3]), + .q (va_wtchpt1_addr[47:3]), + .clk (va_wtchpt1_clk), + .se (1'b0), .si (), .so () + ); + +//VA_watchpoint_thread2 + wire va_wtchpt2_clk ; + wire [47:3] va_wtchpt2_addr; + +clken_buf clkbf_va_wtchpt2 ( + .rclk (clk), + .enb_l (lsu_va_wtchpt2_wr_en_l), + .tmb_l (~se), + .clk (va_wtchpt2_clk) + ) ; + +dff #(45) va_wtchpt2_ff ( + .din (lsu_tlu_st_rs3_data_g[47:3]), + .q (va_wtchpt2_addr[47:3]), + .clk (va_wtchpt2_clk), + .se (1'b0), .si (), .so () + ); + +//VA_watchpoint_thread3 + wire va_wtchpt3_clk ; + wire [47:3] va_wtchpt3_addr; + +clken_buf clkbf_va_wtchpt3 ( + .rclk (clk), + .enb_l (lsu_va_wtchpt3_wr_en_l), + .tmb_l (~se), + .clk (va_wtchpt3_clk) + ) ; + +dff #(45) va_wtchpt3_ff ( + .din (lsu_tlu_st_rs3_data_g[47:3]), + .q (va_wtchpt3_addr[47:3]), + .clk (va_wtchpt3_clk), + .se (1'b0), .si (), .so () + ); + + wire [47:3] va_wtchpt_addr; + +mux4ds #(45) va_wtchpt_mx_m ( + .in0 (va_wtchpt0_addr[47:3]), + .in1 (va_wtchpt1_addr[47:3]), + .in2 (va_wtchpt2_addr[47:3]), + .in3 (va_wtchpt3_addr[47:3]), + .sel0 (thread0_m), + .sel1 (thread1_m), + .sel2 (thread2_m), + .sel3 (thread3_m), + .dout (va_wtchpt_addr[47:3]) + ); + +mux4ds #(45) va_wtchpt_mx_g ( + .in0 (va_wtchpt0_addr[47:3]), + .in1 (va_wtchpt1_addr[47:3]), + .in2 (va_wtchpt2_addr[47:3]), + .in3 (va_wtchpt3_addr[47:3]), + .sel0 (thread0_g), + .sel1 (thread1_g), + .sel2 (thread2_g), + .sel3 (thread3_g), + .dout (lsu_va_wtchpt_addr[47:3]) + ); + +//VA wtchpt comparison at M stage +//assign lsu_va_match_m = (lsu_ldst_va_m[47:3] == va_wtchpt_addr[47:3]); +//bug6480/eco6623 +assign lsu_va_match_b47_b32_m = (lsu_ldst_va_m[47:32] == va_wtchpt_addr[47:32]); +assign lsu_va_match_b31_b3_m = (lsu_ldst_va_m[31:3 ] == va_wtchpt_addr[31:3 ]); + +//==================================================================== +//dc_fill CP + wire [63:0] l2fill_data_m; + +//dff #(64) stgm_l2fd ( +// .din (lsu_l2fill_data[63:0]), +// .q (l2fill_data_m[63:0]), +// .clk (clk), +// .se (se), .si (), .so () +// ); + assign l2fill_data_m[63:0] = lsu_l2fill_data[63:0]; + + + wire [63:0] ld_byp_data_m; + +mux4ds #(64) ld_byp_mx ( + .in0 (lmq0_bypass_data[63:0]), + .in1 (lmq1_bypass_data[63:0]), + .in2 (lmq2_bypass_data[63:0]), + .in3 (lmq3_bypass_data[63:0]), + .sel0 (ld_thrd_byp_sel_m[0]), + .sel1 (ld_thrd_byp_sel_m[1]), + .sel2 (ld_thrd_byp_sel_m[2]), + .sel3 (ld_thrd_byp_sel_m[3]), + .dout (ld_byp_data_m[63:0]) +); + +assign dcache_alt_data_w0_m[63:0] = + l2fill_vld_m ? l2fill_data_m[63:0] : + ld_byp_data_m[63:0]; + +//assign lsu_l2fill_or_byp_msb_m[7:0] +// = {lsu_l2fill_or_byp_data_m[63], +// lsu_l2fill_or_byp_data_m[55], +// lsu_l2fill_or_byp_data_m[47], +// lsu_l2fill_or_byp_data_m[39], +// lsu_l2fill_or_byp_data_m[31], +// lsu_l2fill_or_byp_data_m[23], +// lsu_l2fill_or_byp_data_m[15], +// lsu_l2fill_or_byp_data_m[07]} ; +//==================================================================== + +endmodule Index: trunk/hdl/rtl/s1_top/request.txt =================================================================== --- trunk/hdl/rtl/s1_top/request.txt (nonexistent) +++ trunk/hdl/rtl/s1_top/request.txt (revision 4) @@ -0,0 +1,4170 @@ +// ========== Copyright Header Begin ========================================== +// +// OpenSPARC T1 Processor File: lsu_qctl1.v +// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +// +// The above named program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// The above named program is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this work; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +// +// ========== Copyright Header End ============================================ +////////////////////////////////////////////////////////////////////// +/* +// Description: LSU Queue Control for Sparc Core +// - includes monitoring for pcx queues +// - control for lsu datapath +// - rd/wr control of dfq +*/ +//////////////////////////////////////////////////////////////////////// +// header file includes +//////////////////////////////////////////////////////////////////////// +`include "sys.h" // system level definition file which contains the + // time scale definition +`include "iop.h" + +`include "lsu.h" + +//////////////////////////////////////////////////////////////////////// +// Local header file includes / local defines +//////////////////////////////////////////////////////////////////////// + +module lsu_qctl1 ( /*AUTOARG*/ + // Outputs + lsu_bld_helper_cmplt_m, lsu_bld_cnt_m, lsu_bld_reset, + lsu_pcx_rq_sz_b3, lsu_ramtest_rd_w, ld_stb_full_raw_w2, + lsu_ld_pcx_rq_sel_d2, spc_pcx_req_pq, spc_pcx_atom_pq, + lsu_ifu_pcxpkt_ack_d, pcx_pkt_src_sel, lmq_enable, + imiss_pcx_mx_sel, fwd_int_fp_pcx_mx_sel, lsu_ffu_bld_cnt_w, + lsu_ld_pcx_rq_mxsel, ld_pcx_thrd, lsu_spu_ldst_ack, + pcx_rq_for_stb, pcx_rq_for_stb_d1, lsu_ffu_ack, + lsu_ifu_ld_pcxpkt_vld, lsu_pcx_req_squash0, lsu_pcx_req_squash1, + lsu_pcx_req_squash2, lsu_pcx_req_squash3, lsu_pcx_req_squash_d1, + lsu_pcx_ld_dtag_perror_w2, lsu_tlu_dcache_miss_w2, lsu_bld_pcx_rq, + lsu_bld_rq_addr, lsu_fwdpkt_pcx_rq_sel, lsu_imiss_pcx_rq_sel_d1, + lsu_tlu_pcxpkt_ack, lsu_intrpt_cmplt, lsu_lmq_byp_misc_sel, + lsu_sscan_data, so, lsu_dfq_byp_tid_d1_sel, lmq0_pcx_pkt_way, + lmq1_pcx_pkt_way, lmq2_pcx_pkt_way, lmq3_pcx_pkt_way, + lsu_st_pcx_rq_pick, lsu_stb_pcx_rvld_d1, lsu_stb_rd_tid, + lsu_ld0_spec_vld_kill_w2, lsu_ld1_spec_vld_kill_w2, + lsu_ld2_spec_vld_kill_w2, lsu_ld3_spec_vld_kill_w2, + lsu_st_pcx_rq_vld, + // Inputs + rclk, si, se, sehold, grst_l, arst_l, lsu_quad_word_access_g, + pcx_spc_grant_px, ld_inst_vld_e, lsu_ldst_va_m, stb0_l2b_addr, + stb1_l2b_addr, stb2_l2b_addr, stb3_l2b_addr, lsu_ld_miss_g, + ifu_lsu_ldst_fp_e, ld_rawp_st_ced_w2, ld_rawp_st_ackid_w2, + stb0_crnt_ack_id, stb1_crnt_ack_id, stb2_crnt_ack_id, + stb3_crnt_ack_id, ifu_tlu_thrid_e, ldxa_internal, + spu_lsu_ldst_pckt, spu_lsu_ldst_pckt_vld, ifu_tlu_inst_vld_m, + ifu_lsu_flush_w, ifu_lsu_casa_e, lsu_ldstub_g, lsu_swap_g, + stb0_atm_rq_type, stb1_atm_rq_type, stb2_atm_rq_type, + stb3_atm_rq_type, tlb_pgnum_g, stb_rd_for_pcx, ffu_lsu_data, + ffu_lsu_fpop_rq_vld, ifu_lsu_ldst_dbl_e, ifu_lsu_pcxreq_d, + ifu_lsu_destid_s, ifu_lsu_pref_inst_e, tlb_cam_hit_g, + lsu_blk_asi_m, stb_cam_hit_bf, lsu_fwdpkt_vld, + lsu_dcfill_active_e, dfq_byp_sel, lsu_dfq_ld_vld, lsu_fldd_vld_en, + lsu_dfill_dcd_thrd, lsu_fwdpkt_dest, tlu_lsu_pcxpkt_tid, + lsu_stb_empty, tlu_lsu_pcxpkt_vld, tlu_lsu_pcxpkt_l2baddr, + ld_sec_hit_thrd0, ld_sec_hit_thrd1, ld_sec_hit_thrd2, + ld_sec_hit_thrd3, ld_thrd_byp_sel_e, lsu_st_pcx_rq_kill_w2, + ifu_lsu_alt_space_e, lsu_dfq_byp_tid, dfq_byp_ff_en, + stb_ld_full_raw, stb_ld_partial_raw, stb_cam_mhit, + lsu_ldquad_inst_m, stb_cam_wr_no_ivld_m, lsu_ldst_va_way_g, + lsu_dcache_rand, lsu_encd_way_hit, lsu_way_hit_or, dc_direct_map, + lsu_tlb_perr_ld_rq_kill_w, lsu_dcache_tag_perror_g, + lsu_ld_inst_vld_g, asi_internal_m, ifu_lsu_pcxpkt_e_b50, + lda_internal_m, atomic_m, lsu_dcache_iob_rd_w, + ifu_lsu_fwd_data_vld, rst_tri_en, lsu_no_spc_pref, + tlu_early_flush_pipe2_w, lsu_ttype_vld_m2 + ); + + +input rclk ; +input si; +input se; +input sehold; +input grst_l; +input arst_l; + +//input [1:0] ld_pcx_pkt_wy_g ; +input lsu_quad_word_access_g ; + +// LSU <- PCX +// bit5 - FP, bit4 - IO. +input [4:0] pcx_spc_grant_px ; // pcx grants packet to destination. +input ld_inst_vld_e; // valid ld inst; d-stage +input [7:6] lsu_ldst_va_m ; // Virt. Addr. of ld/st/atomic. + +input [2:0] stb0_l2b_addr ; // st's addr for pcx - thread0. +input [2:0] stb1_l2b_addr ; // st's addr for pcx - thread1. +input [2:0] stb2_l2b_addr ; // st's addr for pcx - thread2. +input [2:0] stb3_l2b_addr ; // st's addr for pcx - thread3. +input lsu_ld_miss_g ; // load misses in dcache. +//input lsu_ld_hit_g ; // load hits in dcache. +input ifu_lsu_ldst_fp_e ; // fp load/store. + +//input ld_stb_full_raw_g ; // full raw for load - thread0 +//input ld_stb_partial_raw_g ; // partial raw for load - thread0 +input ld_rawp_st_ced_w2 ; // store has been acked - thread0 +//input ld_rawp_st_ced_g ; // store has been acked - thread0 +input [2:0] ld_rawp_st_ackid_w2 ; // ackid for acked store - thread0 +input [2:0] stb0_crnt_ack_id ; // ackid for crnt outstanding st. +input [2:0] stb1_crnt_ack_id ; // ackid for crnt outstanding st. +input [2:0] stb2_crnt_ack_id ; // ackid for crnt outstanding st. +input [2:0] stb3_crnt_ack_id ; // ackid for crnt outstanding st. +input [1:0] ifu_tlu_thrid_e ; // thread-id +input ldxa_internal ; // internal ldxa, stg g + +input [`PCX_AD_LO+7:`PCX_AD_LO+6] spu_lsu_ldst_pckt ; // addr bits +input spu_lsu_ldst_pckt_vld ; // vld +input ifu_tlu_inst_vld_m ; // inst is vld - wstage + +input ifu_lsu_flush_w ; // ifu's flush +input ifu_lsu_casa_e ; // compare-swap instr +input lsu_ldstub_g ; // ldstub(a) instruction +input lsu_swap_g ; // swap(a) instruction +input [2:1] stb0_atm_rq_type ; // stb pcx rq type - atomic +input [2:1] stb1_atm_rq_type ; // stb pcx rq type - atomic +input [2:1] stb2_atm_rq_type ; // stb pcx rq type - atomic +input [2:1] stb3_atm_rq_type ; // stb_pcx_rq_type - atomic +input [39:37] tlb_pgnum_g ; // ldst access to io +input [3:0] stb_rd_for_pcx ; // rd for pcx can be scheduled +input [80:79] ffu_lsu_data ; +input ffu_lsu_fpop_rq_vld ; // ffu dispatches fpop issue request. +input ifu_lsu_ldst_dbl_e ; // ld/st double +input ifu_lsu_pcxreq_d ; +input [2:0] ifu_lsu_destid_s ; +input ifu_lsu_pref_inst_e ; // prefetch inst +input tlb_cam_hit_g ; // tlb cam hit ; error included +input lsu_blk_asi_m ; +//input stb_cam_wptr_vld; +input stb_cam_hit_bf; + +input lsu_fwdpkt_vld; +//input [3:0] lsu_error_rst; +input lsu_dcfill_active_e; +input [3:0] dfq_byp_sel ; +//input [3:0] lsu_dfq_byp_mxsel ; +//input [3:0] lsu_st_ack_rq_stb ; +input lsu_dfq_ld_vld; +input lsu_fldd_vld_en; +input [3:0] lsu_dfill_dcd_thrd ; +input [4:0] lsu_fwdpkt_dest ; + +input [19:18] tlu_lsu_pcxpkt_tid ; +input [3:0] lsu_stb_empty ; +input tlu_lsu_pcxpkt_vld ; +input [11:10] tlu_lsu_pcxpkt_l2baddr ; +input ld_sec_hit_thrd0 ; // ld has sec. hit against th0 +input ld_sec_hit_thrd1 ; // ld has sec. hit against th1 +input ld_sec_hit_thrd2 ; // ld has sec. hit against th2 +input ld_sec_hit_thrd3 ; // ld has sec. hit against th3 +input [2:0] ld_thrd_byp_sel_e ; // stb,ldxa thread byp sel +input [3:0] lsu_st_pcx_rq_kill_w2 ; + +input ifu_lsu_alt_space_e ; +input [1:0] lsu_dfq_byp_tid; + +input dfq_byp_ff_en; + +//input [3:0] lsu_dtag_perror_w2 ; + +input [7:0] stb_ld_full_raw ; +input [7:0] stb_ld_partial_raw ; + +input stb_cam_mhit ; // multiple hits in stb +input lsu_ldquad_inst_m ; // ldquad inst + +input stb_cam_wr_no_ivld_m ; + +input [1:0] lsu_ldst_va_way_g ; // 12:11 for direct map +input [1:0] lsu_dcache_rand; +input [1:0] lsu_encd_way_hit; +input lsu_way_hit_or; +input dc_direct_map; +//input lsu_quad_asi_g; + +input lsu_tlb_perr_ld_rq_kill_w ; + +input lsu_dcache_tag_perror_g ; // dcache tag parity error +input [3:0] lsu_ld_inst_vld_g ; +//input lsu_pcx_ld_dtag_perror_w2 ; // from qctl2 + +input asi_internal_m ; + +input ifu_lsu_pcxpkt_e_b50 ; + +input lda_internal_m ; +input atomic_m ; + +input lsu_dcache_iob_rd_w ; +input ifu_lsu_fwd_data_vld ; + +input rst_tri_en ; + +output lsu_bld_helper_cmplt_m ; +output [2:0] lsu_bld_cnt_m ; +output lsu_bld_reset ; + +output lsu_pcx_rq_sz_b3 ; + +output lsu_ramtest_rd_w ; + + +output ld_stb_full_raw_w2 ; + +output [3:0] lsu_ld_pcx_rq_sel_d2 ; + +output [4:0] spc_pcx_req_pq; // request destination for packet. + // FPU, IO, L2_BANK[3:0]. + // 1-hot - create monitor ! +output spc_pcx_atom_pq ; // atomic packet. +output lsu_ifu_pcxpkt_ack_d ; // ack for I$ fill request. +output [3:0] pcx_pkt_src_sel ; // - qdp1 +output [3:0] lmq_enable ; // - qdp1 +output imiss_pcx_mx_sel ; // - qdp1 +output [2:0] fwd_int_fp_pcx_mx_sel ; // - qdp1 +output [2:0] lsu_ffu_bld_cnt_w ; +//output [3:0] ld_pcx_rq_sel ; // - qctl2 +output [3:0] lsu_ld_pcx_rq_mxsel ; // - qdp1 +output [1:0] ld_pcx_thrd ; // - qdp1 +output lsu_spu_ldst_ack ; // strm ld/st ack to spu +//output strm_sldst_cam_vld; // strm ld/st xslate rq +//output strm_sld_dc_rd_vld; // strm alloc. ld xslate rq. +//output strm_sldst_cam_d2; // strm ld/st xslate rq-d2 +output [3:0] pcx_rq_for_stb ; // pcx demands rd for store - stb_ctl +output [3:0] pcx_rq_for_stb_d1 ; // pcx demands rd for store - qdp2 +output lsu_ffu_ack ; // ack to ffu. +output lsu_ifu_ld_pcxpkt_vld ; +//output [3:0] lsu_iobrdge_rply_data_sel ; // - qdp1 +//output lsu_pcx_req_squash ; +output lsu_pcx_req_squash0 ; +output lsu_pcx_req_squash1 ; +output lsu_pcx_req_squash2 ; +output lsu_pcx_req_squash3 ; +output lsu_pcx_req_squash_d1 ; +output lsu_pcx_ld_dtag_perror_w2 ; // - qdp1 +output [3:0] lsu_tlu_dcache_miss_w2 ; +output lsu_bld_pcx_rq ; // cycle after request // - qdp1 +output [1:0] lsu_bld_rq_addr ; // cycle after request // - qdp1 +//output lsu_ifu_flush_ireg ; + +output lsu_fwdpkt_pcx_rq_sel ; +//output lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1 ; +//output lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1 ; +output lsu_imiss_pcx_rq_sel_d1 ; +output lsu_tlu_pcxpkt_ack; +output [3:0] lsu_intrpt_cmplt ; // intrpt can restart thread +//output lsu_ld_sec_hit_l2access_g ; +//output [1:0] lsu_ld_sec_hit_wy_g ; +output [3:0] lsu_lmq_byp_misc_sel ; // select g-stage lmq source + +output [12:0] lsu_sscan_data ; + +output so; +output [3:0] lsu_dfq_byp_tid_d1_sel; + + + input [3:0] lsu_no_spc_pref; + +//output [1:0] lsu_lmq_pkt_way_g; +output [1:0] lmq0_pcx_pkt_way; +output [1:0] lmq1_pcx_pkt_way; +output [1:0] lmq2_pcx_pkt_way; +output [1:0] lmq3_pcx_pkt_way; +output [3:0] lsu_st_pcx_rq_pick; + +// signals related to logic moved from stb_rwctl +output lsu_stb_pcx_rvld_d1; +output [1:0] lsu_stb_rd_tid; + +output lsu_ld0_spec_vld_kill_w2 ; +output lsu_ld1_spec_vld_kill_w2 ; +output lsu_ld2_spec_vld_kill_w2 ; +output lsu_ld3_spec_vld_kill_w2 ; + +output lsu_st_pcx_rq_vld ; + + + input tlu_early_flush_pipe2_w; + input lsu_ttype_vld_m2; + +/*AUTOWIRE*/ +// Beginning of automatic wires (for undeclared instantiated-module outputs) +// End of automatics + +wire thread0_e,thread1_e,thread2_e,thread3_e; +wire thread0_w2,thread1_w2,thread2_w2,thread3_w2; +wire ld0_inst_vld_e,ld1_inst_vld_e,ld2_inst_vld_e,ld3_inst_vld_e ; +wire ld0_inst_vld_g,ld1_inst_vld_g,ld2_inst_vld_g,ld3_inst_vld_g ; +wire ld0_inst_vld_w2,ld1_inst_vld_w2,ld2_inst_vld_w2,ld3_inst_vld_w2 ; +//wire st_inst_vld_m,st_inst_vld_g; +wire imiss_pcx_rq_sel_d1, strm_pcx_rq_sel_d1 ; +wire imiss_pcx_rq_sel_d2 ; +wire fpop_pcx_rq_sel_d1, fpop_pcx_rq_sel_d2 ; +wire imiss_pcx_rq_sel ; +wire imiss_pkt_vld ; +wire [2:0] imiss_l2bnk_addr ; +wire [4:0] imiss_l2bnk_dest ; +wire fpst_vld_m, fpst_vld_g ; +wire fpop_vld_reset ; +wire fpop_pcx_rq_sel ; +wire fpop_pcx_rq_sel_tmp ; +wire fpop_vld_en ; +wire fpop_pkt1 ; +wire fpop_pkt_vld,fpop_pkt_vld_unmasked ; +wire fpop_atom_req, fpop_atom_rq_pq ; +wire [4:0] fpop_l2bnk_dest ; +wire pcx_req_squash ; +wire [4:0] strm_l2bnk_dest ; +wire strm_pkt_vld; +wire st0_pkt_vld ; +wire st1_pkt_vld ; +wire st2_pkt_vld ; +wire st3_pkt_vld ; +wire st0_pcx_rq_sel_d1, st1_pcx_rq_sel_d1; +wire st2_pcx_rq_sel_d1, st3_pcx_rq_sel_d1; +wire st0_pcx_rq_sel_d2, st1_pcx_rq_sel_d2; +wire st2_pcx_rq_sel_d2, st3_pcx_rq_sel_d2; +wire st0_pcx_rq_sel_d3, st1_pcx_rq_sel_d3; +wire st2_pcx_rq_sel_d3, st3_pcx_rq_sel_d3; +wire st0_cas_vld, st1_cas_vld, st2_cas_vld, st3_cas_vld ; +wire st0_atomic_vld, st1_atomic_vld, st2_atomic_vld, st3_atomic_vld ; +wire [4:0] st0_l2bnk_dest,st1_l2bnk_dest ; +wire [4:0] st2_l2bnk_dest,st3_l2bnk_dest ; +wire bld_helper_cmplt_e, bld_helper_cmplt_m, bld_helper_cmplt_g ; +wire bld_din,bld_dout ; +wire bld_g ; +wire bld_en ; +wire [1:0] bld_cnt ; +wire [1:0] bcnt_din ; +wire [2:0] bld_rd_din, bld_rd_dout, bld_rd_dout_m ; +wire [3:0] bld_annul,bld_annul_d1 ; +wire bld_rd_en ; +wire casa_m, casa_g ; +wire ld0_vld_reset, ld0_pkt_vld ; +wire ld0_pcx_rq_sel_d2, ld1_pcx_rq_sel_d2 ; +wire ld2_pcx_rq_sel_d2, ld3_pcx_rq_sel_d2 ; +wire ld0_fill_reset, ld1_fill_reset,ld2_fill_reset,ld3_fill_reset; +wire ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1; +wire ld0_fill_reset_d2,ld1_fill_reset_d2,ld2_fill_reset_d2,ld3_fill_reset_d2; +wire ld0_fill_reset_d2_tmp,ld1_fill_reset_d2_tmp,ld2_fill_reset_d2_tmp,ld3_fill_reset_d2_tmp; +wire [4:0] ld0_l2bnk_dest, ld1_l2bnk_dest ; +wire [4:0] ld2_l2bnk_dest, ld3_l2bnk_dest ; +wire ld1_vld_reset, ld1_pkt_vld ; +wire ld2_vld_reset, ld2_pkt_vld ; +wire ld3_vld_reset, ld3_pkt_vld ; +//wire casa0_g, casa1_g, casa2_g, casa3_g; +wire ld0_rawp_reset,ld0_rawp_en,ld0_rawp_disabled; +wire ld1_rawp_reset,ld1_rawp_en,ld1_rawp_disabled; +wire ld2_rawp_reset,ld2_rawp_en,ld2_rawp_disabled; +wire ld3_rawp_reset,ld3_rawp_en,ld3_rawp_disabled; +wire [2:0] ld0_rawp_ackid,ld1_rawp_ackid ; +wire [2:0] ld2_rawp_ackid,ld3_rawp_ackid ; +wire ld0_pcx_rq_vld, ld1_pcx_rq_vld ; +wire ld2_pcx_rq_vld, ld3_pcx_rq_vld ; +wire [4:0] queue_write ; +wire mcycle_squash_d1 ; +//wire ld_pcx_rq_vld, st_pcx_rq_vld ; +wire [4:0] st0_q_wr,st1_q_wr,st2_q_wr,st3_q_wr ; +wire [4:0] sel_qentry0 ; +wire st0_atom_rq,st1_atom_rq,st2_atom_rq,st3_atom_rq ; +wire st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1 ; +wire st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1 ; +wire st0_atom_rq_d2,st1_atom_rq_d2,st2_atom_rq_d2,st3_atom_rq_d2 ; +wire st0_cas_vld_d2,st1_cas_vld_d2,st2_cas_vld_d2,st3_cas_vld_d2 ; +//wire st_cas_rq_d2,st_quad_rq_d2; +wire st_cas_rq_d2 ; +wire st0_pcx_rq_vld, st1_pcx_rq_vld; +wire st2_pcx_rq_vld, st3_pcx_rq_vld; +wire st_atom_rq ; +wire st_atom_rq_d1 ; +wire imiss_pcx_rq_vld ; +wire [4:0] spc_pcx_req_update_g,spc_pcx_req_update_w2 ; +wire strm_pcx_rq_vld ; +wire fwdpkt_rq_vld ; +wire intrpt_pcx_rq_vld ; +wire fpop_pcx_rq_vld ; +wire [4:0] pre_qwr ; +wire ld0_pcx_rq_sel, ld1_pcx_rq_sel ; +wire ld2_pcx_rq_sel, ld3_pcx_rq_sel ; +wire strm_pcx_rq_sel ; +wire intrpt_pcx_rq_sel ; +//wire imiss_strm_pcx_rq_sel ; +//wire [2:0] dest_pkt_sel ; +wire [4:0] spc_pcx_req_g ; +wire [1:0] strm_l2bnk_addr ; +wire [2:0] ld0_l2bnk_addr, ld1_l2bnk_addr ; +wire [2:0] ld2_l2bnk_addr, ld3_l2bnk_addr ; +wire [4:0] current_pkt_dest ; +wire [7:6] ldst_va_m, ldst_va_g ; +wire [4:0] ld_pkt_dest ; +wire [4:0] st_pkt_dest ; + + +wire [4:0] intrpt_l2bnk_dest ; +wire pcx_req_squash_d1, pcx_req_squash_d2 ; +wire intrpt_pcx_rq_sel_d1 ; +wire [2:0] intrpt_l2bnk_addr ; +//wire st0_stq_vld,st1_stq_vld,st2_stq_vld,st3_stq_vld ; +wire st0_pcx_rq_sel, st1_pcx_rq_sel; +wire st2_pcx_rq_sel, st3_pcx_rq_sel; +//wire ld0_sec_hit_g,ld1_sec_hit_g,ld2_sec_hit_g,ld3_sec_hit_g; +wire ld0_sec_hit_w2,ld1_sec_hit_w2,ld2_sec_hit_w2,ld3_sec_hit_w2; +//wire [3:0] dfq_byp_sel_m, dfq_byp_sel_g ; +//wire [3:0] dfq_byp_sel_m; +wire ld0_unfilled,ld1_unfilled,ld2_unfilled,ld3_unfilled; +wire ld0_unfilled_tmp,ld1_unfilled_tmp,ld2_unfilled_tmp,ld3_unfilled_tmp; +wire [1:0] ld0_unfilled_wy,ld1_unfilled_wy,ld2_unfilled_wy,ld3_unfilled_wy ; +wire ld0_l2cache_rq,ld1_l2cache_rq ; +wire ld2_l2cache_rq,ld3_l2cache_rq ; +wire ld0_pcx_rq_sel_d1, ld1_pcx_rq_sel_d1 ; +wire ld2_pcx_rq_sel_d1, ld3_pcx_rq_sel_d1 ; +wire intrpt_pkt_vld; +wire fwdpkt_pcx_rq_sel; +wire fwdpkt_pcx_rq_sel_d1,fwdpkt_pcx_rq_sel_d2,fwdpkt_pcx_rq_sel_d3 ; +wire reset,dbb_reset_l; +wire clk; +//wire st_inst_vld_unflushed; +wire ldst_dbl_g; +//wire lsu_ld_sec_hit_l2access_g ; +wire lsu_ld_sec_hit_l2access_w2 ; +//wire [1:0] lsu_ld_sec_hit_wy_g ; +wire [1:0] lsu_ld_sec_hit_wy_w2 ; +//wire [1:0] ld_way; +//wire [1:0] ld_pcx_pkt_wy_g ; + +wire [3:0] lsu_dtag_perror_w2 ; + +wire [3:0] lmq_enable_w2 ; +wire ld0_spec_pick_vld_g , + ld0_spec_pick_vld_w2 ; +wire ld1_spec_pick_vld_g , + ld1_spec_pick_vld_w2 ; +wire ld2_spec_pick_vld_g , + ld2_spec_pick_vld_w2 ; +wire ld3_spec_pick_vld_g , + ld3_spec_pick_vld_w2 ; +wire non_l2bnk_mx0_d1 ; +wire non_l2bnk_mx1_d1 ; +wire non_l2bnk_mx2_d1 ; +wire non_l2bnk_mx3_d1 ; +wire lsu_pcx_req_squash ; +wire spc_pcx_atom_pq_buf2 ; +wire [4:0] spc_pcx_req_pq_buf2 ; +wire lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1 ; +wire lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1 ; + +wire [3:0] ld_thrd_force_d1 ; +wire [3:0] st_thrd_force_d1 ; +wire [3:0] misc_thrd_force_d1 ; +wire [3:0] ld_thrd_force_vld ; +wire [3:0] st_thrd_force_vld ; +wire [3:0] misc_thrd_force_vld ; +wire [3:0] all_thrd_force_vld ; +wire [3:0] ld_thrd_pick_din ; +wire [3:0] st_thrd_pick_din ; +wire [3:0] misc_thrd_pick_din ; +wire [3:0] ld_thrd_pick_status_din ; +wire [3:0] st_thrd_pick_status_din ; +wire [3:0] misc_thrd_pick_status_din ; +wire [3:0] ld_thrd_pick_status ; +wire [3:0] st_thrd_pick_status ; +wire [3:0] misc_thrd_pick_status ; +wire ld_thrd_pick_rst ; +wire st_thrd_pick_rst ; +wire misc_thrd_pick_rst ; +wire all_thrd_pick_rst ; + + + + +assign clk = rclk; + + dffrl_async rstff(.din (grst_l), + .q (dbb_reset_l), + .clk (clk), .se(se), .si(), .so(), + .rst_l (arst_l)); + +assign reset = ~dbb_reset_l; + + +//assign lsu_ifu_flush_ireg = 1'b0 ; +//================================================================================================= +// TEMP !! rm from vlin.filter also !! +//================================================================================================= + +wire atm_in_stb_g ; +assign atm_in_stb_g = 1'b0 ; + +//================================================================================================= +// LOGIC MOVED FROM STB_RWCTL +//================================================================================================= + +// pcx is making request for data in current cycle. Can be multi-hot. +//assign pcx_any_rq_for_stb = |pcx_rq_for_stb[3:0] ; +//assign pcx_any_rq_for_stb = +// (pcx_rq_for_stb[0] & ~lsu_st_pcx_rq_kill_w2[0]) | +// (pcx_rq_for_stb[1] & ~lsu_st_pcx_rq_kill_w2[1]) | +// (pcx_rq_for_stb[2] & ~lsu_st_pcx_rq_kill_w2[2]) | +// (pcx_rq_for_stb[3] & ~lsu_st_pcx_rq_kill_w2[3]) ; +// +//dff #(1) prvld_stgd1 ( +// .din (pcx_any_rq_for_stb), +// .q (lsu_stb_pcx_rvld_d1), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +// replacement for above logic - pcx_rq_for_stb is already qual'ed w/ lsu_st_pcx_rq_kill_w2 +// this signal is used in qdp1 and qdp2 as pcx paket valids. +assign lsu_stb_pcx_rvld_d1 = st3_pcx_rq_sel_d1 | + st2_pcx_rq_sel_d1 | + st1_pcx_rq_sel_d1 | + st0_pcx_rq_sel_d1 ; + + +//assign stb_rd_tid[0] = pcx_rq_for_stb[1] | pcx_rq_for_stb[3] ; +//assign stb_rd_tid[1] = pcx_rq_for_stb[2] | pcx_rq_for_stb[3] ; +// +//dff #(2) stbtid_stgd1 ( +// .din (stb_rd_tid[1:0]), .q (lsu_stb_rd_tid[1:0]), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +assign lsu_stb_rd_tid[0] = st1_pcx_rq_sel_d1 | st3_pcx_rq_sel_d1; +assign lsu_stb_rd_tid[1] = st2_pcx_rq_sel_d1 | st3_pcx_rq_sel_d1; + +//================================================================================================= + +assign lsu_ramtest_rd_w = lsu_dcache_iob_rd_w | ifu_lsu_fwd_data_vld ; + +//================================================================================================= +// LD PCX PKT WAY +//================================================================================================= + + +// For direct-map mode, assume that addition set-index bits 12:11 are +// used to file line in set. +// timing fix: 5/19/03: move secondary hit way generation to w2 +//assign ld_way[1:0] = +// lsu_way_hit_or ? lsu_encd_way_hit[1:0]: +// lsu_ld_sec_hit_l2access_g ? lsu_ld_sec_hit_wy_g[1:0] : +// (dc_direct_map ? lsu_ldst_va_way_g[1:0] : lsu_dcache_rand[1:0]) ; +// +//assign lsu_lmq_pkt_way_g[1:0] = +//(ldst_dbl_g & st_inst_vld_unflushed & lsu_quad_asi_g) ? 2'b01 : +// casa_g ? 2'b00 : ld_way[1:0] ; +// +//assign ld_pcx_pkt_wy_g[1:0] = lsu_lmq_pkt_way_g[1:0]; +wire [1:0] ld_way_mx1_g , ld_way_mx2_g , ld_way_mx2_w2; + +assign ld_way_mx1_g[1:0] = + lsu_way_hit_or ? lsu_encd_way_hit[1:0]: + (dc_direct_map ? lsu_ldst_va_way_g[1:0] : lsu_dcache_rand[1:0]) ; + +assign ld_way_mx2_g[1:0] = +//(ldst_dbl_g & st_inst_vld_unflushed & lsu_quad_asi_g) ? 2'b01 : //quad st, obsolete + casa_g ? 2'b00 : ld_way_mx1_g[1:0] ; + +dff #(2) ff_ld_way_mx2_w2 ( + .din (ld_way_mx2_g[1:0]), + .q (ld_way_mx2_w2[1:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire [1:0] lsu_lmq_pkt_way_w2; +assign lsu_lmq_pkt_way_w2[1:0] = lsu_ld_sec_hit_l2access_w2 ? lsu_ld_sec_hit_wy_w2[1:0] : + ld_way_mx2_w2[1:0]; + +//bug2705 - add mx for way in w2-cycle +wire [1:0] lmq0_pcx_pkt_way_tmp, lmq1_pcx_pkt_way_tmp, lmq2_pcx_pkt_way_tmp, lmq3_pcx_pkt_way_tmp ; + +assign lmq0_pcx_pkt_way[1:0] = ld0_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq0_pcx_pkt_way_tmp[1:0] ; +assign lmq1_pcx_pkt_way[1:0] = ld1_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq1_pcx_pkt_way_tmp[1:0] ; +assign lmq2_pcx_pkt_way[1:0] = ld2_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq2_pcx_pkt_way_tmp[1:0] ; +assign lmq3_pcx_pkt_way[1:0] = ld3_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq3_pcx_pkt_way_tmp[1:0] ; + +wire qword_access0,qword_access1,qword_access2,qword_access3; + +// Extend by 1-b to add support for 3rd size bit for iospace. +// move the flops from qdp1 to qctl1 +dffe #(2) ff_lmq0_pcx_pkt_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (lmq0_pcx_pkt_way_tmp[1:0]), + .en (lmq_enable_w2[0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe #(2) ff_lmq1_pcx_pkt_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (lmq1_pcx_pkt_way_tmp[1:0]), + .en (lmq_enable_w2[1]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe #(2) ff_lmq2_pcx_pkt_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (lmq2_pcx_pkt_way_tmp[1:0]), + .en (lmq_enable_w2[2]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe #(2) ff_lmq3_pcx_pkt_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (lmq3_pcx_pkt_way_tmp[1:0]), + .en (lmq_enable_w2[3]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Q Word Access to IO +dffe ff_lmq0_qw ( + .din (lsu_quad_word_access_g), + .q (qword_access0), + .en (lmq_enable[0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe ff_lmq1_qw ( + .din (lsu_quad_word_access_g), + .q (qword_access1), + .en (lmq_enable[1]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe ff_lmq2_qw( + .din (lsu_quad_word_access_g), + .q (qword_access2), + .en (lmq_enable[2]), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffe ff_lmq3_qw ( + .din (lsu_quad_word_access_g), + .q (qword_access3), + .en (lmq_enable[3]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_pcx_rq_sz_b3 = + (ld0_pcx_rq_sel_d1 & qword_access0) | + (ld1_pcx_rq_sel_d1 & qword_access1) | + (ld2_pcx_rq_sel_d1 & qword_access2) | + (ld3_pcx_rq_sel_d1 & qword_access3) ; + +//================================================================================================= +// SHADOW SCAN +//================================================================================================= + + +// Monitors outstanding loads. This would hang a thread. +assign lsu_sscan_data[3:0] = + {ld0_pcx_rq_vld, ld1_pcx_rq_vld , ld2_pcx_rq_vld , ld3_pcx_rq_vld} ; +// Monitors outstanding loads. This would hang issue from stb +assign lsu_sscan_data[7:4] = + {st0_pcx_rq_vld, st1_pcx_rq_vld, st2_pcx_rq_vld, st3_pcx_rq_vld} ; +assign lsu_sscan_data[8] = imiss_pcx_rq_vld ; // imiss +assign lsu_sscan_data[9] = strm_pcx_rq_vld ; // strm +assign lsu_sscan_data[10] = fwdpkt_rq_vld ; // fwd rply/rq +assign lsu_sscan_data[11] = intrpt_pcx_rq_vld ; // intrpt +assign lsu_sscan_data[12] = fpop_pcx_rq_vld ; // fpop + + +//================================================================================================= +// QDP1 selects +//================================================================================================= + +wire [3:0] dfq_byp_tid_sel; + +assign dfq_byp_tid_sel[0] = (lsu_dfq_byp_tid[1:0]==2'b00); +assign dfq_byp_tid_sel[1] = (lsu_dfq_byp_tid[1:0]==2'b01); +assign dfq_byp_tid_sel[2] = (lsu_dfq_byp_tid[1:0]==2'b10); +assign dfq_byp_tid_sel[3] = (lsu_dfq_byp_tid[1:0]==2'b11); +//assign dfq_byp_tid__sel[3] = ~|(lsu_dfq_byp_d1_sel[2:0]); + +wire [3:0] lsu_dfq_byp_tid_d1_sel_tmp ; + +dffe #(4) dfq_byp_tid_sel_ff ( + .din (dfq_byp_tid_sel[3:0]), + .q (lsu_dfq_byp_tid_d1_sel_tmp[3:0]), + .en (dfq_byp_ff_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//11/21/03 - add rst_tri_en to lsu_dfq_byp_tid_d1_sel[3:0] going to qdp1 as dfq_byp_sel[3:0] + +assign lsu_dfq_byp_tid_d1_sel[2:0] = lsu_dfq_byp_tid_d1_sel_tmp[2:0] & {3{~rst_tri_en}}; +assign lsu_dfq_byp_tid_d1_sel[3] = lsu_dfq_byp_tid_d1_sel_tmp[3] | rst_tri_en; + + +//================================================================================================= +// INST_VLD_W GENERATION +//================================================================================================= + + +wire [1:0] thrid_m, thrid_g ; +dff #(2) stgm_thrid ( + .din (ifu_tlu_thrid_e[1:0]), + .q (thrid_m[1:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(2) stgg_thrid ( + .din (thrid_m[1:0]), + .q (thrid_g[1:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire flush_w_inst_vld_m ; +wire lsu_inst_vld_w,lsu_inst_vld_tmp ; +wire other_flush_pipe_w ; +wire qctl1_flush_pipe_w; + +assign flush_w_inst_vld_m = + ifu_tlu_inst_vld_m & + ~(qctl1_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w + +dff stgw_ivld ( + .din (flush_w_inst_vld_m), + .q (lsu_inst_vld_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +assign other_flush_pipe_w = tlu_early_flush_pipe2_w | (lsu_ttype_vld_m2 & lsu_inst_vld_tmp); +assign qctl1_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ; + +assign lsu_inst_vld_w = lsu_inst_vld_tmp & ~qctl1_flush_pipe_w ; + + +//================================================================================================= +// SECONDARY VS. PRIMARY LOADS +//================================================================================================= + +// An incoming load can hit can match addresses with an outstanding load request +// from another thread. In this case, the secondary load must wait until the primary +// load returns and then it will bypass (but not fill). There can only be one primary +// load but multiple secondary loads. The secondary loads will not enter the dfq. +// The primary load will however be recirculated until all secondary loads have bypassed. + +// Could have multiple secondary hits. Only one thread can be chosen +// as primary though. + +//An incoming load can match addresses with any outstanding load request from other threads. +//can be multiple hits +// timing fix: 5/19/03: move secondary hit way generation to w2 +// +//assign ld0_sec_hit_g = ld_sec_hit_thrd0 & ld0_unfilled ; +//assign ld1_sec_hit_g = ld_sec_hit_thrd1 & ld1_unfilled ; +//assign ld2_sec_hit_g = ld_sec_hit_thrd2 & ld2_unfilled ; +//assign ld3_sec_hit_g = ld_sec_hit_thrd3 & ld3_unfilled ; +// +// +// Fix for Bug1606 +//assign lsu_ld_sec_hit_l2access_g = +// ld0_sec_hit_g | ld1_sec_hit_g | ld2_sec_hit_g | ld3_sec_hit_g ; +// +//phase 2 +//since can be multiple hits, it isn't one-hot mux, but fix priority-sel mux +//assign lsu_ld_sec_hit_wy_g[1:0] = +// ld0_sec_hit_g ? ld0_unfilled_wy[1:0] : +// ld1_sec_hit_g ? ld1_unfilled_wy[1:0] : +// ld2_sec_hit_g ? ld2_unfilled_wy[1:0] : +// ld3_sec_hit_g ? ld3_unfilled_wy[1:0] : 2'bxx ; + +wire ld_sec_hit_thrd0_w2,ld_sec_hit_thrd1_w2,ld_sec_hit_thrd2_w2,ld_sec_hit_thrd3_w2; + +dff #(4) ff_ld_sec_hit_thrd0to3_d1 ( + .din ({ld_sec_hit_thrd0,ld_sec_hit_thrd1,ld_sec_hit_thrd2,ld_sec_hit_thrd3}), + .q ({ld_sec_hit_thrd0_w2,ld_sec_hit_thrd1_w2,ld_sec_hit_thrd2_w2,ld_sec_hit_thrd3_w2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign ld0_sec_hit_w2 = ld_sec_hit_thrd0_w2 & ld0_unfilled ; +assign ld1_sec_hit_w2 = ld_sec_hit_thrd1_w2 & ld1_unfilled ; +assign ld2_sec_hit_w2 = ld_sec_hit_thrd2_w2 & ld2_unfilled ; +assign ld3_sec_hit_w2 = ld_sec_hit_thrd3_w2 & ld3_unfilled ; + +// Fix for Bug1606 +assign lsu_ld_sec_hit_l2access_w2 = + ld0_sec_hit_w2 | ld1_sec_hit_w2 | ld2_sec_hit_w2 | ld3_sec_hit_w2 ; + +//phase 2 +//since can be multiple hits, it isn't one-hot mux, but fix priority-sel mux +assign lsu_ld_sec_hit_wy_w2[1:0] = + ld0_sec_hit_w2 ? ld0_unfilled_wy[1:0] : + ld1_sec_hit_w2 ? ld1_unfilled_wy[1:0] : + ld2_sec_hit_w2 ? ld2_unfilled_wy[1:0] : + ld3_sec_hit_w2 ? ld3_unfilled_wy[1:0] : 2'bxx ; + +//dff #(4) stgm_dbypsel ( +// .din (dfq_byp_sel[3:0]), +// .q (dfq_byp_sel_m[3:0]), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +//dff #(4) stgg_dbypsel ( +// .din (dfq_byp_sel_m[3:0]), +// .q (dfq_byp_sel_g[3:0]), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +// select g-stage lmq source. +// Selects for lmq contents shared by fill/hit and alternate sources such as ldxa/raw. +// Is qualification of dfq_byp_sel_g by ld_thrd_byp_sel necessary ??? + +wire [3:0] lmq_byp_misc_sel_e ; + +assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw. + dfq_byp_sel[0] ; // select for dfq. +assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw. + dfq_byp_sel[1] ; // select for dfq. +assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw. + dfq_byp_sel[2] ; // select for dfq. +assign lmq_byp_misc_sel_e[3] = ~|lmq_byp_misc_sel_e[2:0]; + //ld_thrd_byp_sel_e[3] | // select for ldxa/raw. + //dfq_byp_sel[3] ; // select for dfq. + +/* +assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw. + (dfq_byp_sel[0] & ~ld_thrd_byp_sel_e[0]) ; // select for dfq. +assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw. + (dfq_byp_sel[1] & ~ld_thrd_byp_sel_e[1]) ; // select for dfq. +assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw. + (dfq_byp_sel[2] & ~ld_thrd_byp_sel_e[2]) ; // select for dfq. +assign lmq_byp_misc_sel_e[3] = ld_thrd_byp_sel_e[3] | // select for ldxa/raw. + (dfq_byp_sel[3] & ~ld_thrd_byp_sel_e[3]) ; // select for dfq. +*/ + +// M-Stage +//10/27/03 - add rst_tri_en for the select - lsu_lmq_byp_misc_sel to qdp1 +wire [3:0] lsu_lmq_byp_misc_sel_tmp ; +dff #(4) stgg_lbsel ( + .din (lmq_byp_misc_sel_e[3:0]), + .q (lsu_lmq_byp_misc_sel_tmp[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_lmq_byp_misc_sel[2:0]= lsu_lmq_byp_misc_sel_tmp[2:0] & {3{~rst_tri_en}} ; +assign lsu_lmq_byp_misc_sel[3] = lsu_lmq_byp_misc_sel_tmp[3] | rst_tri_en ; + + +/* +assign lsu_lmq_byp_misc_sel[0] = ld_thrd_byp_sel[0] | // select for ldxa/raw. + (dfq_byp_sel_g[0] & ~ld_thrd_byp_sel[0]) ; // select for dfq. +assign lsu_lmq_byp_misc_sel[1] = ld_thrd_byp_sel[1] | // select for ldxa/raw. + (dfq_byp_sel_g[1] & ~ld_thrd_byp_sel[1]) ; // select for dfq. +assign lsu_lmq_byp_misc_sel[2] = ld_thrd_byp_sel[2] | // select for ldxa/raw. + (dfq_byp_sel_g[2] & ~ld_thrd_byp_sel[2]) ; // select for dfq. +assign lsu_lmq_byp_misc_sel[3] = ld_thrd_byp_sel[3] | // select for ldxa/raw. + (dfq_byp_sel_g[3] & ~ld_thrd_byp_sel[3]) ; // select for dfq. +*/ + + + +//================================================================================================= +// Miscellaneous Staging +//================================================================================================= + + +assign thread0_e = ~ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0] ; +assign thread1_e = ~ifu_tlu_thrid_e[1] & ifu_tlu_thrid_e[0] ; +assign thread2_e = ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0] ; +assign thread3_e = ifu_tlu_thrid_e[1] & ifu_tlu_thrid_e[0] ; + +assign ld0_inst_vld_e = ld_inst_vld_e & thread0_e ; +assign ld1_inst_vld_e = ld_inst_vld_e & thread1_e ; +assign ld2_inst_vld_e = ld_inst_vld_e & thread2_e ; +assign ld3_inst_vld_e = ld_inst_vld_e & thread3_e ; + +assign ldst_va_m[7:6] = lsu_ldst_va_m[7:6]; + +dff #(6) stgm_ad_m ( + .din ({ld0_inst_vld_e,ld1_inst_vld_e, + ld2_inst_vld_e,ld3_inst_vld_e,ifu_lsu_ldst_fp_e, + ifu_lsu_ldst_dbl_e}), + .q ({ld0_inst_vld_m,ld1_inst_vld_m, + ld2_inst_vld_m,ld3_inst_vld_m,ldst_fp_m, + ldst_dbl_m}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +dff #(8) stgm_ad_g ( + .din ({ldst_va_m[7:6],ld0_inst_vld_m,ld1_inst_vld_m, + //.din ({ldst_va_m[8:6],ld0_inst_vld_m,ld1_inst_vld_m, + ld2_inst_vld_m,ld3_inst_vld_m,ldst_fp_m, + //ld2_inst_vld_m,ld3_inst_vld_m,st_inst_vld_m,ldst_fp_m, + ldst_dbl_m}), + .q ({ldst_va_g[7:6],ld0_inst_vld_unflushed,ld1_inst_vld_unflushed, + //.q ({ldst_va_g[8:6],ld0_inst_vld_unflushed,ld1_inst_vld_unflushed, + ld2_inst_vld_unflushed,ld3_inst_vld_unflushed, + //ld2_inst_vld_unflushed,ld3_inst_vld_unflushed,st_inst_vld_unflushed, + ldst_fp_g,ldst_dbl_g}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign ld0_inst_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_w ; +assign ld1_inst_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_w ; +assign ld2_inst_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_w ; +assign ld3_inst_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_w ; +//assign st_inst_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w ; + +dff #(4) ivld_stgw2 ( + .din ({ld0_inst_vld_g,ld1_inst_vld_g,ld2_inst_vld_g,ld3_inst_vld_g}), + .q ({ld0_inst_vld_w2,ld1_inst_vld_w2,ld2_inst_vld_w2,ld3_inst_vld_w2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) th_stgm ( + .din ({thread0_e,thread1_e,thread2_e,thread3_e}), + .q ({thread0_m,thread1_m,thread2_m,thread3_m}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) th_stgg ( + .din ({thread0_m,thread1_m,thread2_m,thread3_m}), + .q ({thread0_g,thread1_g,thread2_g,thread3_g}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) th_stgw2 ( + .din ({thread0_g,thread1_g,thread2_g,thread3_g}), + .q ({thread0_w2,thread1_w2,thread2_w2,thread3_w2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + + +//================================================================================================= +// +// IMISS PCX PKT REQ CTL +// +//================================================================================================= + + +// ** ifu request packet should be sent out in e-stage ** +// ** Prefer not to make dfq dual-ported ** + +// Format of IFU pcx packet (50b) : +// b49 - valid +// b48:44 - req type +// b43:42 - rep way (for "eviction" - maintains directory consistency ) +// b41:40 - mil id +// b39:0 - imiss address +// * +// destid : +// b2 - b39 of pa +// b1 - b8 of pa +// b0 - b7 of pa +// pcxpkt : +// b51 - valid +// b50 - reserved +// b49 - NC +// b48:44 - req type +// b43:42 - rep way (for "eviction" - maintains directory consistency ) +// b41:40 - mil id +// b39:0 - imiss address + +// IMISS REQUEST CONTROL +// Vld is reset if imiss pkt requests and request is not subsequently +// squashed and new imiss pkt unavailable. + +// Request rate is 1/3 cycles. + +/*dff iack_stg ( + .din (imiss_pcx_rq_sel), + .q (lsu_ifu_pcxpkt_ack_d), + .clk (clk), + .se (1'b0), .si (), .so () + ); */ + +assign lsu_ifu_pcxpkt_ack_d = imiss_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + +assign imiss_pkt_vld = ifu_lsu_pcxreq_d & ~(imiss_pcx_rq_sel_d1 | imiss_pcx_rq_sel_d2) ; + +//timing fix: 5/21/03 - ifu sends destid 1 cycle early +//assign imiss_l2bnk_addr[2:0] = ifu_lsu_destid_d[2:0] ; + +wire ifu_destid_en ; +assign ifu_destid_en = ~ifu_lsu_pcxreq_d | (lsu_ifu_pcxpkt_ack_d & ~ifu_lsu_pcxpkt_e_b50); + +wire [2:0] ifu_destid_d; +dffe #(3) ff_ifu_destid_d ( + .din (ifu_lsu_destid_s[2:0]), + .q (ifu_destid_d[2:0]), + .en (ifu_destid_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); +assign imiss_l2bnk_addr[2:0] = ifu_destid_d[2:0] ; + +assign imiss_l2bnk_dest[0] = +~imiss_l2bnk_addr[2] & ~imiss_l2bnk_addr[1] & ~imiss_l2bnk_addr[0] ; +assign imiss_l2bnk_dest[1] = +~imiss_l2bnk_addr[2] & ~imiss_l2bnk_addr[1] & imiss_l2bnk_addr[0] ; +assign imiss_l2bnk_dest[2] = +~imiss_l2bnk_addr[2] & imiss_l2bnk_addr[1] & ~imiss_l2bnk_addr[0] ; +assign imiss_l2bnk_dest[3] = +~imiss_l2bnk_addr[2] & imiss_l2bnk_addr[1] & imiss_l2bnk_addr[0] ; +assign imiss_l2bnk_dest[4] = imiss_l2bnk_addr[2] ; + + +//================================================================================================= +// FPOP PCX RQ CTL +//================================================================================================= + + +assign fpst_vld_m = ffu_lsu_data[80] & ffu_lsu_data[79] ; + +dff fpst_stg ( + .din (fpst_vld_m), + .q (fpst_vld_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// ffu req is never speculative as it must always begin with the queue empty +assign lsu_ffu_ack = + fpop_pcx_rq_sel_d1 | // fpop needs to wait until selected;d1 for timing + //fpop_pcx_rq_sel | // fpop needs to wait until selected + fpst_vld_g ; // fpst responds immediately. + +// req_squash needs to match up with rq_sel_d1 !!! +// keep vld around for two cycles. +assign fpop_vld_reset = + (reset | fpop_pcx_rq_sel) ; + //(reset | fpop_pcx_rq_sel_d1) ; + +assign fpop_vld_en = ffu_lsu_fpop_rq_vld ; + +// fpop valid +dffre #(1) fpop_vld ( + .din (ffu_lsu_fpop_rq_vld), + .q (fpop_pkt_vld_unmasked), + .rst (fpop_vld_reset), .en (fpop_vld_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// ** fpop_pkt1 should not be required. +assign fpop_pkt1 = fpop_pkt_vld_unmasked & ~fpop_pcx_rq_sel_d1 ; + +assign fpop_pkt_vld = fpop_pkt_vld_unmasked ; // & ~ffu_lsu_kill_fpop_rq ; + +assign fpop_atom_req = fpop_pkt1 & fpop_pcx_rq_sel ; + +dff fpatm_stg ( + .din (fpop_atom_req), + .q (fpop_atom_rq_pq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign fpop_l2bnk_dest[4:0] = 5'b10000 ; + + + +//================================================================================================= +// SPU PCX PKT REQ CONTROL +//================================================================================================= + +// If ack is sent in a given cycle, then the earliest the spu can send +// a response is in the same cycle. + +wire strm_pcx_rq_sel_d2 ; +assign lsu_spu_ldst_ack = + strm_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; // spu request sent to pcx. + //strm_pcx_rq_sel_d1 & ~pcx_req_squash ; // spu request sent to pcx. + +dff #(1) rqsel_d2 ( + .din (strm_pcx_rq_sel_d1), + .q (strm_pcx_rq_sel_d2), + .clk (clk), + .se (1'b0), .si (), .so () +); + +wire spu_ack_d1 ; +dff #(1) spuack_d1 ( + .din (lsu_spu_ldst_ack), + .q (spu_ack_d1), + .clk (clk), + .se (1'b0), .si (), .so () +); + +dff #(2) ff_spu_lsu_ldst_pckt_d1 ( + .din (spu_lsu_ldst_pckt[`PCX_AD_LO+7:`PCX_AD_LO+6]), + .q (strm_l2bnk_addr[1:0]), + .clk (clk), + .se (1'b0), .si (), .so () +); + +// Streaming does not access io space. +assign strm_l2bnk_dest[0] = +~strm_l2bnk_addr[1] & ~strm_l2bnk_addr[0] ; +assign strm_l2bnk_dest[1] = +~strm_l2bnk_addr[1] & strm_l2bnk_addr[0] ; +assign strm_l2bnk_dest[2] = +strm_l2bnk_addr[1] & ~strm_l2bnk_addr[0] ; +assign strm_l2bnk_dest[3] = +strm_l2bnk_addr[1] & strm_l2bnk_addr[0] ; +assign strm_l2bnk_dest[4] = 1'b0 ; + +wire strm_pkt_vld_unmasked ; + +dff #(1) spu_pkt_vld_d1 ( + .din (spu_lsu_ldst_pckt_vld), + .q (strm_pkt_vld_unmasked), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign strm_pkt_vld = + strm_pkt_vld_unmasked & ~(strm_pcx_rq_sel_d1 | lsu_spu_ldst_ack | spu_ack_d1); + +// temp = remove strming interface +//assign strm_sldst_cam_vld = 1'b0 ; +//assign strm_sld_dc_rd_vld = 1'b0 ; +//assign strm_sldst_cam_d2 = 1'b0 ; +// temp = remove strming interface + + +//================================================================================================= +// STORE PCX PKT REQ CONTROL +//================================================================================================= + +// Stage by a cycle. + +// Thread0 +wire [2:1] stb0_rqtype ; +wire [2:0] stb0_rqaddr ; +dff #(5) stgd1_s0rq ( + .din ({stb0_atm_rq_type[2:1], stb0_l2b_addr[2:0]}), + .q ({stb0_rqtype[2:1],stb0_rqaddr[2:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread1 +wire [2:1] stb1_rqtype ; +wire [2:0] stb1_rqaddr ; +dff #(5) stgd1_s1rq ( + .din ({stb1_atm_rq_type[2:1], stb1_l2b_addr[2:0]}), + .q ({stb1_rqtype[2:1],stb1_rqaddr[2:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread2 +wire [2:1] stb2_rqtype ; +wire [2:0] stb2_rqaddr ; +dff #(5) stgd1_s2rq ( + .din ({stb2_atm_rq_type[2:1], stb2_l2b_addr[2:0]}), + .q ({stb2_rqtype[2:1],stb2_rqaddr[2:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread3 +wire [2:1] stb3_rqtype ; +wire [2:0] stb3_rqaddr ; +dff #(5) stgd1_s3rq ( + .din ({stb3_atm_rq_type[2:1], stb3_l2b_addr[2:0]}), + .q ({stb3_rqtype[2:1],stb3_rqaddr[2:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire stb0_rd_for_pcx,stb1_rd_for_pcx,stb2_rd_for_pcx,stb3_rd_for_pcx ; +wire stb0_rd_for_pcx_tmp,stb1_rd_for_pcx_tmp,stb2_rd_for_pcx_tmp,stb3_rd_for_pcx_tmp ; +dff #(4) stgd1_rdpcx ( + .din (stb_rd_for_pcx[3:0]), + .q ({stb3_rd_for_pcx_tmp,stb2_rd_for_pcx_tmp,stb1_rd_for_pcx_tmp,stb0_rd_for_pcx_tmp}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// timing fix: 5/6 - move kill qual after store pick +//assign stb0_rd_for_pcx = stb0_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[0] ; +//assign stb1_rd_for_pcx = stb1_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[1] ; +//assign stb2_rd_for_pcx = stb2_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[2] ; +//assign stb3_rd_for_pcx = stb3_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[3] ; + +assign stb0_rd_for_pcx = stb0_rd_for_pcx_tmp; +assign stb1_rd_for_pcx = stb1_rd_for_pcx_tmp; +assign stb2_rd_for_pcx = stb2_rd_for_pcx_tmp; +assign stb3_rd_for_pcx = stb3_rd_for_pcx_tmp; + +// STORE REQUEST CONTROL +// ** Data must come from bypass mux output. +// THREAD0 + +// Reads for stores will have to be made non-speculative ???? +// or delay when ced bit is set such that there is no need +// to replay store. +// The size of atm_rq_type can be reduced in stb_ctl etc !!! +assign st0_pkt_vld = stb0_rd_for_pcx & ~st0_pcx_rq_sel_d1 ; +assign st0_cas_vld = ~stb0_rqtype[2] & stb0_rqtype[1] ; +// stquad not supported. +//assign st0_stq_vld = 1'b0 ; +assign st0_atomic_vld = st0_cas_vld ; + //st0_stq_vld | // stq(1) + //(~stb0_rqtype[2] & stb0_rqtype[1] & ~stb0_rqtype[0]) ; // cas(1) + +assign st1_pkt_vld = stb1_rd_for_pcx & ~st1_pcx_rq_sel_d1 ; +assign st1_cas_vld = ~stb1_rqtype[2] & stb1_rqtype[1] ; +//assign st1_stq_vld = 1'b0 ; +assign st1_atomic_vld = st1_cas_vld ; + +assign st2_pkt_vld = stb2_rd_for_pcx & ~st2_pcx_rq_sel_d1 ; +assign st2_cas_vld = ~stb2_rqtype[2] & stb2_rqtype[1] ; +//assign st2_stq_vld = 1'b0 ; +assign st2_atomic_vld = st2_cas_vld ; + +assign st3_pkt_vld = stb3_rd_for_pcx & ~st3_pcx_rq_sel_d1 ; +assign st3_cas_vld = ~stb3_rqtype[2] & stb3_rqtype[1] ; +//assign st3_stq_vld = 1'b0 ; +assign st3_atomic_vld = st3_cas_vld ; + +// Can this be based on st0_pcx_rq_vld instead to ease critical path. + +//assign pcx_rq_for_stb[0] = st_pcx_rq_mhot_sel[0] ; +//assign pcx_rq_for_stb[1] = st_pcx_rq_mhot_sel[1] ; +//assign pcx_rq_for_stb[2] = st_pcx_rq_mhot_sel[2] ; +//assign pcx_rq_for_stb[3] = st_pcx_rq_mhot_sel[3] ; + + +assign st0_l2bnk_dest[0] = +~stb0_rqaddr[2] & ~stb0_rqaddr[1] & ~stb0_rqaddr[0] ; +assign st0_l2bnk_dest[1] = +~stb0_rqaddr[2] & ~stb0_rqaddr[1] & stb0_rqaddr[0] ; +assign st0_l2bnk_dest[2] = +~stb0_rqaddr[2] & stb0_rqaddr[1] & ~stb0_rqaddr[0] ; +assign st0_l2bnk_dest[3] = +~stb0_rqaddr[2] & stb0_rqaddr[1] & stb0_rqaddr[0] ; +assign st0_l2bnk_dest[4] = stb0_rqaddr[2] ; + +assign st1_l2bnk_dest[0] = +~stb1_rqaddr[2] & ~stb1_rqaddr[1] & ~stb1_rqaddr[0] ; +assign st1_l2bnk_dest[1] = +~stb1_rqaddr[2] & ~stb1_rqaddr[1] & stb1_rqaddr[0] ; +assign st1_l2bnk_dest[2] = +~stb1_rqaddr[2] & stb1_rqaddr[1] & ~stb1_rqaddr[0] ; +assign st1_l2bnk_dest[3] = +~stb1_rqaddr[2] & stb1_rqaddr[1] & stb1_rqaddr[0] ; +assign st1_l2bnk_dest[4] = stb1_rqaddr[2] ; + +assign st2_l2bnk_dest[0] = +~stb2_rqaddr[2] & ~stb2_rqaddr[1] & ~stb2_rqaddr[0] ; +assign st2_l2bnk_dest[1] = +~stb2_rqaddr[2] & ~stb2_rqaddr[1] & stb2_rqaddr[0] ; +assign st2_l2bnk_dest[2] = +~stb2_rqaddr[2] & stb2_rqaddr[1] & ~stb2_rqaddr[0] ; +assign st2_l2bnk_dest[3] = +~stb2_rqaddr[2] & stb2_rqaddr[1] & stb2_rqaddr[0] ; +assign st2_l2bnk_dest[4] = stb2_rqaddr[2] ; + +assign st3_l2bnk_dest[0] = +~stb3_rqaddr[2] & ~stb3_rqaddr[1] & ~stb3_rqaddr[0] ; +assign st3_l2bnk_dest[1] = +~stb3_rqaddr[2] & ~stb3_rqaddr[1] & stb3_rqaddr[0] ; +assign st3_l2bnk_dest[2] = +~stb3_rqaddr[2] & stb3_rqaddr[1] & ~stb3_rqaddr[0] ; +assign st3_l2bnk_dest[3] = +~stb3_rqaddr[2] & stb3_rqaddr[1] & stb3_rqaddr[0] ; +assign st3_l2bnk_dest[4] = stb3_rqaddr[2] ; + +//================================================================================================= +// BLK-LOAD TRACKING +//================================================================================================= + +// The 64B load request is divided into 4 16B requests, i.e., 4 pcx pkts. +// The last bld request to the pcx must be marked as so. +// Only one bld can be processed at any time. + + wire [1:0] bld_thrd_din; + wire [1:0] bld_thrd_dout; + wire [3:0] bld_dcd_thrd; + wire ld_03_inst_vld_g; + wire bld_pcx_rq_sel_d1; + +dff stgg_blkasi ( + .din (lsu_blk_asi_m), + .q (blk_asi_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign bld_helper_cmplt_e = lsu_fldd_vld_en & bld_dout & ( + bld_dcd_thrd[0] & lsu_dfill_dcd_thrd[0] | + bld_dcd_thrd[1] & lsu_dfill_dcd_thrd[1] | + bld_dcd_thrd[2] & lsu_dfill_dcd_thrd[2] | + bld_dcd_thrd[3] & lsu_dfill_dcd_thrd[3] ); + + +dff #(1) stgm_bldhlpr ( + .din (bld_helper_cmplt_e), + .q (bld_helper_cmplt_m), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_bld_helper_cmplt_m = bld_helper_cmplt_m ; + +dff #(1) stgg_bldhlpr ( + .din (bld_helper_cmplt_m), + .q (bld_helper_cmplt_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire alt_space_m, alt_space_g, alt_space_w2 ; +dff stg_aspacem( + .din (ifu_lsu_alt_space_e), + .q (alt_space_m), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff stg_aspaceg( + .din (alt_space_m), + .q (alt_space_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff stg_aspacew2 ( + .din (alt_space_g), + .q (alt_space_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +// PCX bld helper issue : +// 00-1st->01-2nd->10-3rd->11-4th->00 + + assign bld_thrd_din[0] = ld1_inst_vld_unflushed | ld3_inst_vld_unflushed; + assign bld_thrd_din[1] = ld2_inst_vld_unflushed | ld3_inst_vld_unflushed; + + + assign ld_03_inst_vld_g = lsu_inst_vld_w & ( + ld0_inst_vld_unflushed | ld1_inst_vld_unflushed | + ld2_inst_vld_unflushed | ld3_inst_vld_unflushed ); + + assign bld_g = blk_asi_g & ldst_fp_g & ldst_dbl_g & alt_space_g & ld_03_inst_vld_g ; + //~lsu_tlb_perr_ld_rq_kill_w ; // Bug 4645 + +wire bld_w2 ; +dff #(1) bldstg ( + .din (bld_g), + .q (bld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire perr_ld_rq_kill_w2 ; +wire bld_perr_kill_w2 ; +assign bld_perr_kill_w2 = bld_w2 & perr_ld_rq_kill_w2 ; + +dffre #(2) bld_thrd ( + .din (bld_thrd_din[1:0] ), + .q (bld_thrd_dout[1:0]), + .rst (bld_reset), .en (bld_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + assign bld_dcd_thrd[0] = ~bld_thrd_dout[1] & ~bld_thrd_dout[0]; + assign bld_dcd_thrd[1] = ~bld_thrd_dout[1] & bld_thrd_dout[0]; + assign bld_dcd_thrd[2] = bld_thrd_dout[1] & ~bld_thrd_dout[0]; + assign bld_dcd_thrd[3] = bld_thrd_dout[1] & bld_thrd_dout[0]; + +//bug 2757 + assign bld_pcx_rq_sel_d1 = ld0_pcx_rq_sel_d1 & bld_dcd_thrd[0] | + ld1_pcx_rq_sel_d1 & bld_dcd_thrd[1] | + ld2_pcx_rq_sel_d1 & bld_dcd_thrd[2] | + ld3_pcx_rq_sel_d1 & bld_dcd_thrd[3]; + + //wire bld_pcx_rq_sel_d2, bld_pcx_rq_sel; + wire bld_pcx_rq_sel; + //bug 3322 +// assign bld_pcx_rq_sel = bld_pcx_rq_sel_d2 & ~pcx_req_squash_d1; + +//dff #(1) ff_bld_pcx_rq_sel_d2 ( +// .din (bld_pcx_rq_sel_d1), +// .q (bld_pcx_rq_sel_d2), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + + assign bld_pcx_rq_sel = (ld0_pcx_rq_sel_d2 & bld_dcd_thrd[0] | + ld1_pcx_rq_sel_d2 & bld_dcd_thrd[1] | + ld2_pcx_rq_sel_d2 & bld_dcd_thrd[2] | + ld3_pcx_rq_sel_d2 & bld_dcd_thrd[3] ) & + ~pcx_req_squash_d1; + + assign bld_en = bld_g | (bld_pcx_rq_sel & bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ; + assign bld_din = bld_g | bld_dout ; + assign bcnt_din[1:0] = bld_cnt[1:0] + {1'b0,(bld_pcx_rq_sel & bld_dout)} ; + +// Reset by last completing bld helper. + assign bld_reset = + reset | bld_perr_kill_w2 | + (bld_rd_dout[2] & bld_rd_dout[1] & bld_rd_dout[0] & bld_helper_cmplt_g) ; + +assign lsu_bld_reset = bld_reset ; + +wire bld_dout_tmp ; +dffre #(3) bld_pcx_cnt ( + .din ({bcnt_din[1:0],bld_din}), + .q ({bld_cnt[1:0], bld_dout_tmp}), + .rst (bld_reset), .en (bld_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign bld_dout = bld_dout_tmp & ~bld_perr_kill_w2 ; + +// Last one allows ld-rq-vld to be reset. +assign bld_annul[0] = bld_dcd_thrd[0] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ; +assign bld_annul[1] = bld_dcd_thrd[1] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ; +assign bld_annul[2] = bld_dcd_thrd[2] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ; +assign bld_annul[3] = bld_dcd_thrd[3] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ; + +dff #(4) bannul_d1 ( + .din (bld_annul[3:0]), + .q (bld_annul_d1[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Maintain rd (cpx return pkt counter). This is based on when the blk ld helper completes. +// lower 3b of rd have to start out as zero. +// Should be asserted 8 times for the entire bld. +assign bld_rd_en = (bld_helper_cmplt_m & bld_dout) ; +assign bld_rd_din[2:0] = bld_rd_dout_m[2:0] + {2'b00,(bld_helper_cmplt_m & bld_dout)} ; +//assign bld_rd_en = (bld_helper_cmplt_g & bld_dout) ; +//assign bld_rd_din[2:0] = bld_rd_dout[2:0] + {2'b00,(bld_helper_cmplt_g & bld_dout)} ; + +dffre #(3) bld_cpx_cnt ( + .din (bld_rd_din[2:0]), + .q (bld_rd_dout_m[2:0]), + .rst (bld_reset), .en (bld_rd_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(3) bld_cnt_stg ( + .din (bld_rd_dout_m[2:0]), + .q (bld_rd_dout[2:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Select appr. rd. (cpx return pkt counter) +assign lsu_ffu_bld_cnt_w[2:0] = bld_rd_dout[2:0] ; +assign lsu_bld_cnt_m[2:0] = bld_rd_dout_m[2:0] ; + +// pcx pkt address cntrl. +wire [1:0] addr_b54 ; +assign addr_b54[1:0] = bld_cnt[1:0]; + +/*wire bld_rq_w2 ; +assign bld_rq_w2 = bld_dout; */ + +dff #(2) blkrq_d1 ( + .din ({addr_b54[1:0]}), + .q ({lsu_bld_rq_addr[1:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_bld_pcx_rq = bld_pcx_rq_sel_d1 & bld_dout ; + +/*dff #(3) blkrq_d1 ( + .din ({addr_b54[1:0],bld_rq_w2}), + .q ({lsu_bld_rq_addr[1:0],lsu_bld_pcx_rq}), + .clk (clk), + .se (1'b0), .si (), .so () + );*/ + + +//================================================================================================= +// LOAD PCX PKT REQ CONTROL +//================================================================================================= + +// Staging pref. +wire pref_inst_m, pref_inst_g ; + +dff stgm_prf ( + .din (ifu_lsu_pref_inst_e), + .q (pref_inst_m), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff stgg_prf ( + .din (pref_inst_m), + .q (pref_inst_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Performance Ctr Info +dff #(4) stgg_dmiss ( + .din ({ld3_l2cache_rq,ld2_l2cache_rq,ld1_l2cache_rq,ld0_l2cache_rq}), + .q (lsu_tlu_dcache_miss_w2[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire ld0_l2cache_rq_w2, ld1_l2cache_rq_w2, ld2_l2cache_rq_w2, ld3_l2cache_rq_w2 ; + +assign ld0_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[0]; +assign ld1_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[1]; +assign ld2_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[2]; +assign ld3_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[3]; + +wire pref_vld0_g, pref_vld1_g, pref_vld2_g, pref_vld3_g ; +wire pref_rq_vld0_g, pref_rq_vld1_g, pref_rq_vld2_g, pref_rq_vld3_g ; +wire pref_vld_g ; +assign pref_vld_g = pref_inst_g & ~tlb_pgnum_g[39] & tlb_cam_hit_g ; // Bug 4318. +assign pref_rq_vld0_g = pref_vld_g & thread0_g & lsu_inst_vld_w ; +assign pref_rq_vld1_g = pref_vld_g & thread1_g & lsu_inst_vld_w ; +assign pref_rq_vld2_g = pref_vld_g & thread2_g & lsu_inst_vld_w ; +assign pref_rq_vld3_g = pref_vld_g & thread3_g & lsu_inst_vld_w ; +assign pref_vld0_g = pref_inst_g & thread0_g ; +assign pref_vld1_g = pref_inst_g & thread1_g ; +assign pref_vld2_g = pref_inst_g & thread2_g ; +assign pref_vld3_g = pref_inst_g & thread3_g ; + +//========================================================================================= +// Shift full-raw/partial-raw logic from rw_ctl to qctl1 + +wire ldquad_inst_g ; +dff ldq_stgg ( + .din (lsu_ldquad_inst_m), .q (ldquad_inst_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire io_ld,io_ld_w2 ; +assign io_ld = tlb_pgnum_g[39] ; // Bug 4362 +//assign io_ld = tlb_pgnum_g[39] & ~(~tlb_pgnum_g[38] & tlb_pgnum_g[37]) ; + +wire stb_not_empty ; +assign stb_not_empty = + thread0_g ? ~lsu_stb_empty[0] : + thread1_g ? ~lsu_stb_empty[1] : + thread2_g ? ~lsu_stb_empty[2] : + ~lsu_stb_empty[3] ; + +wire ldq_hit_g,ldq_hit_w2 ; +wire ldq_stb_cam_hit ; +assign ldq_stb_cam_hit = stb_cam_hit_bf & ldquad_inst_g ; +// Terms can be made common. +assign ldq_hit_g = ldq_stb_cam_hit ; + +wire full_raw_g,partial_raw_g ; +wire full_raw_w2,partial_raw_w2 ; +assign full_raw_g = |stb_ld_full_raw[7:0] ; +assign partial_raw_g = |stb_ld_partial_raw[7:0] ; + +wire stb_cam_mhit_w2 ; +wire stb_not_empty_w2 ; +dff #(6) stgw2_rawcond ( + .din ({full_raw_g,partial_raw_g,stb_cam_mhit,ldq_hit_g,io_ld,stb_not_empty}), + .q ({full_raw_w2,partial_raw_w2,stb_cam_mhit_w2,ldq_hit_w2,io_ld_w2, + stb_not_empty_w2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// BEGIN !!! ld_stb_full_raw_g for SAS support only !!! +//wire ld_stb_full_raw_g ; +//wire ld_stb_partial_raw_g ; + +// END !!! ld_stb_full_raw_g for SAS support only !!! +assign ld_stb_full_raw_w2 = + (full_raw_w2 & ~(stb_cam_mhit_w2 | ldq_hit_w2 | io_ld_w2)) ; + //(full_raw_w2 & ~(stb_cam_mhit_w2 | ldq_hit_w2 | io_ld_w2)) ; // Bug 3624 +wire ld_stb_partial_raw_w2 ; +wire stb_cam_hit_w2 ; +assign ld_stb_partial_raw_w2 = + (partial_raw_w2 | stb_cam_mhit_w2 | ldq_hit_w2 | + (io_ld_w2 & stb_not_empty_w2)) ; + //(partial_raw_w2 | stb_cam_mhit_w2 | ldq_hit_w2 | (io_ld_w2 & stb_not_empty_w2)) ; + +//========================================================================================= + +/*wire ld_stb_full_raw_w2 ; +dff #(1) stgw2_fraw ( + .din (ld_stb_full_raw_g), + .q (ld_stb_full_raw_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); */ + +// THREAD0 LOAD PCX REQUEST CONTROL + +//===== +// For delayed ld0,1,2,3_l2cache_rq, we need to delay certain +// inputs to flops enabled by ld0,1,2,3_l2cache_rq. + +wire ld0_ldbl_rq_w2 ; +wire ld1_ldbl_rq_w2 ; +wire ld2_ldbl_rq_w2 ; +wire ld3_ldbl_rq_w2 ; +// wire [1:0] ld_pcx_pkt_wy_w2 ; + wire pref_rq_vld0_w2,pref_rq_vld1_w2,pref_rq_vld2_w2,pref_rq_vld3_w2 ; + wire non_l2bnk ; + wire non_l2bnk_w2 ; + wire [7:6] ldst_va_w2 ; + +dff #(7) stgw2_l2crqmx ( + .din ({ + //ld_pcx_pkt_wy_g[1:0], + pref_rq_vld0_g,pref_rq_vld1_g,pref_rq_vld2_g,pref_rq_vld3_g, + non_l2bnk, + ldst_va_g[7:6]}), + .q ({ + //ld_pcx_pkt_wy_w2[1:0], + pref_rq_vld0_w2,pref_rq_vld1_w2,pref_rq_vld2_w2,pref_rq_vld3_w2, + non_l2bnk_w2, + ldst_va_w2[7:6]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// wire [1:0] ld_pcx_pkt_wy_mx0,ld_pcx_pkt_wy_mx1,ld_pcx_pkt_wy_mx2,ld_pcx_pkt_wy_mx3 ; + wire pref_rq_vld0_mx,pref_rq_vld1_mx,pref_rq_vld2_mx,pref_rq_vld3_mx ; + wire non_l2bnk_mx0,non_l2bnk_mx1,non_l2bnk_mx2,non_l2bnk_mx3 ; + wire [7:6] ldst_va_mx0,ldst_va_mx1,ldst_va_mx2,ldst_va_mx3 ; + +// timing fix: 5/19/03: move secondary hit way generation to w2 +// remove ld_pcx_pkt_wy_mx[0-3] and replace w/ lsu_lmq_pkt_way_w2 +// assign ld_pcx_pkt_wy_mx0[1:0] = +// ld0_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ; +// assign ld_pcx_pkt_wy_mx1[1:0] = +// ld1_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ; +// assign ld_pcx_pkt_wy_mx2[1:0] = +// ld2_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ; +// assign ld_pcx_pkt_wy_mx3[1:0] = +// ld3_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ; + + + assign pref_rq_vld0_mx = + ld0_ldbl_rq_w2 ? pref_rq_vld0_w2 : pref_rq_vld0_g ; + assign pref_rq_vld1_mx = + ld1_ldbl_rq_w2 ? pref_rq_vld1_w2 : pref_rq_vld1_g ; + assign pref_rq_vld2_mx = + ld2_ldbl_rq_w2 ? pref_rq_vld2_w2 : pref_rq_vld2_g ; + assign pref_rq_vld3_mx = + ld3_ldbl_rq_w2 ? pref_rq_vld3_w2 : pref_rq_vld3_g ; + assign non_l2bnk_mx0 = + ld0_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ; + assign non_l2bnk_mx1 = + ld1_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ; + assign non_l2bnk_mx2 = + ld2_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ; + assign non_l2bnk_mx3 = + ld3_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ; + +//timing fix: 10/13/03 - ldst_va_mx[0-3] is used in the same cycle 'cos of perf bug fix-bug2705 +// this delays the ld request valid which in turn delays pcx_rq_for_stb +// fix is to isolate this mux and the following l2bank addr mux from ld?_ldbl_rq_w2; +// use ld[0-3]_inst_vld_w2 instead of ld[0-3]_ldbl_rq_w2 as select + assign ldst_va_mx0[7:6] = + ld0_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ; + assign ldst_va_mx1[7:6] = + ld1_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ; + assign ldst_va_mx2[7:6] = + ld2_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ; + assign ldst_va_mx3[7:6] = + ld3_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ; + +//===== + +wire atomic_g ; +assign atomic_g = casa_g | lsu_swap_g | lsu_ldstub_g ; + + wire dbl_force_l2access_g; + wire dbl_force_l2access_w2; + assign dbl_force_l2access_g = ldst_dbl_g & ~(ldst_fp_g & ~(alt_space_g & blk_asi_g)); + +dff #(2) stgw2_atm ( + .din ({atomic_g, dbl_force_l2access_g}), + .q ({atomic_w2,dbl_force_l2access_w2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(1) stgw2_perrkill ( + .din (lsu_tlb_perr_ld_rq_kill_w), + .q (perr_ld_rq_kill_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire asi_internal_g,asi_internal_w2; +dff #(1) stgg_intasi ( + .din (asi_internal_m), + .q (asi_internal_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(1) stgw2_intasi ( + .din (asi_internal_g), + .q (asi_internal_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire ld0_l2cache_rq_kill ; +assign ld0_l2cache_rq_kill = + ld0_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ; + // full-raw which looks like partial +assign ld0_ldbl_rq_w2 = + ((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2) + & ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) + & ld0_inst_vld_w2 ; + +//bug:2877 - dtag parity error 2nd packet request; dont reset if dtag parity error 2nd pkt valid +// dtag error is reset 1 cycle after 1st pkt sent +//---------------------------------------------------------------------------------------------------------- +// | 1 | 2 | 3 | 4 | 5 | 6 | +// spc_pcx_rq_pq=1 ld_err-pkt1 spc_pcx_rq_pq=1 ld_err-pkt2 +// ld0_vld_reset=0 pick 2nd pkt +// error_rst=1 +//---------------------------------------------------------------------------------------------------------- + +wire [3:0] dtag_perr_pkt2_vld_d1 ; +assign ld0_vld_reset = + (reset | (ld0_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld0_inst_vld_g | bld_annul_d1[0] | dtag_perr_pkt2_vld_d1[0]))) | + ld0_l2cache_rq_kill ; + //(reset | (ld0_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld0_inst_vld_g | bld_annul_d1[0]))) | + +// The equation for partial raw has redundancy !! Change it. +// prefetch will not bypass from stb +/* prim vs sec phase 2 change +assign ld0_l2cache_rq = + (((lsu_ld_miss_g & ~ld_stb_full_raw_g & ~ld_sec_hit_g & ~ldxa_internal) | + ((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g | (ld_stb_full_raw_g & ldst_dbl_g)))) + & ~atomic_g & ld0_inst_vld_g) | + | (pref_inst_g & tlb_cam_hit_g & thread0_g) ; +*/ + + +wire ld0_l2cache_rq_g; + +assign ld0_l2cache_rq_g = + (((lsu_ld_miss_g & ~ldxa_internal)) + //((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) + & ~atomic_g & ld0_inst_vld_g) + | pref_rq_vld0_g; + +assign ld0_l2cache_rq = ld0_l2cache_rq_g | ld0_ldbl_rq_w2 ; + +wire ld0_pkt_vld_unmasked ; +wire ld1_pkt_vld_unmasked ; +wire ld2_pkt_vld_unmasked ; +wire ld3_pkt_vld_unmasked ; + +// ld valid until request made. +wire pref_rq_vld0; +dffre #(2) ld0_vld ( + .din ({ld0_l2cache_rq, pref_rq_vld0_mx} ), + .q ({ld0_pkt_vld_unmasked, pref_rq_vld0}), + .rst (ld0_vld_reset), .en (ld0_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// bug2705 - speculative pick in w-cycle -begin +// dbl_force_l2access_g is set for ldd(f),std(f),ldq,stq +//perf fix: 7/29/03 - kill spec vld if other thread non-spec valids are set +//timing fix: 8/29/03 - flop atomic_m and ldxa_internal_m from dctl for spec req +wire atomic_or_ldxa_internal_rq_m ; +assign atomic_or_ldxa_internal_rq_m = atomic_m | lda_internal_m ; + +dff #(1) ff_atomic_or_ldxa_internal_rq_g ( + .din (atomic_or_ldxa_internal_rq_m), + .q (atomic_or_ldxa_internal_rq_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire ld0_spec_vld_g ; +assign ld0_spec_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g & + ~atomic_or_ldxa_internal_rq_g & + ~(ld1_pkt_vld_unmasked | ld2_pkt_vld_unmasked | ld3_pkt_vld_unmasked); +//assign ld0_spec_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ; + +dff #(1) ff_ld0_spec_pick_vld_w2 ( + .din (ld0_spec_pick_vld_g), + .q (ld0_spec_pick_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// kill packet valid if spec req is picked in w and stb hits in w2 +// cannot use ld0_ldbl_rawp_en_w2 because it is late signal instead use ld0_ldbl_rq_w2 +//timing fix: 7/21/03 - kill pkt vld if spec pick in w-cycle was to non$ address +//timing fix: 8/6/03 - kill pkt_vld if ld?_l2cache_rq_g=0 in w-cycle but spec_pick=1 +wire ld0_pkt_vld_tmp ; +//bug 3964 - replace ld0_pkt_vld_unmasked w/ ld0_l2cache_rq_w2 +//assign lsu_ld0_spec_vld_kill_w2 = ld0_spec_pick_vld_w2 & (~ld0_pkt_vld_unmasked | ld0_l2cache_rq_kill | ld0_ldbl_rq_w2 | non_l2bnk_mx0_d1) ; +assign lsu_ld0_spec_vld_kill_w2 = ld0_spec_pick_vld_w2 & (~ld0_l2cache_rq_w2 | ld0_l2cache_rq_kill | ld0_ldbl_rq_w2 | non_l2bnk_mx0_d1) ; + +assign ld0_pkt_vld_tmp = ld0_pkt_vld_unmasked & ~(ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2) & + ~(ld0_l2cache_rq_kill | ld0_ldbl_rq_w2) & + ~(pref_rq_vld0 & lsu_no_spc_pref[0]) ; // prefetch pending + +assign ld0_pkt_vld = ld0_pkt_vld_tmp | ld0_spec_vld_g ; +// bug2705 - speculative pick in w-cycle -end + +//assign ld0_pkt_vld = ld0_pkt_vld_unmasked & ~ld0_pcx_rq_sel_d1 ; + +assign ld0_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[0]) ; + + +dff #(4) stgm_lduwyd1 ( + .din ({ld0_fill_reset,ld1_fill_reset,ld2_fill_reset,ld3_fill_reset}), + .q ({ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) stgm_lduwyd2 ( + .din ({ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1}), + .q ({ld0_fill_reset_d2_tmp,ld1_fill_reset_d2_tmp,ld2_fill_reset_d2_tmp,ld3_fill_reset_d2_tmp}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire ld0_l2cache_rq_w2_tmp; +wire ld0_l2cache_rq_g_tmp; + +assign ld0_l2cache_rq_g_tmp = ld0_l2cache_rq_g & ~pref_inst_g ; + +dff #(1) ff_ld0_l2cache_rq_w2 ( + .din (ld0_l2cache_rq_g_tmp), + .q (ld0_l2cache_rq_w2_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +//wire ld0_unfilled_en ; +//assign ld0_unfilled_en = ld0_l2cache_rq & ~pref_inst_g ; +wire ld0_unfilled_wy_en ; +assign ld0_unfilled_wy_en = ld0_l2cache_rq_w2_tmp | ld0_ldbl_rq_w2 ; + +wire ld0_l2cache_rq_tmp; +assign ld0_l2cache_rq_tmp = ld0_unfilled_wy_en & ~ld0_l2cache_rq_kill; + +// ld valid until fill occur. +dffre #(1) ld0out_state ( + //.din (ld0_l2cache_rq), + .din (ld0_l2cache_rq_tmp), + .q (ld0_unfilled_tmp), + .rst (ld0_fill_reset_d2), .en (ld0_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dffre #(2) ld0out_state_way ( + //.din (ld_pcx_pkt_wy_mx0[1:0]}), + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (ld0_unfilled_wy[1:0]), + .rst (ld0_fill_reset_d2), .en (ld0_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign ld0_fill_reset_d2 = ld0_fill_reset_d2_tmp | ld0_l2cache_rq_kill ; +//assign ld0_unfilled = ld0_unfilled_tmp & ~ld0_l2cache_rq_kill ; +assign ld0_unfilled = ld0_unfilled_tmp ; + +//bug3516 +//assign non_l2bnk = tlb_pgnum_g[39] & tlb_pgnum_g[38] ; +assign non_l2bnk = tlb_pgnum_g[39] & ~(~tlb_pgnum_g[38] & tlb_pgnum_g[37]) ; + +// ld l2bank address +dffe #(3) ld0_l2bnka ( + .din ({non_l2bnk_mx0,ldst_va_mx0[7:6]}), + .q (ld0_l2bnk_addr[2:0]), + .en (ld0_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - add byp for address to be available in w-cycle +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access) +wire [2:0] ld0_l2bnk_addr_mx ; +assign ld0_l2bnk_addr_mx[2:0] = ld0_pkt_vld_unmasked ? ld0_l2bnk_addr[2:0] : + {1'b0,ldst_va_mx0[7:6]} ; // assume $able access for spec pick + +//assign ld0_l2bnk_addr_mx[2:0] = (ld0_inst_vld_unflushed & lsu_inst_vld_tmp) ? +// {1'b0,ldst_va_mx0[7:6]} : // assume $able access for spec pick +// //{non_l2bnk_mx0,ldst_va_mx0[7:6]} : +// ld0_l2bnk_addr[2:0] ; + +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 +dff #(1) ff_non_l2bnk_mx0_d1 ( + .din (non_l2bnk_mx0), + .q (non_l2bnk_mx0_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - change ld0_l2bnk_addr[2:0] to ld0_l2bnk_addr_mx[2:0] +assign ld0_l2bnk_dest[0] = ~ld0_l2bnk_addr_mx[2] & ~ld0_l2bnk_addr_mx[1] & ~ld0_l2bnk_addr_mx[0] ; +assign ld0_l2bnk_dest[1] = ~ld0_l2bnk_addr_mx[2] & ~ld0_l2bnk_addr_mx[1] & ld0_l2bnk_addr_mx[0] ; +assign ld0_l2bnk_dest[2] = ~ld0_l2bnk_addr_mx[2] & ld0_l2bnk_addr_mx[1] & ~ld0_l2bnk_addr_mx[0] ; +assign ld0_l2bnk_dest[3] = ~ld0_l2bnk_addr_mx[2] & ld0_l2bnk_addr_mx[1] & ld0_l2bnk_addr_mx[0] ; +assign ld0_l2bnk_dest[4] = ld0_l2bnk_addr_mx[2] ; + +// THREAD1 LOAD PCX REQUEST CONTROL + +wire ld1_l2cache_rq_kill ; +assign ld1_l2cache_rq_kill = + ld1_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ; + // full-raw which looks like partial +assign ld1_ldbl_rq_w2 = + ((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2) + & ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) & + ld1_inst_vld_w2 ; + +assign ld1_vld_reset = + (reset | (ld1_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld1_inst_vld_g | bld_annul_d1[1] | dtag_perr_pkt2_vld_d1[1]))) | + ld1_l2cache_rq_kill ; + //(reset | (ld1_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld1_inst_vld_g | bld_annul_d1[1]))) | // bug2877 + //(reset | (ld1_pcx_rq_sel_d1 & ~(pcx_req_squash | ld1_inst_vld_g | bld_annul[1]))) ; + +wire ld1_l2cache_rq_g; +assign ld1_l2cache_rq_g = + (((lsu_ld_miss_g & ~ldxa_internal)) + //((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs + & ~atomic_g & ld1_inst_vld_g) + | pref_rq_vld1_g ; + +assign ld1_l2cache_rq = ld1_l2cache_rq_g | ld1_ldbl_rq_w2 ; + + +// ld valid +wire pref_rq_vld1; +dffre #(2) ld1_vld ( + .din ({ld1_l2cache_rq, pref_rq_vld1_mx}), + .q ({ld1_pkt_vld_unmasked, pref_rq_vld1}), + .rst (ld1_vld_reset), .en (ld1_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// bug2705 - speculative pick in w-cycle-begin +wire ld1_spec_vld_g ; +assign ld1_spec_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g & + ~atomic_or_ldxa_internal_rq_g & + ~(ld0_pkt_vld_unmasked | ld2_pkt_vld_unmasked | ld3_pkt_vld_unmasked); +//assign ld1_spec_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ; + +dff #(1) ff_ld1_spec_pick_vld_w2 ( + .din (ld1_spec_pick_vld_g), + .q (ld1_spec_pick_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// kill packet valid if spec req is picked in w and stb hits in w2 +wire ld1_pkt_vld_tmp ; +assign lsu_ld1_spec_vld_kill_w2 = ld1_spec_pick_vld_w2 & (~ld1_l2cache_rq_w2 | ld1_l2cache_rq_kill | ld1_ldbl_rq_w2 | non_l2bnk_mx1_d1) ; + +assign ld1_pkt_vld_tmp = ld1_pkt_vld_unmasked & ~(ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2) & + ~(ld1_l2cache_rq_kill | ld1_ldbl_rq_w2) & + ~(pref_rq_vld1 & lsu_no_spc_pref[1]) ; + +assign ld1_pkt_vld = ld1_pkt_vld_tmp | ld1_spec_vld_g ; +// bug2705 - speculative pick in w-cycle-end + +//assign ld1_pkt_vld = ld1_pkt_vld_unmasked & ~ld1_pcx_rq_sel_d1 ; + + +assign ld1_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[1]) ; + +wire ld1_l2cache_rq_g_tmp; +wire ld1_l2cache_rq_w2_tmp; + +assign ld1_l2cache_rq_g_tmp = ld1_l2cache_rq_g & ~pref_inst_g ; + +dff #(1) ff_ld1_l2cache_rq_w2 ( + .din (ld1_l2cache_rq_g_tmp), + .q (ld1_l2cache_rq_w2_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//wire ld1_unfilled_en ; +//assign ld1_unfilled_en = ld1_l2cache_rq & ~pref_inst_g ; +wire ld1_unfilled_wy_en ; +assign ld1_unfilled_wy_en = ld1_l2cache_rq_w2_tmp | ld1_ldbl_rq_w2 ; + +wire ld1_l2cache_rq_tmp; +assign ld1_l2cache_rq_tmp = ld1_unfilled_wy_en & ~ld1_l2cache_rq_kill; + +// ld valid until fill occur. +dffre #(1) ld1out_state ( + //.din (ld1_l2cache_rq), + .din (ld1_l2cache_rq_tmp), + .q (ld1_unfilled_tmp), + .rst (ld1_fill_reset_d2), .en (ld1_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffre #(2) ld1out_state_way ( + //.din (ld_pcx_pkt_wy_mx1[1:0]), + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (ld1_unfilled_wy[1:0]), + .rst (ld1_fill_reset_d2), .en (ld1_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +assign ld1_fill_reset_d2 = ld1_fill_reset_d2_tmp | ld1_l2cache_rq_kill ; +//assign ld1_unfilled = ld1_unfilled_tmp & ~ld1_l2cache_rq_kill ; +assign ld1_unfilled = ld1_unfilled_tmp ; + +// ld l2bank address +dffe #(3) ld1_l2bnka ( + .din ({non_l2bnk_mx1,ldst_va_mx1[7:6]}), + .q (ld1_l2bnk_addr[2:0]), + .en (ld1_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - add byp for address to be available in w-cycle +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access) + +wire [2:0] ld1_l2bnk_addr_mx ; +assign ld1_l2bnk_addr_mx[2:0] = ld1_pkt_vld_unmasked ? ld1_l2bnk_addr[2:0] : + {1'b0,ldst_va_mx1[7:6]} ; + +//assign ld1_l2bnk_addr_mx[2:0] = (ld1_inst_vld_unflushed & lsu_inst_vld_tmp) ? +// {1'b0,ldst_va_mx1[7:6]} : +// //{non_l2bnk_mx1,ldst_va_mx1[7:6]} : +// ld1_l2bnk_addr[2:0] ; + +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 +dff #(1) ff_non_l2bnk_mx1_d1 ( + .din (non_l2bnk_mx1), + .q (non_l2bnk_mx1_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - change ld1_l2bnk_addr[2:0] to ld1_l2bnk_addr_mx[2:0] +assign ld1_l2bnk_dest[0] = ~ld1_l2bnk_addr_mx[2] & ~ld1_l2bnk_addr_mx[1] & ~ld1_l2bnk_addr_mx[0] ; +assign ld1_l2bnk_dest[1] = ~ld1_l2bnk_addr_mx[2] & ~ld1_l2bnk_addr_mx[1] & ld1_l2bnk_addr_mx[0] ; +assign ld1_l2bnk_dest[2] = ~ld1_l2bnk_addr_mx[2] & ld1_l2bnk_addr_mx[1] & ~ld1_l2bnk_addr_mx[0] ; +assign ld1_l2bnk_dest[3] = ~ld1_l2bnk_addr_mx[2] & ld1_l2bnk_addr_mx[1] & ld1_l2bnk_addr_mx[0] ; +assign ld1_l2bnk_dest[4] = ld1_l2bnk_addr_mx[2] ; + + +// THREAD2 LOAD PCX REQUEST CONTROL + +wire ld2_l2cache_rq_kill ; +assign ld2_l2cache_rq_kill = + ld2_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ; + // full-raw which looks like partial +assign ld2_ldbl_rq_w2 = + ((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2) + & ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) & + ld2_inst_vld_w2 ; +//assign ld2_l2cache_rq_kill = ld2_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 ; +//assign ld2_ldbl_rq_w2 = ld_stb_full_raw_w2 & dbl_force_l2access_w2 & ~atomic_w2 & ld2_inst_vld_w2 ; + +assign ld2_vld_reset = + (reset | (ld2_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld2_inst_vld_g | bld_annul_d1[2] | dtag_perr_pkt2_vld_d1[2]))) | + ld2_l2cache_rq_kill ; + //(reset | (ld2_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld2_inst_vld_g | bld_annul_d1[2]))) | // bug2877 + //(reset | (ld2_pcx_rq_sel_d1 & ~(pcx_req_squash | ld2_inst_vld_g | bld_annul[2]))) ; + +wire ld2_l2cache_rq_g; + +assign ld2_l2cache_rq_g = + (((lsu_ld_miss_g & ~ldxa_internal)) + //((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs + & ~atomic_g & ld2_inst_vld_g ) + | pref_rq_vld2_g ; + +assign ld2_l2cache_rq = ld2_l2cache_rq_g | ld2_ldbl_rq_w2 ; + + +// ld valid +wire pref_rq_vld2; +dffre #(2) ld2_vld ( + .din ({ld2_l2cache_rq, pref_rq_vld2_mx}), + .q ({ld2_pkt_vld_unmasked, pref_rq_vld2} ), + .rst (ld2_vld_reset), .en (ld2_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// bug2705 - speculative pick in w-cycle - begin +wire ld2_spec_vld_g ; +assign ld2_spec_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g & + ~atomic_or_ldxa_internal_rq_g & + ~(ld0_pkt_vld_unmasked | ld1_pkt_vld_unmasked | ld3_pkt_vld_unmasked); +//assign ld2_spec_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ; + +dff #(1) ff_ld2_spec_pick_vld_w2 ( + .din (ld2_spec_pick_vld_g), + .q (ld2_spec_pick_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// kill packet valid if spec req is picked in w and stb hits in w2 +wire ld2_pkt_vld_tmp ; +assign lsu_ld2_spec_vld_kill_w2 = ld2_spec_pick_vld_w2 & (~ld2_l2cache_rq_w2 | ld2_l2cache_rq_kill | ld2_ldbl_rq_w2 | non_l2bnk_mx2_d1) ; + +assign ld2_pkt_vld_tmp = ld2_pkt_vld_unmasked & ~(ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2) & + ~(ld2_l2cache_rq_kill | ld2_ldbl_rq_w2) & + ~(pref_rq_vld2 & lsu_no_spc_pref[2]) ; + +assign ld2_pkt_vld = ld2_pkt_vld_tmp | ld2_spec_vld_g ; +// bug2705 - speculative pick in w-cycle - end + +//assign ld2_pkt_vld = ld2_pkt_vld_unmasked & ~ld2_pcx_rq_sel_d1 ; + + +assign ld2_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[2]) ; + +wire ld2_l2cache_rq_g_tmp; +wire ld2_l2cache_rq_w2_tmp; + +assign ld2_l2cache_rq_g_tmp = ld2_l2cache_rq_g & ~pref_inst_g ; + +dff #(1) ff_ld2_l2cache_rq_w2 ( + .din (ld2_l2cache_rq_g_tmp), + .q (ld2_l2cache_rq_w2_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//wire ld2_unfilled_en ; +//assign ld2_unfilled_en = ld2_l2cache_rq & ~pref_inst_g ; +wire ld2_unfilled_wy_en ; +assign ld2_unfilled_wy_en = ld2_l2cache_rq_w2_tmp | ld2_ldbl_rq_w2 ; + +wire ld2_l2cache_rq_tmp; +assign ld2_l2cache_rq_tmp = ld2_unfilled_wy_en & ~ld2_l2cache_rq_kill; + +// ld valid until fill occur. +dffre #(1) ld2out_state ( + //.din (ld2_l2cache_rq), + .din (ld2_l2cache_rq_tmp), + .q (ld2_unfilled_tmp), + .rst (ld2_fill_reset_d2), .en (ld2_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffre #(2) ld2out_state_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (ld2_unfilled_wy[1:0]), + .rst (ld2_fill_reset_d2), .en (ld2_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +assign ld2_fill_reset_d2 = ld2_fill_reset_d2_tmp | ld2_l2cache_rq_kill ; +//assign ld2_unfilled = ld2_unfilled_tmp & ~ld2_l2cache_rq_kill ; +assign ld2_unfilled = ld2_unfilled_tmp ; + +// ld l2bank address +dffe #(3) ld2_l2bnka ( + .din ({non_l2bnk_mx2,ldst_va_mx2[7:6]}), + .q (ld2_l2bnk_addr[2:0]), + .en (ld2_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - add byp for address to be available in w-cycle +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access) + +wire [2:0] ld2_l2bnk_addr_mx ; +assign ld2_l2bnk_addr_mx[2:0] = ld2_pkt_vld_unmasked ? ld2_l2bnk_addr[2:0] : + {1'b0,ldst_va_mx2[7:6]} ; + +//assign ld2_l2bnk_addr_mx[2:0] = (ld2_inst_vld_unflushed & lsu_inst_vld_tmp) ? +// {1'b0,ldst_va_mx2[7:6]} : +// //{non_l2bnk_mx2,ldst_va_mx2[7:6]} : +// ld2_l2bnk_addr[2:0] ; + +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 +dff #(1) ff_non_l2bnk_mx2_d1 ( + .din (non_l2bnk_mx2), + .q (non_l2bnk_mx2_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - change ld2_l2bnk_addr[2:0] to ld2_l2bnk_addr_mx[2:0] +assign ld2_l2bnk_dest[0] = ~ld2_l2bnk_addr_mx[2] & ~ld2_l2bnk_addr_mx[1] & ~ld2_l2bnk_addr_mx[0] ; +assign ld2_l2bnk_dest[1] = ~ld2_l2bnk_addr_mx[2] & ~ld2_l2bnk_addr_mx[1] & ld2_l2bnk_addr_mx[0] ; +assign ld2_l2bnk_dest[2] = ~ld2_l2bnk_addr_mx[2] & ld2_l2bnk_addr_mx[1] & ~ld2_l2bnk_addr_mx[0] ; +assign ld2_l2bnk_dest[3] = ~ld2_l2bnk_addr_mx[2] & ld2_l2bnk_addr_mx[1] & ld2_l2bnk_addr_mx[0] ; +assign ld2_l2bnk_dest[4] = ld2_l2bnk_addr_mx[2] ; + +// THREAD3 LOAD PCX REQUEST CONTROL + +wire ld3_l2cache_rq_kill ; +assign ld3_l2cache_rq_kill = + ld3_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ; + // full-raw which looks like partial +assign ld3_ldbl_rq_w2 = + ((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2) + & ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) & + ld3_inst_vld_w2 ; +//assign ld3_l2cache_rq_kill = ld3_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 ; +//assign ld3_ldbl_rq_w2 = ld_stb_full_raw_w2 & dbl_force_l2access_w2 & ~atomic_w2 & ld3_inst_vld_w2 ; + +assign ld3_vld_reset = + (reset | (ld3_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld3_inst_vld_g | bld_annul_d1[3] | dtag_perr_pkt2_vld_d1[3]))) | + ld3_l2cache_rq_kill ; + //(reset | (ld3_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld3_inst_vld_g | bld_annul_d1[3]))) | // bug 2877 + //(reset | (ld3_pcx_rq_sel_d1 & ~(pcx_req_squash | ld3_inst_vld_g | bld_annul[3]))) ; + +wire ld3_l2cache_rq_g; +assign ld3_l2cache_rq_g = + (((lsu_ld_miss_g & ~ldxa_internal)) + //((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs + & ~atomic_g & ld3_inst_vld_g) + | pref_rq_vld3_g ; + +assign ld3_l2cache_rq = ld3_l2cache_rq_g | ld3_ldbl_rq_w2 ; + + +// ld valid +wire pref_rq_vld3; +dffre #(2) ld3_vld ( + .din ({ld3_l2cache_rq, pref_rq_vld3_mx} ), + .q ({ld3_pkt_vld_unmasked, pref_rq_vld3}), + .rst (ld3_vld_reset), .en (ld3_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// bug2705 - speculative pick in w-cycle - begin +wire ld3_spec_vld_g ; +assign ld3_spec_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g & + ~atomic_or_ldxa_internal_rq_g & + ~(ld0_pkt_vld_unmasked | ld1_pkt_vld_unmasked | ld2_pkt_vld_unmasked); +//assign ld3_spec_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ; + + +dff #(1) ff_ld3_spec_pick_vld_w2 ( + .din (ld3_spec_pick_vld_g), + .q (ld3_spec_pick_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// kill packet valid if spec req is picked in w and stb hits in w2 +wire ld3_pkt_vld_tmp ; +assign lsu_ld3_spec_vld_kill_w2 = ld3_spec_pick_vld_w2 & (~ld3_l2cache_rq_w2 | ld3_l2cache_rq_kill | ld3_ldbl_rq_w2 | non_l2bnk_mx3_d1) ; + +assign ld3_pkt_vld_tmp = ld3_pkt_vld_unmasked & ~(ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2) & + ~(ld3_l2cache_rq_kill | ld3_ldbl_rq_w2) & + ~(pref_rq_vld3 & lsu_no_spc_pref[3]) ; + +assign ld3_pkt_vld = ld3_pkt_vld_tmp | ld3_spec_vld_g ; +// bug2705 - speculative pick in w-cycle - end + +//assign ld3_pkt_vld = ld3_pkt_vld_unmasked & ~ld3_pcx_rq_sel_d1 ; + +assign ld3_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[3]) ; + +wire ld3_l2cache_rq_g_tmp; +wire ld3_l2cache_rq_w2_tmp; + +assign ld3_l2cache_rq_g_tmp = ld3_l2cache_rq_g & ~pref_inst_g ; + +dff #(1) ff_ld3_l2cache_rq_w2 ( + .din (ld3_l2cache_rq_g_tmp), + .q (ld3_l2cache_rq_w2_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//wire ld3_unfilled_en ; +//assign ld3_unfilled_en = ld3_l2cache_rq & ~pref_inst_g ; +wire ld3_unfilled_wy_en ; +assign ld3_unfilled_wy_en = ld3_l2cache_rq_w2_tmp | ld3_ldbl_rq_w2 ; + +wire ld3_l2cache_rq_tmp; +assign ld3_l2cache_rq_tmp = ld3_unfilled_wy_en & ~ld3_l2cache_rq_kill; + +// ld valid until fill occur. +dffre #(1) ld3out_state ( + //.din (ld3_l2cache_rq), + .din (ld3_l2cache_rq_tmp), + .q (ld3_unfilled_tmp), + .rst (ld3_fill_reset_d2), .en (ld3_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); +dffre #(2) ld3out_state_way ( + .din (lsu_lmq_pkt_way_w2[1:0]), + .q (ld3_unfilled_wy[1:0]), + .rst (ld3_fill_reset_d2), .en (ld3_unfilled_wy_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +assign ld3_fill_reset_d2 = ld3_fill_reset_d2_tmp | ld3_l2cache_rq_kill ; +//assign ld3_unfilled = ld3_unfilled_tmp & ~ld3_l2cache_rq_kill ; +assign ld3_unfilled = ld3_unfilled_tmp; + +// ld l2bank address +dffe #(3) ld3_l2bnka ( + .din ({non_l2bnk_mx3,ldst_va_mx3[7:6]}), + .q (ld3_l2bnk_addr[2:0]), + .en (ld3_l2cache_rq), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705 - add byp for address to be available in w-cycle +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access) + +wire [2:0] ld3_l2bnk_addr_mx ; +assign ld3_l2bnk_addr_mx[2:0] = ld3_pkt_vld_unmasked ? ld3_l2bnk_addr[2:0] : + {1'b0,ldst_va_mx3[7:6]} ; + +//assign ld3_l2bnk_addr_mx[2:0] = (ld3_inst_vld_unflushed & lsu_inst_vld_tmp) ? +// {1'b0,ldst_va_mx3[7:6]} : +// //{non_l2bnk_mx3,ldst_va_mx3[7:6]} : +// ld3_l2bnk_addr[2:0] ; + +//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps) +// this will cause timing paths in spec pick in w-cycle; hence assume $able access for +// spec pick and kill pkt vld in w2 +dff #(1) ff_non_l2bnk_mx3_d1 ( + .din (non_l2bnk_mx3), + .q (non_l2bnk_mx3_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +//bug2705 - change ld3_l2bnk_addr[2:0] to ld3_l2bnk_addr_mx[2:0] +assign ld3_l2bnk_dest[0] = ~ld3_l2bnk_addr_mx[2] & ~ld3_l2bnk_addr_mx[1] & ~ld3_l2bnk_addr_mx[0] ; +assign ld3_l2bnk_dest[1] = ~ld3_l2bnk_addr_mx[2] & ~ld3_l2bnk_addr_mx[1] & ld3_l2bnk_addr_mx[0] ; +assign ld3_l2bnk_dest[2] = ~ld3_l2bnk_addr_mx[2] & ld3_l2bnk_addr_mx[1] & ~ld3_l2bnk_addr_mx[0] ; +assign ld3_l2bnk_dest[3] = ~ld3_l2bnk_addr_mx[2] & ld3_l2bnk_addr_mx[1] & ld3_l2bnk_addr_mx[0] ; +assign ld3_l2bnk_dest[4] = ld3_l2bnk_addr_mx[2] ; + +//================================================================================================= +// LMQ Miscellaneous Control +//================================================================================================= + +dff #(1) stgm_cas ( + .din (ifu_lsu_casa_e), + .q (casa_m), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(1) stgg_cas ( + .din (casa_m), + .q (casa_g), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//assign casa0_g = casa_g & thread0_g ; +//assign casa1_g = casa_g & thread1_g ; +//assign casa2_g = casa_g & thread2_g ; +//assign casa3_g = casa_g & thread3_g ; + +// PARTIAL RAW BYPASSING. + +// Partial raw of load in stb. Even if the load hits in the dcache, it must follow +// the st to the pcx, obtain merged data to bypass to the pipeline. This load will +// also fill the dcache. i.e., once the store is received it looks like a normal load. + +// This path is also used for 2nd cas pkt. rs1(addr) and rs2(cmp data) are in 1st +// pkt which is written to stb. rd(swap value) is written to lmq as 2nd pkt. The +// 2nd pkt will wait in the lmq until the 1st pkt is sent. + +// *** Atomics need to switch out the thread *** + +// THREAD0 + +// timing fix: 9/15/03 - reduce loading on pcx_rq_for_stb[3:0] to stb_clt[0-3]. it had FO2 (stb_ctl,qdp2 - cap=0.5-0.8) +// move the flop from qdp2 to qctl1 + +dff #(4) ff_pcx_rq_for_stb_d1 ( + .din (pcx_rq_for_stb[3:0]), + .q (pcx_rq_for_stb_d1[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) srqsel_d1 ( + .din (pcx_rq_for_stb[3:0]), + //.q ({st3_pcx_rq_tmp, st2_pcx_rq_tmp,st1_pcx_rq_tmp, st0_pcx_rq_tmp}), + .q ({st3_pcx_rq_sel_d1, st2_pcx_rq_sel_d1,st1_pcx_rq_sel_d1, st0_pcx_rq_sel_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) srqsel_d2 ( + .din ({st3_pcx_rq_sel_d1, st2_pcx_rq_sel_d1,st1_pcx_rq_sel_d1, st0_pcx_rq_sel_d1}), + .q ({st3_pcx_rq_sel_d2, st2_pcx_rq_sel_d2,st1_pcx_rq_sel_d2, st0_pcx_rq_sel_d2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) srqsel_d3 ( + .din ({st3_pcx_rq_sel_d2, st2_pcx_rq_sel_d2,st1_pcx_rq_sel_d2, st0_pcx_rq_sel_d2}), + .q ({st3_pcx_rq_sel_d3, st2_pcx_rq_sel_d3,st1_pcx_rq_sel_d3, st0_pcx_rq_sel_d3}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire ld0_ldbl_rawp_en_w2 ; +assign ld0_ldbl_rawp_en_w2 = ld0_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld0_rawp_reset ; + +/*assign st3_pcx_rq_sel_d1 = st3_pcx_rq_tmp & ~pcx_req_squash ; +assign st2_pcx_rq_sel_d1 = st2_pcx_rq_tmp & ~pcx_req_squash ; +assign st1_pcx_rq_sel_d1 = st1_pcx_rq_tmp & ~pcx_req_squash ; +assign st0_pcx_rq_sel_d1 = st0_pcx_rq_tmp & ~pcx_req_squash ;*/ + +assign ld0_rawp_reset = + (reset | (st0_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld0_rawp_disabled & (ld0_rawp_ackid[2:0] == stb0_crnt_ack_id[2:0]))); + //(reset | (st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld0_rawp_disabled & (ld0_rawp_ackid[2:0] == stb0_crnt_ack_id[2:0]))); + +// TO BE REMOVED ALONG WITH defines !!! +//wire ld_rawp_st_ced_g ; +//assign ld_rawp_st_ced_g = 1'b0 ; + +// reset needs to be dominant in case ack comes on fly. +// atomics will not set rawp_disabled +assign ld0_rawp_en = + //(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld0_rawp_reset) // partial_raw + //& ~atomic_g & ld0_inst_vld_g) | // cas inst - 2nd pkt + ld0_ldbl_rawp_en_w2 ; + +// ack-id and wait-for-ack disable - Thread 0 +dffre #(1) ldrawp0_dis ( + .din (ld0_rawp_en), + .q (ld0_rawp_disabled), + .rst (ld0_rawp_reset), .en (ld0_rawp_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dffe #(3) ldrawp0_ackid ( + .din (ld_rawp_st_ackid_w2[2:0]), + .q (ld0_rawp_ackid[2:0]), + .en (ld0_inst_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// THREAD1 + +wire ld1_ldbl_rawp_en_w2 ; +assign ld1_ldbl_rawp_en_w2 = ld1_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld1_rawp_reset ; + +// 1st st ack for st-quad will not cause ack. + +assign ld1_rawp_reset = + (reset | (st1_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld1_rawp_disabled & + //(reset | (st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld1_rawp_disabled & + (ld1_rawp_ackid[2:0] == stb1_crnt_ack_id[2:0]))); + +// reset needs to be dominant in case ack comes on fly. +// atomics will not set rawp_disabled +assign ld1_rawp_en = + //(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld1_rawp_reset) // partial raw + //(((ld_stb_partial_raw_g | (ld_stb_full_raw_g & ldst_dbl_g)) & ~ld_rawp_st_ced_g & ~ld1_rawp_reset) // partial raw + //& ~atomic_g & ld1_inst_vld_g) | // cas inst - 2nd pkt + ld1_ldbl_rawp_en_w2 ; + +// ack-id and wait-for-ack disable - Thread 0 +dffre #(1) ldrawp1_dis ( + .din (ld1_rawp_en), + .q (ld1_rawp_disabled), + .rst (ld1_rawp_reset), .en (ld1_rawp_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dffe #(3) ldrawp1_ackid ( + .din (ld_rawp_st_ackid_w2[2:0]), + .q (ld1_rawp_ackid[2:0]), + .en (ld1_inst_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// THREAD2 + +wire ld2_ldbl_rawp_en_w2 ; +assign ld2_ldbl_rawp_en_w2 = ld2_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld2_rawp_reset ; + +assign ld2_rawp_reset = + (reset | (st2_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld2_rawp_disabled & + //(reset | (st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld2_rawp_disabled & + (ld2_rawp_ackid[2:0] == stb2_crnt_ack_id[2:0]))); + +// reset needs to be dominant in case ack comes on fly. +// atomics will not set rawp_disabled +assign ld2_rawp_en = + //(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld2_rawp_reset) // partial raw + //& ~atomic_g & ld2_inst_vld_g) | // cas inst - 2nd pkt + ld2_ldbl_rawp_en_w2 ; + +// ack-id and wait-for-ack disable - Thread 0 +dffre #(1) ldrawp2_dis ( + .din (ld2_rawp_en), + .q (ld2_rawp_disabled), + .rst (ld2_rawp_reset), .en (ld2_rawp_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dffe #(3) ldrawp2_ackid ( + .din (ld_rawp_st_ackid_w2[2:0]), + .q (ld2_rawp_ackid[2:0]), + .en (ld2_inst_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// THREAD3 + +wire ld3_ldbl_rawp_en_w2 ; +assign ld3_ldbl_rawp_en_w2 = ld3_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld3_rawp_reset ; + +assign ld3_rawp_reset = + (reset | (st3_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld3_rawp_disabled & + //(reset | (st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld3_rawp_disabled & + (ld3_rawp_ackid[2:0] == stb3_crnt_ack_id[2:0]))); + +// reset needs to be dominant in case ack comes on fly. +// atomics will not set rawp_disabled +assign ld3_rawp_en = + //(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld3_rawp_reset) // partial raw + //& ~atomic_g & ld3_inst_vld_g) | // cas inst - 2nd pkt + ld3_ldbl_rawp_en_w2 ; + +// ack-id and wait-for-ack disable - Thread 0 +dffre #(1) ldrawp3_dis ( + .din (ld3_rawp_en), + .q (ld3_rawp_disabled), + .rst (ld3_rawp_reset), .en (ld3_rawp_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dffe #(3) ldrawp3_ackid ( + .din (ld_rawp_st_ackid_w2[2:0]), + .q (ld3_rawp_ackid[2:0]), + .en (ld3_inst_vld_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + + +//================================================================================================= +// INTERRUPT PCX PKT REQ CTL +//================================================================================================= + +wire intrpt_pcx_rq_sel_d2 ; +wire intrpt_vld_reset; +wire intrpt_vld_en ; +wire [3:0] intrpt_thread ; +wire intrpt_clr ; + + +assign lsu_tlu_pcxpkt_ack = intrpt_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + +assign intrpt_vld_reset = + reset | lsu_tlu_pcxpkt_ack ; + //reset | (intrpt_pcx_rq_sel_d1 & ~pcx_req_squash); +wire intrpt_pkt_vld_unmasked ; +// assumption is that pkt vld cannot be turned around in same cycle +assign intrpt_vld_en = ~intrpt_pkt_vld_unmasked ; +//assign intrpt_vld_en = ~lsu_intrpt_pkt_vld ; + +dff #(1) intpkt_stgd2 ( + .din (intrpt_pcx_rq_sel_d1), + .q (intrpt_pcx_rq_sel_d2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// intrpt valid +dffre intrpt_vld ( + .din (tlu_lsu_pcxpkt_vld), + .q (intrpt_pkt_vld_unmasked), + .rst (intrpt_vld_reset), .en (intrpt_vld_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign intrpt_thread[0] = ~tlu_lsu_pcxpkt_tid[19] & ~tlu_lsu_pcxpkt_tid[18] ; +assign intrpt_thread[1] = ~tlu_lsu_pcxpkt_tid[19] & tlu_lsu_pcxpkt_tid[18] ; +assign intrpt_thread[2] = tlu_lsu_pcxpkt_tid[19] & ~tlu_lsu_pcxpkt_tid[18] ; +assign intrpt_thread[3] = tlu_lsu_pcxpkt_tid[19] & tlu_lsu_pcxpkt_tid[18] ; + +assign intrpt_clr = + (intrpt_thread[0] & lsu_stb_empty[0]) | + (intrpt_thread[1] & lsu_stb_empty[1]) | + (intrpt_thread[2] & lsu_stb_empty[2]) | + (intrpt_thread[3] & lsu_stb_empty[3]) ; + +wire intrpt_clr_d1 ; +dff #(1) intclr_stgd1 ( + .din (intrpt_clr), + .q (intrpt_clr_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire [3:0] intrpt_cmplt ; + +assign intrpt_cmplt[0] = lsu_tlu_pcxpkt_ack & intrpt_thread[0] ; +assign intrpt_cmplt[1] = lsu_tlu_pcxpkt_ack & intrpt_thread[1] ; +assign intrpt_cmplt[2] = lsu_tlu_pcxpkt_ack & intrpt_thread[2] ; +assign intrpt_cmplt[3] = lsu_tlu_pcxpkt_ack & intrpt_thread[3] ; + +dff #(4) intrpt_stg ( + .din (intrpt_cmplt[3:0]), + .q (lsu_intrpt_cmplt[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign intrpt_pkt_vld = +intrpt_pkt_vld_unmasked & ~(intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2) & intrpt_clr_d1 ; + +// ** enabled flop should not be required !! +// intrpt l2bank address +// ?? Can interrupt requests go to io-bridge ?? +// Using upper 3b of 5b thread field of INTR_W to address 4 l2 banks +dffe #(3) intrpt_l2bnka ( + .din ({1'b0,tlu_lsu_pcxpkt_l2baddr[11:10]}), + .q (intrpt_l2bnk_addr[2:0]), + .en (intrpt_vld_en), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// IO Requests should not go to iobrdge. +assign intrpt_l2bnk_dest[0] = +~intrpt_l2bnk_addr[2] & ~intrpt_l2bnk_addr[1] & ~intrpt_l2bnk_addr[0] ; +assign intrpt_l2bnk_dest[1] = +~intrpt_l2bnk_addr[2] & ~intrpt_l2bnk_addr[1] & intrpt_l2bnk_addr[0] ; +assign intrpt_l2bnk_dest[2] = +~intrpt_l2bnk_addr[2] & intrpt_l2bnk_addr[1] & ~intrpt_l2bnk_addr[0] ; +assign intrpt_l2bnk_dest[3] = +~intrpt_l2bnk_addr[2] & intrpt_l2bnk_addr[1] & intrpt_l2bnk_addr[0] ; +assign intrpt_l2bnk_dest[4] = intrpt_l2bnk_addr[2] ; + +//================================================================================================= +// +// QDP Specific Control +// +//================================================================================================= + + +// Qualify with thread. +// Write cas pckt 2 to lmq +// Timing Change : ld0_l2cache_rq guarantees validity. +//assign lmq_enable[0] = lsu_ld_miss_g & thread0_g ; +//assign lmq_enable[0] = ld0_inst_vld_g | pref_vld0_g ; + +//assign lmq_enable[0] = (ld0_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld0_g ; +//assign lmq_enable[1] = (ld1_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld1_g ; +//assign lmq_enable[2] = (ld2_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld2_g ; +//assign lmq_enable[3] = (ld3_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld3_g ; + +//bug 2771; timing path - remove flush-pipe, add ifu's flush signal +//assign lmq_enable[0] = (ld0_inst_vld_unflushed | pref_vld0_g) & lsu_inst_vld_w ; +assign lmq_enable[0] = (ld0_inst_vld_unflushed | pref_vld0_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ; +assign lmq_enable[1] = (ld1_inst_vld_unflushed | pref_vld1_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ; +assign lmq_enable[2] = (ld2_inst_vld_unflushed | pref_vld2_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ; +assign lmq_enable[3] = (ld3_inst_vld_unflushed | pref_vld3_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ; + +// timing fix: 5/19/03: move secondary hit way generation to w2 +dff #(4) ff_lmq_enable_w2 ( + .din (lmq_enable[3:0]), + .q (lmq_enable_w2[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +// needs to be 1-hot always. +assign imiss_pcx_mx_sel = imiss_pcx_rq_sel_d1 ; +//assign imiss_pcx_mx_sel[1] = strm_pcx_rq_sel_d1 ; +//assign imiss_pcx_mx_sel[2] = intrpt_pcx_rq_sel_d1 ; +//assign imiss_pcx_mx_sel[3] = fpop_pcx_rq_sel_d1 ; + +//11/7/03: add rst_tri_en +wire [2:0] fwd_int_fp_pcx_mx_sel_tmp ; + +assign fwd_int_fp_pcx_mx_sel_tmp[0]= ~fwd_int_fp_pcx_mx_sel[1] & ~fwd_int_fp_pcx_mx_sel[2]; +assign fwd_int_fp_pcx_mx_sel_tmp[1]= intrpt_pcx_rq_sel_d1 ; +assign fwd_int_fp_pcx_mx_sel_tmp[2]= fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 ; + +assign fwd_int_fp_pcx_mx_sel[1:0] = fwd_int_fp_pcx_mx_sel_tmp[1:0] & ~{2{rst_tri_en}} ; +assign fwd_int_fp_pcx_mx_sel[2] = fwd_int_fp_pcx_mx_sel_tmp[2] | rst_tri_en ; + + +//************************************************************************************************* +// PCX REQUEST GENERATION (BEGIN) + +//================================================================================================= +// PCX REQUEST SELECTION CONTROL +//================================================================================================= + +// LOAD +// fpops have to squash other rqs in the 2nd cycle also. +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign ld0_pcx_rq_vld = + (|(queue_write[4:0] & ld0_l2bnk_dest[4:0])) & + ld0_pkt_vld & ~ld0_rawp_disabled; + //ld0_pkt_vld & ~ld0_rawp_disabled & ~mcycle_squash_d1; + //ld0_pkt_vld & ~ld0_rawp_disabled & ~st_atom_rq_d1 ; +assign ld1_pcx_rq_vld = + (|(queue_write[4:0] & ld1_l2bnk_dest[4:0])) & + ld1_pkt_vld & ~ld1_rawp_disabled; + //ld1_pkt_vld & ~ld1_rawp_disabled & ~mcycle_squash_d1; + //ld1_pkt_vld & ~ld1_rawp_disabled & ~st_atom_rq_d1 ; +assign ld2_pcx_rq_vld = + (|(queue_write[4:0] & ld2_l2bnk_dest[4:0])) & + ld2_pkt_vld & ~ld2_rawp_disabled ; + //ld2_pkt_vld & ~ld2_rawp_disabled & ~mcycle_squash_d1; + //ld2_pkt_vld & ~ld2_rawp_disabled & ~st_atom_rq_d1 ; +assign ld3_pcx_rq_vld = + (|(queue_write[4:0] & ld3_l2bnk_dest[4:0])) & + ld3_pkt_vld & ~ld3_rawp_disabled; + //ld3_pkt_vld & ~ld3_rawp_disabled & ~mcycle_squash_d1; + //ld3_pkt_vld & ~ld3_rawp_disabled & ~st_atom_rq_d1 ; + +//assign ld_pcx_rq_vld = ld0_pcx_rq_vld | ld1_pcx_rq_vld +// | ld2_pcx_rq_vld | ld3_pcx_rq_vld ; + +wire st0_atomic_pend_d1, st1_atomic_pend_d1, st2_atomic_pend_d1, st3_atomic_pend_d1 ; + +assign st0_q_wr[4:0] = st0_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ; +assign st1_q_wr[4:0] = st1_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ; +assign st2_q_wr[4:0] = st2_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ; +assign st3_q_wr[4:0] = st3_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ; + +assign st0_atom_rq = (st0_pcx_rq_sel & st0_atomic_vld) ; +assign st1_atom_rq = (st1_pcx_rq_sel & st1_atomic_vld) ; +assign st2_atom_rq = (st2_pcx_rq_sel & st2_atomic_vld) ; +assign st3_atom_rq = (st3_pcx_rq_sel & st3_atomic_vld) ; + +dff #(8) avlds_d1 ( + .din ({st0_atom_rq,st1_atom_rq,st2_atom_rq,st3_atom_rq, + st0_cas_vld,st1_cas_vld,st2_cas_vld,st3_cas_vld}), + .q ({st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1, + st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(8) avlds_d2 ( + .din ({st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1, + st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1}), + .q ({st0_atom_rq_d2,st1_atom_rq_d2,st2_atom_rq_d2,st3_atom_rq_d2, + st0_cas_vld_d2,st1_cas_vld_d2,st2_cas_vld_d2,st3_cas_vld_d2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//timing fix : 7/28/03 - move the OR before flop +assign st_atom_rq = st0_atom_rq | st1_atom_rq | st2_atom_rq | st3_atom_rq ; +//assign st_atom_rq_d1 = st0_atom_rq_d1 | st1_atom_rq_d1 | st2_atom_rq_d1 | st3_atom_rq_d1 ; + +// timing fix: 7/28/03 - move the OR before flop +dff #(1) ff_st_atom_pq ( + .din (st_atom_rq), + .q (st_atom_rq_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +assign st_cas_rq_d2 = + (st0_atom_rq_d2 & st0_cas_vld_d2) | + (st1_atom_rq_d2 & st1_cas_vld_d2) | + (st2_atom_rq_d2 & st2_cas_vld_d2) | + (st3_atom_rq_d2 & st3_cas_vld_d2) ; +//assign st_quad_rq_d2 = +// (st0_atom_rq_d2 & ~st0_cas_vld_d2) | +// (st1_atom_rq_d2 & ~st1_cas_vld_d2) | +// (st2_atom_rq_d2 & ~st2_cas_vld_d2) | +// (st3_atom_rq_d2 & ~st3_cas_vld_d2) ; + +//timing fix: 9/17/03 - move the OR to previous cycle and add flop for spc_pcx_atom_pq +// instantiate buf30 for flop output +//assign spc_pcx_atom_pq = +// st_atom_rq_d1 | +// fpop_atom_rq_pq ; + +wire spc_pcx_atom_w, spc_pcx_atom_pq_tmp ; +assign spc_pcx_atom_w = st_atom_rq | fpop_atom_req ; + +dff #(1) ff_spc_pcx_atom_pq ( + .din (spc_pcx_atom_w), + .q (spc_pcx_atom_pq_tmp), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +bw_u1_buf_30x UZfix_spc_pcx_atom_pq_buf1 ( .a(spc_pcx_atom_pq_tmp), .z(spc_pcx_atom_pq) ); +bw_u1_buf_30x UZsize_spc_pcx_atom_pq_buf2 ( .a(spc_pcx_atom_pq_tmp), .z(spc_pcx_atom_pq_buf2) ); + +// STORE +// st will wait in pcx bypass until previous st in chain is acked !!!! +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign st0_pcx_rq_vld = + (|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld ; + //(|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld & ~mcycle_squash_d1; + //(|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld & ~st_atom_rq_d1 ; +assign st1_pcx_rq_vld = + (|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld ; + //(|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld & ~mcycle_squash_d1; + //(|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld & ~st_atom_rq_d1 ; +assign st2_pcx_rq_vld = + (|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld ; + //(|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld & ~mcycle_squash_d1; + //(|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld & ~st_atom_rq_d1 ; +assign st3_pcx_rq_vld = + (|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld ; + //(|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld & ~mcycle_squash_d1; + //(|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld & ~st_atom_rq_d1 ; + +// IMISS +// imiss requests will not speculate - ** change !!! +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign imiss_pcx_rq_vld = + (|(queue_write[4:0] & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld ; + //(|(queue_write[4:0] & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld & ~mcycle_squash_d1; + //(|((queue_write[4:0] & (sel_qentry0[4:0] | (~sel_qentry0[4:0] & ~spc_pcx_req_update_w2[4:0]))) & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld & ~mcycle_squash_d1; + +// SPU +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign strm_pcx_rq_vld = + (|(queue_write[4:0] & strm_l2bnk_dest[4:0])) & strm_pkt_vld ; + //(|(queue_write[4:0] & strm_l2bnk_dest[4:0])) & strm_pkt_vld & ~mcycle_squash_d1; + +wire lsu_fwdpkt_vld_d1 ; +wire [4:0] fwdpkt_dest_d1 ; +// This delay is to compensate for the 1-cycle delay for internal rd/wr. +dff #(6) fvld_stgd1 ( + .din ({lsu_fwdpkt_vld,lsu_fwdpkt_dest[4:0]}), + .q ({lsu_fwdpkt_vld_d1,fwdpkt_dest_d1[4:0]}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// FWD PKT +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign fwdpkt_rq_vld = + (|(queue_write[4:0] & fwdpkt_dest_d1[4:0])) & + lsu_fwdpkt_vld_d1 & + ~(fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2 | // screen vld until reset can be sent. + fwdpkt_pcx_rq_sel_d3) ; // extra cycle since fwdpkt_vld is now flop delayed. + //~mcycle_squash_d1; + +// This to reset state. It must thus take into account speculative requests. +assign lsu_fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + +// INTERRUPT +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign intrpt_pcx_rq_vld = + (|(queue_write[4:0] & intrpt_l2bnk_dest[4:0])) & intrpt_pkt_vld ; + //(|(queue_write[4:0] & intrpt_l2bnk_dest[4:0])) & intrpt_pkt_vld & ~mcycle_squash_d1; + +// FFU +// fpop will never get squashed. +// ** Should be able to simplify equation. +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +//for fpop pre_qwr is good enough to qual 'cos there are no ld/st atomics to IOB +wire [4:0] fpop_q_wr ; +assign fpop_pcx_rq_vld = + //sel_qentry0[4] & fpop_l2bnk_dest[4] & fpop_pkt_vld ; + //(|(queue_write[4:0] & fpop_l2bnk_dest[4:0])) & + //(|(pre_qwr[4:0] & fpop_l2bnk_dest[4:0])) & + (|(fpop_q_wr[4:0] & fpop_l2bnk_dest[4:0])) & + // change sel_qentry0[5] to sel_qentry0[4] for fpio merge + fpop_pkt_vld ; + //fpop_pkt_vld & ((sel_qentry0[4] & fpop_pkt1) | ~fpop_pkt1) ; + //~mcycle_squash_d1 ; + + +//================================================================================================= +// HIERARCHICAL PICKER FOR PCX REQ GENERATION +//================================================================================================= + +// 13 requests to choose from : +// - imiss, 4 ld, 4 st, (intrpt,strm,fpop,fwdpkt). +// - 4 categories are thus formed, each with equal weight. +// - As a consequence, imiss has the highest priority (because it is one vs. 4 in others) +// - Fair scheduling thru round-robin is ensured between and within categories. +// - Starvation for 2-cycle b2b ops (cas/fpop) is prevented. +// - strm requests, even though they lie in the misc category, will get good +// thruput as the other misc requests will be infrequent. + +// LEVEL ONE - PICK WITHIN CATEGORIES + +// Note : picker defaults to 1-hot. + +wire [3:0] all_pcx_rq_pick ; +wire [3:0] ld_events_raw ; +//wire [3:0] ld_events_final ; +wire ld3_pcx_rq_pick,ld2_pcx_rq_pick,ld1_pcx_rq_pick,ld0_pcx_rq_pick ; + +//bug6807 - kill load events raw when partial raw is detected. +assign ld_events_raw[0] = (ld0_pkt_vld_unmasked & ~ld0_rawp_disabled) | ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2 ; +assign ld_events_raw[1] = (ld1_pkt_vld_unmasked & ~ld1_rawp_disabled) | ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2 ; +assign ld_events_raw[2] = (ld2_pkt_vld_unmasked & ~ld2_rawp_disabled) | ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2 ; +assign ld_events_raw[3] = (ld3_pkt_vld_unmasked & ~ld3_rawp_disabled) | ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2 ; + +//bug4814 - change rrobin_picker1 to rrobin_picker2 +// Choose one among 4 loads. +//lsu_rrobin_picker1 ld4_rrobin ( +// .events ({ld3_pcx_rq_vld,ld2_pcx_rq_vld, +// ld1_pcx_rq_vld,ld0_pcx_rq_vld}), +// .events_raw ({ld3_pkt_vld_unmasked,ld2_pkt_vld_unmasked, +// ld1_pkt_vld_unmasked,ld0_pkt_vld_unmasked}), +// .pick_one_hot ({ld3_pcx_rq_pick,ld2_pcx_rq_pick, +// ld1_pcx_rq_pick,ld0_pcx_rq_pick}), +// .events_final (ld_events_final[3:0]), +// .rclk (rclk), +// .grst_l (grst_l), +// .arst_l (arst_l), +// .si(), +// .se(se), +// .so() +// ); + +lsu_rrobin_picker2 ld4_rrobin ( + .events ({ld3_pcx_rq_vld,ld2_pcx_rq_vld,ld1_pcx_rq_vld,ld0_pcx_rq_vld}), + .thread_force (ld_thrd_force_vld[3:0]), + .pick_one_hot ({ld3_pcx_rq_pick,ld2_pcx_rq_pick,ld1_pcx_rq_pick,ld0_pcx_rq_pick}), + .events_picked({ld3_pcx_rq_sel,ld2_pcx_rq_sel,ld1_pcx_rq_sel,ld0_pcx_rq_sel}), + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so() + ); + + + + +//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick +//assign ld3_pcx_rq_sel = ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] ; +//assign ld2_pcx_rq_sel = ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] ; +//assign ld1_pcx_rq_sel = ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] ; +//assign ld0_pcx_rq_sel = ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] ; +//bug2705 - add spec valid qualification +//assign ld3_pcx_rq_sel = ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +//timing fix: 08/06/03 - tag_rdata->gen tag_parity_err->lsu_ld_miss_g arrives @625 in qctl1 +// cache_way_hit ->lsu_ld_miss_g arrives @525 in qctl1 +// cache_way_hit ->lsu_way_hit_or arrives @510 in qctl1 +// 625ps + ld?_l2cache_rq_g (130ps) + urq_stgpq flop logic(100ps) (slack=-100ps) +//assign ld0_spec_pick_vld_g = ld0_spec_vld_g & ld0_l2cache_rq_g & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +wire ld0_nspec_pick_vld , + ld1_nspec_pick_vld , + ld2_nspec_pick_vld , + ld3_nspec_pick_vld ; + +assign ld0_spec_pick_vld_g = ld0_spec_vld_g & ~lsu_way_hit_or & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +assign ld0_nspec_pick_vld = ~ld0_spec_vld_g & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; + +assign ld1_spec_pick_vld_g = ld1_spec_vld_g & ~lsu_way_hit_or & ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +assign ld1_nspec_pick_vld = ~ld1_spec_vld_g & ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; + +assign ld2_spec_pick_vld_g = ld2_spec_vld_g & ~lsu_way_hit_or & ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +assign ld2_nspec_pick_vld = ~ld2_spec_vld_g & ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; + +assign ld3_spec_pick_vld_g = ld3_spec_vld_g & ~lsu_way_hit_or & ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; +assign ld3_nspec_pick_vld = ~ld3_spec_vld_g & ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ; + + +assign ld0_pcx_rq_sel = (ld0_spec_pick_vld_g | ld0_nspec_pick_vld) ; +assign ld1_pcx_rq_sel = (ld1_spec_pick_vld_g | ld1_nspec_pick_vld) ; +assign ld2_pcx_rq_sel = (ld2_spec_pick_vld_g | ld2_nspec_pick_vld) ; +assign ld3_pcx_rq_sel = (ld3_spec_pick_vld_g | ld3_nspec_pick_vld) ; + +//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx +//assign ld_events_final[3] = ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign ld_events_final[2] = ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign ld_events_final[1] = ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign ld_events_final[0] = ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + + + +wire st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick ; + +// Choose one among 4 st. + +wire pcx_rq_for_stb_en; +//wire [3:0] st_events_final ; +wire [3:0] st_events_raw ; + +//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle +assign st_events_raw[0] = stb0_rd_for_pcx | st0_pcx_rq_sel_d1 | st0_pcx_rq_sel_d2 ; +assign st_events_raw[1] = stb1_rd_for_pcx | st1_pcx_rq_sel_d1 | st1_pcx_rq_sel_d2 ; +assign st_events_raw[2] = stb2_rd_for_pcx | st2_pcx_rq_sel_d1 | st2_pcx_rq_sel_d2 ; +assign st_events_raw[3] = stb3_rd_for_pcx | st3_pcx_rq_sel_d1 | st3_pcx_rq_sel_d2 ; + +//bug4814 - change rrobin_picker1 to rrobin_picker2 +//lsu_rrobin_picker1 st4_rrobin ( +// .events ({st3_pcx_rq_vld,st2_pcx_rq_vld, +// st1_pcx_rq_vld,st0_pcx_rq_vld}), +// .events_raw (st_events_raw[3:0]), +// .pick_one_hot ({st3_pcx_rq_pick,st2_pcx_rq_pick, +// st1_pcx_rq_pick,st0_pcx_rq_pick}), +// //.en (pcx_rq_for_stb_en), +// .events_final (st_events_final[3:0]), +// .rclk (rclk), +// .grst_l (grst_l), +// .arst_l (arst_l), +// .si(), +// .se(se), +// .so() +// +// ); + +lsu_rrobin_picker2 st4_rrobin ( + .events ({st3_pcx_rq_vld,st2_pcx_rq_vld,st1_pcx_rq_vld,st0_pcx_rq_vld}), + .thread_force(st_thrd_force_vld[3:0]), + .pick_one_hot ({st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick}), + + .events_picked(pcx_rq_for_stb[3:0]), + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so() + ); + + + +assign lsu_st_pcx_rq_pick[3:0] = {st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick}; +//timing fix: 9/2/03 - reduce fanout in stb_rwctl for lsu_st_pcx_rq_pick - gen separate signal for +// stb_cam_rptr_vld and stb_data_rptr_vld +assign lsu_st_pcx_rq_vld = st0_pcx_rq_vld | st1_pcx_rq_vld | st2_pcx_rq_vld | st3_pcx_rq_vld ; + +//wire st0_pcx_rq_sel_tmp, st1_pcx_rq_sel_tmp; +//wire st2_pcx_rq_sel_tmp, st3_pcx_rq_sel_tmp; + + + wire stb_cam_hit_w; + +//bug3503 +assign stb_cam_hit_w = stb_cam_hit_bf & lsu_inst_vld_w ; + +dff #(1) stb_cam_hit_stg_w2 ( + .din (stb_cam_hit_w), + .q (stb_cam_hit_w2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +//RAW read STB at W3 (not W2), so stb_cam_hit_w2 isn't critical +//assign pcx_rq_for_stb_en = ~(|lsu_st_ack_rq_stb[3:0]) & ~stb_cam_hit_w2 & ~stb_cam_wptr_vld; +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +assign pcx_rq_for_stb_en = ~stb_cam_hit_w2 & ~stb_cam_wr_no_ivld_m & ~mcycle_squash_d1 ; + +//timing fix : 5/6 - move kill_w2 after store pick +//assign pcx_rq_for_stb[3] = st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en; +//assign pcx_rq_for_stb[2] = st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en; +//assign pcx_rq_for_stb[1] = st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en; +//assign pcx_rq_for_stb[0] = st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en; + +//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick +//bug4513 - kill pcx_rq_for_stb if atomic request is picked and 2 entries to the l2bank are not available + +wire [3:0] pcx_rq_for_stb_tmp ; +wire st0_qmon_2entry_avail,st1_qmon_2entry_avail,st2_qmon_2entry_avail,st3_qmon_2entry_avail ; + +assign pcx_rq_for_stb_tmp[3] = + st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[3] & ~mcycle_squash_d1 ; + //st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[3]; + +assign pcx_rq_for_stb_tmp[2] = + st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[2] & ~mcycle_squash_d1 ; + //st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[2]; + +assign pcx_rq_for_stb_tmp[1] = + st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[1] & ~mcycle_squash_d1 ; + //st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[1]; + +assign pcx_rq_for_stb_tmp[0] = + st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[0] & ~mcycle_squash_d1 ; + //st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[0]; + +//bug4513 - kill pcx_rq_for_stb if atomic request is picked and 2 entries to the l2bank are not available +assign pcx_rq_for_stb[3] = ((st3_atomic_vld & st3_qmon_2entry_avail) | ~st3_atomic_vld) & pcx_rq_for_stb_tmp[3] ; +assign pcx_rq_for_stb[2] = ((st2_atomic_vld & st2_qmon_2entry_avail) | ~st2_atomic_vld) & pcx_rq_for_stb_tmp[2] ; +assign pcx_rq_for_stb[1] = ((st1_atomic_vld & st1_qmon_2entry_avail) | ~st1_atomic_vld) & pcx_rq_for_stb_tmp[1] ; +assign pcx_rq_for_stb[0] = ((st0_atomic_vld & st0_qmon_2entry_avail) | ~st0_atomic_vld) & pcx_rq_for_stb_tmp[0] ; + +//assign st3_pcx_rq_sel_tmp = st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] ; +//assign st2_pcx_rq_sel_tmp = st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] ; +//assign st1_pcx_rq_sel_tmp = st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] ; +//assign st0_pcx_rq_sel_tmp = st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] ; + +//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx +//assign st_events_final[3] = st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign st_events_final[2] = st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign st_events_final[1] = st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; +//assign st_events_final[0] = st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + + + +wire strm_pcx_rq_pick,fpop_pcx_rq_pick,intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick; +//wire [3:0] misc_events_final ; +wire [3:0] misc_events_raw ; + +//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle +assign misc_events_raw[0] = lsu_fwdpkt_vld_d1 | fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2 ; +//bug6807 - kill interrupt events raw when store buffer is not empty i.e. interrupt clear=0 +assign misc_events_raw[1] = (intrpt_pkt_vld_unmasked & intrpt_clr_d1) | intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2 ; +assign misc_events_raw[2] = fpop_pkt_vld_unmasked | fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 ; +assign misc_events_raw[3] = strm_pkt_vld_unmasked | strm_pcx_rq_sel_d1 | strm_pcx_rq_sel_d2 ; + + +//bug4814 - change rrobin_picker1 to rrobin_picker2 +//lsu_rrobin_picker1 misc4_rrobin ( +// .events ({strm_pcx_rq_vld,fpop_pcx_rq_vld, +// intrpt_pcx_rq_vld,fwdpkt_rq_vld}), +// .events_raw (misc_events_raw[3:0]), +// .pick_one_hot ({strm_pcx_rq_pick,fpop_pcx_rq_pick, +// intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick}), +// .events_final (misc_events_final[3:0]), +// .rclk (rclk), +// .grst_l (grst_l), +// .arst_l (arst_l), +// .si(), +// .se(se), +// .so() +// ); + +lsu_rrobin_picker2 misc4_rrobin ( + .events ({strm_pcx_rq_vld,fpop_pcx_rq_vld,intrpt_pcx_rq_vld,fwdpkt_rq_vld}), + .thread_force(misc_thrd_force_vld[3:0]), + .pick_one_hot ({strm_pcx_rq_pick,fpop_pcx_rq_pick,intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick}), + + .events_picked({strm_pcx_rq_sel,fpop_pcx_rq_sel,intrpt_pcx_rq_sel,fwdpkt_pcx_rq_sel}), + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so() + ); + + +//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick +//assign strm_pcx_rq_sel = strm_pcx_rq_pick & strm_pcx_rq_vld & all_pcx_rq_pick[3] ; +//assign fpop_pcx_rq_sel = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] ; +//assign intrpt_pcx_rq_sel = intrpt_pcx_rq_pick & intrpt_pcx_rq_vld & all_pcx_rq_pick[3] ; +//assign fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_pick & fwdpkt_rq_vld & all_pcx_rq_pick[3] ; +assign strm_pcx_rq_sel = strm_pcx_rq_pick & strm_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ; + +//11/15/03 - change fpop atomic to be same as store atomic (bug4513) +//assign fpop_pcx_rq_sel = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ; +wire fpop_qmon_2entry_avail ; +assign fpop_pcx_rq_sel_tmp = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ; +assign fpop_pcx_rq_sel = fpop_pcx_rq_sel_tmp & fpop_qmon_2entry_avail ; + +assign intrpt_pcx_rq_sel = intrpt_pcx_rq_pick & intrpt_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ; +assign fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_pick & fwdpkt_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ; + + +//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx +//assign misc_events_final[3] = lsu_spu_ldst_ack ; +//assign misc_events_final[2] = lsu_tlu_pcxpkt_ack ; +//assign misc_events_final[1] = lsu_fwdpkt_pcx_rq_sel ; +//assign misc_events_final[0] = fpop_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; + + + + +// LEVEL TWO - PICK AMONG CATEGORIES +// In parallel with level one + +wire ld_pcx_rq_all, st_pcx_rq_all, misc_pcx_rq_all ; +assign ld_pcx_rq_all = ld3_pcx_rq_vld | ld2_pcx_rq_vld | ld1_pcx_rq_vld | ld0_pcx_rq_vld ; +assign st_pcx_rq_all = st3_pcx_rq_vld | st2_pcx_rq_vld | st1_pcx_rq_vld | st0_pcx_rq_vld ; +assign misc_pcx_rq_all = strm_pcx_rq_vld | fpop_pcx_rq_vld | intrpt_pcx_rq_vld | fwdpkt_rq_vld ; + +//bug3506- raw valid used in resetting pick status +//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle + +//wire all4_rrobin_en; +//timing fix: 5/20/03 - pcx_rq_for_stb will be independent of ifu_lsu_pcxreq_d +//assign all4_rrobin_en = ~(all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) ; +//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick +//assign all4_rrobin_en = ~((all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) | imiss_pcx_rq_vld ); +//bug3348 - setting history moved from w-stage to w3-stage(1-cycle after spc_pcx_req_pq) +// and hence there are no cases to disable logging of history +//assign all4_rrobin_en = ~((all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) | imiss_pcx_rq_vld | mcycle_squash_d1); +//wire spc_pcx_req_vld_pq1 ; +//assign all4_rrobin_en = spc_pcx_req_vld_pq1 ; + +//wire [3:1] all_pcx_rq_pick_no_iqual; +wire [3:0] all_pcx_rq_pick_no_iqual; +//wire [3:0] all_pcx_pick_status_d2; // bug 3348 +//wire [3:0] all_pick_status_rst_d2; //bug 3506 +wire [3:0] all_pick_status_set; + +//bug3506: set pick status in the same cycle +assign all_pick_status_set[3] = |{ strm_pcx_rq_sel, intrpt_pcx_rq_sel,fpop_pcx_rq_sel, fwdpkt_pcx_rq_sel} ; +assign all_pick_status_set[2] = |pcx_rq_for_stb[3:0] ; +assign all_pick_status_set[1] = |{ld0_pcx_rq_sel,ld1_pcx_rq_sel,ld2_pcx_rq_sel,ld3_pcx_rq_sel} ; +assign all_pick_status_set[0] = 1'b0 ; + + + +lsu_rrobin_picker2 all4_rrobin ( + .events ({misc_pcx_rq_all,st_pcx_rq_all,ld_pcx_rq_all,1'b0}), + .thread_force(all_thrd_force_vld[3:0]), + .pick_one_hot (all_pcx_rq_pick_no_iqual[3:0]), + + .events_picked(all_pick_status_set[3:0]), + //.en (all4_rrobin_en), // bug 3348 + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so() + ); + + +// 5/22/03: cmp1_regr fail - qual all pick w/ ~mcycle_squash_d1; not doing this causes multi-hot select to +// pcx_pkt mux +assign all_pcx_rq_pick[0] = imiss_pcx_rq_vld & ~mcycle_squash_d1; +assign all_pcx_rq_pick[3:1] = all_pcx_rq_pick_no_iqual[3:1] & ~{3{imiss_pcx_rq_vld | mcycle_squash_d1}}; + +wire all_pcx_rq_dest_sel3 ; +assign all_pcx_rq_dest_sel3 = ~|all_pcx_rq_pick[2:0]; + +//timing fix: 5/20/03 - pcx_rq_for_stb will be independent of ifu_lsu_pcxreq_d +//assign imiss_pcx_rq_sel = imiss_pcx_rq_vld & all_pcx_rq_pick[0] ; +//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick +//assign imiss_pcx_rq_sel = imiss_pcx_rq_vld; +assign imiss_pcx_rq_sel = imiss_pcx_rq_vld & ~mcycle_squash_d1 ; + +//================================================================================================= + +// Select appr. load. Need a scheme which allows threads to +// make fwd progress. +/*assign ld0_pcx_rq_sel = ld0_pcx_rq_vld ; +assign ld1_pcx_rq_sel = ld1_pcx_rq_vld & ~ld0_pcx_rq_vld ; +assign ld2_pcx_rq_sel = ld2_pcx_rq_vld & ~(ld0_pcx_rq_vld | ld1_pcx_rq_vld); +assign ld3_pcx_rq_sel = ld3_pcx_rq_vld & ~(ld0_pcx_rq_vld | ld1_pcx_rq_vld | ld2_pcx_rq_vld) ; */ + +dff #(4) lrsel_stgd1 ( + .din ({ld0_pcx_rq_sel, ld1_pcx_rq_sel, ld2_pcx_rq_sel, ld3_pcx_rq_sel}), + .q ({ld0_pcx_rq_sel_d1, ld1_pcx_rq_sel_d1, ld2_pcx_rq_sel_d1, ld3_pcx_rq_sel_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug2705- kill pcx pick if spec vld kill is set +assign lsu_ld0_pcx_rq_sel_d1 = ld0_pcx_rq_sel_d1 & ~lsu_ld0_spec_vld_kill_w2 ; +assign lsu_ld1_pcx_rq_sel_d1 = ld1_pcx_rq_sel_d1 & ~lsu_ld1_spec_vld_kill_w2 ; +assign lsu_ld2_pcx_rq_sel_d1 = ld2_pcx_rq_sel_d1 & ~lsu_ld2_spec_vld_kill_w2 ; +assign lsu_ld3_pcx_rq_sel_d1 = ld3_pcx_rq_sel_d1 & ~lsu_ld3_spec_vld_kill_w2 ; + + +dff #(4) lrsel_stgd2 ( + .din ({lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1, lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1}), + .q ({ld0_pcx_rq_sel_d2, ld1_pcx_rq_sel_d2, ld2_pcx_rq_sel_d2, ld3_pcx_rq_sel_d2}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Used to complete prefetch. Be careful ! ld could be squashed. Add pcx_req_squash. +assign lsu_ld_pcx_rq_sel_d2[3] = ld3_pcx_rq_sel_d2 ; +assign lsu_ld_pcx_rq_sel_d2[2] = ld2_pcx_rq_sel_d2 ; +assign lsu_ld_pcx_rq_sel_d2[1] = ld1_pcx_rq_sel_d2 ; +assign lsu_ld_pcx_rq_sel_d2[0] = ld0_pcx_rq_sel_d2 ; + +//bug2705- kill pcx pick if spec vld kill is set +wire ld_pcxpkt_vld ; +assign ld_pcxpkt_vld = + lsu_ld0_pcx_rq_sel_d1 | lsu_ld1_pcx_rq_sel_d1 | lsu_ld2_pcx_rq_sel_d1 | lsu_ld3_pcx_rq_sel_d1 ; + //ld0_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d1 ; + +dff #(1) icindx_stgd1 ( + .din (ld_pcxpkt_vld), + .q (lsu_ifu_ld_pcxpkt_vld), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +wire [3:0] ld_pcx_rq_sel ; + +assign ld_pcx_rq_sel[0] = ld0_pcx_rq_sel_d1 | st0_atom_rq_d2 ; +assign ld_pcx_rq_sel[1] = ld1_pcx_rq_sel_d1 | st1_atom_rq_d2 ; +assign ld_pcx_rq_sel[2] = ld2_pcx_rq_sel_d1 | st2_atom_rq_d2 ; +assign ld_pcx_rq_sel[3] = ld3_pcx_rq_sel_d1 | st3_atom_rq_d2 ; + +//11/7/03: add rst_tri_en +assign lsu_ld_pcx_rq_mxsel[2:0] = ld_pcx_rq_sel[2:0] & {3{~rst_tri_en}} ; +assign lsu_ld_pcx_rq_mxsel[3] = (~|ld_pcx_rq_sel[2:0]) | rst_tri_en ; + +assign ld_pcx_thrd[0] = ld_pcx_rq_sel[1] | ld_pcx_rq_sel[3] ; +assign ld_pcx_thrd[1] = ld_pcx_rq_sel[2] | ld_pcx_rq_sel[3] ; + +// Assume a simple priority based scheme for now. +// This should not be prioritized at this point. +//assign st_pcx_rq_mhot_sel[0] = st0_pcx_rq_sel_tmp ; +//assign st_pcx_rq_mhot_sel[1] = st1_pcx_rq_sel_tmp ; +//assign st_pcx_rq_mhot_sel[2] = st2_pcx_rq_sel_tmp ; +//assign st_pcx_rq_mhot_sel[3] = st3_pcx_rq_sel_tmp ; + +/*assign st_pcx_rq_mhot_sel[0] = + ~ld_pcx_rq_vld & st0_pcx_rq_vld ; +assign st_pcx_rq_mhot_sel[1] = + ~ld_pcx_rq_vld & st1_pcx_rq_vld ; +assign st_pcx_rq_mhot_sel[2] = + ~ld_pcx_rq_vld & st2_pcx_rq_vld ; +assign st_pcx_rq_mhot_sel[3] = + ~ld_pcx_rq_vld & st3_pcx_rq_vld ;*/ + + +assign st0_pcx_rq_sel = pcx_rq_for_stb[0] ; +assign st1_pcx_rq_sel = pcx_rq_for_stb[1] ; +assign st2_pcx_rq_sel = pcx_rq_for_stb[2] ; +assign st3_pcx_rq_sel = pcx_rq_for_stb[3] ; + +//assign st_pcx_rq_vld = (|pcx_rq_for_stb[3:0]); + +// Temporary. +//assign st0_pcx_rq_sel = stb_rd_for_pcx_sel[0] ; +//assign st1_pcx_rq_sel = stb_rd_for_pcx_sel[1] ; +//assign st2_pcx_rq_sel = stb_rd_for_pcx_sel[2] ; +//assign st3_pcx_rq_sel = stb_rd_for_pcx_sel[3] ; + +// This will be on a critical path. Massage !!! +// Allows for speculative requests. +//assign st_pcx_rq_vld = +// (st0_pcx_rq_sel & stb_rd_for_pcx_sel[0]) | +// (st1_pcx_rq_sel & stb_rd_for_pcx_sel[1]) | +// (st2_pcx_rq_sel & stb_rd_for_pcx_sel[2]) | +// (st3_pcx_rq_sel & stb_rd_for_pcx_sel[3]) ; + + + +/*assign imiss_pcx_rq_sel = + imiss_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld) ; +assign strm_pcx_rq_sel = + strm_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_sel) ; +assign fpop_pcx_rq_sel = + fpop_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld) ; +assign intrpt_pcx_rq_sel = + intrpt_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | fpop_pcx_rq_sel) ; +assign fwdpkt_pcx_rq_sel = + fwdpkt_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld + | fpop_pcx_rq_sel) ; */ + + +//assign imiss_strm_pcx_rq_sel = imiss_pcx_rq_sel | strm_pcx_rq_sel ; + +// request was made with the queues full but not grant. +assign pcx_req_squash = + (|(spc_pcx_req_pq_buf2[4:0] & ~pre_qwr[4:0] & ~pcx_spc_grant_px[4:0])) ; +//(|(spc_pcx_req_pq[4:0] & ~queue_write[4:0] & ~pcx_spc_grant_px[4:0])) ; +// (|lsu_error_rst[3:0]) | // dtag parity error requires two ld pkts +// (st_atom_rq_d1) ; // cas,stq - 2 pkt requests + +//bug:2877 - dtag parity error 2nd packet request; +//wire error_rst ; + +//assign error_rst = +// (ld0_pcx_rq_sel_d1 & lsu_dtag_perror_w2[0]) | +// (ld1_pcx_rq_sel_d1 & lsu_dtag_perror_w2[1]) | +// (ld2_pcx_rq_sel_d1 & lsu_dtag_perror_w2[2]) | +// (ld3_pcx_rq_sel_d1 & lsu_dtag_perror_w2[3]) ; + +//wire error_rst_d1 ; +//dff #(1) erst_stgd1 ( +// .din (error_rst), +// .q (error_rst_d1), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +wire [3:0] dtag_perr_pkt2_vld ; +assign dtag_perr_pkt2_vld[0] = lsu_ld0_pcx_rq_sel_d1 & lsu_dtag_perror_w2[0]; +assign dtag_perr_pkt2_vld[1] = lsu_ld1_pcx_rq_sel_d1 & lsu_dtag_perror_w2[1]; +assign dtag_perr_pkt2_vld[2] = lsu_ld2_pcx_rq_sel_d1 & lsu_dtag_perror_w2[2]; +assign dtag_perr_pkt2_vld[3] = lsu_ld3_pcx_rq_sel_d1 & lsu_dtag_perror_w2[3]; + +//bug:2877 - dtag parity error 2nd packet request; flop to sync w/ ld?_pcx_rq_sel_d2 +dff #(4) ff_dtag_perr_pkt2_vld_d1 ( + .din (dtag_perr_pkt2_vld[3:0]), + .q (dtag_perr_pkt2_vld_d1[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + + +//bug:2877 - dtag parity error 2nd packet request; error_rst can be removed from mcycle_mask_d1 since +// it does not behave like an atomic i.e. it is sent as 2 separate packets. +assign mcycle_squash_d1 = + // error_rst | // dtag parity error requires two ld pkts + //(|lsu_error_rst[3:0]) | // dtag parity error requires two ld pkts + spc_pcx_atom_pq_buf2 ; // cas/fpop + +dff #(1) sqsh_stgd1 ( + .din (pcx_req_squash), + .q (pcx_req_squash_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(1) sqsh_stgd2 ( + .din (pcx_req_squash_d1), + .q (pcx_req_squash_d2), + .clk (clk), + .se (1'b0), .si (), .so () + ); +//timing fix: 9/19/03 - split the lsu_pcx_req_squash to 4 signals to stb_ctl[0-3] to reduce loading +assign lsu_pcx_req_squash = pcx_req_squash & ~st_atom_rq_d1 ; +assign lsu_pcx_req_squash0 = lsu_pcx_req_squash ; +assign lsu_pcx_req_squash1 = lsu_pcx_req_squash ; +assign lsu_pcx_req_squash2 = lsu_pcx_req_squash ; +assign lsu_pcx_req_squash3 = lsu_pcx_req_squash ; + +assign lsu_pcx_req_squash_d1 = pcx_req_squash_d1 ; + +dff #(5) rsel_stgd1 ( + //.din ({imiss_strm_pcx_rq_sel, + .din ({ + imiss_pcx_rq_sel, strm_pcx_rq_sel, intrpt_pcx_rq_sel, fpop_pcx_rq_sel, + fwdpkt_pcx_rq_sel}), + //.q ({imiss_strm_pcx_rq_sel_d1, + .q ({ + imiss_pcx_rq_sel_d1, strm_pcx_rq_sel_d1, intrpt_pcx_rq_sel_d1,fpop_pcx_rq_sel_d1, + fwdpkt_pcx_rq_sel_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_imiss_pcx_rq_sel_d1 = imiss_pcx_rq_sel_d1; + +dff imrqs_stgd2 ( + .din (imiss_pcx_rq_sel_d1), + .q (imiss_pcx_rq_sel_d2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff fwdrqs_stgd2 ( + .din (fwdpkt_pcx_rq_sel_d1), + .q (fwdpkt_pcx_rq_sel_d2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff fwdrqs_stgd3 ( + .din (fwdpkt_pcx_rq_sel_d2), + .q (fwdpkt_pcx_rq_sel_d3), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff fpop_stgd2 ( + .din (fpop_pcx_rq_sel_d1), .q (fpop_pcx_rq_sel_d2), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug4665: add sehold to pcx_pkt_src_sel[1] +//wire ld_pcx_rq_sel_d1,st_pcx_rq_sel_d1,misc_pcx_rq_sel_d1; +wire ld_pcx_rq_sel_d1,st_pcx_rq_sel_d1; +wire all_pcx_rq_pick_b2 ; +assign all_pcx_rq_pick_b2 = sehold ? st_pcx_rq_sel_d1 : all_pcx_rq_pick[2] ; + +dff #(2) pick_stgd1 ( + .din ({all_pcx_rq_pick_b2, all_pcx_rq_pick[1]}), + .q ({st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}), + //.din ({all_pcx_rq_pick[3], all_pcx_rq_pick_b2, all_pcx_rq_pick[1]}), + //.q ({misc_pcx_rq_sel_d1,st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}), + //.din (all_pcx_rq_pick[2:1]), .q ({st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// add other sources in such as interrupt and fpop. +//bug:2877 - dtag parity error 2nd packet request; remove error_rst_d1 since dtag parity error does not +// behave as an atomic +//assign pcx_pkt_src_sel[0] = ld_pcx_rq_sel_d1 | st_cas_rq_d2 | error_rst_d1 ; + +//11/7/03 - add rst_tri_en +wire [3:0] pcx_pkt_src_sel_tmp ; +assign pcx_pkt_src_sel_tmp[0] = ld_pcx_rq_sel_d1 | st_cas_rq_d2 ; +assign pcx_pkt_src_sel_tmp[1] = st_pcx_rq_sel_d1 ; +assign pcx_pkt_src_sel_tmp[2] = ~|{pcx_pkt_src_sel[3],pcx_pkt_src_sel[1:0]}; + //imiss_strm_pcx_rq_sel_d1 ; +assign pcx_pkt_src_sel_tmp[3] = fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 | + fwdpkt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d1 ; + +//bug4888 - change rst_tri_en to select b[1] instead of b[3] + +assign pcx_pkt_src_sel[3:2] = pcx_pkt_src_sel_tmp[3:2] & {2{~rst_tri_en}} ; +assign pcx_pkt_src_sel[1] = pcx_pkt_src_sel_tmp[1] | rst_tri_en ; +assign pcx_pkt_src_sel[0] = pcx_pkt_src_sel_tmp[0] & ~rst_tri_en ; + +//assign dest_pkt_sel[0] = ld_pcx_rq_vld ; +//assign dest_pkt_sel[1] = st_pcx_rq_vld ; +//assign dest_pkt_sel[2] = ~(ld_pcx_rq_vld | st_pcx_rq_vld); + +//================================================================================================= +// SELECT DESTINATION +//================================================================================================= + +// Select dest for load. +mux4ds #(5) ldsel_dest ( + .in0 (ld0_l2bnk_dest[4:0]), + .in1 (ld1_l2bnk_dest[4:0]), + .in2 (ld2_l2bnk_dest[4:0]), + .in3 (ld3_l2bnk_dest[4:0]), + .sel0 (ld0_pcx_rq_pick), + .sel1 (ld1_pcx_rq_pick), + .sel2 (ld2_pcx_rq_pick), + .sel3 (ld3_pcx_rq_pick), + .dout (ld_pkt_dest[4:0]) +); + +// Select dest for store +mux4ds #(5) stsel_dest ( + .in0 (st0_l2bnk_dest[4:0]), + .in1 (st1_l2bnk_dest[4:0]), + .in2 (st2_l2bnk_dest[4:0]), + .in3 (st3_l2bnk_dest[4:0]), + .sel0 (st0_pcx_rq_pick), + .sel1 (st1_pcx_rq_pick), + .sel2 (st2_pcx_rq_pick), + .sel3 (st3_pcx_rq_pick), + .dout (st_pkt_dest[4:0]) +); + +wire [4:0] misc_pkt_dest ; +mux4ds #(5) miscsel_dest ( + .in0 (strm_l2bnk_dest[4:0]), + .in1 (fpop_l2bnk_dest[4:0]), + .in2 (intrpt_l2bnk_dest[4:0]), + .in3 (fwdpkt_dest_d1[4:0]), + .sel0 (strm_pcx_rq_pick), + .sel1 (fpop_pcx_rq_pick), + .sel2 (intrpt_pcx_rq_pick), + .sel3 (fwdpkt_pcx_rq_pick), + .dout (misc_pkt_dest[4:0]) +); + +// This is temporary until the req/ack path is restructured +/*assign imiss_strm_pkt_dest[4:0] = + imiss_pcx_rq_sel ? imiss_l2bnk_dest[4:0] : + strm_pcx_rq_sel ? strm_l2bnk_dest[4:0] : + fpop_pcx_rq_sel ? fpop_l2bnk_dest[4:0] : + intrpt_pcx_rq_sel ? intrpt_l2bnk_dest[4:0] : + lsu_fwdpkt_dest[4:0] ; */ + +/* +// This needs to be replaced with structural mux once rq/ack resolved. +mux4ds #(5) istrmsel_dest ( + .in0 (imiss_l2bnk_dest[4:0]), + .in1 (strm_l2bnk_dest[4:0]), + .in2 (fpop_l2bnk_dest[4:0]), + .in3 (intrpt_l2bnk_dest[4:0]), + .sel0 (imiss_pcx_rq_sel), + .sel1 (strm_pcx_rq_sel), + .sel2 (fpop_pcx_rq_sel), + .sel3 (intrpt_pcx_rq_sel), + .dout (imiss_strm_pkt_dest[4:0]) +); +*/ + +mux4ds #(5) sel_final_dest ( + .in0 (imiss_l2bnk_dest[4:0]), + .in1 (ld_pkt_dest[4:0]), + .in2 (st_pkt_dest[4:0]), + .in3 (misc_pkt_dest[4:0]), + .sel0 (all_pcx_rq_pick[0]), + .sel1 (all_pcx_rq_pick[1]), + .sel2 (all_pcx_rq_pick[2]), + .sel3 (all_pcx_rq_dest_sel3), + //.sel3 (all_pcx_rq_pick[3]), + .dout (current_pkt_dest[4:0]) +); + +/*mux3ds #(5) sel_dest ( + .in0 (ld_pkt_dest[4:0]), + .in1 (st_pkt_dest[4:0]), + .in2 (imiss_strm_pkt_dest[4:0]), + .sel0 (dest_pkt_sel[0]), + .sel1 (dest_pkt_sel[1]), + .sel2 (dest_pkt_sel[2]), + .dout (current_pkt_dest[4:0]) +);*/ + +wire pcx_rq_sel ; +assign pcx_rq_sel = + ld0_pcx_rq_sel | ld1_pcx_rq_sel | ld2_pcx_rq_sel | ld3_pcx_rq_sel | + st0_pcx_rq_sel | st1_pcx_rq_sel | st2_pcx_rq_sel | st3_pcx_rq_sel | + imiss_pcx_rq_sel | strm_pcx_rq_sel | fpop_pcx_rq_sel | intrpt_pcx_rq_sel | + fwdpkt_pcx_rq_sel ; + +assign spc_pcx_req_g[4:0] = + (current_pkt_dest[4:0] & {5{pcx_rq_sel}}) ; + //(current_pkt_dest[4:0] & + //{5{(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld | fpop_atom_req | fwdpkt_rq_vld)}}) ; + +//timing fix: 9/19/03 - instantiate buffer for spc_pcx_req_pq +wire [4:0] spc_pcx_req_pq_tmp ; +dff #(5) rq_stgpq ( + .din (spc_pcx_req_g[4:0]), .q (spc_pcx_req_pq_tmp[4:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +bw_u1_buf_30x UZfix_spc_pcx_req_pq0_buf1 ( .a(spc_pcx_req_pq_tmp[0]), .z(spc_pcx_req_pq[0]) ); +bw_u1_buf_30x UZfix_spc_pcx_req_pq1_buf1 ( .a(spc_pcx_req_pq_tmp[1]), .z(spc_pcx_req_pq[1]) ); +bw_u1_buf_30x UZfix_spc_pcx_req_pq2_buf1 ( .a(spc_pcx_req_pq_tmp[2]), .z(spc_pcx_req_pq[2]) ); +bw_u1_buf_30x UZfix_spc_pcx_req_pq3_buf1 ( .a(spc_pcx_req_pq_tmp[3]), .z(spc_pcx_req_pq[3]) ); +bw_u1_buf_30x UZfix_spc_pcx_req_pq4_buf1 ( .a(spc_pcx_req_pq_tmp[4]), .z(spc_pcx_req_pq[4]) ); + +bw_u1_buf_30x UZsize_spc_pcx_req_pq0_buf2 ( .a(spc_pcx_req_pq_tmp[0]), .z(spc_pcx_req_pq_buf2[0]) ); +bw_u1_buf_30x UZsize_spc_pcx_req_pq1_buf2 ( .a(spc_pcx_req_pq_tmp[1]), .z(spc_pcx_req_pq_buf2[1]) ); +bw_u1_buf_30x UZsize_spc_pcx_req_pq2_buf2 ( .a(spc_pcx_req_pq_tmp[2]), .z(spc_pcx_req_pq_buf2[2]) ); +bw_u1_buf_30x UZsize_spc_pcx_req_pq3_buf2 ( .a(spc_pcx_req_pq_tmp[3]), .z(spc_pcx_req_pq_buf2[3]) ); +bw_u1_buf_30x UZsize_spc_pcx_req_pq4_buf2 ( .a(spc_pcx_req_pq_tmp[4]), .z(spc_pcx_req_pq_buf2[4]) ); + +//bug3348 - not needed +//wire spc_pcx_req_vld_pq ; +//assign spc_pcx_req_vld_pq = |spc_pcx_req_pq[4:0]; +// +//dff #(1) rq_stgpq1 ( +// .din (spc_pcx_req_vld_pq), .q (spc_pcx_req_vld_pq1), +// .clk (clk), +// .se (1'b0), .si (), .so () +// ); + +assign spc_pcx_req_update_g[4:0] = + (st_atom_rq_d1 | fpop_atom_rq_pq) ? + spc_pcx_req_pq_buf2[4:0] : // Recirculate same request if back to back case - stda, cas etc + (current_pkt_dest[4:0] & + {5{pcx_rq_sel}}) ; + //{5{(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld | fpop_pcx_rq_vld | fwdpkt_rq_vld)}}) ; + // Standard request + +dff #(5) urq_stgpq ( + .din (spc_pcx_req_update_g[4:0]), .q (spc_pcx_req_update_w2[4:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//================================================================================================= +// 2-CYCLE OP HANDLING +//================================================================================================= + +// cas,fpop,dtag-error pkt. dtag-error pkt does not have to be b2b. +// prevent starvation, ensure requests are b2b. +// fpop can only request to fpu.(bit4) cas can only request to L2 (b3:0) +// ** error rst needs to be handled correctly. + +// ** This needs to be massaged for timing. +// timing fix: 5/7/03 - delay the mask 1 cycle for stores. +wire [3:0] mcycle_mask_qwr ; +wire [4:0] mcycle_mask_qwr_d1 ; +//assign mcycle_mask_qwr[3:0] = +// ({4{(stb0_rd_for_pcx & st0_atomic_vld)}} & st0_l2bnk_dest[3:0]) | +// ({4{(stb1_rd_for_pcx & st1_atomic_vld)}} & st1_l2bnk_dest[3:0]) | +// ({4{(stb2_rd_for_pcx & st2_atomic_vld)}} & st2_l2bnk_dest[3:0]) | +// ({4{(stb3_rd_for_pcx & st3_atomic_vld)}} & st3_l2bnk_dest[3:0]) ; + + +//bug4513- kill the atomic store pcx req in this cycle if only 1 entry is available - +// atomic packets have to be sent b2bto pcx. +// +// ex. thread0 to l2 bank0 atomic store - w/ only 1 bank0 entry available +//--------------------------------------------------------------------------------- +// 1 2 3 4 5 6 7 +//--------------------------------------------------------------------------------- +// st0_atomic_vld-------------->1 +// pcx_rq_for_stb_tmp[0]------->1 +// pcx_rq_for_stb[0]----------->0 1 +// st0_qmon_2entry_avail------->0 1 +//--------------------------------------------------------------------------------- +// st0_atomic_pend------------->1 0 +// st0_atomic_pend_d1------------------>1 0 +// mcycle_mask_qwr_d1[0]--------------->1 0 +//--------------------------------------------------------------------------------- + + +assign st0_qmon_2entry_avail = |(st0_l2bnk_dest[3:0] & sel_qentry0[3:0]) ; +assign st1_qmon_2entry_avail = |(st1_l2bnk_dest[3:0] & sel_qentry0[3:0]) ; +assign st2_qmon_2entry_avail = |(st2_l2bnk_dest[3:0] & sel_qentry0[3:0]) ; +assign st3_qmon_2entry_avail = |(st3_l2bnk_dest[3:0] & sel_qentry0[3:0]) ; +assign fpop_qmon_2entry_avail = fpop_l2bnk_dest[4] & sel_qentry0[4] ; + + +//bug4513 - when atomic is picked, if 2 entries are not free, kill all requests until 2entries are free +wire st0_atomic_pend, st1_atomic_pend, st2_atomic_pend, st3_atomic_pend ; + +assign st0_atomic_pend = (pcx_rq_for_stb_tmp[0] & st0_atomic_vld & ~st0_qmon_2entry_avail) | //set + (st0_atomic_pend_d1 & ~st0_qmon_2entry_avail) ; //recycle/reset + +assign st1_atomic_pend = (pcx_rq_for_stb_tmp[1] & st1_atomic_vld & ~st1_qmon_2entry_avail) | //set + (st1_atomic_pend_d1 & ~st1_qmon_2entry_avail) ; //recycle/reset + +assign st2_atomic_pend = (pcx_rq_for_stb_tmp[2] & st2_atomic_vld & ~st2_qmon_2entry_avail) | //set + (st2_atomic_pend_d1 & ~st2_qmon_2entry_avail) ; //recycle/reset + +assign st3_atomic_pend = (pcx_rq_for_stb_tmp[3] & st3_atomic_vld & ~st3_qmon_2entry_avail) | //set + (st3_atomic_pend_d1 & ~st3_qmon_2entry_avail) ; //recycle/reset + +dff #(4) ff_st0to3_atomic_pend_d1 ( + .din ({st3_atomic_pend,st2_atomic_pend,st1_atomic_pend,st0_atomic_pend}), + .q ({st3_atomic_pend_d1,st2_atomic_pend_d1,st1_atomic_pend_d1,st0_atomic_pend_d1}), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +//bug4513 - kill all requests after atomic if 2 entries to the bank are not available +assign mcycle_mask_qwr[3:0] = + ({4{st0_atomic_pend}} & st0_l2bnk_dest[3:0]) | + ({4{st1_atomic_pend}} & st1_l2bnk_dest[3:0]) | + ({4{st2_atomic_pend}} & st2_l2bnk_dest[3:0]) | + ({4{st3_atomic_pend}} & st3_l2bnk_dest[3:0]) ; + +//11/15/03 - change fpop atomic to be same as store atomic (bug4513) +//assign mcycle_mask_qwr[4] = fpop_pkt_vld | fpop_pcx_rq_sel_d1 ; + +wire fpop_atomic_pend, fpop_atomic_pend_d1 ; + + +assign fpop_atomic_pend = (fpop_pcx_rq_sel_tmp & ~fpop_qmon_2entry_avail) | + (fpop_atomic_pend_d1 & ~fpop_qmon_2entry_avail) ; + +assign fpop_q_wr[4:0] = fpop_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ; + +dff #(1) ff_fpop_atomic_pend_d1 ( + .din (fpop_atomic_pend), + .q (fpop_atomic_pend_d1), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +dff #(5) ff_mcycle_mask_qwr_b4to0 ( + .din ({fpop_atomic_pend,mcycle_mask_qwr[3:0]}), + .q (mcycle_mask_qwr_d1[4:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + + +// PCX REQUEST GENERATION (END) +//************************************************************************************************* + +//================================================================================================= +// +// CPX Packet Processing +// +//================================================================================================= + + +// D-SIDE PROCESSING + +/*input [3:0] lsu_cpx_pkt_rqtype ; +input lsu_cpx_pkt_vld ;*/ + +// non-cacheables are processed at the head of the dfq. +// cpx_ld_type may not have to factor in strm load. + +//================================================================================================= +// +// PCX Queue Control +// +//================================================================================================= + +//timing fix: 5/7/03 - delay mask 1 cycle for stores +//11/15/03 - change fpop atomic to be same as store atomic (bug4513) +//assign queue_write[4:0] = pre_qwr[4:0] & ~{mcycle_mask_qwr[4],mcycle_mask_qwr_d1[3:0]} ; +assign queue_write[4:0] = pre_qwr[4:0] & ~mcycle_mask_qwr_d1[4:0] ; + +//bug4513 - mcycle_mask_qwr will kill all requests other than stores. stores can be killed +// by fpop atomics +//11/14/03- fox for bug4513 was incorrect ; st_queue_write[3:0] not needed 'cos st[0-3]_q_wr +// has been changed to use st0_atomic_pend instead of st0_atomic_vld +//assign st_queue_write[4] = pre_qwr[4] & ~mcycle_mask_qwr[4] ; +//assign st_queue_write[3:0] = pre_qwr[3:0] ; + +//assign queue_write[4:0] = pre_qwr[4:0] & ~mcycle_mask_qwr[4:0] ; // timing fix +// assign queue_write[4:0] = pre_qwr[4:0] ; + +// PCX Queue Control +// - qctl tracks 2-input queue state for each of 6 destinations +// through grant signals available from pcx. + +// L2 Bank0 Queue Monitor +lsu_pcx_qmon l2bank0_qmon ( + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so(), + .send_by_pcx (pcx_spc_grant_px[0]), + .send_to_pcx (spc_pcx_req_update_w2[0]), + //.qwrite (queue_write[0]), + .qwrite (pre_qwr[0]), + .sel_qentry0 (sel_qentry0[0]) +); + +// L2 Bank1 Queue Monitor +lsu_pcx_qmon l2bank1_qmon ( + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so(), + .send_by_pcx (pcx_spc_grant_px[1]), + .send_to_pcx (spc_pcx_req_update_w2[1]), + //.qwrite (queue_write[1]), + .qwrite (pre_qwr[1]), + .sel_qentry0 (sel_qentry0[1]) +); + +// L2 Bank2 Queue Monitor +lsu_pcx_qmon l2bank2_qmon ( + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so(), + .send_by_pcx (pcx_spc_grant_px[2]), + .send_to_pcx (spc_pcx_req_update_w2[2]), + //.qwrite (queue_write[2]), + .qwrite (pre_qwr[2]), + .sel_qentry0 (sel_qentry0[2]) +); + +// L2 Bank3 Queue Monitor +lsu_pcx_qmon l2bank3_qmon ( + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so(), + .send_by_pcx (pcx_spc_grant_px[3]), + .send_to_pcx (spc_pcx_req_update_w2[3]), + //.qwrite (queue_write[3]), + .qwrite (pre_qwr[3]), + .sel_qentry0 (sel_qentry0[3]) +); + +// FP/IO Bridge Queue Monitor +lsu_pcx_qmon fpiobridge_qmon ( + .rclk (rclk), + .grst_l (grst_l), + .arst_l (arst_l), + .si(), + .se(se), + .so(), + .send_by_pcx (pcx_spc_grant_px[4]), + .send_to_pcx (spc_pcx_req_update_w2[4]), + //.qwrite (queue_write[4]), + .qwrite (pre_qwr[4]), + .sel_qentry0 (sel_qentry0[4]) +); + + + + +// 5/13/03: timing fix for lsu_dtag_perror_w2 thru st_pick +wire [3:0] error_en; +wire [3:0] error_rst_thrd; + +//assign error_en[0] = lmq_enable[0] | (lsu_cpx_pkt_atm_st_cmplt & dcfill_active_e & dfq_byp_sel[0]); +assign error_en[0] = lsu_ld_inst_vld_g[0]; +assign error_en[1] = lsu_ld_inst_vld_g[1]; +assign error_en[2] = lsu_ld_inst_vld_g[2]; +assign error_en[3] = lsu_ld_inst_vld_g[3]; + +//assign error_rst_thrd[0] = reset | (lsu_ld0_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ; +//assign error_rst_thrd[1] = reset | (lsu_ld1_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ; +//assign error_rst_thrd[2] = reset | (lsu_ld2_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ; +//assign error_rst_thrd[3] = reset | (lsu_ld3_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ; + +// reset moved to d2 'cos if 1st pkt is speculative and grant=0, error should not be reset. +//bug4512 - stb_full_raw has to be qual w/ ld[0-3] inst_vld_w2 +// also, need to qualify stb_full_raw w/ fp loads i.e. dont reset error if full raw is for fp double loads +assign error_rst_thrd[0] = reset | (ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1) + | (ld0_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread0_w2) ; // Bug4512 + //| (ld_stb_full_raw_w2 & thread0_w2) ; // Bug 4361 + +assign error_rst_thrd[1] = reset | (ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1) + | (ld1_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread1_w2) ; + +assign error_rst_thrd[2] = reset | (ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1) + | (ld2_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread2_w2) ; + +assign error_rst_thrd[3] = reset | (ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1) + | (ld3_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread3_w2) ; + +//assign lsu_error_rst[3:0] = error_rst[3:0]; + +wire dtag_perror3,dtag_perror2,dtag_perror1,dtag_perror0; + +// Thread 0 +dffre #(1) error_t0 ( + .din (lsu_dcache_tag_perror_g), + .q (dtag_perror0), + .rst (error_rst_thrd[0]), .en (error_en[0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread 1 +dffre #(1) error_t1 ( + .din (lsu_dcache_tag_perror_g), + .q (dtag_perror1), + .rst (error_rst_thrd[1]), .en (error_en[1]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread 2 +dffre #(1) error_t2 ( + .din (lsu_dcache_tag_perror_g), + .q (dtag_perror2), + .rst (error_rst_thrd[2]), .en (error_en[2]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +// Thread 3 +dffre #(1) error_t3 ( + .din (lsu_dcache_tag_perror_g), + .q (dtag_perror3), + .rst (error_rst_thrd[3]), .en (error_en[3]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign lsu_dtag_perror_w2[3] = dtag_perror3 ; +assign lsu_dtag_perror_w2[2] = dtag_perror2 ; +assign lsu_dtag_perror_w2[1] = dtag_perror1 ; +assign lsu_dtag_perror_w2[0] = dtag_perror0 ; + +// Determine if ld pkt requires correction due to dtag parity error. +assign lsu_pcx_ld_dtag_perror_w2 = + ld_pcx_rq_sel[0] ? dtag_perror0 : + ld_pcx_rq_sel[1] ? dtag_perror1 : + ld_pcx_rq_sel[2] ? dtag_perror2 : dtag_perror3 ; + + +//================================================================================================= +// +// THREAD RETRY DETECTION (picker related logic) +// +//================================================================================================= + +//bug4814 - move pick_staus out of picker and reset pick status when all 12 valid requests have +// is picked and not squashed. + +assign ld_thrd_pick_din[0] = ld_thrd_pick_status[0] | (ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign ld_thrd_pick_din[1] = ld_thrd_pick_status[1] | (ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign ld_thrd_pick_din[2] = ld_thrd_pick_status[2] | (ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign ld_thrd_pick_din[3] = ld_thrd_pick_status[3] | (ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; + +assign ld_thrd_pick_rst = ~|(ld_events_raw[3:0] & ~ld_thrd_pick_din[3:0]) ; + +assign ld_thrd_pick_status_din[3:0] = ld_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ; +//assign ld_thrd_pick_status_din[3:0] = ld_thrd_pick_din[3:0] & ~{4{ld_thrd_pick_rst}} ; + +assign st_thrd_pick_din[0] = st_thrd_pick_status[0] | (st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign st_thrd_pick_din[1] = st_thrd_pick_status[1] | (st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign st_thrd_pick_din[2] = st_thrd_pick_status[2] | (st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign st_thrd_pick_din[3] = st_thrd_pick_status[3] | (st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; + +assign st_thrd_pick_rst = ~|(st_events_raw[3:0] & ~st_thrd_pick_din[3:0]) ; +assign st_thrd_pick_status_din[3:0] = st_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ; +//assign st_thrd_pick_status_din[3:0] = st_thrd_pick_din[3:0] & ~{4{st_thrd_pick_rst}} ; + +assign misc_thrd_pick_din[3] = misc_thrd_pick_status[3] | lsu_spu_ldst_ack ; +assign misc_thrd_pick_din[2] = misc_thrd_pick_status[2] | (fpop_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ; +assign misc_thrd_pick_din[1] = misc_thrd_pick_status[1] | lsu_tlu_pcxpkt_ack ; +assign misc_thrd_pick_din[0] = misc_thrd_pick_status[0] | lsu_fwdpkt_pcx_rq_sel ; + +assign misc_thrd_pick_rst = ~|(misc_events_raw[3:0] & ~misc_thrd_pick_din[3:0]) ; + +assign misc_thrd_pick_status_din[3:0] = misc_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ; +//assign misc_thrd_pick_status_din[3:0] = misc_thrd_pick_din[3:0] & ~{4{misc_thrd_pick_rst}} ; + +assign all_thrd_pick_rst = ld_thrd_pick_rst & st_thrd_pick_rst & misc_thrd_pick_rst ; + + +dff #(4) ff_ld_thrd_force( + .din (ld_thrd_pick_status_din[3:0]), + .q (ld_thrd_pick_status[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) ff_st_thrd_force( + .din (st_thrd_pick_status_din[3:0]), + .q (st_thrd_pick_status[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +dff #(4) ff_misc_thrd_force( + .din (misc_thrd_pick_status_din[3:0]), + .q (misc_thrd_pick_status[3:0]), + .clk (clk), + .se (1'b0), .si (), .so () + ); + +assign ld_thrd_force_d1[3:0] = ~ld_thrd_pick_status[3:0] ; +assign st_thrd_force_d1[3:0] = ~st_thrd_pick_status[3:0] ; +assign misc_thrd_force_d1[3:0] = ~misc_thrd_pick_status[3:0] ; + +assign ld_thrd_force_vld[0] = ld_thrd_force_d1[0] & + ~(ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2) ; + +assign ld_thrd_force_vld[1] = ld_thrd_force_d1[1] & + ~(ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2) ; + +assign ld_thrd_force_vld[2] = ld_thrd_force_d1[2] & + ~(ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2) ; + +assign ld_thrd_force_vld[3] = ld_thrd_force_d1[3] & + ~(ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2) ; + + +// force valid to store picker if 1 entry is free and if it not picked in d1/d2 +assign st_thrd_force_vld[0] = st_thrd_force_d1[0] & + ~(st0_pcx_rq_sel_d1 | st0_pcx_rq_sel_d2) ; + +assign st_thrd_force_vld[1] = st_thrd_force_d1[1] & + ~(st1_pcx_rq_sel_d1 | st1_pcx_rq_sel_d2) ; + +assign st_thrd_force_vld[2] = st_thrd_force_d1[2] & + ~(st2_pcx_rq_sel_d1 | st2_pcx_rq_sel_d2) ; + +assign st_thrd_force_vld[3] = st_thrd_force_d1[3] & + ~(st3_pcx_rq_sel_d1 | st3_pcx_rq_sel_d2) ; + + + +// force valid to misc picker if 1 entry is free and if it is not picked in d1/d2 +assign misc_thrd_force_vld[0] = misc_thrd_force_d1[0] & + ~(fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2) ; + +assign misc_thrd_force_vld[1] = misc_thrd_force_d1[1] & + ~(intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2); + +assign misc_thrd_force_vld[2] = misc_thrd_force_d1[2] & + ~(fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2) ; + +assign misc_thrd_force_vld[3] = misc_thrd_force_d1[3] & + ~(strm_pcx_rq_sel_d1 | strm_pcx_rq_sel_d2) ; + +//2nd level pick thread force - force only req are valid and l2bnk is free +assign all_thrd_force_vld[0] = 1'b0 ; + +assign all_thrd_force_vld[1] = + |(ld_thrd_force_vld[3:0] & + {ld3_pcx_rq_vld,ld2_pcx_rq_vld,ld1_pcx_rq_vld,ld0_pcx_rq_vld}) ; + +assign all_thrd_force_vld[2] = + |(st_thrd_force_vld[3:0] & + {st3_pcx_rq_vld,st2_pcx_rq_vld,st1_pcx_rq_vld,st0_pcx_rq_vld}) ; + +assign all_thrd_force_vld[3] = + |(misc_thrd_force_vld[3:0] & + {strm_pcx_rq_vld,fpop_pcx_rq_vld,intrpt_pcx_rq_vld,fwdpkt_rq_vld}) ; + + +endmodule Index: trunk/hdl/rtl/s1_top/s1_top.v =================================================================== --- trunk/hdl/rtl/s1_top/s1_top.v (nonexistent) +++ trunk/hdl/rtl/s1_top/s1_top.v (revision 4) @@ -0,0 +1,322 @@ +/* + * Simply RISC S1 Core Top-Level + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This block implements the top-level of the S1 Core. + * It is just a schematic with four instances: + * 1) one single SPARC Core of the OpenSPARC T1; + * 2) a SPARC Core to Wishbone Master bridge; + * 3) a Reset Controller; + * 4) an Interrupt Controller. + * + */ + +`include "s1_defs.h" + +module s1_top ( + sys_clock_i, sys_reset_i, sys_irq_i, + wbm_ack_i, wbm_data_i, + wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o + ); + + /* + * Inputs + */ + + // System inputs + input sys_clock_i; // System Clock + input sys_reset_i; // System Reset + input[63:0] sys_irq_i; // Interrupt Requests + + // Wishbone Interconnect Master Interface inputs + input wbm_ack_i; // Ack + input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In + + /* + * Outputs + */ + + // Wishbone Interconnect Master Interface outputs + output wbm_cycle_o; // Cycle Start + output wbm_strobe_o; // Strobe Request + output wbm_we_o; // Write Enable + output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus + output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out + output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output + + /* + * Wires + */ + + // Wires connected to SPARC Core outputs + + // pcx + wire [4:0] spc_pcx_req_pq; // processor to pcx request + wire spc_pcx_atom_pq; // processor to pcx atomic request + wire [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet + + // shadow scan + wire spc_sscan_so; // From ifu of sparc_ifu.v + wire spc_scanout0; // From test_stub of test_stub_bist.v + wire spc_scanout1; // From test_stub of test_stub_bist.v + + // bist + wire tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v + wire tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v + + // fuse + wire spc_efc_ifuse_data; // From ifu of sparc_ifu.v + wire spc_efc_dfuse_data; // From ifu of sparc_ifu.v + + // Wires connected to SPARC Core inputs + + // cpx interface + wire [4:0] pcx_spc_grant_px; // pcx to processor grant info + wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc + wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet + wire wbm_spc_stallreq; // Stall request + + wire [3:0] const_cpuid; + wire [7:0] const_maskid; // To ifu of sparc_ifu.v + + // sscan + wire ctu_tck; // To ifu of sparc_ifu.v + wire ctu_sscan_se; // To ifu of sparc_ifu.v + wire ctu_sscan_snap; // To ifu of sparc_ifu.v + wire [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v + + // bist + wire ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v + + // efuse + wire efc_spc_fuse_clk1; + wire efc_spc_fuse_clk2; + wire efc_spc_ifuse_ashift; + wire efc_spc_ifuse_dshift; + wire efc_spc_ifuse_data; + wire efc_spc_dfuse_ashift; + wire efc_spc_dfuse_dshift; + wire efc_spc_dfuse_data; + + // scan and macro test + wire ctu_tst_macrotest; // To test_stub of test_stub_bist.v + wire ctu_tst_scan_disable; // To test_stub of test_stub_bist.v + wire ctu_tst_short_chain; // To test_stub of test_stub_bist.v + wire global_shift_enable; // To test_stub of test_stub_two_bist.v + wire ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v + wire spc_scanin0; + wire spc_scanin1; + + // clk + wire cluster_cken; // To spc_hdr of cluster_header.v + wire gclk; // To spc_hdr of cluster_header.v + + // reset + wire cmp_grst_l; + wire cmp_arst_l; + wire ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v + + wire adbginit_l; // To spc_hdr of cluster_header.v + wire gdbginit_l; // To spc_hdr of cluster_header.v + + // Reset signal from the reset controller to the bridge + wire sys_reset_final; + + // Interrupt Source from the interrupt controller to the bridge + wire[5:0] sys_interrupt_source; + + /* + * SPARC Core module instance + */ + + sparc sparc_0 ( + + // Wires connected to SPARC Core outputs + .spc_pcx_req_pq(spc_pcx_req_pq), + .spc_pcx_atom_pq(spc_pcx_atom_pq), + .spc_pcx_data_pa(spc_pcx_data_pa), + .spc_sscan_so(spc_sscan_so), + .spc_scanout0(spc_scanout0), + .spc_scanout1(spc_scanout1), + .tst_ctu_mbist_done(tst_ctu_mbist_done), + .tst_ctu_mbist_fail(tst_ctu_mbist_fail), + .spc_efc_ifuse_data(spc_efc_ifuse_data), + .spc_efc_dfuse_data(spc_efc_dfuse_data), + + // Wires connected to SPARC Core inputs + .pcx_spc_grant_px(pcx_spc_grant_px), + .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2), + .cpx_spc_data_cx2(cpx_spc_data_cx2), + .wbm_spc_stallreq(wbm_spc_stallreq), + .const_cpuid(const_cpuid), + .const_maskid(const_maskid), + .ctu_tck(ctu_tck), + .ctu_sscan_se(ctu_sscan_se), + .ctu_sscan_snap(ctu_sscan_snap), + .ctu_sscan_tid(ctu_sscan_tid), + .ctu_tst_mbist_enable(ctu_tst_mbist_enable), + .efc_spc_fuse_clk1(efc_spc_fuse_clk1), + .efc_spc_fuse_clk2(efc_spc_fuse_clk2), + .efc_spc_ifuse_ashift(efc_spc_ifuse_ashift), + .efc_spc_ifuse_dshift(efc_spc_ifuse_dshift), + .efc_spc_ifuse_data(efc_spc_ifuse_data), + .efc_spc_dfuse_ashift(efc_spc_dfuse_ashift), + .efc_spc_dfuse_dshift(efc_spc_dfuse_dshift), + .efc_spc_dfuse_data(efc_spc_dfuse_data), + .ctu_tst_macrotest(ctu_tst_macrotest), + .ctu_tst_scan_disable(ctu_tst_scan_disable), + .ctu_tst_short_chain(ctu_tst_short_chain), + .global_shift_enable(global_shift_enable), + .ctu_tst_scanmode(ctu_tst_scanmode), + .spc_scanin0(spc_scanin0), + .spc_scanin1(spc_scanin1), + .cluster_cken(cluster_cken), + .gclk(gclk), + .cmp_grst_l(cmp_grst_l), + .cmp_arst_l(cmp_arst_l), + .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l), + .adbginit_l(adbginit_l), + .gdbginit_l(gdbginit_l) + + ); + + /* + * SPARC Core to Wishbone Master bridge + */ + + spc2wbm spc2wbm_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_final), + .sys_interrupt_source_i(sys_interrupt_source), + + // Bridge inputs connected to SPARC Core outputs + .spc_req_i(spc_pcx_req_pq), + .spc_atom_i(spc_pcx_atom_pq), + .spc_packetout_i(spc_pcx_data_pa), + + // Bridge outputs connected to SPARC Core inputs + .spc_grant_o(pcx_spc_grant_px), + .spc_ready_o(cpx_spc_data_rdy_cx2), + .spc_packetin_o(cpx_spc_data_cx2), + .spc_stallreq_o(wbm_spc_stallreq), + + // Top-level Wishbone Interconnect inputs + .wbm_ack_i(wbm_ack_i), + .wbm_data_i(wbm_data_i), + + // Top-level Wishbone Interconnect outputs + .wbm_cycle_o(wbm_cycle_o), + .wbm_strobe_o(wbm_strobe_o), + .wbm_we_o(wbm_we_o), + .wbm_addr_o(wbm_addr_o), + .wbm_data_o(wbm_data_o), + .wbm_sel_o(wbm_sel_o) + + ); + + /* + * Reset Controller + */ + + rst_ctrl rst_ctrl_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_i), + + // Reset Controller outputs connected to SPARC Core inputs + .cluster_cken_o(cluster_cken), + .gclk_o(gclk), + .cmp_grst_o(cmp_grst_l), + .cmp_arst_o(cmp_arst_l), + .ctu_tst_pre_grst_o(ctu_tst_pre_grst_l), + .adbginit_o(adbginit_l), + .gdbginit_o(gdbginit_l), + .sys_reset_final_o(sys_reset_final) + + ); + + /* + * Interrupt Controller + */ + + int_ctrl int_ctrl_0 ( + + // Top-level system inputs + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_final), + .sys_irq_i(sys_irq_i), + + // Interrupt Controller outputs connected to bridge inputs + .sys_interrupt_source_o(sys_interrupt_source) + + ); + + /* + * Continuous assignments + */ + + assign const_cpuid = 4'h0; + assign const_maskid = 8'h20; + + // sscan + assign ctu_tck = 1'b0; + assign ctu_sscan_se = 1'b0; + assign ctu_sscan_snap = 1'b0; + assign ctu_sscan_tid = 4'h1; + + // bist + assign ctu_tst_mbist_enable = 1'b0; + + // efuse + assign efc_spc_fuse_clk1 = 1'b0; // Activity + assign efc_spc_fuse_clk2 = 1'b0; // Activity + assign efc_spc_ifuse_ashift = 1'b0; + assign efc_spc_ifuse_dshift = 1'b0; + assign efc_spc_ifuse_data = 1'b0; // Activity + assign efc_spc_dfuse_ashift = 1'b0; + assign efc_spc_dfuse_dshift = 1'b0; + assign efc_spc_dfuse_data = 1'b0; // Activity + + // scan and macro test + assign ctu_tst_macrotest = 1'b0; + assign ctu_tst_scan_disable = 1'b0; + assign ctu_tst_short_chain = 1'b0; + assign global_shift_enable = 1'b0; + assign ctu_tst_scanmode = 1'b0; + assign spc_scanin0 = 1'b0; + assign spc_scanin1 = 1'b0; + + /* + + The following signals are handled by the Reset Controller: + + // clk + assign cluster_cken = ...; + assign gclk = ...; + + // reset + assign cmp_grst_l = ...; + assign cmp_arst_l = ...; + assign ctu_tst_pre_grst_l = ...; + + assign adbginit_l = ...; + assign gdbginit_l = ...; + + */ + +endmodule
trunk/hdl/rtl/s1_top/s1_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/rtl/s1_top/s1_defs.h =================================================================== --- trunk/hdl/rtl/s1_top/s1_defs.h (nonexistent) +++ trunk/hdl/rtl/s1_top/s1_defs.h (revision 4) @@ -0,0 +1,48 @@ +/* + * Simply RISC S1 Definitions + * + * (C) Copyleft 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * Simple constant definitions used by the S1 Core design. + */ + +`include "t1_defs.h" +`timescale 1ns/100ps + +// Size of the buses +`define WB_ADDR_WIDTH 64 +`define WB_DATA_WIDTH 64 + +// States of the FSM of the bridge +`define STATE_WAKEUP 4'b0000 +`define STATE_IDLE 4'b0001 +`define STATE_REQUEST_LATCHED 4'b0010 +`define STATE_PACKET_LATCHED 4'b0011 +`define STATE_REQUEST_GRANTED 4'b0100 +`define STATE_ACCESS2_BEGIN 4'b0101 +`define STATE_ACCESS2_END 4'b0110 +`define STATE_ACCESS3_BEGIN 4'b0111 +`define STATE_ACCESS3_END 4'b1000 +`define STATE_ACCESS4_BEGIN 4'b1001 +`define STATE_ACCESS4_END 4'b1010 +`define STATE_PACKET_READY 4'b1011 + +// Constants used by the timer of the Reset Controller +`define TIMER_BITS 16 +`define RESET_CYCLES_1 100 +`define RESET_CYCLES_2 1000 +`define RESET_CYCLES_3 2000 +`define RESET_CYCLES_4 3000 +`define GCLK_CYCLES 900 +
trunk/hdl/rtl/s1_top/s1_defs.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/rtl/s1_top/t1_defs.h =================================================================== --- trunk/hdl/rtl/s1_top/t1_defs.h (nonexistent) +++ trunk/hdl/rtl/s1_top/t1_defs.h (revision 4) @@ -0,0 +1,839 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: iop.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +//-*- verilog -*- +//////////////////////////////////////////////////////////////////////// +/* +// +// Description: Global header file that contain definitions that +// are common/shared at the IOP chip level +*/ +//////////////////////////////////////////////////////////////////////// + + +// Address Map Defines +// =================== +`define ADDR_MAP_HI 39 +`define ADDR_MAP_LO 32 +`define IO_ADDR_BIT 39 + +// CMP space +`define DRAM_DATA_LO 8'h00 +`define DRAM_DATA_HI 8'h7f + +// IOP space +`define JBUS1 8'h80 +`define RESERVED_5 8'h81 //`define HASH_TBL_NRAM_CSR 8'h81 +`define RESERVED_1 8'h82 +`define RESERVED_6_LO 8'h83 //`define ENET_MAC_CSR 8'h83 + //`define ENET_ING_CSR 8'h84 + //`define ENET_EGR_CMD_CSR 8'h85 +`define RESERVED_6_HI 8'h86 //`define ENET_EGR_DP_CSR 8'h86 +`define RESERVED_2_LO 8'h87 +`define RESERVED_2_HI 8'h92 +`define RESERVED_7 8'h93 //`define BSC_CSR 8'h93 +`define RESERVED_3 8'h94 +`define RESERVED_8 8'h95 //`define RAND_GEN_CSR 8'h95 +`define CLOCK_UNIT_CSR 8'h96 +`define DRAM_CSR 8'h97 +`define IOB_MAN_CSR 8'h98 +`define TAP_CSR 8'h99 +`define RESERVED_4_L0 8'h9a +`define RESERVED_4_HI 8'h9d +`define CPU_ASI 8'h9e +`define IOB_INT_CSR 8'h9f + +// L2 space +`define L2C_CSR_LO 8'ha0 +`define L2C_CSR_HI 8'hbf + +// More IOP space +`define JBUS2_LO 8'hc0 +`define JBUS2_HI 8'hfe +`define SPI_CSR 8'hff + + +//Cache Crossbar Width and Field Defines +//====================================== +`define PCX_WIDTH 124 //PCX payload packet width +`define CPX_WIDTH 145 //CPX payload packet width + +`define PCX_VLD 123 //PCX packet valid +`define PCX_RQ_HI 122 //PCX request type field +`define PCX_RQ_LO 118 +`define PCX_NC 117 //PCX non-cacheable bit +`define PCX_R 117 //PCX read/!write bit +`define PCX_CP_HI 116 //PCX cpu_id field +`define PCX_CP_LO 114 +`define PCX_TH_HI 113 //PCX Thread field +`define PCX_TH_LO 112 +`define PCX_BF_HI 111 //PCX buffer id field +`define PCX_INVALL 111 +`define PCX_BF_LO 109 +`define PCX_WY_HI 108 //PCX replaced L1 way field +`define PCX_WY_LO 107 +`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 +`define PCX_P_LO 107 +`define PCX_SZ_HI 106 //PCX load/store size field +`define PCX_SZ_LO 104 +`define PCX_ERR_HI 106 //PCX error field +`define PCX_ERR_LO 104 +`define PCX_AD_HI 103 //PCX address field +`define PCX_AD_LO 64 +`define PCX_DA_HI 63 //PCX Store data +`define PCX_DA_LO 0 + +`define PCX_SZ_1B 3'b000 // encoding for 1B access +`define PCX_SZ_2B 3'b001 // encoding for 2B access +`define PCX_SZ_4B 3'b010 // encoding for 4B access +`define PCX_SZ_8B 3'b011 // encoding for 8B access +`define PCX_SZ_16B 3'b111 // encoding for 16B access + +`define CPX_VLD 144 //CPX payload packet valid + +`define CPX_RQ_HI 143 //CPX Request type +`define CPX_RQ_LO 140 +`define CPX_ERR_HI 139 //CPX error field +`define CPX_ERR_LO 137 +`define CPX_NC 136 //CPX non-cacheable +`define CPX_R 136 //CPX read/!write bit +`define CPX_TH_HI 135 //CPX thread ID field +`define CPX_TH_LO 134 + +//bits 133:128 are shared by different fields +//for different packet types. + +`define CPX_IN_HI 133 //CPX Interrupt source +`define CPX_IN_LO 128 + +`define CPX_WYVLD 133 //CPX replaced way valid +`define CPX_WY_HI 132 //CPX replaced I$/D$ way +`define CPX_WY_LO 131 +`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits +`define CPX_BF_LO 128 + +`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits +`define CPX_SI_LO 128 //used for invalidates + +`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 +`define CPX_P_LO 130 + +`define CPX_ASI 130 //CPX forward request to ASI +`define CPX_IF4B 130 +`define CPX_IINV 124 +`define CPX_DINV 123 +`define CPX_INVPA5 122 +`define CPX_INVPA4 121 +`define CPX_CPUID_HI 120 +`define CPX_CPUID_LO 118 +`define CPX_INV_PA_HI 116 +`define CPX_INV_PA_LO 112 +`define CPX_INV_IDX_HI 117 +`define CPX_INV_IDX_LO 112 + +`define CPX_DA_HI 127 //CPX data payload +`define CPX_DA_LO 0 + +`define LOAD_RQ 5'b00000 +`define IMISS_RQ 5'b10000 +`define STORE_RQ 5'b00001 +`define CAS1_RQ 5'b00010 +`define CAS2_RQ 5'b00011 +`define SWAP_RQ 5'b00110 +`define STRLOAD_RQ 5'b00100 +`define STRST_RQ 5'b00101 +`define STQ_RQ 5'b00111 +`define INT_RQ 5'b01001 +`define FWD_RQ 5'b01101 +`define FWD_RPY 5'b01110 +`define RSVD_RQ 5'b11111 + +`define LOAD_RET 4'b0000 +`define INV_RET 4'b0011 +`define ST_ACK 4'b0100 +`define AT_ACK 4'b0011 +`define INT_RET 4'b0111 +`define TEST_RET 4'b0101 +`define FP_RET 4'b1000 +`define IFILL_RET 4'b0001 +`define EVICT_REQ 4'b0011 +`define ERR_RET 4'b1100 +`define STRLOAD_RET 4'b0010 +`define STRST_ACK 4'b0110 +`define FWD_RQ_RET 4'b1010 +`define FWD_RPY_RET 4'b1011 +`define RSVD_RET 4'b1111 + +//End cache crossbar defines + + +// Number of COS supported by EECU +`define EECU_COS_NUM 2 + + +// +// BSC bus sizes +// ============= +// + +// General +`define BSC_ADDRESS 40 +`define MAX_XFER_LEN 7'b0 +`define XFER_LEN_WIDTH 6 + +// CTags +`define BSC_CTAG_SZ 12 +`define EICU_CTAG_PRE 5'b11101 +`define EICU_CTAG_REM 7 +`define EIPU_CTAG_PRE 3'b011 +`define EIPU_CTAG_REM 9 +`define EECU_CTAG_PRE 8'b11010000 +`define EECU_CTAG_REM 4 +`define EEPU_CTAG_PRE 6'b010000 +`define EEPU_CTAG_REM 6 +`define L2C_CTAG_PRE 2'b00 +`define L2C_CTAG_REM 10 +`define JBI_CTAG_PRE 2'b10 +`define JBI_CTAG_REM 10 +// reinstated temporarily +`define PCI_CTAG_PRE 7'b1101100 +`define PCI_CTAG_REM 5 + + +// CoS +`define EICU_COS 1'b0 +`define EIPU_COS 1'b1 +`define EECU_COS 1'b0 +`define EEPU_COS 1'b1 +`define PCI_COS 1'b0 + +// L2$ Bank +`define BSC_L2_BNK_HI 8 +`define BSC_L2_BNK_LO 6 + +// L2$ Req +`define BSC_L2_REQ_SZ 62 +`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code +`define BSC_L2_BUS 64 +`define BSC_L2_CTAG_HI 61 +`define BSC_L2_CTAG_LO 50 +`define BSC_L2_ADD_HI 49 +`define BSC_L2_ADD_LO 10 +`define BSC_L2_LEN_HI 9 +`define BSC_L2_LEN_LO 3 +`define BSC_L2_ALLOC 2 +`define BSC_L2_COS 1 +`define BSC_L2_READ 0 + +// L2$ Ack +`define L2_BSC_ACK_SZ 16 +`define L2_BSC_BUS 64 +`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address +`define L2_BSC_CBA_LO 13 +`define L2_BSC_READ 12 +`define L2_BSC_CTAG_HI 11 +`define L2_BSC_CTAG_LO 0 + +// Enet Egress Command Unit +`define EECU_REQ_BUS 44 +`define EECU_REQ_SZ 44 +`define EECU_R_QID_HI 43 +`define EECU_R_QID_LO 40 +`define EECU_R_ADD_HI 39 +`define EECU_R_ADD_LO 0 + +`define EECU_ACK_BUS 64 +`define EECU_ACK_SZ 5 +`define EECU_A_NACK 4 +`define EECU_A_QID_HI 3 +`define EECU_A_QID_LO 0 + + +// Enet Egress Packet Unit +`define EEPU_REQ_BUS 55 +`define EEPU_REQ_SZ 55 +`define EEPU_R_TLEN_HI 54 +`define EEPU_R_TLEN_LO 48 +`define EEPU_R_SOF 47 +`define EEPU_R_EOF 46 +`define EEPU_R_PORT_HI 45 +`define EEPU_R_PORT_LO 44 +`define EEPU_R_QID_HI 43 +`define EEPU_R_QID_LO 40 +`define EEPU_R_ADD_HI 39 +`define EEPU_R_ADD_LO 0 + +// This is cleaved in between Egress Datapath Ack's +`define EEPU_ACK_BUS 6 +`define EEPU_ACK_SZ 6 +`define EEPU_A_EOF 5 +`define EEPU_A_NACK 4 +`define EEPU_A_QID_HI 3 +`define EEPU_A_QID_LO 0 + + +// Enet Egress Datapath +`define EEDP_ACK_BUS 128 +`define EEDP_ACK_SZ 28 +`define EEDP_A_NACK 27 +`define EEDP_A_QID_HI 26 +`define EEDP_A_QID_LO 21 +`define EEDP_A_SOF 20 +`define EEDP_A_EOF 19 +`define EEDP_A_LEN_HI 18 +`define EEDP_A_LEN_LO 12 +`define EEDP_A_TAG_HI 11 +`define EEDP_A_TAG_LO 0 +`define EEDP_A_PORT_HI 5 +`define EEDP_A_PORT_LO 4 +`define EEDP_A_PORT_WIDTH 2 + + +// In-Order / Ordered Queue: EEPU +// Tag is: TLEN, SOF, EOF, QID = 15 +`define EEPU_TAG_ARY (7+1+1+6) +`define EEPU_ENTRIES 16 +`define EEPU_E_IDX 4 +`define EEPU_PORTS 4 +`define EEPU_P_IDX 2 + +// Nack + Tag Info + CTag +`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) +`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) + + +// ENET Ingress Queue Management Req +`define EICU_REQ_BUS 64 +`define EICU_REQ_SZ 62 +`define EICU_R_CTAG_HI 61 +`define EICU_R_CTAG_LO 50 +`define EICU_R_ADD_HI 49 +`define EICU_R_ADD_LO 10 +`define EICU_R_LEN_HI 9 +`define EICU_R_LEN_LO 3 +`define EICU_R_COS 1 +`define EICU_R_READ 0 + + +// ENET Ingress Queue Management Ack +`define EICU_ACK_BUS 64 +`define EICU_ACK_SZ 14 +`define EICU_A_NACK 13 +`define EICU_A_READ 12 +`define EICU_A_CTAG_HI 11 +`define EICU_A_CTAG_LO 0 + + +// Enet Ingress Packet Unit +`define EIPU_REQ_BUS 128 +`define EIPU_REQ_SZ 59 +`define EIPU_R_CTAG_HI 58 +`define EIPU_R_CTAG_LO 50 +`define EIPU_R_ADD_HI 49 +`define EIPU_R_ADD_LO 10 +`define EIPU_R_LEN_HI 9 +`define EIPU_R_LEN_LO 3 +`define EIPU_R_COS 1 +`define EIPU_R_READ 0 + + +// ENET Ingress Packet Unit Ack +`define EIPU_ACK_BUS 10 +`define EIPU_ACK_SZ 10 +`define EIPU_A_NACK 9 +`define EIPU_A_CTAG_HI 8 +`define EIPU_A_CTAG_LO 0 + + +// In-Order / Ordered Queue: PCI +// Tag is: CTAG +`define PCI_TAG_ARY 12 +`define PCI_ENTRIES 16 +`define PCI_E_IDX 4 +`define PCI_PORTS 2 + +// PCI-X Request +`define PCI_REQ_BUS 64 +`define PCI_REQ_SZ 62 +`define PCI_R_CTAG_HI 61 +`define PCI_R_CTAG_LO 50 +`define PCI_R_ADD_HI 49 +`define PCI_R_ADD_LO 10 +`define PCI_R_LEN_HI 9 +`define PCI_R_LEN_LO 3 +`define PCI_R_COS 1 +`define PCI_R_READ 0 + +// PCI_X Acknowledge +`define PCI_ACK_BUS 64 +`define PCI_ACK_SZ 14 +`define PCI_A_NACK 13 +`define PCI_A_READ 12 +`define PCI_A_CTAG_HI 11 +`define PCI_A_CTAG_LO 0 + + +`define BSC_MAX_REQ_SZ 62 + + +// +// BSC array sizes +//================ +// +`define BSC_REQ_ARY_INDEX 6 +`define BSC_REQ_ARY_DEPTH 64 +`define BSC_REQ_ARY_WIDTH 62 +`define BSC_REQ_NXT_WIDTH 12 +`define BSC_ACK_ARY_INDEX 6 +`define BSC_ACK_ARY_DEPTH 64 +`define BSC_ACK_ARY_WIDTH 14 +`define BSC_ACK_NXT_WIDTH 12 +`define BSC_PAY_ARY_INDEX 6 +`define BSC_PAY_ARY_DEPTH 64 +`define BSC_PAY_ARY_WIDTH 256 + +// ECC syndrome bits per memory element +`define BSC_PAY_ECC 10 +`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) + + +// +// BSC Port Definitions +// ==================== +// +// Bits 7 to 4 of curr_port_id +`define BSC_PORT_NULL 4'h0 +`define BSC_PORT_SC 4'h1 +`define BSC_PORT_EICU 4'h2 +`define BSC_PORT_EIPU 4'h3 +`define BSC_PORT_EECU 4'h4 +`define BSC_PORT_EEPU 4'h8 +`define BSC_PORT_PCI 4'h9 + +// Number of ports of each type +`define BSC_PORT_SC_CNT 8 + +// Bits needed to represent above +`define BSC_PORT_SC_IDX 3 + +// How wide the linked list pointers are +// 60b for no payload (2CoS) +// 80b for payload (2CoS) + +//`define BSC_OBJ_PTR 80 +//`define BSC_HD1_HI 69 +//`define BSC_HD1_LO 60 +//`define BSC_TL1_HI 59 +//`define BSC_TL1_LO 50 +//`define BSC_CT1_HI 49 +//`define BSC_CT1_LO 40 +//`define BSC_HD0_HI 29 +//`define BSC_HD0_LO 20 +//`define BSC_TL0_HI 19 +//`define BSC_TL0_LO 10 +//`define BSC_CT0_HI 9 +//`define BSC_CT0_LO 0 + +`define BSC_OBJP_PTR 48 +`define BSC_PYP1_HI 47 +`define BSC_PYP1_LO 42 +`define BSC_HDP1_HI 41 +`define BSC_HDP1_LO 36 +`define BSC_TLP1_HI 35 +`define BSC_TLP1_LO 30 +`define BSC_CTP1_HI 29 +`define BSC_CTP1_LO 24 +`define BSC_PYP0_HI 23 +`define BSC_PYP0_LO 18 +`define BSC_HDP0_HI 17 +`define BSC_HDP0_LO 12 +`define BSC_TLP0_HI 11 +`define BSC_TLP0_LO 6 +`define BSC_CTP0_HI 5 +`define BSC_CTP0_LO 0 + +`define BSC_PTR_WIDTH 192 +`define BSC_PTR_REQ_HI 191 +`define BSC_PTR_REQ_LO 144 +`define BSC_PTR_REQP_HI 143 +`define BSC_PTR_REQP_LO 96 +`define BSC_PTR_ACK_HI 95 +`define BSC_PTR_ACK_LO 48 +`define BSC_PTR_ACKP_HI 47 +`define BSC_PTR_ACKP_LO 0 + +`define BSC_PORT_SC_PTR 96 // R, R+P +`define BSC_PORT_EECU_PTR 48 // A+P +`define BSC_PORT_EICU_PTR 96 // A, A+P +`define BSC_PORT_EIPU_PTR 48 // A + +// I2C STATES in DRAMctl +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 + + +// +// IOB defines +// =========== +// +`define IOB_ADDR_WIDTH 40 +`define IOB_LOCAL_ADDR_WIDTH 32 + +`define IOB_CPU_INDEX 3 +`define IOB_CPU_WIDTH 8 +`define IOB_THR_INDEX 2 +`define IOB_THR_WIDTH 4 +`define IOB_CPUTHR_INDEX 5 +`define IOB_CPUTHR_WIDTH 32 + +`define IOB_MONDO_DATA_INDEX 5 +`define IOB_MONDO_DATA_DEPTH 32 +`define IOB_MONDO_DATA_WIDTH 64 +`define IOB_MONDO_SRC_WIDTH 5 +`define IOB_MONDO_BUSY 5 + +`define IOB_INT_TAB_INDEX 2 +`define IOB_INT_TAB_DEPTH 4 + +//`define IOB_INT_STAT_WIDTH 32 +//`define IOB_INT_STAT_HI 31 +//`define IOB_INT_STAT_LO 0 + +`define IOB_INT_VEC_WIDTH 6 +`define IOB_INT_VEC_HI 5 +`define IOB_INT_VEC_LO 0 + +`define IOB_INT_CPU_WIDTH 5 +`define IOB_INT_CPU_HI 12 +`define IOB_INT_CPU_LO 8 + +`define IOB_INT_MASK 2 +`define IOB_INT_CLEAR 1 +`define IOB_INT_PEND 0 + +`define IOB_DISP_TYPE_HI 17 +`define IOB_DISP_TYPE_LO 16 +`define IOB_DISP_THR_HI 12 +`define IOB_DISP_THR_LO 8 +`define IOB_DISP_VEC_HI 5 +`define IOB_DISP_VEC_LO 0 + +`define IOB_JBI_RESET 1 +`define IOB_ENET_RESET 0 + +`define IOB_RESET_STAT_WIDTH 3 +`define IOB_RESET_STAT_HI 3 +`define IOB_RESET_STAT_LO 1 + +`define IOB_SERNUM_WIDTH 64 + +`define IOB_FUSE_WIDTH 22 + +`define IOB_TMSTAT_THERM 63 + +`define IOB_POR_TT 6'b01 // power-on-reset trap type + +`define IOB_CPU_BUF_INDEX 4 + +`define IOB_INT_BUF_INDEX 4 +`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width + +`define IOB_IO_BUF_INDEX 4 +`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width + +`define IOB_L2_VIS_BUF_INDEX 5 +`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width + +`define IOB_INT_AVEC_WIDTH 9 // availibility vector width +`define IOB_ACK_AVEC_WIDTH 9 // availibility vector width + +// fixme - double check address mapping +// CREG in `IOB_INT_CSR space +`define IOB_DEV_ADDR_MASK 32'hffffffe7 +`define IOB_CREG_INTSTAT 32'h00000000 +`define IOB_CREG_MDATA0 32'h00000400 +`define IOB_CREG_MDATA1 32'h00000500 +`define IOB_CREG_MBUSY 32'h00000900 +`define IOB_THR_ADDR_MASK 32'hffffff07 +`define IOB_CREG_MDATA0_ALIAS 32'h00000600 +`define IOB_CREG_MDATA1_ALIAS 32'h00000700 +`define IOB_CREG_MBUSY_ALIAS 32'h00000b00 + +// CREG in `IOB_MAN_CSR space +`define IOB_CREG_INTMAN 32'h00000000 +`define IOB_CREG_INTCTL 32'h00000400 +`define IOB_CREG_INTVECDISP 32'h00000800 +`define IOB_CREG_RESETSTAT 32'h00000810 +`define IOB_CREG_SERNUM 32'h00000820 +`define IOB_CREG_TMSTATCTRL 32'h00000828 +`define IOB_CREG_COREAVAIL 32'h00000830 +`define IOB_CREG_SSYSRESET 32'h00000838 +`define IOB_CREG_FUSESTAT 32'h00000840 +`define IOB_CREG_MARGIN 32'h00000850 +`define IOB_CREG_JINTV 32'h00000a00 + +`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 +`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 +`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 +`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 +`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 +`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 +`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 +`define IOB_CREG_DBG_ENET_CTRL 32'h00002000 +`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 +`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 +`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 +`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 +`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 +`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 +`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 +`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 +`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 +`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 +`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 +`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 +`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 +`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 + +`define IOB_CREG_TESTSTUB 32'h80000000 + +// Address map for TAP access of SPARC ASI +`define IOB_ASI_PC 4'b0000 +`define IOB_ASI_BIST 4'b0001 +`define IOB_ASI_MARGIN 4'b0010 +`define IOB_ASI_DEFEATURE 4'b0011 +`define IOB_ASI_L1DD 4'b0100 +`define IOB_ASI_L1ID 4'b0101 +`define IOB_ASI_L1DT 4'b0110 + +`define IOB_INT 2'b00 +`define IOB_RESET 2'b01 +`define IOB_IDLE 2'b10 +`define IOB_RESUME 2'b11 + +// +// CIOP UCB Bus Width +// ================== +// +//`define IOB_EECU_WIDTH 16 // ethernet egress command +//`define EECU_IOB_WIDTH 16 + +//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) +//`define NRAM_IOB_WIDTH 4 + +`define IOB_JBI_WIDTH 64 // JBI +`define JBI_IOB_WIDTH 16 + +//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress +//`define ENET_ING_IOB_WIDTH 8 + +//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress +//`define ENET_EGR_IOB_WIDTH 4 + +//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC +//`define ENET_MAC_IOB_WIDTH 4 + +`define IOB_DRAM_WIDTH 4 // DRAM controller +`define DRAM_IOB_WIDTH 4 + +//`define IOB_BSC_WIDTH 4 // BSC +//`define BSC_IOB_WIDTH 4 + +`define IOB_SPI_WIDTH 4 // SPI (Boot ROM) +`define SPI_IOB_WIDTH 4 + +`define IOB_CLK_WIDTH 4 // clk unit +`define CLK_IOB_WIDTH 4 + +//`define IOB_CLSP_WIDTH 4 // clk spine unit +//`define CLSP_IOB_WIDTH 4 + +`define IOB_TAP_WIDTH 8 // TAP +`define TAP_IOB_WIDTH 8 + + +// +// CIOP UCB Buf ID Type +// ==================== +// +`define UCB_BID_CMP 2'b00 +`define UCB_BID_TAP 2'b01 + +// +// Interrupt Device ID +// =================== +// +// Caution: DUMMY_DEV_ID has to be 9 bit wide +// for fields to line up properly in the IOB. +`define DUMMY_DEV_ID 9'h00 // 0 +`define UNCOR_ECC_DEV_ID 7'd1 // 1 + +// +// Soft Error related definitions +// ============================== +// +`define COR_ECC_CNT_WIDTH 16 + + +// +// CMP clock +// ========= +// + +`define CMP_CLK_PERIOD 1333 + + +// +// NRAM/IO Interface +// ================= +// + +`define DRAM_CLK_PERIOD 6000 + +`define NRAM_IO_DQ_WIDTH 32 +`define IO_NRAM_DQ_WIDTH 32 + +`define NRAM_IO_ADDR_WIDTH 15 +`define NRAM_IO_BA_WIDTH 2 + + +// +// NRAM/ENET Interface +// =================== +// + +`define NRAM_ENET_DATA_WIDTH 64 +`define ENET_NRAM_ADDR_WIDTH 20 + +`define NRAM_DBG_DATA_WIDTH 40 + + +// +// IO/FCRAM Interface +// ================== +// + +`define FCRAM_DATA1_HI 63 +`define FCRAM_DATA1_LO 32 +`define FCRAM_DATA0_HI 31 +`define FCRAM_DATA0_LO 0 + +// +// PCI Interface +// ================== +// Load/store size encodings +// ------------------------- +// Size encoding +// 000 - byte +// 001 - half-word +// 010 - word +// 011 - double-word +// 100 - quad +`define LDST_SZ_BYTE 3'b000 +`define LDST_SZ_HALF_WORD 3'b001 +`define LDST_SZ_WORD 3'b010 +`define LDST_SZ_DOUBLE_WORD 3'b011 +`define LDST_SZ_QUAD 3'b100 + +// +// JBI<->SCTAG Interface +// ======================= +// Outbound Header Format +`define JBI_BTU_OUT_ADDR_LO 0 +`define JBI_BTU_OUT_ADDR_HI 42 +`define JBI_BTU_OUT_RSV0_LO 43 +`define JBI_BTU_OUT_RSV0_HI 43 +`define JBI_BTU_OUT_TYPE_LO 44 +`define JBI_BTU_OUT_TYPE_HI 48 +`define JBI_BTU_OUT_RSV1_LO 49 +`define JBI_BTU_OUT_RSV1_HI 51 +`define JBI_BTU_OUT_REPLACE_LO 52 +`define JBI_BTU_OUT_REPLACE_HI 56 +`define JBI_BTU_OUT_RSV2_LO 57 +`define JBI_BTU_OUT_RSV2_HI 59 +`define JBI_BTU_OUT_BTU_ID_LO 60 +`define JBI_BTU_OUT_BTU_ID_HI 71 +`define JBI_BTU_OUT_DATA_RTN 72 +`define JBI_BTU_OUT_RSV3_LO 73 +`define JBI_BTU_OUT_RSV3_HI 75 +`define JBI_BTU_OUT_CE 76 +`define JBI_BTU_OUT_RSV4_LO 77 +`define JBI_BTU_OUT_RSV4_HI 79 +`define JBI_BTU_OUT_UE 80 +`define JBI_BTU_OUT_RSV5_LO 81 +`define JBI_BTU_OUT_RSV5_HI 83 +`define JBI_BTU_OUT_DRAM 84 +`define JBI_BTU_OUT_RSV6_LO 85 +`define JBI_BTU_OUT_RSV6_HI 127 + +// Inbound Header Format +`define JBI_SCTAG_IN_ADDR_LO 0 +`define JBI_SCTAG_IN_ADDR_HI 39 +`define JBI_SCTAG_IN_SZ_LO 40 +`define JBI_SCTAG_IN_SZ_HI 42 +`define JBI_SCTAG_IN_RSV0 43 +`define JBI_SCTAG_IN_TAG_LO 44 +`define JBI_SCTAG_IN_TAG_HI 55 +`define JBI_SCTAG_IN_REQ_LO 56 +`define JBI_SCTAG_IN_REQ_HI 58 +`define JBI_SCTAG_IN_POISON 59 +`define JBI_SCTAG_IN_RSV1_LO 60 +`define JBI_SCTAG_IN_RSV1_HI 63 + +`define JBI_SCTAG_REQ_WRI 3'b100 +`define JBI_SCTAG_REQ_WR8 3'b010 +`define JBI_SCTAG_REQ_RDD 3'b001 +`define JBI_SCTAG_REQ_WRI_BIT 2 +`define JBI_SCTAG_REQ_WR8_BIT 1 +`define JBI_SCTAG_REQ_RDD_BIT 0 + +// +// JBI->IOB Mondo Header Format +// ============================ +// +`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 +`define JBI_IOB_MONDO_RSV1_LO 13 +`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target +`define JBI_IOB_MONDO_TRG_LO 8 +`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 +`define JBI_IOB_MONDO_RSV0_LO 5 +`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source +`define JBI_IOB_MONDO_SRC_LO 0 + +`define JBI_IOB_MONDO_RSV1_WIDTH 3 +`define JBI_IOB_MONDO_TRG_WIDTH 5 +`define JBI_IOB_MONDO_RSV0_WIDTH 3 +`define JBI_IOB_MONDO_SRC_WIDTH 5 + +// JBI->IOB Mondo Bus Width/Cycle +// ============================== +// Cycle 1 Header[15:8] +// Cycle 2 Header[ 7:0] +// Cycle 3 J_AD[127:120] +// Cycle 4 J_AD[119:112] +// ..... +// Cycle 18 J_AD[ 7: 0] +`define JBI_IOB_MONDO_BUS_WIDTH 8 +`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data Index: trunk/hdl/behav/testbench/testbench.v =================================================================== --- trunk/hdl/behav/testbench/testbench.v (nonexistent) +++ trunk/hdl/behav/testbench/testbench.v (revision 4) @@ -0,0 +1,375 @@ +/* + * Simply RISC S1 Testbench + * + * (C) 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * This is the testbench for the functional verification of the + * S1 Core: it makes and instance of the S1 module to make it + * possible to access one or more memory harnesses. + */ + +`include "s1_defs.h" + +module testbench (); + + /* + * Wires + */ + + // Interrupt Requests + wire[63:0] sys_irq; + + // Wishbone Master inputs / Wishbone Slave ouputs + wire wb_ack; // Ack + wire[(`WB_DATA_WIDTH-1):0] wb_datain; // Data In + + // Wishbone Master outputs / Wishbone Slave inputs + wire wb_cycle; // Cycle Start + wire wb_strobe; // Strobe Request + wire wb_we_o; // Write Enable + wire[`WB_ADDR_WIDTH-1:0] wb_addr; // Address Bus + wire[`WB_DATA_WIDTH-1:0] wb_dataout; // Data Out + wire[`WB_DATA_WIDTH/8-1:0] wb_sel; // Select Output + + // Separate Cycle wires for memory harnesses + wire wb_cycle_RED_EXT_SEC; + wire wb_cycle_HTRAPS; + wire wb_cycle_TRAPS; + wire wb_cycle_HPRIV_RESET; + wire wb_cycle_KERNEL_text; + wire wb_cycle_KERNEL_data; + wire wb_cycle_MAIN; + wire wb_cycle_RED_SEC; + + // Separate Strobe wires for memory harnesses + wire wb_strobe_RED_EXT_SEC; + wire wb_strobe_HTRAPS; + wire wb_strobe_TRAPS; + wire wb_strobe_HPRIV_RESET; + wire wb_strobe_KERNEL_text; + wire wb_strobe_KERNEL_data; + wire wb_strobe_MAIN; + wire wb_strobe_RED_SEC; + + // Separate Ack wires for memory harnesses + wire wb_ack_RED_EXT_SEC; + wire wb_ack_HTRAPS; + wire wb_ack_TRAPS; + wire wb_ack_HPRIV_RESET; + wire wb_ack_KERNEL_text; + wire wb_ack_KERNEL_data; + wire wb_ack_MAIN; + wire wb_ack_RED_SEC; + + /* + * Registers + */ + + // System signals + reg sys_clock; + reg sys_reset; + + /* + * Behavior + */ + + always #1 sys_clock = ~sys_clock; + assign sys_irq = 64'b0; + + initial begin + + // Display start message + $display("INFO: TBENCH: Starting Simply RISC S1 Core simulation..."); + + // Create VCD trace file + $dumpfile("trace.vcd"); + $dumpvars(); + + // Run the simulation + sys_clock <= 1'b1; + sys_reset <= 1'b1; + #100 + sys_reset <= 1'b0; + #9900 + $display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!"); + $finish; + + end + + /* + * Simply RISC S1 module instance + */ + + s1_top s1_top_0 ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + .sys_irq_i(sys_irq), + + // Wishbone Master inputs + .wbm_ack_i(wb_ack), + .wbm_data_i(wb_datain), + + // Wishbone Master outputs + .wbm_cycle_o(wb_cycle), + .wbm_strobe_o(wb_strobe), + .wbm_we_o(wb_we), + .wbm_addr_o(wb_addr), + .wbm_data_o(wb_dataout), + .wbm_sel_o(wb_sel) + + ); + + /* + * Memory Harnesses with Wishbone Slave interface + */ + + // Section '.RED_EXT_SEC', segment 'text' - From PA 0000040000 to 0000047FFF and then together with + // Section '.RED_EXT_SEC', segment 'data' - From PA 000004C000 to 000004FFFF => 16-3=13 addr_bits + defparam mem_RED_EXT_SEC.addr_bits = 13; + defparam mem_RED_EXT_SEC.memfilename = "mem_RED_EXT_SEC.image"; + defparam mem_RED_EXT_SEC.memdefaultcontent = 64'h0100000001000000; + + // Section '.HTRAPS', segment 'text' - From PA 0000080000 to 0000087FFF and then together with + // Section '.HTRAPS', segment 'data' - From PA 000008C000 to 000008FFFF (zeroes) => 16-3=13 addr_bits + defparam mem_HTRAPS.addr_bits = 13; + defparam mem_HTRAPS.memfilename = "mem_HTRAPS.image"; + defparam mem_HTRAPS.memdefaultcontent = 64'h0100000001000000; + + // Section '.TRAPS', segment 'text' - From PA 1000120000 to 1000127FFF and then together with + // Section '.TRAPS', segment 'data' - From PA 100012C000 to 100012FFFF (zeroes) => 16-3=13 addr_bits + defparam mem_TRAPS.addr_bits = 13; + defparam mem_TRAPS.memfilename = "mem_TRAPS.image"; + defparam mem_TRAPS.memdefaultcontent = 64'h0100000001000000; + + // Section '.HPRIV_RESET', segment 'text' - From PA 1000144000 to 1000144FFF => 12-3=9 addr_bits + defparam mem_HPRIV_RESET.addr_bits = 9; + defparam mem_HPRIV_RESET.memfilename = "mem_HPRIV_RESET.image"; + defparam mem_HPRIV_RESET.memdefaultcontent = 64'h0100000001000000; + + // Section '.KERNEL', segment 'text' - From PA 1101834000 to 1101834FFF => 12-3=9 addr_bits + defparam mem_KERNEL_text.addr_bits = 9; + defparam mem_KERNEL_text.memfilename = "mem_KERNEL_text.image"; + defparam mem_KERNEL_text.memdefaultcontent = 64'h0100000001000000; + + // Section '.KERNEL', segment 'data' - From PA 1101C34000 to 1101C34FFF => 12-3=9 addr_bits + defparam mem_KERNEL_data.addr_bits = 9; + defparam mem_KERNEL_data.memfilename = "mem_KERNEL_data.image"; + defparam mem_KERNEL_data.memdefaultcontent = 64'h0000000000000000; + + // Section '.MAIN', segment 'text' - From PA 1130000000 to 113000FFFF => 16-3=13 addr_bits + // Section '.MAIN', segment 'data' - From PA 1170000000 but should be empty + // Section '.USER_HEAP', segment 'data' - From PA 1178020000 but should be empty + // Section '.MAIN', segment 'bss' - From PA 1178030000 but should be empty + defparam mem_MAIN.addr_bits = 13; + defparam mem_MAIN.memfilename = "mem_MAIN.image"; + defparam mem_MAIN.memdefaultcontent = 64'h0100000001000000; + + // Section '.RED_SEC', segment 'text' - From PA FFF0000000 to FFF0000FFF => 12-3=9 addr_bits + // Section '.RED_SEC', segment 'data' - From PA FFF0010000 but should contain only an unused word + defparam mem_RED_SEC.addr_bits = 9; + defparam mem_RED_SEC.memfilename = "mem_RED_SEC.image"; + defparam mem_RED_SEC.memdefaultcontent = 64'h0100000001000000; + + // Decode the address and select the proper memory bank + + assign wb_cycle_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 ); + assign wb_strobe_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 ); + + assign wb_cycle_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_cycle : 0 ); + assign wb_strobe_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_strobe : 0 ); + + assign wb_cycle_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_cycle : 0 ); + assign wb_strobe_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_strobe : 0 ); + + assign wb_cycle_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_cycle : 0 ); + assign wb_strobe_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_strobe : 0 ); + + assign wb_cycle_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_cycle : 0 ); + assign wb_strobe_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_strobe : 0 ); + + assign wb_cycle_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_cycle : 0 ); + assign wb_strobe_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_strobe : 0 ); + + assign wb_cycle_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_cycle : 0 ); + assign wb_strobe_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_strobe : 0 ); + + assign wb_cycle_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 ); + assign wb_strobe_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 ); + + assign wb_ack = wb_ack_RED_EXT_SEC | wb_ack_HTRAPS | wb_ack_TRAPS | wb_ack_HPRIV_RESET | + wb_ack_KERNEL_text | wb_ack_KERNEL_data | wb_ack_MAIN | wb_ack_RED_SEC; + + mem_harness mem_RED_EXT_SEC ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_RED_EXT_SEC), + .wbs_strobe_i(wb_strobe_RED_EXT_SEC), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_RED_EXT_SEC) + + ); + + mem_harness mem_HTRAPS ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_HTRAPS), + .wbs_strobe_i(wb_strobe_HTRAPS), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_HTRAPS) + + ); + + mem_harness mem_TRAPS ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_TRAPS), + .wbs_strobe_i(wb_strobe_TRAPS), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_TRAPS) + + ); + + mem_harness mem_HPRIV_RESET ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_HPRIV_RESET), + .wbs_strobe_i(wb_strobe_HPRIV_RESET), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_HPRIV_RESET) + + ); + + mem_harness mem_KERNEL_text ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_KERNEL_text), + .wbs_strobe_i(wb_strobe_KERNEL_text), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_KERNEL_text) + + ); + + mem_harness mem_KERNEL_data ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_KERNEL_data), + .wbs_strobe_i(wb_strobe_KERNEL_data), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_KERNEL_data) + + ); + + mem_harness mem_MAIN ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_MAIN), + .wbs_strobe_i(wb_strobe_MAIN), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_MAIN) + + ); + + mem_harness mem_RED_SEC ( + + // System inputs + .sys_clock_i(sys_clock), + .sys_reset_i(sys_reset), + + // Wishbone Slave inputs + .wbs_addr_i(wb_addr), + .wbs_data_i(wb_dataout), + .wbs_cycle_i(wb_cycle_RED_SEC), + .wbs_strobe_i(wb_strobe_RED_SEC), + .wbs_sel_i(wb_sel), + .wbs_we_i(wb_we), + + // Wishbone Slave outputs + .wbs_data_o(wb_datain), + .wbs_ack_o(wb_ack_RED_SEC) + + ); + +endmodule
trunk/hdl/behav/testbench/testbench.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/behav/testbench/mem_harness.v =================================================================== --- trunk/hdl/behav/testbench/mem_harness.v (nonexistent) +++ trunk/hdl/behav/testbench/mem_harness.v (revision 4) @@ -0,0 +1,135 @@ +/* + * Memory Harness with Wishbone Slave interface + * + * (C) Copyleft 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * Filename is a parameter, and the corresponding file content + * must follow the rules stated in Verilog standard for the + * $readmemh() system task. + * For instance if you don't change the default name you just + * have to put a text file named "memory.hex" in your simulation + * directory with the following content inside: + * + * // We start from address zero by default: + * 1234567812345678 + * FEDCBA9876543210 + * // Now we jump to doubleword number 10 (i.e. address 80): + * @ 10 + * 02468ACE13579BDF + * + * This memory harness was originally based upon a Wishbone Slave + * model written by Rudolf Usselmann but now I've + * written it again entirely from scratch. + */ + +module mem_harness ( + sys_clock_i, sys_reset_i, + wbs_addr_i, wbs_data_i, wbs_data_o, wbs_cycle_i, wbs_strobe_i, + wbs_sel_i, wbs_we_i, wbs_ack_o + ); + + // System inputs + input sys_clock_i; // System Clock + input sys_reset_i; // System Reset + + // Wishbone Slave interface inputs + input wbs_cycle_i; // Wishbone Cycle + input wbs_strobe_i; // Wishbone Strobe + input[63:0] wbs_addr_i; // Wishbone Address + input[63:0] wbs_data_i; // Wishbone Data Input + input wbs_we_i; // Wishbone Write Enable + input[7:0] wbs_sel_i; // Wishbone Byte Select + + // Wishbone Slave interface registered outputs + output wbs_ack_o; // Wishbone Ack + reg wbs_ack_o; // Wishbone Ack + output[63:0] wbs_data_o; // Wishbone Data Output + reg[63:0] wbs_data_o; // Wishbone Data Output + + // Parameters + parameter addr_bits = 20; + parameter addr_max = (1<
trunk/hdl/behav/testbench/mem_harness.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/behav/testbench/s1_defs.h =================================================================== --- trunk/hdl/behav/testbench/s1_defs.h (nonexistent) +++ trunk/hdl/behav/testbench/s1_defs.h (revision 4) @@ -0,0 +1,48 @@ +/* + * Simply RISC S1 Definitions + * + * (C) Copyleft 2007 Simply RISC LLP + * AUTHOR: Fabrizio Fazzino + * + * LICENSE: + * This is a Free Hardware Design; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * The above named program is distributed in the hope that it will + * be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * DESCRIPTION: + * Simple constant definitions used by the S1 Core design. + */ + +`include "t1_defs.h" +`timescale 1ns/100ps + +// Size of the buses +`define WB_ADDR_WIDTH 64 +`define WB_DATA_WIDTH 64 + +// States of the FSM of the bridge +`define STATE_WAKEUP 4'b0000 +`define STATE_IDLE 4'b0001 +`define STATE_REQUEST_LATCHED 4'b0010 +`define STATE_PACKET_LATCHED 4'b0011 +`define STATE_REQUEST_GRANTED 4'b0100 +`define STATE_ACCESS2_BEGIN 4'b0101 +`define STATE_ACCESS2_END 4'b0110 +`define STATE_ACCESS3_BEGIN 4'b0111 +`define STATE_ACCESS3_END 4'b1000 +`define STATE_ACCESS4_BEGIN 4'b1001 +`define STATE_ACCESS4_END 4'b1010 +`define STATE_PACKET_READY 4'b1011 + +// Constants used by the timer of the Reset Controller +`define TIMER_BITS 16 +`define RESET_CYCLES_1 100 +`define RESET_CYCLES_2 1000 +`define RESET_CYCLES_3 2000 +`define RESET_CYCLES_4 3000 +`define GCLK_CYCLES 900 +
trunk/hdl/behav/testbench/s1_defs.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hdl/behav/sparc_libs/u1_lib.v =================================================================== --- trunk/hdl/behav/sparc_libs/u1_lib.v (nonexistent) +++ trunk/hdl/behav/sparc_libs/u1_lib.v (revision 4) @@ -0,0 +1,4330 @@ +// ========== Copyright Header Begin ========================================== +// +// OpenSPARC T1 Processor File: u1.behV +// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +// +// The above named program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// The above named program is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this work; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +// +// ========== Copyright Header End ============================================ +//////////////////////////////////////////////////////////////////////// +// +// basic gates { +// +//////////////////////////////////////////////////////////////////////// + + +//bw_u1_inv_0p6x +// +// + +module bw_u1_inv_0p6x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_1x +// +// + +module bw_u1_inv_1x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_1p4x +// +// + +module bw_u1_inv_1p4x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_2x +// +// + +module bw_u1_inv_2x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_3x +// +// + +module bw_u1_inv_3x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_4x +// +// + +module bw_u1_inv_4x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + + +//bw_u1_inv_5x +// +// + +module bw_u1_inv_5x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_8x +// +// + +module bw_u1_inv_8x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_10x +// +// + +module bw_u1_inv_10x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_15x +// +// + +module bw_u1_inv_15x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_20x +// +// + +module bw_u1_inv_20x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_30x +// +// + +module bw_u1_inv_30x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_inv_40x +// +// + +module bw_u1_inv_40x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + +//bw_u1_invh_15x +// +// + +module bw_u1_invh_15x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + +//bw_u1_invh_25x +// +// + +module bw_u1_invh_25x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_invh_30x +// +// + +module bw_u1_invh_30x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_invh_50x +// +// + +module bw_u1_invh_50x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + +//bw_u1_invh_60x +// +// + +module bw_u1_invh_60x ( + z, + a ); + + output z; + input a; + + assign z = ~( a ); + +endmodule + + + + +//bw_u1_nand2_0p4x +// +// +module bw_u1_nand2_0p4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_0p6x +// +// +module bw_u1_nand2_0p6x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_1x +// +// +module bw_u1_nand2_1x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_1p4x +// +// +module bw_u1_nand2_1p4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_2x +// +// +module bw_u1_nand2_2x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_3x +// +// +module bw_u1_nand2_3x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_4x +// +// +module bw_u1_nand2_4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_5x +// +// +module bw_u1_nand2_5x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_7x +// +// +module bw_u1_nand2_7x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_10x +// +// +module bw_u1_nand2_10x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand2_15x +// +// +module bw_u1_nand2_15x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a & b ); + +endmodule + + +//bw_u1_nand3_0p4x +// +// +module bw_u1_nand3_0p4x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + + + +//bw_u1_nand3_0p6x +// +// +module bw_u1_nand3_0p6x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + + +//bw_u1_nand3_1x + +// +// +module bw_u1_nand3_1x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_1p4x + +// +// +module bw_u1_nand3_1p4x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_2x + +// +// +module bw_u1_nand3_2x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_3x + +// +// +module bw_u1_nand3_3x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_4x + +// +// +module bw_u1_nand3_4x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_5x + +// +// +module bw_u1_nand3_5x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_7x + +// +// +module bw_u1_nand3_7x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand3_10x + +// +// +module bw_u1_nand3_10x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a & b & c ); + +endmodule + + +//bw_u1_nand4_0p6x + +// +// +module bw_u1_nand4_0p6x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_1x +// +// +module bw_u1_nand4_1x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_1p4x +// +// +module bw_u1_nand4_1p4x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_2x +// +// +module bw_u1_nand4_2x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_3x +// +// +module bw_u1_nand4_3x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_4x +// +// +module bw_u1_nand4_4x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + assign z = ~( a & b & c & d ); + +endmodule + + +//bw_u1_nand4_6x +// +// + +module bw_u1_nand4_6x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + + nand( z, a, b,c,d); + +endmodule + +//bw_u1_nand4_8x +// +// + +module bw_u1_nand4_8x ( + z, + a, + b, + c, + d ); + + output z; + input a; + input b; + input c; + input d; + + + nand( z, a, b,c,d); + +endmodule + +//bw_u1_nor2_0p6x +// +// + +module bw_u1_nor2_0p6x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_1x +// +// + +module bw_u1_nor2_1x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_1p4x +// +// + +module bw_u1_nor2_1p4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_2x +// +// + +module bw_u1_nor2_2x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_3x +// +// + +module bw_u1_nor2_3x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_4x +// +// + +module bw_u1_nor2_4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_6x +// +// + +module bw_u1_nor2_6x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_8x +// +// + +module bw_u1_nor2_8x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + +//bw_u1_nor2_12x +// +// + +module bw_u1_nor2_12x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a | b ); + +endmodule + + + + +//bw_u1_nor3_0p6x +// +// + +module bw_u1_nor3_0p6x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_1x +// +// + +module bw_u1_nor3_1x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_1p4x +// +// + +module bw_u1_nor3_1p4x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_2x +// +// + +module bw_u1_nor3_2x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_3x +// +// + +module bw_u1_nor3_3x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_4x +// +// + +module bw_u1_nor3_4x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_6x +// +// + +module bw_u1_nor3_6x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_nor3_8x +// +// + +module bw_u1_nor3_8x ( + z, + a, + b, + c ); + + output z; + input a; + input b; + input c; + + assign z = ~( a | b | c ); + +endmodule + + +//bw_u1_aoi21_0p4x +// +// +module bw_u1_aoi21_0p4x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi21_1x +// +// +module bw_u1_aoi21_1x ( + + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi21_2x +// +// +module bw_u1_aoi21_2x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi21_4x +// +// +module bw_u1_aoi21_4x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi21_8x +// +// +module bw_u1_aoi21_8x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi21_12x +// +// +module bw_u1_aoi21_12x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule +//bw_u1_aoi22_0p4x +// +// +module bw_u1_aoi22_0p4x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 & a2 ) | ( b1 & b2 )); + +endmodule +//bw_u1_aoi22_1x +// +// +module bw_u1_aoi22_1x ( + z, + b1, + b2, + a1, + a2 ); + + output z; + input b1; + input b2; + input a1; + input a2; + + + assign z = ~(( a1 & a2 ) | ( b1 & b2 )); + +endmodule +//bw_u1_aoi22_2x +// +// +module bw_u1_aoi22_2x ( + + + z, + b1, + b2, + a1, + a2 ); + + output z; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( a1 & a2 ) | ( b1 & b2 )); + +endmodule +//bw_u1_aoi22_4x +// +// +module bw_u1_aoi22_4x ( + + z, + b1, + b2, + a1, + a2 ); + + output z; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( a1 & a2 ) | ( b1 & b2 )); + +endmodule +//bw_u1_aoi22_8x +// +// +module bw_u1_aoi22_8x ( + + z, + b1, + b2, + a1, + a2 ); + + output z; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( a1 & a2 ) | ( b1 & b2 )); + +endmodule +//bw_u1_aoi211_0p3x +// +// +module bw_u1_aoi211_0p3x ( + + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 & c2 ) | (a)| (b)); + +endmodule + +//bw_u1_aoi211_1x +// +// +module bw_u1_aoi211_1x ( + + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 & c2 ) | (a)| (b)); + +endmodule + +//bw_u1_aoi211_2x +// +// +module bw_u1_aoi211_2x ( + + + + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + + assign z = ~(( c1 & c2 ) | (a)| (b)); + +endmodule + +//bw_u1_aoi211_4x +// +// +module bw_u1_aoi211_4x ( + + + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + + + assign z = ~(( c1 & c2 ) | (a)| (b)); + +endmodule + +//bw_u1_aoi211_8x +// +// +module bw_u1_aoi211_8x ( + + + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + + + assign z = ~(( c1 & c2 ) | (a)| (b)); + +endmodule + +//bw_u1_oai21_0p4x +// +// +module bw_u1_oai21_0p4x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai21_1x +// +// +module bw_u1_oai21_1x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai21_2x +// +// +module bw_u1_oai21_2x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai21_4x +// +// +module bw_u1_oai21_4x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai21_8x +// +// +module bw_u1_oai21_8x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai21_12x +// +// +module bw_u1_oai21_12x ( + z, + b1, + b2, + a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + +//bw_u1_oai22_0p4x +// +module bw_u1_oai22_0p4x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 | a2 ) & ( b1 | b2 )); + +endmodule + +//bw_u1_oai22_1x +// +module bw_u1_oai22_1x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 | a2 ) & ( b1 | b2 )); + +endmodule + +//bw_u1_oai22_2x +// +module bw_u1_oai22_2x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 | a2 ) & ( b1 | b2 )); + +endmodule + +//bw_u1_oai22_4x +// +module bw_u1_oai22_4x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 | a2 ) & ( b1 | b2 )); + +endmodule + +//bw_u1_oai22_8x +// +module bw_u1_oai22_8x ( + z, + a1, + a2, + b1, + b2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + + assign z = ~(( a1 | a2 ) & ( b1 | b2 )); + +endmodule + +//bw_u1_oai211_0p3x +// +// +module bw_u1_oai211_0p3x ( + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + +//bw_u1_oai211_1x +// +// +module bw_u1_oai211_1x ( + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + +//bw_u1_oai211_2x +// +// +module bw_u1_oai211_2x ( + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + +//bw_u1_oai211_4x +// +// +module bw_u1_oai211_4x ( + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + +//bw_u1_oai211_8x +// +// +module bw_u1_oai211_8x ( + z, + c1, + c2, + b, + a ); + + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + +//bw_u1_aoi31_1x +// +// +module bw_u1_aoi31_1x ( + + + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 & b2&b3 ) | ( a )); + +endmodule +//bw_u1_aoi31_2x +// +// +module bw_u1_aoi31_2x ( + + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 & b2&b3 ) | ( a )); + +endmodule +//bw_u1_aoi31_4x +// +// +module bw_u1_aoi31_4x ( + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 & b2&b3 ) | ( a )); + +endmodule +//bw_u1_aoi31_8x +// +// +module bw_u1_aoi31_8x ( + + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 & b2&b3 ) | ( a )); + +endmodule +//bw_u1_aoi32_1x +// +// +module bw_u1_aoi32_1x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); + +endmodule + +//bw_u1_aoi32_2x +// +// +module bw_u1_aoi32_2x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + + + assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); + +endmodule + +//bw_u1_aoi32_4x +// +// +module bw_u1_aoi32_4x ( + + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + + + assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); + +endmodule + +//bw_u1_aoi32_8x +// +// +module bw_u1_aoi32_8x ( + + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + + assign z = ~(( b1 & b2&b3 ) | ( a1 & a2 )); + +endmodule + +//bw_u1_aoi33_1x +// +// +module bw_u1_aoi33_1x ( + + + + + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); + +endmodule + + +//bw_u1_aoi33_2x +// +// +module bw_u1_aoi33_2x ( + + + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + + assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); + +endmodule + + +//bw_u1_aoi33_4x +// +// +module bw_u1_aoi33_4x ( + + + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + + + assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); + +endmodule + + +//bw_u1_aoi33_8x +// +// +module bw_u1_aoi33_8x ( + + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + + + assign z = ~(( b1 & b2&b3 ) | ( a1&a2&a3 )); + +endmodule + + +//bw_u1_aoi221_1x +// +// +module bw_u1_aoi221_1x ( + + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); + +endmodule + + +//bw_u1_aoi221_2x +// +// +module bw_u1_aoi221_2x ( + + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); + +endmodule + + +//bw_u1_aoi221_4x +// +// +module bw_u1_aoi221_4x ( + + + + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); + +endmodule + + +//bw_u1_aoi221_8x +// +// +module bw_u1_aoi221_8x ( + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a)); + +endmodule + + +//bw_u1_aoi222_1x +// +// +module bw_u1_aoi222_1x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + +//bw_u1_aoi222_2x +// +// +module bw_u1_aoi222_2x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + + +//bw_u1_aoi222_4x +// +// +module bw_u1_aoi222_4x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + + assign z = ~(( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + + +//bw_u1_aoi311_1x +// +// +module bw_u1_aoi311_1x ( + + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 & c2& c3 ) | (a)| (b)); + +endmodule + + + + +//bw_u1_aoi311_2x +// +// +module bw_u1_aoi311_2x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 & c2& c3 ) | (a)| (b)); + +endmodule + + + + +//bw_u1_aoi311_4x +// +// +module bw_u1_aoi311_4x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + + assign z = ~(( c1 & c2& c3 ) | (a)| (b)); + +endmodule + + + + +//bw_u1_aoi311_8x +// +// +module bw_u1_aoi311_8x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 & c2& c3 ) | (a)| (b)); + +endmodule + + + + +//bw_u1_oai31_1x +// +// +module bw_u1_oai31_1x ( + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 | b2|b3 ) & ( a )); + +endmodule + + + + +//bw_u1_oai31_2x +// +// +module bw_u1_oai31_2x ( + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 | b2|b3 ) & ( a )); + +endmodule + + + + +//bw_u1_oai31_4x +// +// +module bw_u1_oai31_4x ( + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 | b2|b3 ) & ( a )); + +endmodule + + + + +//bw_u1_oai31_8x +// +// +module bw_u1_oai31_8x ( + z, + b1, + b2, + b3, + a ); + + output z; + input b1; + input b2; + input b3; + input a; + + assign z = ~(( b1 | b2|b3 ) & ( a )); + +endmodule + + + + +//bw_u1_oai32_1x +// +// +module bw_u1_oai32_1x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); + +endmodule + + + +//bw_u1_oai32_2x +// +// +module bw_u1_oai32_2x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); + +endmodule + + + +//bw_u1_oai32_4x +// +// +module bw_u1_oai32_4x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); + +endmodule + + + +//bw_u1_oai32_8x +// +// +module bw_u1_oai32_8x ( + z, + b1, + b2, + b3, + a1, + a2 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + + assign z = ~(( b1 | b2 | b3 ) & ( a1 | a2 )); + +endmodule + + + +//bw_u1_oai33_1x +// +// +module bw_u1_oai33_1x ( + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); + +endmodule + + +//bw_u1_oai33_2x +// +// +module bw_u1_oai33_2x ( + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); + +endmodule + + +//bw_u1_oai33_4x +// +// +module bw_u1_oai33_4x ( + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); + +endmodule + + +//bw_u1_oai33_8x +// +// +module bw_u1_oai33_8x ( + z, + b1, + b2, + b3, + a1, + a2, + a3 ); + + output z; + input b1; + input b2; + input b3; + input a1; + input a2; + input a3; + + assign z = ~(( b1 | b2|b3 ) & ( a1|a2|a3 )); + +endmodule + + +//bw_u1_oai221_1x +// +// +module bw_u1_oai221_1x ( + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); + +endmodule + +//bw_u1_oai221_2x +// +// +module bw_u1_oai221_2x ( + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); + +endmodule + +//bw_u1_oai221_4x +// +// +module bw_u1_oai221_4x ( + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); + +endmodule + +//bw_u1_oai221_8x +// +// +module bw_u1_oai221_8x ( + z, + c1, + c2, + b1, + b2, + a ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b1|b2)); + +endmodule + +//bw_u1_oai222_1x +// +// +module bw_u1_oai222_1x ( + z, + c1, + c2, + b1, + b2, + a1, + a2 ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); + +endmodule + + +//bw_u1_oai222_2x +// +// +module bw_u1_oai222_2x ( + z, + c1, + c2, + b1, + b2, + a1, + a2 ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); + +endmodule + + +//bw_u1_oai222_4x +// +// +module bw_u1_oai222_4x ( + z, + c1, + c2, + b1, + b2, + a1, + a2 ); + + output z; + input c1; + input c2; + input b1; + input b2; + input a1; + input a2; + + assign z = ~(( c1 | c2 ) & ( a1|a2 ) & (b1|b2)); + +endmodule + + +//bw_u1_oai311_1x +// +// +module bw_u1_oai311_1x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); + +endmodule + + +//bw_u1_oai311_2x +// +// +module bw_u1_oai311_2x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); + +endmodule + + +//bw_u1_oai311_4x +// +// +module bw_u1_oai311_4x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 | c2 | c3 ) & ( a ) & (b)); + +endmodule + + +//bw_u1_oai311_8x +// +// +module bw_u1_oai311_8x ( + z, + c1, + c2, + c3, + b, + a ); + + output z; + input c1; + input c2; + input c3; + input b; + input a; + + assign z = ~(( c1 | c2|c3 ) & ( a ) & (b)); + +endmodule + + +//bw_u1_muxi21_0p6x + + + +module bw_u1_muxi21_0p6x (z, d0, d1, s); +output z; +input d0, d1, s; + + assign z = s ? ~d1 : ~d0; +endmodule + + +//bw_u1_muxi21_1x + + + +module bw_u1_muxi21_1x (z, d0, d1, s); +output z; +input d0, d1, s; + + assign z = s ? ~d1 : ~d0; +endmodule + + + + + + + +//bw_u1_muxi21_2x + + + +module bw_u1_muxi21_2x (z, d0, d1, s); +output z; +input d0, d1, s; + + assign z = s ? ~d1 : ~d0; +endmodule + + +//bw_u1_muxi21_4x + + + +module bw_u1_muxi21_4x (z, d0, d1, s); +output z; +input d0, d1, s; + + assign z = s ? ~d1 : ~d0; +endmodule + + + + +//bw_u1_muxi21_6x + + +module bw_u1_muxi21_6x (z, d0, d1, s); +output z; +input d0, d1, s; + + assign z = s ? ~d1 : ~d0; +endmodule + +//bw_u1_muxi31d_4x +// + +module bw_u1_muxi31d_4x (z, d0, d1, d2, s0, s1, s2); +output z; +input d0, d1, d2, s0, s1, s2; + zmuxi31d_prim i0 ( z, d0, d1, d2, s0, s1, s2 ); +endmodule + +//bw_u1_muxi41d_4x +// + +module bw_u1_muxi41d_4x (z, d0, d1, d2, d3, s0, s1, s2, s3); +output z; +input d0, d1, d2, d3, s0, s1, s2, s3; + zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 ); +endmodule + +//bw_u1_muxi41d_6x +// + +module bw_u1_muxi41d_6x (z, d0, d1, d2, d3, s0, s1, s2, s3); +output z; +input d0, d1, d2, d3, s0, s1, s2, s3; + zmuxi41d_prim i0 ( z, d0, d1, d2, d3, s0, s1, s2, s3 ); +endmodule + + +//bw_u1_xor2_0p6x +// +// +module bw_u1_xor2_0p6x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ( a ^ b ); + +endmodule +//bw_u1_xor2_1x +// +// +module bw_u1_xor2_1x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ( a ^ b ); + +endmodule +//bw_u1_xor2_2x +// +// +module bw_u1_xor2_2x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ( a ^ b ); + +endmodule +//bw_u1_xor2_4x +// +// +module bw_u1_xor2_4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ( a ^ b ); + +endmodule +//bw_u1_xnor2_0p6x +// +// +module bw_u1_xnor2_0p6x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a ^ b ); + +endmodule +//bw_u1_xnor2_1x +// +// +module bw_u1_xnor2_1x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a ^ b ); + +endmodule +//bw_u1_xnor2_2x +// +// +module bw_u1_xnor2_2x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a ^ b ); + +endmodule +//bw_u1_xnor2_4x +// +// +module bw_u1_xnor2_4x ( + z, + a, + b ); + + output z; + input a; + input b; + + assign z = ~( a ^ b ); + +endmodule + +//bw_u1_buf_1x +// + +module bw_u1_buf_1x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + +//bw_u1_buf_5x +// + +module bw_u1_buf_5x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_buf_10x +// + +module bw_u1_buf_10x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_buf_15x +// + +module bw_u1_buf_15x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_buf_20x +// + +module bw_u1_buf_20x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_buf_30x +// + +module bw_u1_buf_30x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_buf_40x +// + +module bw_u1_buf_40x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + + +//bw_u1_ao2222_1x +// +// +module bw_u1_ao2222_1x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2, + d1, + d2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + input d1; + input d2; + + assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + + +//bw_u1_ao2222_2x +// +// +module bw_u1_ao2222_2x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2, + d1, + d2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + input d1; + input d2; + + assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + +//bw_u1_ao2222_4x +// +// +module bw_u1_ao2222_4x ( + + z, + a1, + a2, + b1, + b2, + c1, + c2, + d1, + d2 ); + + output z; + input a1; + input a2; + input b1; + input b2; + input c1; + input c2; + input d1; + input d2; + + assign z = ((d1&d2) | ( c1 & c2 ) | (b1&b2)| (a1& a2)); + +endmodule + +//////////////////////////////////////////////////////////////////////// +// +// flipflops { +// +//////////////////////////////////////////////////////////////////////// + +// scanable D-flipflop with scanout + +module bw_u1_soff_1x (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; + zsoff_prim i0 ( q, so, ck, d, se, sd ); +endmodule + +module bw_u1_soff_2x (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; + zsoff_prim i0 ( q, so, ck, d, se, sd ); +endmodule + +module bw_u1_soff_4x (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; + zsoff_prim i0 ( q, so, ck, d, se, sd ); +endmodule + +module bw_u1_soff_8x (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; + zsoff_prim i0 ( q, so, ck, d, se, sd ); +endmodule + +// fast scanable D-flipflop with scanout with inverted Q output + +module bw_u1_soffi_4x (q_l, so, ck, d, se, sd); +output q_l, so; +input ck, d, se, sd; + zsoffi_prim i0 ( q_l, so, ck, d, se, sd ); +endmodule + +module bw_u1_soffi_8x (q_l, so, ck, d, se, sd); +output q_l, so; +input ck, d, se, sd; + zsoffi_prim i0 ( q_l, so, ck, d, se, sd ); +endmodule + +// scanable D-flipflop with scanout with 2-to-1 input mux + +module bw_u1_soffm2_4x (q, so, ck, d0, d1, s, se, sd); +output q, so; +input ck, d0, d1, s, se, sd; + zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd ); +endmodule + +module bw_u1_soffm2_8x (q, so, ck, d0, d1, s, se, sd); +output q, so; +input ck, d0, d1, s, se, sd; + zsoffm2_prim i0 ( q, so, ck, d0, d1, s, se, sd ); +endmodule + +// scanable D-flipflop with scanout with sync reset-bar + +module bw_u1_soffr_2x (q, so, ck, d, se, sd, r_l); +output q, so; +input ck, d, se, sd, r_l; + zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); +endmodule + +module bw_u1_soffr_4x (q, so, ck, d, se, sd, r_l); +output q, so; +input ck, d, se, sd, r_l; + zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); +endmodule + +module bw_u1_soffr_8x (q, so, ck, d, se, sd, r_l); +output q, so; +input ck, d, se, sd, r_l; + zsoffr_prim i0 ( q, so, ck, d, se, sd, r_l ); +endmodule + +//bw_u1_soffasr_2x + +module bw_u1_soffasr_2x (q, so, ck, d, r_l, s_l, se, sd); +output q, so; +input ck, d, r_l, s_l, se, sd; + zsoffasr_prim i0 (q, so, ck, d, r_l, s_l, se, sd); +endmodule + + +//bw_u1_ckbuf_1p5x + + +module bw_u1_ckbuf_1p5x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + + +//bw_u1_ckbuf_3x + + +module bw_u1_ckbuf_3x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + +//bw_u1_ckbuf_4p5x + + +module bw_u1_ckbuf_4p5x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + + +//bw_u1_ckbuf_6x + + +module bw_u1_ckbuf_6x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + +//bw_u1_ckbuf_7x +// + +module bw_u1_ckbuf_7x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + +//bw_u1_ckbuf_8x +// +module bw_u1_ckbuf_8x (clk, rclk); +output clk; +input rclk; + buf (clk, rclk); +endmodule + + +//bw_u1_ckbuf_11x +// + +module bw_u1_ckbuf_11x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + +//bw_u1_ckbuf_14x +// + +module bw_u1_ckbuf_14x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + +//bw_u1_ckbuf_17x +// + +module bw_u1_ckbuf_17x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + + + + +//bw_u1_ckbuf_19x +// + +module bw_u1_ckbuf_19x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + + + + +//bw_u1_ckbuf_22x +// + +module bw_u1_ckbuf_22x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + +//bw_u1_ckbuf_25x +// + +module bw_u1_ckbuf_25x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + + +//bw_u1_ckbuf_28x +// + +module bw_u1_ckbuf_28x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + + +//bw_u1_ckbuf_30x +// + +module bw_u1_ckbuf_30x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + +//bw_u1_ckbuf_33x +// + +module bw_u1_ckbuf_33x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + +//bw_u1_ckbuf_40x +// + +module bw_u1_ckbuf_40x (clk, rclk); +output clk; +input rclk; + + assign clk = ( rclk ); + +endmodule + + +// gated clock buffers + + +module bw_u1_ckenbuf_6x (clk, rclk, en_l, tm_l); +output clk; +input rclk, en_l, tm_l; + zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); +endmodule + +module bw_u1_ckenbuf_14x (clk, rclk, en_l, tm_l); +output clk; +input rclk, en_l, tm_l; + zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); +endmodule + +//////////////////////////////////////////////////////////////////////// +// +// half cells +// +//////////////////////////////////////////////////////////////////////// + + + +module bw_u1_zhinv_0p6x (z, a); +output z; +input a; + not (z, a); +endmodule + + +module bw_u1_zhinv_1x (z, a); +output z; +input a; + not (z, a); +endmodule + + + +module bw_u1_zhinv_1p4x (z, a); +output z; +input a; + not (z, a); +endmodule + + +module bw_u1_zhinv_2x (z, a); +output z; +input a; + not (z, a); +endmodule + + + +module bw_u1_zhinv_3x (z, a); +output z; +input a; + not (z, a); +endmodule + + + +module bw_u1_zhinv_4x (z, a); +output z; +input a; + not (z, a); +endmodule + + + +module bw_u1_zhnand2_0p4x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand2_0p6x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand2_1x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand2_1p4x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand2_2x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand2_3x (z, a, b); +output z; +input a, b; + nand (z, a, b); +endmodule + + +module bw_u1_zhnand3_0p6x (z, a, b, c); +output z; +input a, b, c; + nand (z, a, b, c); +endmodule + +module bw_u1_zhnand3_1x (z, a, b, c); +output z; +input a, b, c; + nand (z, a, b, c); +endmodule + +module bw_u1_zhnand3_2x (z, a, b, c); +output z; +input a, b, c; + nand (z, a, b, c); +endmodule + + +module bw_u1_zhnand4_0p6x (z, a, b, c, d); +output z; +input a, b, c, d; + nand (z, a, b, c, d); +endmodule + +module bw_u1_zhnand4_1x (z, a, b, c, d); +output z; +input a, b, c, d; + nand (z, a, b, c, d); +endmodule + +module bw_u1_zhnand4_2x (z, a, b, c, d); +output z; +input a, b, c, d; + nand (z, a, b, c, d); +endmodule + + + +module bw_u1_zhnor2_0p6x (z, a, b); +output z; +input a, b; + nor (z, a, b); +endmodule + +module bw_u1_zhnor2_1x (z, a, b); +output z; +input a, b; + nor (z, a, b); +endmodule + +module bw_u1_zhnor2_2x (z, a, b); +output z; +input a, b; + nor (z, a, b); +endmodule + + + +module bw_u1_zhnor3_0p6x (z, a, b, c); +output z; +input a, b, c; + nor (z, a, b, c); +endmodule + + +module bw_u1_zhaoi21_0p4x (z,b1,b2,a); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule + + + +module bw_u1_zhaoi21_1x (z, a, b1, b2); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 & b2 ) | ( a )); + +endmodule + + + +module bw_u1_zhoai21_1x (z,b1,b2,a ); + + output z; + input b1; + input b2; + input a; + + assign z = ~(( b1 | b2 ) & ( a )); + +endmodule + + + + +module bw_u1_zhoai211_0p3x (z, a, b, c1, c2); + output z; + input c1; + input c2; + input b; + input a; + + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + + + + + +module bw_u1_zhoai211_1x (z, a, b, c1, c2); +output z; +input a, b, c1, c2; + assign z = ~(( c1 | c2 ) & ( a ) & (b)); + +endmodule + + + + + +/////////////// Scan data lock up latch /////////////// + +module bw_u1_scanlg_2x (so, sd, ck, se); +output so; +input sd, ck, se; + +reg so_l; + + assign so = ~so_l; + always @ ( ck or sd or se ) + if (~ck) so_l <= ~(sd & se) ; + +endmodule + +module bw_u1_scanl_2x (so, sd, ck); +output so; +input sd, ck; + +reg so_l; + + assign so = ~so_l; + always @ ( ck or sd ) + if (~ck) so_l <= ~sd ; + +endmodule + + + +////////////////// Synchronizer //////////////// + +module bw_u1_syncff_4x (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; + +reg q_r; + always @ (posedge ck) + q_r <= se ? sd : d; + assign q = q_r; + assign so = q_r; + +endmodule + + + + +//////////////////////////////////////////////////////////////////////// +// +// non library cells +// +//////////////////////////////////////////////////////////////////////// + +// These cells are used only in custom DP macros +// Do not use in any block design without prior permission + + +module bw_u1_zzeccxor2_5x (z, a, b); + output z; + input a, b; + assign z = ( a ^ b ); + +endmodule + + + +module bw_u1_zzmulcsa42_5x (sum, carry, cout, a, b, c, d, cin); +output sum, carry, cout; +input a, b, c, d, cin; +wire and_cin_b, or_cin_b, xor_a_c_d, and_or_cin_b_xor_a_c_d; +wire and_a_c, and_a_d, and_c_d; + assign sum = cin ^ a ^ b ^ c ^ d; + assign carry = cin & b | (cin | b) & (a ^ c ^ d); + assign cout = a & c | a & d | c & d; +endmodule + + + +module bw_u1_zzmulcsa32_5x (sum, cout, a, b, c); +output sum, cout; +input a, b, c; +wire and_a_b, and_a_c, and_b_c; + assign sum = a ^ b ^ c ; + assign cout = a & b | a & c | b & c ; +endmodule + + + +module bw_u1_zzmulppmuxi21_2x ( z, d0, d1, s ); +output z; +input d0, d1, s; + assign z = s ? ~d1 : ~d0; +endmodule + + + +module bw_u1_zzmulnand2_2x ( z, a, b ); +output z; +input a; +input b; + assign z = ~( a & b ); +endmodule + + + +// Primitives + + + + +module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2); +output z; +input d0, d1, d2, s0, s1, s2; +// for Blacktie +`ifdef VERPLEX + $constraint dp_1h3 ($one_hot ({s0,s1,s2})); +`endif +wire [2:0] sel = {s0,s1,s2}; // 0in one_hot +reg z; + always @ (s2 or d2 or s1 or d1 or s0 or d0) + casez ({s2,d2,s1,d1,s0,d0}) + 6'b0?0?10: z = 1'b1; + 6'b0?0?11: z = 1'b0; + 6'b0?100?: z = 1'b1; + 6'b0?110?: z = 1'b0; + 6'b0?1010: z = 1'b1; + 6'b0?1111: z = 1'b0; + 6'b100?0?: z = 1'b1; + 6'b110?0?: z = 1'b0; + 6'b100?10: z = 1'b1; + 6'b110?11: z = 1'b0; + 6'b10100?: z = 1'b1; + 6'b11110?: z = 1'b0; + 6'b101010: z = 1'b1; + 6'b111111: z = 1'b0; + default: z = 1'bx; + endcase +endmodule + + + + + + + +module zmuxi41d_prim (z, d0, d1, d2, d3, s0, s1, s2, s3); +output z; +input d0, d1, d2, d3, s0, s1, s2, s3; +// for Blacktie +`ifdef VERPLEX + $constraint dp_1h4 ($one_hot ({s0,s1,s2,s3})); +`endif +wire [3:0] sel = {s0,s1,s2,s3}; // 0in one_hot +reg z; + always @ (s3 or d3 or s2 or d2 or s1 or d1 or s0 or d0) + casez ({s3,d3,s2,d2,s1,d1,s0,d0}) + 8'b0?0?0?10: z = 1'b1; + 8'b0?0?0?11: z = 1'b0; + 8'b0?0?100?: z = 1'b1; + 8'b0?0?110?: z = 1'b0; + 8'b0?0?1010: z = 1'b1; + 8'b0?0?1111: z = 1'b0; + 8'b0?100?0?: z = 1'b1; + 8'b0?110?0?: z = 1'b0; + 8'b0?100?10: z = 1'b1; + 8'b0?110?11: z = 1'b0; + 8'b0?10100?: z = 1'b1; + 8'b0?11110?: z = 1'b0; + 8'b0?101010: z = 1'b1; + 8'b0?111111: z = 1'b0; + 8'b100?0?0?: z = 1'b1; + 8'b110?0?0?: z = 1'b0; + 8'b100?0?10: z = 1'b1; + 8'b110?0?11: z = 1'b0; + 8'b100?100?: z = 1'b1; + 8'b110?110?: z = 1'b0; + 8'b100?1010: z = 1'b1; + 8'b110?1111: z = 1'b0; + 8'b10100?0?: z = 1'b1; + 8'b11110?0?: z = 1'b0; + 8'b10100?10: z = 1'b1; + 8'b11110?11: z = 1'b0; + 8'b1010100?: z = 1'b1; + 8'b1111110?: z = 1'b0; + 8'b10101010: z = 1'b1; + 8'b11111111: z = 1'b0; + default: z = 1'bx; + endcase +endmodule + + + +module zsoff_prim (q, so, ck, d, se, sd); +output q, so; +input ck, d, se, sd; +reg q_r; + always @ (posedge ck) + q_r <= se ? sd : d; + assign q = q_r; + assign so = q_r ; +endmodule + + +module zsoffr_prim (q, so, ck, d, se, sd, r_l); +output q, so; +input ck, d, se, sd, r_l; +reg q_r; + always @ (posedge ck) + q_r <= se ? sd : (d & r_l) ; + assign q = q_r; + assign so = q_r; +endmodule + + +module zsoffi_prim (q_l, so, ck, d, se, sd); +output q_l, so; +input ck, d, se, sd; +reg q_r; + always @ (posedge ck) + q_r <= se ? sd : d; + assign q_l = ~q_r; + assign so = q_r; +endmodule + + + +module zsoffm2_prim (q, so, ck, d0, d1, s, se, sd); +output q, so; +input ck, d0, d1, s, se, sd; +reg q_r; + always @ (posedge ck) + q_r <= se ? sd : (s ? d1 : d0) ; + assign q = q_r; + assign so = q_r; +endmodule + +module zsoffasr_prim (q, so, ck, d, r_l, s_l, se, sd); + output q, so; + input ck, d, r_l, s_l, se, sd; + + // asynchronous reset and asynchronous set + // (priority: r_l > s_l > se > d) + reg q; + wire so; + + always @ (posedge ck or negedge r_l or negedge s_l) begin + if(~r_l) q <= 1'b0; + else if (~s_l) q <= r_l; + else if (se) q <= r_l & s_l & sd; + else q <= r_l & s_l & (~se) & d; + end + + assign so = q | ~se; + +endmodule + + + +module zckenbuf_prim (clk, rclk, en_l, tm_l); +output clk; +input rclk, en_l, tm_l; +reg clken; + always @ (rclk or en_l or tm_l) + if (!rclk) //latch opens on rclk low phase + clken <= ~en_l | ~tm_l; + assign clk = clken & rclk; +endmodule + +module bw_mckbuf_40x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_33x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_30x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_28x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_25x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_22x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_19x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_17x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_14x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_11x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_8x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_7x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_6x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_4p5x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_3x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +module bw_mckbuf_1p5x (clk, rclk, en); +output clk; +input rclk; +input en; + + assign clk = rclk & en ; + +endmodule + +//bw_u1_minbuf_1x +// + +module bw_u1_minbuf_1x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + +//bw_u1_minbuf_4x +// + +module bw_u1_minbuf_4x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + +//bw_u1_minbuf_5x +// + +module bw_u1_minbuf_5x ( + z, + a ); + + output z; + input a; + + assign z = ( a ); + +endmodule + +module bw_u1_ckenbuf_4p5x (clk, rclk, en_l, tm_l); +output clk; +input rclk, en_l, tm_l; + zckenbuf_prim i0 ( clk, rclk, en_l, tm_l ); +endmodule + +// dummy fill modules to get rid of DFT "CAP" property errors (bug 5487) + +module bw_u1_fill_1x(\vdd! ); +input \vdd! ; +endmodule + +module bw_u1_fill_2x(\vdd! ); +input \vdd! ; +endmodule + +module bw_u1_fill_3x(\vdd! ); +input \vdd! ; +endmodule + +module bw_u1_fill_4x(\vdd! ); +input \vdd! ; +endmodule Index: trunk/hdl/behav/sparc_libs/m1_lib.v =================================================================== --- trunk/hdl/behav/sparc_libs/m1_lib.v (nonexistent) +++ trunk/hdl/behav/sparc_libs/m1_lib.v (revision 4) @@ -0,0 +1,1034 @@ +// ========== Copyright Header Begin ========================================== +// +// OpenSPARC T1 Processor File: m1.behV +// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +// +// The above named program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// The above named program is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this work; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +// +// ========== Copyright Header End ============================================ +//////////////////////////////////////////////////////////////////////// +// 64 bit nor gate with first 32 bits out + +module zznor64_32 ( znor64, znor32, a ); + input [63:0] a; + output znor64; + output znor32; + + assign znor32 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]); + + assign znor64 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31] + | a[32] | a[33] | a[34] | a[35] | a[36] | a[37] | a[38] | a[39] + | a[40] | a[41] | a[42] | a[43] | a[44] | a[45] | a[46] | a[47] + | a[48] | a[49] | a[50] | a[51] | a[52] | a[53] | a[54] | a[55] + | a[56] | a[57] | a[58] | a[59] | a[60] | a[61] | a[62] | a[63]); + +endmodule // zznor64_32 + + + +//////////////////////////////////////////////////////////////////////////////// +// 36 bit or gate + +module zzor36 ( z, a ); + input [35:0] a; + output z; + + assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31] + | a[32] | a[33] | a[34] | a[35]); + +endmodule // zzor36 + + + +//////////////////////////////////////////////////////////////////////////////// +// 32 bit or gate + +module zzor32 ( z, a ); + input [31:0] a; + output z; + + assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]); + +endmodule // zzor32 + + + +//////////////////////////////////////////////////////////////////////////////// +// 24 bit nor gate + +module zznor24 ( z, a ); + input [23:0] a; + output z; + + assign z = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23]); + +endmodule // zznor24 + + + +//////////////////////////////////////////////////////////////////////////////// +// 16 bit nor gate + +module zznor16 ( z, a ); + input [15:0] a; + output z; + + assign z = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15]); + +endmodule // zznor16 + + + +//////////////////////////////////////////////////////////////////////////////// +// 8 bit or gate + +module zzor8 ( z, a ); + input [7:0] a; + output z; + + assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7]); + +endmodule // zzor8 + + + + +//////////////////////////////////////////////////////////////////////////////// +// Description: This block implements the adder for the sparc FPU. +// It takes two operands and a carry bit. It adds them together +// and sends the output to adder_out. + +module zzadd13 ( rs1_data, rs2_data, cin, adder_out ); + + input [12:0] rs1_data; // 1st input operand + input [12:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [12:0] adder_out; // result of adder + + assign adder_out = rs1_data + rs2_data + cin; + +endmodule // zzadd13 + + + +//////////////////////////////////////////////////////////////////////////////// +// Description: This block implements the adder for the sparc FPU. +// It takes two operands and a carry bit. It adds them together +// and sends the output to adder_out. + +module zzadd56 ( rs1_data, rs2_data, cin, adder_out ); + + input [55:0] rs1_data; // 1st input operand + input [55:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [55:0] adder_out; // result of adder + + assign adder_out = rs1_data + rs2_data + cin; + +endmodule // zzadd56 + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzadd48 ( rs1_data, rs2_data, cin, adder_out ); + + input [47:0] rs1_data; // 1st input operand + input [47:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [47:0] adder_out; // result of adder + + assign adder_out = rs1_data + rs2_data + cin; + +endmodule // zzadd48 + + + +//////////////////////////////////////////////////////////////////////////////// +// This adder is primarily used in the multiplier. +// The cin to out path is optimized. + +module zzadd34c ( rs1_data, rs2_data, cin, adder_out ); + + input [33:0] rs1_data; + input [33:0] rs2_data; + input cin; + + output [33:0] adder_out; + + assign adder_out = rs1_data + rs2_data + cin; + + +endmodule // zzadd34c + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzadd32 ( rs1_data, rs2_data, cin, adder_out, cout ); + + input [31:0] rs1_data; // 1st input operand + input [31:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [31:0] adder_out; // result of adder + output cout; // carry out + + assign {cout, adder_out} = rs1_data + rs2_data + cin; + +endmodule // zzadd32 + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzadd18 ( rs1_data, rs2_data, cin, adder_out, cout ); + + input [17:0] rs1_data; // 1st input operand + input [17:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [17:0] adder_out; // result of adder + output cout; // carry out + + assign {cout, adder_out} = rs1_data + rs2_data + cin; + +endmodule // zzadd18 + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzadd8 ( rs1_data, rs2_data, cin, adder_out, cout ); + + input [7:0] rs1_data; // 1st input operand + input [7:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [7:0] adder_out; // result of add & decrement + output cout; // carry out + + assign {cout, adder_out} = rs1_data + rs2_data + cin; + +endmodule // zzadd8 + + + +//////////////////////////////////////////////////////////////////////////////// +// Special 4-operand 32b adder used in spu_shamd5 +// Description: This block implements the 4-operand 32-bit adder for SPU +// It takes four 32-bit operands. It add them together and +// output the 32-bit results to adder_out. The overflow of +// 32th bit and higher will be ignored. + +module zzadd32op4 ( rs1_data, rs2_data, rs3_data, rs4_data, adder_out ); + + input [31:0] rs1_data; // 1st input operand + input [31:0] rs2_data; // 2nd input operand + input [31:0] rs3_data; // 3rd input operand + input [31:0] rs4_data; // 4th input operand + + output [31:0] adder_out; // result of add + + assign adder_out = rs1_data + rs2_data + rs3_data + rs4_data; + +endmodule // zzadd32op4 + + +//////////////////////////////////////////////////////////////////////////////// +// Description: This block implements the adder for the sparc alu. +// It takes two operands and a carry bit. It adds them together +// and sends the output to adder_out. It outputs the overflow +// and carry condition codes for both 64 bit and 32 bit operations. + +module zzadd64 ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 ); + + input [63:0] rs1_data; // 1st input operand + input [63:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [63:0] adder_out; // result of adder + output cout32; // carry out from lower 32 bit add + output cout64; // carry out from 64 bit add + + assign {cout32, adder_out[31:0]} = rs1_data[31:0] + rs2_data[31:0] + cin; + assign {cout64, adder_out[63:32]} = rs1_data[63:32] + rs2_data[63:32] + cout32; + +endmodule // zzadd64 + + + +/////////////////////////////////////////////////////////////////////// +/* +// Description: This is the ffu VIS adder. It can do either +// 2 16 bit adds or 1 32 bit add. +*/ + +module zzadd32v (/*AUTOARG*/ + // Outputs + z, + // Inputs + a, b, cin, add32 + ) ; + input [31:0] a; + input [31:0] b; + input cin; + input add32; + + output [31:0] z; + + wire cout15; // carry out from lower 16 bit add + wire cin16; // carry in to the upper 16 bit add + wire cout31; // carry out from the upper 16 bit add + + assign cin16 = (add32)? cout15: cin; + + assign {cout15, z[15:0]} = a[15:0]+b[15:0]+ cin; + assign {cout31, z[31:16]} = a[31:16]+b[31:16]+ cin16; + +endmodule // zzadd32v + + + + +//////////////////////////////////////////////////////////////////////////////// +// 64-bit incrementer + +module zzinc64 ( in, out ); + + input [63:0] in; + + output [63:0] out; // result of increment + + assign out = in + 1'b1; + +endmodule // zzinc64 + + +//////////////////////////////////////////////////////////////////////////////// +// 48-bit incrementer + +module zzinc48 ( in, out, overflow ); + + input [47:0] in; + + output [47:0] out; // result of increment + output overflow; // overflow + + assign out = in + 1'b1; + assign overflow = ~in[47] & out[47]; + +endmodule // zzinc48 + + +//////////////////////////////////////////////////////////////////////////////// +// 32-bit incrementer + +module zzinc32 ( in, out ); + + input [31:0] in; + + output [31:0] out; // result of increment + + assign out = in + 1'b1; + +endmodule // zzinc32 + + +//////////////////////////////////////////////////////////////////////////////// + +module zzecc_exu_chkecc2 ( q,ce, ue, ne, d, p, vld ); + input [63:0] d; + input [7:0] p; + input vld; + output [6:0] q; + output ce, + ue, + ne; + + wire parity; + + assign ce = vld & parity; + + assign ue = vld & ~parity & (q[6] | q[5] | q[4] | q[3] | q[2] | q[1] | q[0]); + + assign ne = ~vld | ~(parity | q[6] | q[5] | q[4] | q[3] | q[2] | q[1] | q[0]); + + + assign q[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] + ^ d[11] ^ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] + ^ d[25] ^ d[26] ^ d[28] ^ d[30] ^ d[32] ^ d[34] ^ d[36] + ^ d[38] ^ d[40] ^ d[42] ^ d[44] ^ d[46] ^ d[48] ^ d[50] + ^ d[52] ^ d[54] ^ d[56] ^ d[57] ^ d[59] ^ d[61] ^ d[63] + ^ p[0] ; + + assign q[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] + ^ d[12] ^ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] + ^ d[25] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[35] ^ d[36] + ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[47] ^ d[48] ^ d[51] + ^ d[52] ^ d[55] ^ d[56] ^ d[58] ^ d[59] ^ d[62] ^ d[63] + ^ p[1] ; + + assign q[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] + ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] + ^ d[25] ^ d[29] ^ d[30] ^ d[31] ^ d[32] ^ d[37] ^ d[38] + ^ d[39] ^ d[40] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[53] + ^ d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[63] + ^ p[2] ; + + assign q[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] + ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] + ^ d[25] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] + ^ d[39] ^ d[40] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53] + ^ d[54] ^ d[55] ^ d[56] ^ p[3] ; + + assign q[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] + ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] + ^ d[25] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] + ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53] + ^ d[54] ^ d[55] ^ d[56] ^ p[4] ; + + assign q[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^ d[32] + ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[39] + ^ d[40] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] + ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53] + ^ d[54] ^ d[55] ^ d[56] ^ p[5] ; + + assign q[6] = d[57] ^ d[58] ^ d[59] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ p[6] ; + + assign parity = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] + ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[39] + ^ d[40] ^ d[41] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] + ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[55] + ^ d[56] ^ d[57] ^ d[58] ^ d[59] ^ d[60] ^ d[61] ^ d[62] ^ d[63] + ^ p[0] ^ p[1] ^ p[2] ^ p[3] ^ p[4] ^ p[5] ^ p[6] ^ p[7]; + +endmodule // zzecc_exu_chkecc2 + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzecc_sctag_24b_gen ( din, dout, parity ) ; + +// Input Ports +input [23:0] din ; + +// Output Ports +output [23:0] dout ; +output [5:0] parity ; + +wire [23:0] dout ; +wire [5:0] parity ; + +// Local Reg and Wires +wire p1 ; +wire p2 ; +wire p4 ; +wire p8 ; +wire p16 ; +wire p30 ; + + +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 | +// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30| +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +//P1 | | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | | +//P2 | | |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | | +//P4 | | | | |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | | +//P8 | | | | | | | | |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | | +//P16 | | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | | +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +//p30 | | |* | |* |* | | |* |* | |* | | | * | | * | * | | * | | | * | * | | | * | | * | | +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| + + +assign p1 = din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^ + din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^ + din[21] ^ din[23] ; + +assign p2 = din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^ + din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^ + din[21] ; + +assign p4 = din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^ + din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^ + din[23] ; + +assign p8 = din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^ + din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^ + din[23] ; + +assign p16 = din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^ + din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^ + din[23] ; + +assign p30 = din[0] ^ din[1] ^ din[2] ^ din[4] ^ din[5] ^ + din[7] ^ din[10] ^ din[11] ^ din[12] ^ din[14] ^ + din[17] ^ din[18] ^ din[21] ^ din[23] ; + +assign dout = din ; +assign parity = {p30, p16, p8, p4, p2, p1} ; + +endmodule + + + +//////////////////////////////////////////////////////////////////////////////// + +module zzecc_sctag_30b_cor ( din, parity, dout, corrected_bit ) ; + +// Input Ports +input [23:0] din ; +input [4:0] parity ; + +// Output Ports +output [23:0] dout ; +output [4:0] corrected_bit ; + +wire [23:0] dout ; +wire [4:0] corrected_bit ; + +// Local Reg and Wires +wire p1 ; +wire p2 ; +wire p4 ; +wire p8 ; +wire p16 ; +wire [23:0] error_bit ; + + +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 | +// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30| +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +//P1 |* | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | | +//P2 | |* |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | | +//P4 | | | |* |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | | +//P8 | | | | | | | |* |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | | +//P16 | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | * | | +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +//p30 |* |* |* |* |* |* |* |* |* |* |* |* |* |* | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * | +//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| + + +assign p1 = parity[0] ^ + din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^ + din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^ + din[21] ^ din[23] ; + +assign p2 = parity[1] ^ + din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^ + din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^ + din[21] ; + +assign p4 = parity[2] ^ + din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^ + din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^ + din[23] ; + +assign p8 = parity[3] ^ + din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^ + din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^ + din[23] ; + +assign p16 = parity[4] ^ + din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^ + din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^ + din[23] ; + +assign error_bit[0] = !p16 & !p8 & !p4 & p2 & p1 ; // 3 +assign error_bit[1] = !p16 & !p8 & p4 & !p2 & p1 ; // 5 +assign error_bit[2] = !p16 & !p8 & p4 & p2 & !p1 ; // 6 +assign error_bit[3] = !p16 & !p8 & p4 & p2 & p1 ; // 7 +assign error_bit[4] = !p16 & p8 & !p4 & !p2 & p1 ; // 9 +assign error_bit[5] = !p16 & p8 & !p4 & p2 & !p1 ; // 10 +assign error_bit[6] = !p16 & p8 & !p4 & p2 & p1 ; // 11 +assign error_bit[7] = !p16 & p8 & p4 & !p2 & !p1 ; // 12 +assign error_bit[8] = !p16 & p8 & p4 & !p2 & p1 ; // 13 +assign error_bit[9] = !p16 & p8 & p4 & p2 & !p1 ; // 14 +assign error_bit[10] = !p16 & p8 & p4 & p2 & p1 ; // 15 +assign error_bit[11] = p16 & !p8 & !p4 & !p2 & p1 ; // 17 +assign error_bit[12] = p16 & !p8 & !p4 & p2 & !p1 ; // 18 +assign error_bit[13] = p16 & !p8 & !p4 & p2 & p1 ; // 19 +assign error_bit[14] = p16 & !p8 & p4 & !p2 & !p1 ; // 20 +assign error_bit[15] = p16 & !p8 & p4 & !p2 & p1 ; // 21 +assign error_bit[16] = p16 & !p8 & p4 & p2 & !p1 ; // 22 +assign error_bit[17] = p16 & !p8 & p4 & p2 & p1 ; // 23 +assign error_bit[18] = p16 & p8 & !p4 & !p2 & !p1 ; // 24 +assign error_bit[19] = p16 & p8 & !p4 & !p2 & p1 ; // 25 +assign error_bit[20] = p16 & p8 & !p4 & p2 & !p1 ; // 26 +assign error_bit[21] = p16 & p8 & !p4 & p2 & p1 ; // 27 +assign error_bit[22] = p16 & p8 & p4 & !p2 & !p1 ; // 28 +assign error_bit[23] = p16 & p8 & p4 & !p2 & p1 ; // 29 + +assign dout = din ^ error_bit ; +assign corrected_bit = {p16, p8, p4, p2, p1} ; + +endmodule + + + +//////////////////////////////////////////////////////////////////////////////// +//Module Name: zzecc_sctag_ecc39 +//Function: Error Detection and Correction +// +// + +module zzecc_sctag_ecc39 ( dout, cflag, pflag, parity, din); + + //Output: 32bit corrected data + output[31:0] dout; + output [5:0] cflag; + output pflag; + + //Input: 32bit data din + input [31:0] din; + input [6:0] parity; + + wire c0,c1,c2,c3,c4,c5; + wire [31:0] err_bit_pos; + + //refer to the comments in parity_gen_32b.v for the position description + + assign c0= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8]) + ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19]) + ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]); + + assign c1= parity[1]^(din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9]) + ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20]) + ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]); + + assign c2= parity[2]^(din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9]) + ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22]) + ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]); + + assign c3= parity[3]^(din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9]) + ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22]) + ^(din[23]^din[24])^din[25]; + + assign c4= parity[4]^(din[11]^din[12])^(din[13]^din[14])^ + (din[15]^din[16])^(din[17]^din[18])^(din[19]^din[20])^ + (din[21]^din[22])^(din[23]^din[24])^din[25]; + + assign c5= parity[5]^(din[26]^din[27])^(din[28]^din[29])^ + (din[30]^din[31]); + + //generate total parity flag + assign pflag= c0 ^ + (( (((parity[1]^parity[2])^(parity[3]^parity[4])) ^ + ((parity[5]^parity[6])^(din[2]^din[5]))) ^ + (((din[7]^din[9])^(din[12]^din[14])) ^ + ((din[16]^din[18])^(din[20]^din[22]))) ) ^ + ((din[24]^din[27])^(din[29]^din[31])) ); + + assign cflag= {c5,c4,c3,c2,c1,c0}; + + //6 to 32 decoder + assign err_bit_pos[0] = (c0)&(c1)&(~c2)&(~c3)&(~c4)&(~c5); + assign err_bit_pos[1] = (c0)&(~c1)&(c2)&(~c3)&(~c4)&(~c5); + assign err_bit_pos[2] = (~c0)&(c1)&(c2)&(~c3)&(~c4)&(~c5); + assign err_bit_pos[3] = (c0)&(c1)&(c2)&(~c3)&(~c4)&(~c5); + assign err_bit_pos[4] = (c0)&(~c1)&(~c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[5] = (~c0)&(c1)&(~c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[6] = (c0)&(c1)&(~c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[7] = (~c0)&(~c1)&(c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[8] = (c0)&(~c1)&(c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[9] = (~c0)&(c1)&(c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[10] = (c0)&(c1)&(c2)&(c3)&(~c4)&(~c5); + assign err_bit_pos[11] = (c0)&(~c1)&(~c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[12] = (~c0)&(c1)&(~c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[13] = (c0)&(c1)&(~c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[14] = (~c0)&(~c1)&(c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[15] = (c0)&(~c1)&(c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[16] = (~c0)&(c1)&(c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[17] = (c0)&(c1)&(c2)&(~c3)&(c4)&(~c5); + assign err_bit_pos[18] = (~c0)&(~c1)&(~c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[19] = (c0)&(~c1)&(~c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[20] = (~c0)&(c1)&(~c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[21] = (c0)&(c1)&(~c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[22] = (~c0)&(~c1)&(c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[23] = (c0)&(~c1)&(c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[24] = (~c0)&(c1)&(c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[25] = (c0)&(c1)&(c2)&(c3)&(c4)&(~c5); + assign err_bit_pos[26] = (c0)&(~c1)&(~c2)&(~c3)&(~c4)&(c5); + assign err_bit_pos[27] = (~c0)&(c1)&(~c2)&(~c3)&(~c4)&(c5); + assign err_bit_pos[28] = (c0)&(c1)&(~c2)&(~c3)&(~c4)&(c5); + assign err_bit_pos[29] = (~c0)&(~c1)&(c2)&(~c3)&(~c4)&(c5); + assign err_bit_pos[30] = (c0)&(~c1)&(c2)&(~c3)&(~c4)&(c5); + assign err_bit_pos[31] = (~c0)&(c1)&(c2)&(~c3)&(~c4)&(c5); + + //correct the error bit, it can only correct one error bit. + + assign dout = din ^ err_bit_pos; + +endmodule // zzecc_sctag_ecc39 + + +//////////////////////////////////////////////////////////////////////////////// +//Module Name: zzecc_sctag_pgen_32b +//Function: Generate 7 parity bits for 32bits input data +// + +module zzecc_sctag_pgen_32b ( dout, parity, din); + + //Output: 32bit dout and 7bit parity bit + output[31:0] dout; + output [6:0] parity; + + //Input: 32bit data din + input [31:0] din; + + //input data passing through this module + assign dout = din ; + + //generate parity bits based on the hamming codes + //the method to generate parity bit is shown as follows + //1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 + //P1 P2 d0 P4 d1 d2 d3 P8 d4 d5 d6 d7 d8 d9 d10 P16 d11 d12 d13 + // + // 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 + //d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 P32 d26 d27 d28 + // + // 36 37 38 + //d29 d30 d31 + //For binary numbers B1-B2-B3-B4-B5-B6: + //B1=1 for (1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,...) + //B2=1 for (2,3,6,7,10,11,14,15,18,19,22,23,26,27,30,31,34,35,38,39...) + //B3=1 for (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31,36,37,38,39....) + //B4=1 for (8,9,10,11,12,13,14,15,24,25,26,27,28,29,30,31,40,41,42,....) + //B5=1 for (16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,48,49,...) + //B6=1 for (32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49...) + //Parity bit P1,P2,P4,P8,P16,P32 can be generated from the above group of + //bits B1=1,B2=1,B3=1,B4=1,B5=1,B6=1 respectively. + + //use parity[5:0] to stand for P1,P2,P4,P8,P16,P32 + assign parity[0] = (din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8]) + ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19]) + ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]); + // + assign parity[1] = (din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9]) + ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20]) + ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]); + // + assign parity[2] = (din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9]) + ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22]) + ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]); + // + assign parity[3] = (din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9]) + ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22]) + ^(din[23]^din[24])^din[25]; + // + assign parity[4] = (din[11]^din[12])^(din[13]^din[14])^(din[15]^din[16]) + ^(din[17]^din[18])^(din[19]^din[20])^(din[21]^din[22]) + ^(din[23]^din[24])^din[25]; + // + assign parity[5] = (din[26]^din[27])^(din[28]^din[29])^(din[30]^din[31]); + + //the last parity bit is the xor of all 38bits + //assign parity[6] = (^din)^(^parity[5:0]); + //it can be further simplified as: + //din= d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + //p0 = x x x x x x x x x x + //p1 = x x x x x x x x x + //p2 = x x x x x x x x x + //p3 = x x x x x x x + //p4 = x x x x x + //p5 = + //------------------------------------------------------------------- + //Total 3 3 3 4 3 3 4 3 4 4 5 3 3 4 3 4 + // + //din=d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 + //p0= x x x x x x x x + //p1= x x x x x x x x x + //p2= x x x x x x x x x + //p3= x x x x x x x x + //p4= x x x x x x x x x x + //p5= x x x x x x + //------------------------------------------------------------------- + //total 4 5 3 4 4 5 4 5 5 6 3 3 4 3 4 4 + + //so total=even number, the corresponding bit will not show up in the + //final xor tree. + assign parity[6] = din[0] ^ din[1] ^ din[2] ^ din[4] ^ din[5] ^ din[7] + ^ din[10] ^ din[11] ^ din[12] ^ din[14] ^ din[17] + ^ din[18] ^ din[21] ^ din[23] ^ din[24] ^ din[26] + ^ din[27] ^ din[29]; + +endmodule // zzecc_sctag_pgen_32b + +//////////////////////////////////////////////////////////////////////////////// +// 34 bit parity tree + +module zzpar34 ( z, d ); + input [33:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] + ^ d[32] ^ d[33]; + +endmodule // zzpar34 + + + +//////////////////////////////////////////////////////////////////////////////// +// 32 bit parity tree + +module zzpar32 ( z, d ); + input [31:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]; + +endmodule // zzpar32 + + + +//////////////////////////////////////////////////////////////////////////////// +// 28 bit parity tree + +module zzpar28 ( z, d ); + input [27:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27]; + +endmodule // zzpar28 + + + +//////////////////////////////////////////////////////////////////////////////// +// 16 bit parity tree + +module zzpar16 ( z, d ); + input [15:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15]; + +endmodule // zzpar16 + + + +//////////////////////////////////////////////////////////////////////////////// +// 8 bit parity tree + +module zzpar8 ( z, d ); + input [7:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]; + +endmodule // zzpar8 + + + +//////////////////////////////////////////////////////////////////////////////// +// 64 -> 6 priority encoder +// Bit 63 has the highest priority + +module zzpenc64 (/*AUTOARG*/ + // Outputs + z, + // Inputs + a + ); + + input [63:0] a; + output [5:0] z; + + integer i; + reg [5:0] z; + + always @ (a) + begin + z = 6'b0; + for (i=0;i<64;i=i+1) + if (a[i]) + z = i; + end + +endmodule // zzpenc64 + +//////////////////////////////////////////////////////////////////////////////// +// 4-bit 60x buffers + +module zzbufh_60x4 (/*AUTOARG*/ + // Outputs + z, + // Inputs + a + ); + + input [3:0] a; + output [3:0] z; + + assign z = a; + +endmodule //zzbufh_60x4 + +// LVT modules added below + +module zzadd64_lv ( rs1_data, rs2_data, cin, adder_out, cout32, cout64 ); + + input [63:0] rs1_data; // 1st input operand + input [63:0] rs2_data; // 2nd input operand + input cin; // carry in + + output [63:0] adder_out; // result of adder + output cout32; // carry out from lower 32 bit add + output cout64; // carry out from 64 bit add + + assign {cout32, adder_out[31:0]} = rs1_data[31:0] + rs2_data[31:0] + cin; + assign {cout64, adder_out[63:32]} = rs1_data[63:32] + rs2_data[63:32] + cout32; + +endmodule // zzadd64_lv + +module zzpar8_lv ( z, d ); + input [7:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7]; + +endmodule // zzpar8_lv + + +module zzpar32_lv ( z, d ); + input [31:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31]; + +endmodule // zzpar32_lv + + + +module zznor64_32_lv ( znor64, znor32, a ); + input [63:0] a; + output znor64; + output znor32; + + assign znor32 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31]); + + assign znor64 = ~(a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31] + | a[32] | a[33] | a[34] | a[35] | a[36] | a[37] | a[38] | a[39] + | a[40] | a[41] | a[42] | a[43] | a[44] | a[45] | a[46] | a[47] + | a[48] | a[49] | a[50] | a[51] | a[52] | a[53] | a[54] | a[55] + | a[56] | a[57] | a[58] | a[59] | a[60] | a[61] | a[62] | a[63]); + +endmodule // zznor64_32_lv + +//////////////////////////////////////////////////////////////////////////////// +// 64 -> 6 priority encoder +// Bit 63 has the highest priority +// LVT version + +module zzpenc64_lv (/*AUTOARG*/ + // Outputs + z, + // Inputs + a + ); + + input [63:0] a; + output [5:0] z; + + integer i; + reg [5:0] z; + + always @ (a) + begin + z = 6'b0; + for (i=0;i<64;i=i+1) + if (a[i]) + z = i; + end + +endmodule // zzpenc64_lv + +//////////////////////////////////////////////////////////////////////////////// +// 36 bit or gate +// LVT version + +module zzor36_lv ( z, a ); + input [35:0] a; + output z; + + assign z = (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7] + | a[8] | a[9] | a[10] | a[11] | a[12] | a[13] | a[14] | a[15] + | a[16] | a[17] | a[18] | a[19] | a[20] | a[21] | a[22] | a[23] + | a[24] | a[25] | a[26] | a[27] | a[28] | a[29] | a[30] | a[31] + | a[32] | a[33] | a[34] | a[35]); + +endmodule // zzor36_lv + +//////////////////////////////////////////////////////////////////////////////// +// 34 bit parity tree +// LVT version + +module zzpar34_lv ( z, d ); + input [33:0] d; + output z; + + assign z = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] + ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] + ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] + ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] + ^ d[32] ^ d[33]; + +endmodule // zzpar34_lv + + Index: trunk/docs/LICENSE.txt =================================================================== --- trunk/docs/LICENSE.txt (nonexistent) +++ trunk/docs/LICENSE.txt (revision 4) @@ -0,0 +1,753 @@ +Simply RISC S1 Core - License for Design and Documentation +========================================================== + +The S1 Core is a free hardware design released under the +GNU General Public License (GPL) version, 2 unless otherwise +specified. + +The documentation provided with the S1 Core is released under +the GNU Free Documentation License (FDL) version 1.2. + +Both the licenses follow. + +---------------------------------------------------------------------- + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Index: trunk/docs/REQUIREMENTS.txt =================================================================== --- trunk/docs/REQUIREMENTS.txt (nonexistent) +++ trunk/docs/REQUIREMENTS.txt (revision 4) @@ -0,0 +1,53 @@ +Simply RISC S1 Core - System Requirements +========================================= + +You can run simulation and synthesis of the S1 Core +almost on any machine: all you need is a Unix-like +machine with the following programs installed: + +- bash shell; +- sed stream editor; +- for simulations: Icarus Verilog (free software) + or Synopsys VCS MX (commercial); +- for synthesis: Icarus Verilog (free software) or + Synopsys Design Compiler (commercial). + +As you can easily understand, whatever GNU/Linux or +Unix machine should be suitable for your purposes; +we haven't tried on Windows with Cygwin but we suspect +that it could work (please let us know your experience +at support@srisc.com and we'll list it here). + +Infact since the only tool you need for simulation and +synthesis is Icarus Verilog, and since it is free +software, you can download its source code and compile +it for your platform. + +On some GNU/Linux distributions there's even no need +to compile it since you can install it from Internet +with one command: + +- on Debian and similar distros like Ubuntu to install + Icarus Verilog just use the command: + + apt-get install verilog + +- if you are a Gentoo maniac you can use the command: + + emerge iverilog + +In both cases you will need an Internet connection and +root privileges to perform the installation (otherwise +go to the official site and compile it from the sources). + +Please note that we have been using Icarus version 0.8 +without any trouble, but some user reported some compiling +error using the latest version 0.8.2. + +Another requirement is related with the SPARC v9 compiler: +there's an x86 to sparc64 GCC cross-compiler available +on the web so you should be able to compile test programs +for the S1 Core using not only a SPARC machine but whatever +GNU/Linux x86 PC; please check on the Download Area of the +Simply RISC website at http://www.srisc.com . + Index: trunk/docs/other/ACCESSES.txt =================================================================== --- trunk/docs/other/ACCESSES.txt (nonexistent) +++ trunk/docs/other/ACCESSES.txt (revision 4) @@ -0,0 +1,86 @@ +Simply RISC S1 Core - List of T1 accesses +========================================= + +This is the list of the first accesses performed by +the SPARC Core in the core1_mini test-suite of the +OpenSPARC T1. + +- receive packet 1700....0010001 (INT_RET) +- following requests go to region 4, base addr FFF0000020 (SSI ROM) +- request packet C2018FFF0000020...00 (ROM Addr 20 -> 1 Byte?) +- receive packet 111040300000005000100821060008410A0C0 (A-Type) +- request packet C2008FFF0000024...00 (ROM Addr 24) +- receive packet 111040300000005000100821060008410A0C0 (A-Type) +- request packet C2008FFF0000028...00 (ROM Addr 28) +- receive packet 111040300000005000100821060008410A0C0 (A-Type) +- request packet C2010FFF000002C...00 (ROM Addr 2C) +- receive packet 111040300000005000100821060008410A0C0 (A-Type) +- request packet C2010FFF0000030...00 (ROM Addr 30) +- receive packet 11104832870208410800181C0800001000000 (B-Type) +- request packet C2008FFF0000034...00 (ROM Addr 34) +- receive packet 11104832870208410800181C0800001000000 (B-Type) +- request packet C2018FFF0000038...00 (ROM Addr 38) +- receive packet 11104832870208410800181C0800001000000 (B-Type) +- request packet C2000FFF000003C...00 (ROM Addr 3C) +- receive packet 11104832870208410800181C0800001000000 (B-Type) +- now we have some requests to region 3 +- request packet C200800000400C0...00 (RAM Bank 3 Addr 400C0) +- very long pause (maybe PLL?) and then receive 2 consecutive packets +- receive packet 11900B5802005A2102000821020A983287020 (C-Type) +- receive packet 11102E2706000E2706040E2706080E27060C0 (D-Type) +- request packet C201000000400C0...00 (RAM Bank 3 Addr 400C0) +- a bit long pause and receive the same two consecutive packets +- receive packet 11900B5802005A2102000821020A983287020 (C-Type) +- receive packet 11102E2706000E2706040E2706080E27060C0 (D-Type) +- now we are at 4900 ns, it is enough for now +- after some other accesses to Bank 3 then they are everywhere in RAM + +And here are some notes about the memory map: + +@0000008000 // Section '.RED_EXT_SEC', segment 'text' - Was PA 0000040000 YES 40000-402C0 (2) RAM3012 +@0000009800 // Section '.RED_EXT_SEC', segment 'data' - Was PA 000004c000 YES 4C000-4C1A0 (5) RAM01 +@0000010000 // Section '.HTRAPS', segment 'text' - Was PA 0000080000 YES 80C80-843A0 (7) RAM2 +@0000011800 // Section '.HTRAPS', segment 'data' - Was PA 000008c000 NO (ZEROES) + +// MMU is useless?!? +@0000200000 // TSB 'part_0_i_ctx_zero_ps0_tsb' - Was PA 0001000000 +@0000200034 // from compressed 0x0000000001000000 - Was PA 00010001a0 +@0000200038 // from compressed 0x0000000001000000 - Was PA 00010001c0 +@0000200120 // from compressed 0x0000000001000000 - Was PA 0001000900 +@000020012C // from compressed 0x0000000001000000 - Was PA 0001000960 +@0000200144 // from compressed 0x0000000001000000 - Was PA 0001000a20 +@0000200148 // from compressed 0x0000000001000000 - Was PA 0001000a40 +@0000400000 // TSB 'part_0_i_ctx_nonzero_ps0_tsb' - Was PA 0002000000 +@0000400004 // from compressed 0x0000000002000000 - Was PA 0002000020 +@0000400034 // from compressed 0x0000000002000000 - Was PA 00020001a0 +@0000400038 // from compressed 0x0000000002000000 - Was PA 00020001c0 +@0000400144 // from compressed 0x0000000002000000 - Was PA 0002000a20 +@0000400148 // from compressed 0x0000000002000000 - Was PA 0002000a40 +@0000A00000 // TSB 'part_0_d_ctx_zero_ps0_tsb' - Was PA 0005000000 +@0000A0012C // from compressed 0x0000000005000000 - Was PA 0005000960 +@0000A00138 // from compressed 0x0000000005000000 - Was PA 00050009c0 +@0000A00434 // from compressed 0x0000000005000000 - Was PA 00050021a0 +@0000A00438 // from compressed 0x0000000005000000 - Was PA 00050021c0 +@0000C00000 // TSB 'part_0_d_ctx_nonzero_ps0_tsb' - Was PA 0006000000 +@0000C00434 // from compressed 0x0000000006000000 - Was PA 00060021a0 +@0000C00438 // from compressed 0x0000000006000000 - Was PA 00060021c0 +@0008200000 // TSB_LINK 'part_0_tsb_link' - Was PA 0041000000 + +@0200024000 // Section '.TRAPS', segment 'text' - Was PA 1000120000 YES 1000122400-10001225C0 (10) RAM31 +@0200025800 // Section '.TRAPS', segment 'data' - Was PA 100012c000 NO (ZEROES) +@0200028800 // Section '.HPRIV_RESET', segment 'text' - Was PA 1000144000 YES 1000144000-1000144020 (8) RAM0 +@0220306800 // Section '.KERNEL', segment 'text' - Was PA 1101834000 YES 1101834000-1101834080 (9) RAM012 +@0220386800 // Section '.KERNEL', segment 'data' - Was PA 1101c34000 YES 1101C34020-1101C34028 (11) RAM0 +@0226000000 // Section '.MAIN', segment 'text' - Was PA 1130000000 YES 1130000000-1130000080 (12) RAM012 +@022E000000 // Section '.MAIN', segment 'data' - Was PA 1170000000 NO (EMPTY) +@022F004000 // Section '.USER_HEAP', segment 'data' - Was PA 1178020000 NO (EMPTY) +@022F006000 // Section '.MAIN', segment 'bss' - Was PA 1178030000 NO (EMPTY) + +// SSI ROM +@1FFE000000 // Section '.RED_SEC', segment 'text' - Was PA fff0000000 YES FFF0000020-FFF000003C (1) I/O +@1FFE002000 // Section '.RED_SEC', segment 'data' - Was PA fff0010000 NO (ONLY 1 WORD) + +// Accessed but missing in mem.image +PA 0000000000-0000000400 (6) +PA A900000000-A9000000C0 (3) RAM0123 +PA AA00000000-AA000000C0 (4) RAM0123 Index: trunk/docs/other/BLOCKS.txt =================================================================== --- trunk/docs/other/BLOCKS.txt (nonexistent) +++ trunk/docs/other/BLOCKS.txt (revision 4) @@ -0,0 +1,66 @@ +Simply RISC S1 Core - Blocks of the SPARC Core +============================================== + +When you are in the OpenSPARC environment and you run +"rsyn sparc" to synthetize just the SPARC Core, you +obtain the following list of blocks to be synthetized: + +rsyn: Running synthesis for 57 modules +rsyn: Running synthesis for sparc/bw_clk_cl_sparc_cmp +rsyn: Running synthesis for sparc/cpx_spc_buf +rsyn: Running synthesis for sparc/cpx_spc_rpt +rsyn: Running synthesis for sparc/exu/sparc_exu_alu +rsyn: Running synthesis for sparc/exu/sparc_exu_byp +rsyn: Running synthesis for sparc/exu/sparc_exu_div +rsyn: Running synthesis for sparc/exu/sparc_exu_ecc +rsyn: Running synthesis for sparc/exu/sparc_exu_ecl +rsyn: Running synthesis for sparc/exu/sparc_exu_rml +rsyn: Running synthesis for sparc/exu/sparc_exu_shft +rsyn: Running synthesis for sparc/ffu/sparc_ffu_ctl +rsyn: Running synthesis for sparc/ffu/sparc_ffu_dp +rsyn: Running synthesis for sparc/ffu/sparc_ffu_vis +rsyn: Running synthesis for sparc/ifu/sparc_ifu_dcl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_dec +rsyn: Running synthesis for sparc/ifu/sparc_ifu_errctl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_errdp +rsyn: Running synthesis for sparc/ifu/sparc_ifu_fcl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_fdp +rsyn: Running synthesis for sparc/ifu/sparc_ifu_ifqctl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_ifqdp +rsyn: Running synthesis for sparc/ifu/sparc_ifu_imd +rsyn: Running synthesis for sparc/ifu/sparc_ifu_invctl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_mbist +rsyn: Running synthesis for sparc/ifu/sparc_ifu_sscan +rsyn: Running synthesis for sparc/ifu/sparc_ifu_swl +rsyn: Running synthesis for sparc/ifu/sparc_ifu_wseldp +rsyn: Running synthesis for sparc/lsu/lsu_dcdp +rsyn: Running synthesis for sparc/lsu/lsu_dctl +rsyn: Running synthesis for sparc/lsu/lsu_dctldp +rsyn: Running synthesis for sparc/lsu/lsu_excpctl +rsyn: Running synthesis for sparc/lsu/lsu_qctl1 +rsyn: Running synthesis for sparc/lsu/lsu_qctl2 +rsyn: Running synthesis for sparc/lsu/lsu_qdp1 +rsyn: Running synthesis for sparc/lsu/lsu_qdp2 +rsyn: Running synthesis for sparc/lsu/lsu_stb_ctl +rsyn: Running synthesis for sparc/lsu/lsu_stb_ctldp +rsyn: Running synthesis for sparc/lsu/lsu_stb_rwctl +rsyn: Running synthesis for sparc/lsu/lsu_stb_rwdp +rsyn: Running synthesis for sparc/lsu/lsu_tagdp +rsyn: Running synthesis for sparc/lsu/lsu_tlbdp +rsyn: Running synthesis for sparc/mul/sparc_mul_top +rsyn: Running synthesis for sparc/spc_pcx_buf +rsyn: Running synthesis for sparc/spu/spu_ctl +rsyn: Running synthesis for sparc/spu/spu_lsurpt +rsyn: Running synthesis for sparc/spu/spu_lsurpt1 +rsyn: Running synthesis for sparc/spu/spu_madp +rsyn: Running synthesis for sparc/tlu/sparc_tlu_intctl +rsyn: Running synthesis for sparc/tlu/sparc_tlu_intdp +rsyn: Running synthesis for sparc/tlu/tlu_hyperv +rsyn: Running synthesis for sparc/tlu/tlu_incr64 +rsyn: Running synthesis for sparc/tlu/tlu_misctl +rsyn: Running synthesis for sparc/tlu/tlu_mmu_ctl +rsyn: Running synthesis for sparc/tlu/tlu_mmu_dp +rsyn: Running synthesis for sparc/tlu/tlu_pib +rsyn: Running synthesis for sparc/tlu/tlu_tcl +rsyn: Running synthesis for sparc/tlu/tlu_tdp + Index: trunk/docs/SIMULATION.txt =================================================================== --- trunk/docs/SIMULATION.txt (nonexistent) +++ trunk/docs/SIMULATION.txt (revision 4) @@ -0,0 +1,41 @@ +Simply RISC S1 Core - Simulation Environment +============================================ + +To run a simulation using the free software Icarus Verilog +simulator use the following commands: + + build_icarus + run_icarus + +If you want to use a commercial tool such as Synopsys VCS then +set up your PATH enviroment variable so that you are able to +find the "vcs" executable, and then type in the following +commands: + + build_vcs + run_vcs + +Within this design the only visible difference between Icarus +and VCS is the speed: the commercial tool could be hundreds of +times faster than its FLOSS counterpart; but with Icarus if +you have time to wait for some minutes you will obtain exactly +the same results just using free software. + +At the end of the simulation you can look at the logfile and +at the waveforms placed at the following paths: + + run/sim/icarus/sim.log + run/sim/icarus/trace.vcd + + run/sim/vcs/sim.log + run/sim/vcs/trace.vcd + +Obviously if you do not have access to a commercial tool you +can use GTKWave to look at the waveforms: for instance from +the top-level directory just type in the following command: + + gtkwave run/sim/icarus/trace.vcd & + +and then from "File|Read Save File" choose the file named +"tools/src/gtkwave.sav". + Index: trunk/docs/TODO.txt =================================================================== --- trunk/docs/TODO.txt (nonexistent) +++ trunk/docs/TODO.txt (revision 4) @@ -0,0 +1,12 @@ +Simply RISC S1 Core - To Do List +================================ + +This is the list of the higher priority tasks: +- sim problem: dirty requests after a while +- synth problem: Icarus assertion failed + +Lower priority: +- support for PCX/CPX packets other than IMISS/LD/ST +- full test-suite for verification +- harness and interrupt handlers to verify INT_CTRL + Index: trunk/docs/INSTALL.txt =================================================================== --- trunk/docs/INSTALL.txt (nonexistent) +++ trunk/docs/INSTALL.txt (revision 4) @@ -0,0 +1,28 @@ +Simply RISC S1 Core - Quick Installation Guide +============================================== + +To install the package just extract it: + + tar zxvf s1.tar.gz + +then edit the top-level "sourceme" file to reflect the locations +of the S1 design (we call "S1 root directory" the one containing +the "hdl" and "tools" subdirectories) and the root of the T1 design: +the first one is mandatory, the second path is needed only if you +want to update the SPARC Core source file bundled with this tarball +with an updated version of the T1 design released by the OpenSPARC +community (using the provided update_sparccore script file). + +After that just use on your GNU/Linux or Unix box a bash shell +to source this file: + + source sourceme + +Then you have to update the list of files to be used, to do so +just run the script: + + update_filelist + +Now you are ready to try the S1 environment to run simulations or +synthesis. + Index: trunk/docs/SYNTHESIS.txt =================================================================== --- trunk/docs/SYNTHESIS.txt (nonexistent) +++ trunk/docs/SYNTHESIS.txt (revision 4) @@ -0,0 +1,33 @@ +Simply RISC S1 Core - Synthesis Environment +=========================================== + +The scripts to run synthesis are similar to the ones +used for simulations, you can still use the free Icarus +Verilog software (that will target an FPGA application) +or a commercial Design Compiler tool from Synopsys (that +will be used for ASIC). + +With Icarus you will use the "fpga" target, to do so +just run: + + build_fpga + +If you want to use Synopsys Design Compiler instead you +have to use: + + build_dc + +Please note that the commercial tools are NOT supported, and +they will probably not work unless you fix all the required +parameters properly (we are focusing on free software since +we want to build up a community of developers around the S1). + +The results for these two kinds of scripts are in the +directories: + + run/synth/fpga/ + +and + + run/synth/dc/ + Index: trunk/docs/SPEC.txt =================================================================== --- trunk/docs/SPEC.txt (nonexistent) +++ trunk/docs/SPEC.txt (revision 4) @@ -0,0 +1,161 @@ +Simply RISC S1 Core - Functional Specification +============================================== + +Preface +------- +The S1 is a CPU core that makes use of a single SPARC Core +extracted from the OpenSPARC T1, with the addition of a +Wishbone Bridge, a Reset Controller and an Interrupt +Controller. + ___________________________________ + | Simply RISC S1 Core | + | _______ _____ ________ ________ | + || || || || || + || Reset || Int || SPARC ||Wishbone|| + || Ctrl. ||Ctrl.|| Core || Bridge || + || || || || || + | ------- ----- ------- -------- | + ----------------------------------- + +Instruction Set Architecture +---------------------------- +The CPU inside the S1 Core is the SPARC Core of the +OpenSPARC T1 microprocessor, so you can read OpenSPARC +documents for the specification of this CPU. +Basically it follows the SPARC v9 64-bit ISA, specified +in the documents freely available on the opensparc.net +website; for the full documentation you also have to read +the datasheet and other specs included in the download +file of the T1 design. + +Software Support +---------------- +The SPARC v9 ISA is obviously supported by the GCC compiler; +also GNU/Linux is supported and the latest versions of the +kernel are ready for the T1. +There's also a complete GNU/Linux distribution, Ubuntu, +that comes ready for the SPARC Core of the T1 and could be +used in a seamless way also for Simply RISC S1 based micros. + +S1 Memory Map +------------- +The S1 Core has 64-bit wide Data Bus and Address Bus. +Each bit of the Address Bus has a different meaning: +- bits [63:59] specify the one-hot encoding for the T1 target region number; +- bits [58:40] are 19 bits always hardwired to zero; +- bits [39:0] are the 40-bit Physical Address as it comes from the SPARC Core. + +For most applications the lowest 40-bit address coming from the SPARC Core +should be enough, so it should be safe to ignore the other bits (unless +you suspect that for instance Physical Address zero in region 0 is +different from address zero in region 1 and so forth). + +S1 Physical Address [63:56] +--------------------------- +the first byte specifies the T1 target region number (one-hot encoded +on the most significant 5 bits, the 3 least significant bits are +hardwired to zero): +- 0x08 RAM Bank 0 (bit 59 set) +- 0x10 RAM Bank 1 (bit 60 set) +- 0x20 RAM Bank 2 (bit 61 set) +- 0x40 RAM Bank 3 (bit 62 set) +- 0x80 I/O Bridge (bit 63 set) + +As you can see one of the five most significant bits of the +address must be always set depending on the target region. + +S1 Physical Address [39:32] +--------------------------- +In the T1 bit 39 is zero for all memory addresses and 1 for I/O +addresses. Then the T1, from which the S1 is derived, uses the +following memory map for bits [39:32] (please note that this +mapping is NOT used by the S1): +- 0x00-0x7F RAM +- 0x80 JBus +- 0x81-0x95 +- 0x96 Clock Unit +- 0x97 RAM Controller +- 0x98 I/O Bridge Management Block +- 0x99 TAP Unit +- 0x9A-0x9D +- 0x9E TAP2ASI +- 0x9F I/O Bridge Interrupt Table +- 0xA0-0xBF L2 Control Registers +- 0xC0-0xFE JBus +- 0xFF Boot ROM + +For the S1 Core the memory map is different and the following +table applies: +- 0x00-0x7F RAM +- 0x80-0x95 +- 0x96 Real Time Clock +- 0x97 RAM Controller +- 0x98 Wishbone Interconnect Arbiter +- 0x99 DMA Controller +- 0x9A-0x9D +- 0x9E General Purpose I/O +- 0x9F Interrupt Controller +- 0xA0-0xFE +- 0xFF Boot ROM + +If you intend to use in your system not only the least significant +40 bits generated by the SPARC Core, take into account that for +accesses not directed to RAM but to configuration registers it +should be an access to the I/O region (bit 63 set), so for instance +the full 64-bit base address for the Interrupt Controller should +be 0x8000_009F_0000_0000. + +S1 Physical Address [2:0] +------------------------- +The S1 Core implements a Wishbone Master interface with a data bus +of 64 bits and a granularity of 1 byte. +Then the address generated by the S1 is always aligned on 64-bit +boundaries, i.e. bits [2:0] are always zero; the information +about the bytes that have to be accessed during a Wishbone +bus cycle is obviously encoded on the SEL signals described +in the Wishbone spec. + +Reset Controller +---------------- +The boot sequence of the T1 is quite complex; we have then written +a reset controller for the S1 that just takes one reset signal +and generates all the signals required by the SPARC Core to boot +up properly. + +Interrupt Controller +-------------------- +Early versions of the S1 Core feature a very basic Interrupt +Controller that latches interrupt requests arriving to the core +that are then signaled to the SPARC Core with the proper CPX +packet. +Currently this block is untested and it will be enhanced in +the future. + +Wishbone Bridge +--------------- +The eight SPARC Cores inside the OpenSPARC T1 microprocessor +make use of a proprietary protocol to communicate with the +rest of the chip; this protocol is often referred to as +PCX/CPX protocol, where PCX stands for "Processor-to-Cache +Xbar" and is used for the requests outgoing the SPARC Cores +and CPX stands for "Cache-to-Processor Xbar" and is used for +incoming packets. +The main block designed specifically for the S1 Core is the +"SPARC Core to Wishbone Master interface bridge" that translates +the requests and return packets of the SPARC Core into the +Wishbone protocol. +You can find the full specification of the Wishbone protocol +on the OpenCores site at http://www.opencores.org + +Interface Details +----------------- +These are the features of the bus interface of the S1 Core +(they can also be referred to as "Wishbone Datasheet"): +- Wishbone Master interface that follows revision B.3; +- standard signals names identified by leading "wbm_" chars; +- no ERR/RTY support; +- 64-bit Address Bus (with some bits unused, see above); +- 64-bit Data Bus supporting 8, 16, 32 and 64 bit accesses; +- data transfer ordering is Big Endian; +- supports Single Read/Write Cycles. + Index: trunk/docs/SUPPORT.txt~ =================================================================== --- trunk/docs/SUPPORT.txt~ (nonexistent) +++ trunk/docs/SUPPORT.txt~ (revision 4) @@ -0,0 +1,68 @@ +Simply RISC S1 Core - Support and References +============================================ + +The S1 Core has been developed by Simply RISC and +released as Free Hardware Design under the GPL +license version 2. You have all the freedom granted +by this license, but to avoid legal problems we have +to state clearly that: + +1) all the files bundled with this package come +WITHOUT WARRANTY, so USE THEM AT YOUR OWN RISK; + +2) you do NOT have the right to pretend the support +you need from Simply RISC. + +Anyway we will try to provide all the free support +that we can, and now we try to list how to ask for +it. + +Basically since the S1 Core is based upon the OpenSPARC +T1 microprocessor released by Sun Microsystems, for +issues related with the SPARC Core inside the S1 you +can refer to the OpenSPARC website: + + http://www.opensparc.net + +In the documentation section of this site you will +find several documents about the SPARC v9 64-bit +Instruction Set Architecture (you should be able to +read them without registration). + +For the specification of the T1 implementation of +the 64-bit SPARC ISA you need a free registration +to download the full design (it's a very large file) +that contains also the full specification of the T1 +microprocessor. + +On the OpenSPARC website listed above there are also +public forums online where you can ask for free +support. + +If you need support about the Wishbone Interconnect, +the URL you need is: + + http://www.opencores.org + +Here you will find also several other cores that can +be connected to the S1 seamlessly; again, there are +mailing lists available from this site when you can +discuss with real experts about your problems with +the Wishbone interconnect protocol. + +If you still need support or you want to take part +in the development of the S1 Core, then you can +contact us at + + support@srisc.com + +and we will try to help you if possible. If you find +something that can be corrected and/or improved in +the design or in the documentation please let us know +and we will fix it in the next release. + +To see if there is a new release available just check +from time to time on the Simply RISC website: + + http://www.srisc.com + Index: trunk/docs/README.txt~ =================================================================== --- trunk/docs/README.txt~ (nonexistent) +++ trunk/docs/README.txt~ (revision 4) @@ -0,0 +1,24 @@ +Simply RISC S1 Core +=================== + +This is the README file for the S1 Core (codename "Sirocco"); +all the informations you need are contained in the text files +that you can find in the "docs" subdirectory: + + - README.txt Summary (this file) + - INSTALL.txt Quick Installation Guide + - REQUIREMENTS.txt System Requirements + - SIMULATION.txt Simulation Environment + - SYNTHESIS.txt Synthesis Environment + - SPEC.txt Functional Specification + - SUPPORT.txt Support and References + - LICENSE.txt License for Design and Documentation + - TODO.txt To Do List + +Probably now you just have to read the docs/INSTALL.txt file. + +Please note that from the Simply RISC site http://www.srisc.com +you can always download a single PDF specification that is just +a collection of the text files bundled with the design and +listed above. + Index: trunk/docs/SUPPORT.txt =================================================================== --- trunk/docs/SUPPORT.txt (nonexistent) +++ trunk/docs/SUPPORT.txt (revision 4) @@ -0,0 +1,68 @@ +Simply RISC S1 Core - Support and References +============================================ + +The S1 Core has been developed by Simply RISC LLP and +the OpenCores community, and it's been released as +Free Hardware Design under the GPL license version 2. +You have all the freedom granted by this license, but +to avoid legal problems we have to state clearly that: + +1) all the files bundled with this package come +WITHOUT WARRANTY, so USE THEM AT YOUR OWN RISK; + +2) you do NOT have the right to pretend the support +you need from Simply RISC LLP. + +Anyway we will try to provide all the free support +that we can, and now we try to list how to ask for +it. + +Basically since the S1 Core is based upon the OpenSPARC +T1 microprocessor released by Sun Microsystems, for +issues related with the SPARC Core inside the S1 you +can refer to the OpenSPARC website: + + http://www.opensparc.net + +In the documentation section of this site you will +find several documents about the SPARC v9 64-bit +Instruction Set Architecture (you should be able to +read them without registration). + +For the specification of the T1 implementation of +the 64-bit SPARC ISA you need a free registration +to download the full design (it's a very large file) +that contains also the full specification of the T1 +microprocessor. + +On the OpenSPARC website listed above there are also +public forums online where you can ask for free +support. + +If you need support about the Wishbone Interconnect, +the URL you need is: + + http://www.opencores.org + +Here you will find also several other cores that can +be connected to the S1 seamlessly; again, there are +mailing lists available from this site when you can +discuss with real experts about your problems with +the Wishbone interconnect protocol. + +If you still need support or you want to take part +in the development of the S1 Core, then you can +contact us at + + support@srisc.com + +and we will try to help you if possible. If you find +something that can be corrected and/or improved in +the design or in the documentation please let us know +and we will fix it in the next release. + +To see if there is a new release available just check +from time to time on the Simply RISC website: + + http://www.srisc.com + Index: trunk/docs/README.txt =================================================================== --- trunk/docs/README.txt (nonexistent) +++ trunk/docs/README.txt (revision 4) @@ -0,0 +1,24 @@ +Simply RISC S1 Core +=================== + +This is the README file for the S1 Core (codename "Sirocco"); +all the informations you need are contained in the text files +that you can find in the "docs" subdirectory: + + - README.txt Summary (this file) + - INSTALL.txt Quick Installation Guide + - REQUIREMENTS.txt System Requirements + - SIMULATION.txt Simulation Environment + - SYNTHESIS.txt Synthesis Environment + - SPEC.txt Functional Specification + - SUPPORT.txt Support and References + - LICENSE.txt License for Design and Documentation + - TODO.txt To Do List + +Probably now you just have to read the docs/INSTALL.txt file. + +Please note that from OpenCores http://www.opencores.org or the +Simply RISC website at http://www.srisc.com you can always +download a single PDF specification that is just a collection of +the text files included in the CVS tree and listed above. +

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