URL
https://opencores.org/ocsvn/sardmips/sardmips/trunk
Subversion Repositories sardmips
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- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/PROGRAMMING_exception/link.xn
0,0 → 1,88
/* |
* Linker script for the mips programs. Created for the 32bit mips |
* little endian achitecture. |
*/ |
|
OUTPUT(program.elf) /* Default output name */ |
OUTPUT_ARCH(mips) /* Output arch is mips... no shit :-) */ |
ENTRY(_start) /* Entry point for program */ |
|
SECTIONS |
{ |
/**** Code and read-only data ****/ |
|
. = 0x00000000; /* Here the code should be loaded so we */ |
/* set the location counter to this */ |
/* address. */ |
.text . : { |
|
_ftext = .; /* Start of code and read-only data */ |
|
crt0.o (.text) /* This must be the first file since */ |
/* this has the program entry point */ |
*(.text) /* The rest of the object files */ |
_ecode = .; /* End of code */ |
|
*(.rodata) |
|
. = ALIGN(8); |
_etext = .; /* End of code and read-only data */ |
} = 0 |
|
.reginfo : { *(.reginfo) } /* Contains masks of registers used and */ |
/* $gp value ($gp register is not used) */ |
|
/**** Initialised data ****/ |
|
.data : |
{ |
_fdata = .; /* Start of initialised data */ |
*(.data) |
|
. = ALIGN(8); |
|
*(.lit8) /* Place 8-byte constants here */ |
*(.lit4) /* Place 4-byte constants here */ |
*(.sdata) /* Place subsequent data */ |
|
. = ALIGN(8); |
|
_edata = .; /* End of initialised data */ |
} |
|
.reginfo : |
{ |
/**/ |
} |
|
/**** Uninitialised data ****/ |
. = 0x00000000; |
_fbss = .; /* Start of uninitialised data */ |
|
.sbss : |
{ |
*(.dynsbss) |
*(.sbss) |
*(.sbss.*) |
*(.scommon) /* Place small common symbols here */ |
} |
|
.bss : |
{ |
*(.dynbss) |
*(.bss) |
*(.bss.*) |
*(COMMON) /* Place common symbols here */ |
|
_sp_end = .; |
/* Allocate room for stack */ |
. = ALIGN(8) ; |
. = 0x4000 ; |
_sp = . - 16; |
} |
|
_end = .; /* End of unitialised data */ |
|
} |
|
|
/trunk/PROGRAMMING_exception/My_Program.c.hold
0,0 → 1,16
#define ocpstore(address,save) { \ |
unsigned int *ctrlstore = (unsigned int *) address; \ |
*ctrlstore = save;} |
|
#define ADDR_QUICK 0x00005000 |
|
int main(void) |
{ |
int i,j,g; |
i = 15; |
j = 26; |
g = j + i; |
ocpstore(ADDR_QUICK, g); |
asm("nop"); |
return 0; |
} |
/trunk/PROGRAMMING_exception/regdef.h
0,0 → 1,45
/* |
* Register definitions |
* |
* This file is subject to the terms and conditions of the GNU General |
* Public License. See the file "COPYING" in the main directory of |
* this archive for more details. |
*/ |
#ifndef _REGDEF_H |
#define _REGDEF_H |
|
#define zero $0 /* wired zero */ |
#define AT $at /* assembler temp - uppercase because of ".set at" */ |
#define v0 $2 /* return value - caller saved */ |
#define v1 $3 |
#define a0 $4 /* argument registers */ |
#define a1 $5 |
#define a2 $6 |
#define a3 $7 |
#define t0 $8 /* caller saved in 32 bit (arg reg 64 bit) */ |
#define t1 $9 |
#define t2 $10 |
#define t3 $11 |
#define t4 $12 /* caller saved */ |
#define t5 $13 |
#define t6 $14 |
#define t7 $15 |
#define s0 $16 /* callee saved */ |
#define s1 $17 |
#define s2 $18 |
#define s3 $19 |
#define s4 $20 |
#define s5 $21 |
#define s6 $22 |
#define s7 $23 |
#define t8 $24 /* caller saved */ |
#define t9 $25 /* callee address for PIC/temp */ |
#define k0 $26 /* kernel temporary */ |
#define k1 $27 |
#define gp $28 /* global pointer - caller saved for PIC */ |
#define sp $29 /* stack pointer */ |
#define fp $30 /* frame pointer */ |
#define s8 $30 /* callee saved */ |
#define ra $31 /* return address */ |
|
#endif /* _REGDEF_H */ |
/trunk/PROGRAMMING_exception/DISASSEMBLER_ELF
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/PROGRAMMING_exception/DISASSEMBLER_ELF
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/My_Program.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PROGRAMMING_exception/My_Program.bin
===================================================================
--- trunk/PROGRAMMING_exception/My_Program.bin (nonexistent)
+++ trunk/PROGRAMMING_exception/My_Program.bin (revision 4)
trunk/PROGRAMMING_exception/My_Program.bin
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/instructions.asm
===================================================================
--- trunk/PROGRAMMING_exception/instructions.asm (nonexistent)
+++ trunk/PROGRAMMING_exception/instructions.asm (revision 4)
@@ -0,0 +1,344 @@
+@00000000 MIPS (ID): j 16
+@00000004 MIPS (ID): nop
+@00000008 MIPS (ID): j 64
+@0000000c MIPS (ID): nop
+@00000010 MIPS (ID): lui $29, 0
+@00000014 MIPS (ID): addiu $29, $29, 16368
+@00000018 MIPS (ID): addiu $8, $0, 0
+@0000001c MIPS (ID): lui $9, 0
+@00000020 MIPS (ID): addiu $9, $9, 16384
+@00000024 MIPS (ID): MFC0
+@00000028 MIPS (ID): addi $26, $26, 3
+@0000002c MIPS (ID): MTC0
+@00000030 MIPS (ID): jal 716
+@00000034 MIPS (ID): nop
+@00000038 MIPS (ID): j 124
+@0000003c MIPS (ID): nop
+@00000040 MIPS (ID): nop
+@00000044 MIPS (ID): MFC0
+@00000048 MIPS (ID): MFC0
+@0000004c MIPS (ID): srl $26, $26, 2
+@00000050 MIPS (ID): andi $26, $26, 0x1f
+@00000054 MIPS (ID): beq $0, $26, 6
+@00000058 MIPS (ID): nop
+@0000005c MIPS (ID): add $11, $0, $0
+@00000060 MIPS (ID): addiu $11, $27, 4
+@00000064 MIPS (ID): MTC0
+@00000068 MIPS (ID): ERET
+@0000006c MIPS (ID): nop
+@00000070 MIPS (ID): nop
+@00000074 MIPS (ID): ERET
+@00000078 MIPS (ID): nop
+@0000007c MIPS (ID): j 124
+@00000080 MIPS (ID): addiu $29, $29, -40
+@00000084 MIPS (ID): sw $31, 36($29) (36)
+@00000088 MIPS (ID): sw $30, 32($29) (32)
+@0000008c MIPS (ID): or $30, $29, $0
+@00000090 MIPS (ID): sw $4, 40($30) (40)
+@00000094 MIPS (ID): sw $5, 44($30) (44)
+@00000098 MIPS (ID): sw $6, 48($30) (48)
+@0000009c MIPS (ID): lw $2, 44($30) (44)
+@000000a0 MIPS (ID): nop
+@000000a4 MIPS (ID): sw $2, 16($30) (16)
+@000000a8 MIPS (ID): lw $2, 48($30) (48)
+@000000ac MIPS (ID): nop
+@000000b0 MIPS (ID): sw $2, 20($30) (20)
+@000000b4 MIPS (ID): lw $3, 44($30) (44)
+@000000b8 MIPS (ID): lw $2, 48($30) (48)
+@000000bc MIPS (ID): nop
+@000000c0 MIPS (ID): addu $3, $3, $2
+@000000c4 MIPS (ID): sra $2, $3, 31
+@000000c8 MIPS (ID): srl $2, $2, 31
+@000000cc MIPS (ID): addu $2, $3, $2
+@000000d0 MIPS (ID): sra $2, $2, 1
+@000000d4 MIPS (ID): sll $3, $2, 2
+@000000d8 MIPS (ID): lw $2, 40($30) (40)
+@000000dc MIPS (ID): nop
+@000000e0 MIPS (ID): addu $2, $3, $2
+@000000e4 MIPS (ID): lw $2, 0($2) (0)
+@000000e8 MIPS (ID): nop
+@000000ec MIPS (ID): sw $2, 28($30) (28)
+@000000f0 MIPS (ID): lw $2, 16($30) (16)
+@000000f4 MIPS (ID): nop
+@000000f8 MIPS (ID): sll $3, $2, 2
+@000000fc MIPS (ID): lw $2, 40($30) (40)
+@00000100 MIPS (ID): nop
+@00000104 MIPS (ID): addu $2, $3, $2
+@00000108 MIPS (ID): lw $3, 0($2) (0)
+@0000010c MIPS (ID): lw $2, 28($30) (28)
+@00000110 MIPS (ID): nop
+@00000114 MIPS (ID): slt $2, $3, $2
+@00000118 MIPS (ID): bne $0, $2, 3
+@0000011c MIPS (ID): nop
+@00000120 MIPS (ID): beq $0, $0, 6
+@00000124 MIPS (ID): nop
+@00000128 MIPS (ID): lw $2, 16($30) (16)
+@0000012c MIPS (ID): nop
+@00000130 MIPS (ID): addiu $2, $2, 1
+@00000134 MIPS (ID): beq $0, $0, -18
+@00000138 MIPS (ID): sw $2, 16($30) (16)
+@0000013c MIPS (ID): nop
+@00000140 MIPS (ID): lw $2, 20($30) (20)
+@00000144 MIPS (ID): nop
+@00000148 MIPS (ID): sll $3, $2, 2
+@0000014c MIPS (ID): lw $2, 40($30) (40)
+@00000150 MIPS (ID): nop
+@00000154 MIPS (ID): addu $2, $3, $2
+@00000158 MIPS (ID): lw $3, 0($2) (0)
+@0000015c MIPS (ID): lw $2, 28($30) (28)
+@00000160 MIPS (ID): nop
+@00000164 MIPS (ID): slt $2, $2, $3
+@00000168 MIPS (ID): bne $0, $2, 3
+@0000016c MIPS (ID): nop
+@00000170 MIPS (ID): beq $0, $0, 6
+@00000174 MIPS (ID): nop
+@00000178 MIPS (ID): lw $2, 20($30) (20)
+@0000017c MIPS (ID): nop
+@00000180 MIPS (ID): addiu $2, $2, -1
+@00000184 MIPS (ID): beq $0, $0, -18
+@00000188 MIPS (ID): sw $2, 20($30) (20)
+@0000018c MIPS (ID): lw $2, 16($30) (16)
+@00000190 MIPS (ID): lw $3, 20($30) (20)
+@00000194 MIPS (ID): nop
+@00000198 MIPS (ID): slt $2, $3, $2
+@0000019c MIPS (ID): bne $0, $2, 42
+@000001a0 MIPS (ID): nop
+@000001a4 MIPS (ID): lw $2, 16($30) (16)
+@000001a8 MIPS (ID): nop
+@000001ac MIPS (ID): sll $3, $2, 2
+@000001b0 MIPS (ID): lw $2, 40($30) (40)
+@000001b4 MIPS (ID): nop
+@000001b8 MIPS (ID): addu $2, $3, $2
+@000001bc MIPS (ID): lw $2, 0($2) (0)
+@000001c0 MIPS (ID): nop
+@000001c4 MIPS (ID): sw $2, 24($30) (24)
+@000001c8 MIPS (ID): lw $2, 16($30) (16)
+@000001cc MIPS (ID): nop
+@000001d0 MIPS (ID): sll $3, $2, 2
+@000001d4 MIPS (ID): lw $2, 40($30) (40)
+@000001d8 MIPS (ID): nop
+@000001dc MIPS (ID): addu $4, $3, $2
+@000001e0 MIPS (ID): lw $2, 20($30) (20)
+@000001e4 MIPS (ID): nop
+@000001e8 MIPS (ID): sll $3, $2, 2
+@000001ec MIPS (ID): lw $2, 40($30) (40)
+@000001f0 MIPS (ID): nop
+@000001f4 MIPS (ID): addu $2, $3, $2
+@000001f8 MIPS (ID): lw $2, 0($2) (0)
+@000001fc MIPS (ID): nop
+@00000200 MIPS (ID): sw $2, 0($4) (0)
+@00000204 MIPS (ID): lw $2, 20($30) (20)
+@00000208 MIPS (ID): nop
+@0000020c MIPS (ID): sll $3, $2, 2
+@00000210 MIPS (ID): lw $2, 40($30) (40)
+@00000214 MIPS (ID): nop
+@00000218 MIPS (ID): addu $3, $3, $2
+@0000021c MIPS (ID): lw $2, 24($30) (24)
+@00000220 MIPS (ID): nop
+@00000224 MIPS (ID): sw $2, 0($3) (0)
+@00000228 MIPS (ID): lw $2, 16($30) (16)
+@0000022c MIPS (ID): nop
+@00000230 MIPS (ID): addiu $2, $2, 1
+@00000234 MIPS (ID): sw $2, 16($30) (16)
+@00000238 MIPS (ID): lw $2, 20($30) (20)
+@0000023c MIPS (ID): nop
+@00000240 MIPS (ID): addiu $2, $2, -1
+@00000244 MIPS (ID): sw $2, 20($30) (20)
+@00000248 MIPS (ID): lw $2, 16($30) (16)
+@0000024c MIPS (ID): lw $3, 20($30) (20)
+@00000250 MIPS (ID): nop
+@00000254 MIPS (ID): slt $2, $3, $2
+@00000258 MIPS (ID): beq $0, $2, -91
+@0000025c MIPS (ID): nop
+@00000260 MIPS (ID): lw $2, 44($30) (44)
+@00000264 MIPS (ID): lw $3, 20($30) (20)
+@00000268 MIPS (ID): nop
+@0000026c MIPS (ID): slt $2, $2, $3
+@00000270 MIPS (ID): beq $0, $2, 6
+@00000274 MIPS (ID): nop
+@00000278 MIPS (ID): lw $4, 40($30) (40)
+@0000027c MIPS (ID): lw $5, 44($30) (44)
+@00000280 MIPS (ID): lw $6, 20($30) (20)
+@00000284 MIPS (ID): jal 128
+@00000288 MIPS (ID): nop
+@0000028c MIPS (ID): lw $2, 16($30) (16)
+@00000290 MIPS (ID): lw $3, 48($30) (48)
+@00000294 MIPS (ID): nop
+@00000298 MIPS (ID): slt $2, $2, $3
+@0000029c MIPS (ID): beq $0, $2, 6
+@000002a0 MIPS (ID): nop
+@000002a4 MIPS (ID): lw $4, 40($30) (40)
+@000002a8 MIPS (ID): lw $5, 16($30) (16)
+@000002ac MIPS (ID): lw $6, 48($30) (48)
+@000002b0 MIPS (ID): jal 128
+@000002b4 MIPS (ID): nop
+@000002b8 MIPS (ID): or $29, $30, $0
+@000002bc MIPS (ID): lw $31, 36($29) (36)
+@000002c0 MIPS (ID): lw $30, 32($29) (32)
+@000002c4 MIPS (ID): jr $31
+ * UNKNOWN FUNCTION CODE FOR R-format
+@000002c8 MIPS (ID): addiu $29, $29, 40
+@000002cc MIPS (ID): addiu $29, $29, -80
+@000002d0 MIPS (ID): sw $30, 72($29) (72)
+@000002d4 MIPS (ID): or $30, $29, $0
+@000002d8 MIPS (ID): addiu $2, $0, 23
+@000002dc MIPS (ID): sw $2, 52($30) (52)
+@000002e0 MIPS (ID): addiu $2, $0, 24
+@000002e4 MIPS (ID): sw $2, 56($30) (56)
+@000002e8 MIPS (ID): addiu $2, $0, 13
+@000002ec MIPS (ID): sw $2, 0($30) (0)
+@000002f0 MIPS (ID): addiu $2, $0, 34
+@000002f4 MIPS (ID): sw $2, 4($30) (4)
+@000002f8 MIPS (ID): addiu $2, $0, 86
+@000002fc MIPS (ID): sw $2, 8($30) (8)
+@00000300 MIPS (ID): addiu $2, $0, 23
+@00000304 MIPS (ID): sw $2, 12($30) (12)
+@00000308 MIPS (ID): addiu $2, $0, 52
+@0000030c MIPS (ID): sw $2, 16($30) (16)
+@00000310 MIPS (ID): addiu $2, $0, 43
+@00000314 MIPS (ID): sw $2, 20($30) (20)
+@00000318 MIPS (ID): addiu $2, $0, 45
+@0000031c MIPS (ID): sw $2, 24($30) (24)
+@00000320 MIPS (ID): addiu $2, $0, 87
+@00000324 MIPS (ID): sw $2, 28($30) (28)
+@00000328 MIPS (ID): addiu $2, $0, 12
+@0000032c MIPS (ID): sw $2, 32($30) (32)
+@00000330 MIPS (ID): addiu $2, $0, 24
+@00000334 MIPS (ID): sw $2, 36($30) (36)
+@00000338 MIPS (ID): addiu $2, $0, 35
+@0000033c MIPS (ID): sw $2, 40($30) (40)
+@00000340 MIPS (ID): addiu $2, $0, 100
+@00000344 MIPS (ID): sw $2, 44($30) (44)
+@00000348 MIPS (ID): lw $3, 52($30) (52)
+@0000034c MIPS (ID): lw $2, 56($30) (56)
+@00000350 MIPS (ID): nop
+@00000354 MIPS (ID): mult [Hi,Lo], $3, $2
+ * UNKNOWN FUNCTION CODE FOR R-format
+@00000358 MIPS (ID): mflo $2 [Lo]
+ * UNKNOWN FUNCTION CODE FOR R-format
+@0000035c MIPS (ID): sw $2, 48($30) (48)
+@00000360 MIPS (ID): nop
+@00000364 MIPS (ID): sw $0, 60($30) (60)
+@00000368 MIPS (ID): lw $2, 60($30) (60)
+@0000036c MIPS (ID): nop
+@00000370 MIPS (ID): slti $2, $2, 12
+@00000374 MIPS (ID): bne $0, $2, 3
+@00000378 MIPS (ID): nop
+@0000037c MIPS (ID): beq $0, $0, 16
+@00000380 MIPS (ID): nop
+@00000384 MIPS (ID): lw $2, 60($30) (60)
+@00000388 MIPS (ID): nop
+@0000038c MIPS (ID): sll $2, $2, 2
+@00000390 MIPS (ID): addu $4, $30, $2
+@00000394 MIPS (ID): lw $3, 52($30) (52)
+@00000398 MIPS (ID): lw $2, 60($30) (60)
+@0000039c MIPS (ID): nop
+@000003a0 MIPS (ID): mult [Hi,Lo], $3, $2
+ * UNKNOWN FUNCTION CODE FOR R-format
+@000003a4 MIPS (ID): mflo $2 [Lo]
+ * UNKNOWN FUNCTION CODE FOR R-format
+@000003a8 MIPS (ID): sw $2, 0($4) (0)
+@000003ac MIPS (ID): lw $2, 60($30) (60)
+@000003b0 MIPS (ID): nop
+@000003b4 MIPS (ID): addiu $2, $2, 1
+@000003b8 MIPS (ID): beq $0, $0, -21
+@000003bc MIPS (ID): sw $2, 60($30) (60)
+@000003c0 MIPS (ID): addiu $2, $0, 4096
+@000003c4 MIPS (ID): sw $2, 64($30) (64)
+@000003c8 MIPS (ID): lw $3, 64($30) (64)
+@000003cc MIPS (ID): lw $2, 0($30) (0)
+@000003d0 MIPS (ID): nop
+@000003d4 MIPS (ID): sw $2, 0($3) (0)
+@000003d8 MIPS (ID): addiu $2, $0, 4100
+@000003dc MIPS (ID): sw $2, 64($30) (64)
+@000003e0 MIPS (ID): lw $3, 64($30) (64)
+@000003e4 MIPS (ID): lw $2, 4($30) (4)
+@000003e8 MIPS (ID): nop
+@000003ec MIPS (ID): sw $2, 0($3) (0)
+@000003f0 MIPS (ID): addiu $2, $0, 4104
+@000003f4 MIPS (ID): sw $2, 64($30) (64)
+@000003f8 MIPS (ID): lw $3, 64($30) (64)
+@000003fc MIPS (ID): lw $2, 8($30) (8)
+@00000400 MIPS (ID): nop
+@00000404 MIPS (ID): sw $2, 0($3) (0)
+@00000408 MIPS (ID): addiu $2, $0, 4108
+@0000040c MIPS (ID): sw $2, 64($30) (64)
+@00000410 MIPS (ID): lw $3, 64($30) (64)
+@00000414 MIPS (ID): lw $2, 12($30) (12)
+@00000418 MIPS (ID): nop
+@0000041c MIPS (ID): sw $2, 0($3) (0)
+@00000420 MIPS (ID): addiu $2, $0, 4112
+@00000424 MIPS (ID): sw $2, 64($30) (64)
+@00000428 MIPS (ID): lw $3, 64($30) (64)
+@0000042c MIPS (ID): lw $2, 16($30) (16)
+@00000430 MIPS (ID): nop
+@00000434 MIPS (ID): sw $2, 0($3) (0)
+@00000438 MIPS (ID): addiu $2, $0, 4116
+@0000043c MIPS (ID): sw $2, 64($30) (64)
+@00000440 MIPS (ID): lw $3, 64($30) (64)
+@00000444 MIPS (ID): lw $2, 20($30) (20)
+@00000448 MIPS (ID): nop
+@0000044c MIPS (ID): sw $2, 0($3) (0)
+@00000450 MIPS (ID): addiu $2, $0, 4120
+@00000454 MIPS (ID): sw $2, 64($30) (64)
+@00000458 MIPS (ID): lw $3, 64($30) (64)
+@0000045c MIPS (ID): lw $2, 24($30) (24)
+@00000460 MIPS (ID): nop
+@00000464 MIPS (ID): sw $2, 0($3) (0)
+@00000468 MIPS (ID): addiu $2, $0, 4124
+@0000046c MIPS (ID): sw $2, 64($30) (64)
+@00000470 MIPS (ID): lw $3, 64($30) (64)
+@00000474 MIPS (ID): lw $2, 28($30) (28)
+@00000478 MIPS (ID): nop
+@0000047c MIPS (ID): sw $2, 0($3) (0)
+@00000480 MIPS (ID): addiu $2, $0, 4128
+@00000484 MIPS (ID): sw $2, 64($30) (64)
+@00000488 MIPS (ID): lw $3, 64($30) (64)
+@0000048c MIPS (ID): lw $2, 32($30) (32)
+@00000490 MIPS (ID): nop
+@00000494 MIPS (ID): sw $2, 0($3) (0)
+@00000498 MIPS (ID): addiu $2, $0, 4132
+@0000049c MIPS (ID): sw $2, 64($30) (64)
+@000004a0 MIPS (ID): lw $3, 64($30) (64)
+@000004a4 MIPS (ID): lw $2, 36($30) (36)
+@000004a8 MIPS (ID): nop
+@000004ac MIPS (ID): sw $2, 0($3) (0)
+@000004b0 MIPS (ID): addiu $2, $0, 4136
+@000004b4 MIPS (ID): sw $2, 64($30) (64)
+@000004b8 MIPS (ID): lw $3, 64($30) (64)
+@000004bc MIPS (ID): lw $2, 40($30) (40)
+@000004c0 MIPS (ID): nop
+@000004c4 MIPS (ID): sw $2, 0($3) (0)
+@000004c8 MIPS (ID): addiu $2, $0, 4140
+@000004cc MIPS (ID): sw $2, 64($30) (64)
+@000004d0 MIPS (ID): lw $3, 64($30) (64)
+@000004d4 MIPS (ID): lw $2, 44($30) (44)
+@000004d8 MIPS (ID): nop
+@000004dc MIPS (ID): sw $2, 0($3) (0)
+@000004e0 MIPS (ID): addiu $2, $0, 4144
+@000004e4 MIPS (ID): sw $2, 64($30) (64)
+@000004e8 MIPS (ID): lw $3, 64($30) (64)
+@000004ec MIPS (ID): lw $2, 48($30) (48)
+@000004f0 MIPS (ID): nop
+@000004f4 MIPS (ID): sw $2, 0($3) (0)
+@000004f8 MIPS (ID): lui $2, 32767
+@000004fc MIPS (ID): ori $2, $2, 0xfffffffc
+@00000500 MIPS (ID): sw $2, 64($30) (64)
+@00000504 MIPS (ID): lw $2, 64($30) (64)
+@00000508 MIPS (ID): nop
+@0000050c MIPS (ID): sw $0, 0($2) (0)
+@00000510 MIPS (ID): or $2, $0, $0
+@00000514 MIPS (ID): or $29, $30, $0
+@00000518 MIPS (ID): lw $30, 72($29) (72)
+@0000051c MIPS (ID): jr $31
+ * UNKNOWN FUNCTION CODE FOR R-format
+@00000520 MIPS (ID): addiu $29, $29, 80
+@00000524 MIPS (ID): nop
+@00000528 MIPS (ID): nop
+@0000052c MIPS (ID): nop
+@00000530 MIPS (ID): sw $0, 2816($0) (2816)
+@00000534 MIPS (ID): nop
+@00000538 MIPS (ID): nop
+@0000053c MIPS (ID): nop
+@00000540 MIPS (ID): nop
+@00000544 MIPS (ID): nop
Index: trunk/PROGRAMMING_exception/mult.hex
===================================================================
--- trunk/PROGRAMMING_exception/mult.hex (nonexistent)
+++ trunk/PROGRAMMING_exception/mult.hex (revision 4)
@@ -0,0 +1,218 @@
+@00000000 08 00 00 04
+@00000004 00 00 00 00
+@00000008 08 00 00 10
+@0000000c 00 00 00 00
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+@00000364 00 00 00 00
Index: trunk/PROGRAMMING_exception/instructions.hex
===================================================================
--- trunk/PROGRAMMING_exception/instructions.hex (nonexistent)
+++ trunk/PROGRAMMING_exception/instructions.hex (revision 4)
@@ -0,0 +1,338 @@
+@00000000 08 00 00 04
+@00000004 00 00 00 00
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Index: trunk/PROGRAMMING_exception/crt0.S
===================================================================
--- trunk/PROGRAMMING_exception/crt0.S (nonexistent)
+++ trunk/PROGRAMMING_exception/crt0.S (revision 4)
@@ -0,0 +1,69 @@
+/*
+ * Starting point for everything (bootstrap)
+ *
+ * Initializes the stack pointer and jumps to main().
+ */
+
+#include "regdef.h"
+
+ .text
+ .align 2
+ .globl _start
+ .ent _start
+_start:
+ .set noreorder
+
+ j reset_handler
+ nop
+
+ j handling_exception
+ nop
+
+
+reset_handler:
+ /* Setup stack pointer */
+ la sp, _sp
+
+ /* Clear bss */
+ la t0, 0x00000000 /* First address */
+ la t1, _end /* Last address */
+
+ mfc0 k0, $12
+ add k0, k0, 3
+ mtc0 k0, $12
+
+
+ jal main
+ nop
+ j loop
+ nop
+
+handling_exception:
+ nop
+ mfc0 k0, $13
+ mfc0 k1, $14
+
+ srl k0, k0, 2
+ andi k0, k0, 0x1F
+
+ beq k0, $0, handling_interrupt
+ nop
+
+ add $11, $0, $0
+ addiu $11, k1, 4
+ mtc0 $11, $14
+ eret
+ nop
+
+
+handling_interrupt:
+ nop
+ eret
+ nop
+
+ /* Run endless loop when the program terminates */
+loop:
+ j loop
+
+ .set reorder
+ .end _start
Index: trunk/PROGRAMMING_exception/My_Program
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PROGRAMMING_exception/My_Program
===================================================================
--- trunk/PROGRAMMING_exception/My_Program (nonexistent)
+++ trunk/PROGRAMMING_exception/My_Program (revision 4)
trunk/PROGRAMMING_exception/My_Program
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF
===================================================================
--- trunk/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF (nonexistent)
+++ trunk/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF (revision 4)
trunk/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/Disassembler/My_Program.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PROGRAMMING_exception/Disassembler/My_Program.bin
===================================================================
--- trunk/PROGRAMMING_exception/Disassembler/My_Program.bin (nonexistent)
+++ trunk/PROGRAMMING_exception/Disassembler/My_Program.bin (revision 4)
trunk/PROGRAMMING_exception/Disassembler/My_Program.bin
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/Disassembler/instructions.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PROGRAMMING_exception/Disassembler/instructions.dat
===================================================================
--- trunk/PROGRAMMING_exception/Disassembler/instructions.dat (nonexistent)
+++ trunk/PROGRAMMING_exception/Disassembler/instructions.dat (revision 4)
trunk/PROGRAMMING_exception/Disassembler/instructions.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/PROGRAMMING_exception/Disassembler/readme.txt
===================================================================
--- trunk/PROGRAMMING_exception/Disassembler/readme.txt (nonexistent)
+++ trunk/PROGRAMMING_exception/Disassembler/readme.txt (revision 4)
@@ -0,0 +1,11 @@
+
+Disassembler for MipsR2000 Processor!
+This program converts Bin files into HEX or ASM format!
+
+Usage:
+
+ Type ./DISASSEMBLER_ELF "progran_name.bin"
+ where "program_name.bin" is the bin file that you want to convert
+
+ In Run-Time Type "A" for ASM format, or "H" for HEX format, and Hit "Enter"
+
Index: trunk/PROGRAMMING_exception/Makefile
===================================================================
--- trunk/PROGRAMMING_exception/Makefile (nonexistent)
+++ trunk/PROGRAMMING_exception/Makefile (revision 4)
@@ -0,0 +1,88 @@
+# **********************************************
+# Programs to build
+# **********************************************
+
+PROGS = My_Program
+
+# **********************************************
+# Endianness EB | EL
+# **********************************************
+
+#ENDIAN = EB
+ENDIAN = EL
+
+# **********************************************
+# Bootstrap object file
+# **********************************************
+
+BOOTSTRAP = crt0.o
+
+# **********************************************
+# Compiler toolchain
+# **********************************************
+
+ifeq ($(ENDIAN),EL)
+CC = mipsel-linux-gcc
+LD = mipsel-linux-ld
+OBJCOPY = mipsel-linux-objcopy
+OBJDUMP = mipsel-linux-objdump
+endif
+
+ifeq ($(ENDIAN),EB)
+CC = mips-linux-gcc
+LD = mips-linux-ld
+OBJCOPY = mips-linux-objcopy
+OBJDUMP = mips-linux-objdump
+endif
+
+# **********************************************
+# Compiler and linker options
+# **********************************************
+
+W_OPTS = -Wimplicit -Wformat -Wall -Wstrict-prototypes
+W_OPTS_A = -Wformat -Wall -Wstrict-prototypes
+
+
+CC_OPTS = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \
+ -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc
+
+CC_OPTS_A = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \
+ -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc
+
+
+LD_SCRIPT = link.xn
+LD_OPTS = -G 0 -static -T $(LD_SCRIPT)
+
+ifeq ($(ENDIAN),EB)
+LD_FORMAT = elf32-tradbigmips
+endif
+
+ifeq ($(ENDIAN),EL)
+LD_FORMAT = elf32-tradlittlemips
+endif
+
+
+# **********************************************
+# Rules
+# **********************************************
+
+%.o : %.c
+ $(CC) $(W_OPTS) $(CC_OPTS) -o $@ $<
+
+%.o : %.S
+ $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $<
+
+%.o : %.s
+ $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $<
+
+all: $(PROGS)
+
+
+My_Program : $(BOOTSTRAP) My_Program.o
+ $(LD) $(LD_OPTS) -o $@ $?
+ $(OBJCOPY) -O binary $@ $@.bin
+
+clean :
+ rm -f $(PROGS) *.bin *.o
+ rm -f *~
+
Index: trunk/PROGRAMMING_exception/My_Program.c
===================================================================
--- trunk/PROGRAMMING_exception/My_Program.c (nonexistent)
+++ trunk/PROGRAMMING_exception/My_Program.c (revision 4)
@@ -0,0 +1,85 @@
+#define memstore(address,save) { \
+unsigned int *ctrlstore = (unsigned int *) address; \
+*ctrlstore = save;}
+
+#define ADDR_IO 0x00009000
+#define ADDR_STOP 0x7FFFFFFC
+#define ADDR_QUICK 0x00003F00
+
+
+void quicksort (int a[], int lo, int hi)
+{
+ int i=lo, j=hi, h;
+ int x=a[(lo+hi)/2];
+
+ // partition
+ do
+ {
+ while (a[i]x) j--;
+ if (i<=j)
+ {
+ h=a[i]; a[i]=a[j]; a[j]=h;
+ i++; j--;
+ }
+ } while (i<=j);
+
+ // recursion
+ if (lo
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
Index: trunk/source/top.cpp
===================================================================
--- trunk/source/top.cpp (nonexistent)
+++ trunk/source/top.cpp (revision 4)
@@ -0,0 +1,3 @@
+#include "top.h"
+
+
Index: trunk/source/main.cpp
===================================================================
--- trunk/source/main.cpp (nonexistent)
+++ trunk/source/main.cpp (revision 4)
@@ -0,0 +1,420 @@
+//
+// $Id: main.cpp,v 1.1 2006-01-25 16:57:56 igorloi Exp $
+//
+#include
+#include "top_debug.h"
+#include "./constants/config.h"
+
+int sc_main(int argc, char *argv[])
+{
+ sc_clock clk("clock", 20, SC_NS);
+
+ if (argc == 1)
+ {
+ cout << "Usage:" << endl;
+ cout << argv[0] << " [runlength (ns)]" << endl;
+ return 0;
+ }
+
+
+ // Istanzio il modulo top level
+ top_debug *debug_level;
+ debug_level = new top_debug("debug_level", argv[1]);
+ debug_level->in_clk(clk.signal());
+
+
+ // Trace file - VCD format...
+ sc_trace_file * trace_file;
+ trace_file = sc_create_vcd_trace_file("main.trace");
+
+#ifdef SIGNAL_SC_CPU
+ sc_trace(trace_file, debug_level->top_level->in_clk, "clk");
+ sc_trace(trace_file, debug_level->top_level->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->instaddr, "instaddr");
+ sc_trace(trace_file, debug_level->top_level->instdataread, "instdataread");
+ sc_trace(trace_file, debug_level->top_level->instreq, "instreq");
+ sc_trace(trace_file, debug_level->top_level->instrw, "instrw");
+ sc_trace(trace_file, debug_level->top_level->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->dataaddr, "dataaddr");
+ sc_trace(trace_file, debug_level->top_level->dataread_m_dec, "dataread_m_dec");
+ sc_trace(trace_file, debug_level->top_level->dataread_dec_cpu, "dataread_dec_cpu");
+ sc_trace(trace_file, debug_level->top_level->datawrite, "datawrite");
+ sc_trace(trace_file, debug_level->top_level->datareq, "datareq");
+ sc_trace(trace_file, debug_level->top_level->datarw, "datarw");
+ sc_trace(trace_file, debug_level->top_level->databs, "databs");
+ sc_trace(trace_file, debug_level->top_level->datahold, "datahold");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_pc, "enable_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_fetch, "enable_fetch");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_decode, "enable_decode");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_execute, "enable_execute");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_memstage, "enable_memstage");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_exception, "if_exception");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id_exception, "id_exception");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_exception, "ex_exception");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem_exception, "mem_exception");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->wb_exception, "wb_exception");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->DBUS, "DBUS");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrs");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_ovf_excep, "ex_m_ovf_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_syscall_exception, "ex_m_syscall_exception");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_illegal_instruction, "ex_m_illegal_instruction");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_inst_addrl, "ex_m_inst_addrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_IBUS, "ex_m_IBUS");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_id_instaddr, "if_id_instaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id_ex_instaddr, "id_ex_instaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_m_instaddr, "ex_m_instaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_instaddr, "m_wb_instaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_dataaddr, "m_wb_dataaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cause, "cause");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->check_excep, "check_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->Temp_Status_Register, "cp0_r.Temp_Status_Register");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->to_EPC, "to_EPC");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->to_BadVAddr, "to_BadVAddr");
+ //CP0 REGISTERS
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[8] , "cp0_regs[8]");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[14], "cp0_regs[14]");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[13], "cp0_regs[13]");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[12], "cp0_regs[12]");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->insthold, "sspc.insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->new_pc, "sspc.new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->load_epc, "sspc.load_epc");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->check_excep, "sspc.check_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->currentstate, "sspc.currentstate");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->nextstate, "sspc.nextstate");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->x_insthold, "sspc.x_insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->in_clk, "sspc.in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->cp0_inst, "sspc.cp0_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->EPC_FOR_RFE, "sspc.EPC_FOR_RFE");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_mux_fw2, "id.id_mux_fw2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_sign_extend , "id.id_sign_extend");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->interrupt_signal, "interrupt_signal");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->interrupt_signal_out, "interrupt_signal_out");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reg_mem1->datahold, "red_mem.datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reg_mem1->insthold, "reg_mem.insthold");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_interrupt_signal, "m_wb_interrupt_signal");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->excp->to_SR, "excp.to_SR");;
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_reg1, "id_reg1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_reg2, "id_reg2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->rs, "rs");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->rt, "rt");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage0, "ex.stage0");
+ #ifdef _MULT_PIPELINE_
+ #if(DEPTH_MULT_PIPE == 1)
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1");
+ #else
+ #if(DEPTH_MULT_PIPE == 2)
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2");
+ #else
+ #if(DEPTH_MULT_PIPE == 3)
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage3, "ex.stage3");
+ #else
+ #if(DEPTH_MULT_PIPE == 4)
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage3, "ex.stage3");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage4, "ex.stage4");
+ #endif
+ #endif
+ #endif
+ #endif
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->ready, "fsm.ready");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->current_state, "fsm.current_state");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->hold_pipe, "fsm.hold_pipe");
+ #endif
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->hi, "ex.hi");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->lo, "ex.lo");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_id_inst, "cpu.if_id_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id_ex_inst, "cpu.id_ex_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_mem_inst, "cpu.ex_mem_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem_wb_inst, "cpu.mem_wb_inst");
+
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_function, "ex.id_ex_alu_function");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_opcode, "ex.id_ex_alu_opcode");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_function, "id.id_function");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_opcode, "id.id_opcode");
+#endif
+
+#ifdef SIGNAL_DATAMEM
+ // MEMORY3
+ sc_trace(trace_file, debug_level->top_level->datamem->memaddr, "datamem.dataaddr");
+ sc_trace(trace_file, debug_level->top_level->datamem->memdataread, "datamem.dataread");
+ sc_trace(trace_file, debug_level->top_level->datamem->memdatawrite, "datamem.datawrite");
+ sc_trace(trace_file, debug_level->top_level->datamem->memreq, "datamem.datareq");
+ sc_trace(trace_file, debug_level->top_level->datamem->memrw, "datamem.datarw");
+
+ sc_trace(trace_file, debug_level->top_level->datamem->addrl, "data_addrl");
+ sc_trace(trace_file, debug_level->top_level->datamem->addrs, "data_addrs");
+ sc_trace(trace_file, debug_level->top_level->datamem->page_fault, "DBUS");
+
+#endif
+
+#ifdef SIGNAL_PC_STAGE
+ // PC State
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->datahold, "datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_in, "pc_in");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_out, "pc_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instaddr, "instaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instdatawrite, "instdatawrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instreq, "instreq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instrw, "instrw");
+#endif
+
+#ifdef SIGNAL_IF_STAGE
+ // IF State
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->datahold, "datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_out, "pc_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_new_pc, "id_new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_jmp_tar, "id_jmp_tar");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_ctrl, "id_ctrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_branch, "id_branch");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_in, "pc_in");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->instdataread, "instdataread");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_inst, "if_id_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_next_pc, "if_id_next_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->new_pc, "new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->load_epc, "load_epc");
+#endif
+
+#ifdef SIGNAL_ID_STAGE
+ // ID Stage
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->datahold, "datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->if_id_next_pc, "if_id_next_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->if_id_inst, "if_id_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_jmp_tar, "id_jmp_tar");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_new_pc, "id_new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ctrl, "id_ctrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_branch, "id_branch");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu1, "id_ex_alu1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu2, "id_ex_alu2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datastore, "id_ex_datastore");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_alu_ctrl, "id_alu_ctrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_equal, "id_ex_equal");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_byteselect, "id_ex_byteselect");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_bssign, "id_ex_bssign");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu_sa, "id_ex_alu_sa");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datareq, "id_ex_datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datarw, "id_ex_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_memtoreg, "id_ex_memtoreg");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_writeregister_out, "id_ex_writeregister_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_regwrite_out, "id_ex_regwrite_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_writeregister, "id_ex_m_writeregister");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_wb_writeregister, "id_ex_m_wb_writeregister");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_regwrite, "id_ex_m_regwrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_wb_regwrite, "id_ex_m_wb_regwrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->ex_id_forward, "ex_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->m_id_forward, "m_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->wb_id_forward, "wb_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_inst, "cp0_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_no, "cp0_reg_no");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_rw, "cp0_reg_rw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_rs, "cp0_reg_rs");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_out, "cp0_reg_out");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[1], "$1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[2], "$2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[3], "$3");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[4], "$4");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[5], "$5");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[6], "$6");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[7], "$7");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[8], "$8");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[9], "$9");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[10], "$10");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[11], "$11");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[12], "$12");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[13], "$13");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[14], "$14");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[15], "$15");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[16], "$16");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[17], "$17");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[18], "$18");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[19], "$19");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[20], "$20");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[21], "$21");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[22], "$22");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[23], "$23");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[24], "$24");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[25], "$25");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[26], "$26");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[27], "$27");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[28], "$28");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[29], "$29");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[30], "$30");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[31], "$31");
+
+#endif
+
+#ifdef SIGNAL_EX_STAGE
+ // EX Stage
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->datahold, "datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu1, "id_ex_alu1");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu2, "id_ex_alu2");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datastore, "id_ex_datastore");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_ctrl, "id_ex_alu_ctrl");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_equal, "id_ex_equal");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_byteselect, "id_ex_byteselect");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_bssign, "id_ex_bssign");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_sa, "id_ex_alu_sa");
+
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datareq, "id_ex_datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datarw, "id_ex_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_memtoreg, "id_ex_memtoreg");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_writeregister_out, "id_ex_writeregister_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_regwrite_out, "id_ex_regwrite_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_writeregister, "id_ex_m_writeregister");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_regwrite, "id_ex_m_regwrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datareq, "id_ex_m_datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datarw, "id_ex_m_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datastore, "id_ex_m_datastore");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ex_m_alu, "ex_m_alu");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_memtoreg, "id_ex_m_memtoreg");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ex_id_forward, "ex_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_byteselect, "id_ex_m_byteselect");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_bssign, "id_ex_m_bssign");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ovf_excep, "ovf_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->addr_err, "addr_err");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->lo, "multiply.lo");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->hi, "multiply.hi");
+
+
+#endif
+
+#ifdef SIGNAL_MEM_STAGE
+ // MEM Stage
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->insthold, "insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datahold, "datahold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datareq, "id_ex_m_datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datarw, "id_ex_m_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datastore, "id_ex_m_datastore");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_alu, "ex_m_alu");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_memtoreg, "id_ex_m_memtoreg");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_byteselect, "id_ex_m_byteselect");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_bssign, "id_ex_m_bssign");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->dataread, "dataread");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datawrite, "datawrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->dataaddr, "dataaddr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datareq, "datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datarw, "datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->databs, "databs");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_writeregister, "id_ex_m_writeregister");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_regwrite, "id_ex_m_regwrite");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_wb_writeregister, "id_ex_m_wb_writeregister");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->m_id_forward, "m_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->wb_id_forward, "wb_id_forward");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_store, "id_store");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_wb_regwrite, "id_ex_m_wb_regwrite");
+
+
+#endif
+
+#ifdef SIGNAL_CP0
+ // cp0
+ sc_trace(trace_file, debug_level->top_level->risc->co0->in_clk, "in_clk");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->reset, "reset");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->pc_out, "pc_out");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->pc_in, "pc_in");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->id_ex_datarw, "id_ex_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->id_ex_datareq, "id_ex_datareq");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->id_branch, "id_branch");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->id_ctrl, "id_ctrl");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->new_pc, "new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->load_epc, "load_epc");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->m_wb_ovf_excep, "m_wb_ovf_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->ex_alu, "ex_alu");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->addr_err, "addr_err");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_inst, "cp0_inst");
+
+ sc_trace(trace_file, debug_level->top_level->risc->co0->x_insthold, "x_insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->insthold, "insthold");
+
+ sc_trace(trace_file, debug_level->top_level->risc->co0->reg_no, "reg_no");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->reg_rw, "reg_rw");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->reg_rs, "reg_rs");
+ sc_trace(trace_file, debug_level->top_level->risc->co0->reg_out, "reg_out");
+#endif
+
+#ifdef ONEHOT_DEBUG
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_jalr, "onehot_debug.inst_jalr");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_addiu, "onehot_debug.inst_addiu");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_lw, "onehot_debug.inst_lw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_mtc0, "onehot_debug.inst_mtc0");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_mfc0, "onehot_debug.inst_mfc0");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_nop, "onehot_debug.inst_nop");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_sw, "onehot_debug.inst_sw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_wait, "onehot_debug.inst_wait");
+#endif
+
+#ifdef SIGNAL_INTERRUPT
+
+ // remaining inputs/outputs
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->pc_out, "cp0.pc_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->pc_in, "cp0.pc_in");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ex_datarw, "cp0.id_ex_datarw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ex_datareq, "cp0.id_ex_datareq");
+ /*
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_branch, "cp0.id_branch");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ctrl, "cp0.id_ctrl");
+ */
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->new_pc, "cp0.new_pc");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->load_epc, "cp0.load_epc");
+ /*
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->ovf_excep, "cp0.ovf_excep");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->addr_err, "cp0.addr_err");
+ */
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->cp0_inst, "cp0.cp0_inst");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->x_insthold, "cp0.x_insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->insthold, "cp0.insthold");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_no, "cp0.reg_no");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_rw, "cp0.reg_rw");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_rs, "cp0.reg_rs");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_out, "cp0.reg_out");
+ sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->currentstate, "cp0.currentstate");
+
+
+#endif
+
+ /////////////////////////////////////////////////////////////////
+ // Start the simulation
+ /////////////////////////////////////////////////////////////////
+
+ cout << "--->Start<---" << endl;
+ sc_report::suppress_warnings(true);
+
+ int runtime;
+ if (argc == 3)
+ runtime = atoi(argv[2]);
+ else
+ runtime = -1;
+
+ sc_start(runtime);
+
+
+ sc_close_vcd_trace_file(trace_file);
+
+ return 0;
+}
Index: trunk/source/top_debug.cpp.BAK
===================================================================
--- trunk/source/top_debug.cpp.BAK (nonexistent)
+++ trunk/source/top_debug.cpp.BAK (revision 4)
@@ -0,0 +1,439 @@
+#include "top_debug.h"
+
+void decode(sc_lv<32> if_id_inst, unsigned int i, ostream& out)
+{
+
+ sc_lv<32> inst = if_id_inst;
+ sc_lv<6> func = inst.range(5,0);
+ sc_lv<6> op = inst.range(31,26);
+
+ char *charinst=0;
+
+ sc_lv<5> rs, rt ,rd ,lrs, lrt, lrd, lsa; // lv version of reg #
+ sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg #
+ sc_int<32> is, it, id; // integer version of register contents...
+
+ //! The immediate value in an instruction
+ sc_lv<16> imm;
+ sc_lv<32> imm_sign, imm_zero;
+ sc_int<32> iimm_sign, iimm_zero;
+ sc_uint<32> uiimm_sign, uiimm_zero;
+ sc_lv<28> instr_index;
+ sc_uint<28> uiinstr_index;
+
+ // register destinations and recipients
+ rs = inst.range(25,21);
+ rt = inst.range(20,16);
+ rd = inst.range(15,11);
+ uirs = lrs = inst.range(25,21);
+ uirt = lrt = inst.range(20,16);
+ uird = lrd = inst.range(15,11);
+ uisa = lsa = inst.range(10,6);
+
+
+ // Immediate values
+ imm = inst.range(15,0);
+ uiimm_zero = iimm_zero = imm_zero = (HALFWORD_ZERO,imm);
+ if( imm[15] == '1')
+ uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ONE,imm);
+ else
+ uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ZERO,imm);
+
+ uiinstr_index = instr_index = (inst.range(25,0), "00");
+
+
+
+ //switch stage
+ if(op == OP_RFORMAT)
+ {
+ if(func == FUNC_JR)
+ {
+ out << " MIPS (ID): jr $"<< dec << (unsigned int)uirs << endl;
+ }
+ else if(func == FUNC_JALR)
+ {
+ if (uird == 0)
+ out << " MIPS (ID): jalr $" << dec << (unsigned int)uirs << endl;
+ else
+ out << " MIPS (ID): jalr $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << endl;
+ }
+
+ /*
+
+ */
+ else
+ if(func == FUNC_MTHI ||
+ func == FUNC_MFLO ||
+ func == FUNC_MULT ||
+ func == FUNC_MULTU ||
+ func == FUNC_DIV ||
+ func == FUNC_DIVU)
+
+ if (func == FUNC_MTHI) {charinst = "mthi"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uirs << " [Hi]" << endl;}
+
+ if (func == FUNC_MFLO) {charinst = "mflo"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uird << " [Lo]" << endl;}
+
+ if (func == FUNC_MULT) {charinst = "mult"; out << " MIPS (ID): " << charinst << " [Hi,Lo]," <<" $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;}
+
+ if (func == FUNC_MULTU) {charinst = "multu"; out << " MIPS (ID): " << charinst <<" [Hi,Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;}
+
+ if (func == FUNC_DIV) {charinst = "div"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Resto = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;}
+
+ if (func == FUNC_DIVU) {charinst = "divu"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Rest = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;}
+
+
+ else if(func == FUNC_SLL ||
+ func == FUNC_SRL ||
+ func == FUNC_SRA)
+ {
+ if (func == FUNC_SLL) charinst = "sll";
+ if (func == FUNC_SRL) charinst = "srl";
+ if (func == FUNC_SRA) charinst = "sra";
+ if (func == FUNC_SLL && (unsigned int)uird == 0)
+ out << " MIPS (ID): nop" << endl;
+ else
+ out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird <<", $" << dec << (unsigned int)uirt <<", " << dec << (unsigned int)uisa << endl;
+ }
+ else if(func == FUNC_SLLV ||
+ func == FUNC_SRLV ||
+ func == FUNC_SRAV ||
+ func == FUNC_ADD ||
+ func == FUNC_ADDU ||
+ func == FUNC_SUB ||
+ func == FUNC_SUBU ||
+ func == FUNC_AND ||
+ func == FUNC_OR ||
+ func == FUNC_XOR ||
+ func == FUNC_NOR ||
+ func == FUNC_SLT ||
+ func == FUNC_SLTU)
+ {
+
+ // printf("MIPS (ID): R-Format - read next line!\n");
+ if (func == FUNC_SLLV) charinst = "sllv";
+ if (func == FUNC_SRLV) charinst = "srlv";
+ if (func == FUNC_SRAV) charinst = "srav";
+ if (func == FUNC_ADD) charinst = "add";
+ if (func == FUNC_ADDU) charinst = "addu";
+ if (func == FUNC_SUB) charinst = "sub";
+ if (func == FUNC_SUBU) charinst = "subu";
+ if (func == FUNC_AND) charinst = "and";
+ if (func == FUNC_OR) charinst = "or";
+ if (func == FUNC_XOR) charinst = "xor";
+ if (func == FUNC_NOR) charinst = "nor";
+ if (func == FUNC_SLT) charinst = "slt";
+ if (func == FUNC_SLTU) charinst = "sltu";
+ out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;
+ }
+ else if (func == FUNC_BREAK)
+ {
+ out << " MIPS (ID): BREAK" << endl;
+ }
+
+ else if (func == FUNC_SYSCALL)
+ {
+ out << " MIPS (ID): SYSCALL" << endl;
+ }
+
+ else if (func == FUNC_BREAK || func == FUNC_SYSCALL)
+ {
+ out << " Exception!!" << endl;
+ }
+
+ else
+ {
+ out << " * UNKNOWN FUNCTION CODE FOR R-format" << endl;
+ }
+ }
+ else if(op == OP_BRANCH)
+ {
+ // PRINTLN("Branch format");
+ if(lrt.range(1,0) == BRANCH_BLTZ)
+ {
+ out << " MIPS (ID): bltz $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+ else if(lrt.range(1,0) == BRANCH_BGEZ)
+ {
+ out << " MIPS (ID): bgez $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+ else if(lrt.range(1,0) == BRANCH_BLTZAL)
+ {
+ out << " MIPS (ID): bltzal $"<< dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+ else if(lrt.range(1,0) == BRANCH_BGEZAL)
+ {
+
+ out << " MIPS (ID): bgezal $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+ }
+
+
+ else if(op == OP_J)
+ {
+
+ out << " MIPS (ID): j "<< dec << (unsigned int) uiinstr_index << endl;
+ }
+
+
+ else if(op == OP_JAL)
+ {
+ out << " MIPS (ID): jal " << dec << (unsigned int) uiinstr_index << endl;
+ }
+
+
+ else if(op == OP_BEQ)
+ {
+ out << " MIPS (ID): beq $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_BNE)
+ {
+ out << " MIPS (ID): bne $"<< dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_BLEZ)
+ {
+ out << " MIPS (ID): blez $" << dec << (unsigned int) uirs << ", " << dec << (unsigned int) iimm_sign << endl;
+ }
+
+
+ else if(op == OP_BGTZ)
+ {
+ out << " MIPS (ID): bgtz $" << dec << (unsigned int)uirs << ", " << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_ADDI)
+ {
+ out << " MIPS (ID): addi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_ADDIU)
+ {
+ out << " MIPS (ID): addiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (int)uiimm_sign << endl;
+ }
+
+
+ else if(op == OP_SLTI)
+ {
+ out << " MIPS (ID): slti $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_SLTIU)
+ {
+ out << " MIPS (ID): sltiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_ANDI)
+ {
+ out << " MIPS (ID): andi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_ORI)
+ {
+ out << " MIPS (ID): ori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_XORI)
+ {
+ out << " MIPS (ID): xori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_LUI)
+ {
+ out << " MIPS (ID): lui $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << endl;
+ }
+
+
+ else if(op == OP_LB ||
+ op == OP_LH ||
+ op == OP_LWL ||
+ op == OP_LW ||
+ op == OP_LBU ||
+ op == OP_LHU ||
+ op == OP_LWR)
+ {
+ if (op == OP_LB) charinst = "lb";
+ if (op == OP_LH) charinst = "lh";
+ if (op == OP_LWL) charinst = "lwl";
+ if (op == OP_LW) charinst = "lw";
+ if (op == OP_LBU) charinst = "lbu";
+ if (op == OP_LHU) charinst = "lhu";
+ if (op == OP_LWR) charinst = "lwr";
+ out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl;
+ }
+
+
+ else if(op == OP_SB ||
+ op == OP_SH ||
+ op == OP_SWL ||
+ op == OP_SW ||
+ op == OP_SWR)
+ {
+ if (op == OP_SB) charinst = "sb";
+ if (op == OP_SH) charinst = "sh";
+ if (op == OP_SWL) charinst = "swl";
+ if (op == OP_SW) charinst = "sw";
+ if (op == OP_SWR) charinst = "swr";
+ out << " MIPS (ID): " << charinst <<" $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl;
+ }
+
+
+ else if(op == OP_CACHE)
+ {
+ out << " MIPS (ID): CACHE $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)iimm_sign.range(15,0) << "(" << dec << (unsigned int) uirs << ")" << endl;
+ }
+
+
+ else if(op == OP_COPROC0)
+ {
+ out << " MIPS (ID): CP0 instruction" << endl;
+ }
+ else
+ {
+ if(lrs == RS_MFC0)
+ {
+ out << " MIPS (ID): mfc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl;
+ }
+ else if(lrs == RS_MTC0)
+ {
+ out << " MIPS (ID): mtc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl;
+ }
+ }
+ }
+
+
+
+
+
+
+
+
+
+void top_debug::debug_signals()
+{
+ ofstream out("GIGINO.txt");
+
+ out << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << " Simulationon after " << sc_simulation_time() << "ns Clock n°" << sc_simulation_time()/20 << " Reset =" << top_level->reset << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << endl;
+
+ //PC_STAGE
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx PC_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << " pc_in " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->pc->pc_in) << endl;
+ out << " pc_out " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->pc->pc_out) << endl;
+ out << " enable_pc " << top_level->risc->cpu->pc->enable_pc << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << endl;
+
+ //IF_STAGE
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx IF_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << " instadataread " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->if_s->instdataread) << endl;
+ out << " if_id_next_pc " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->if_s->if_id_next_pc) << endl;
+ out << " enable_if " << top_level->risc->cpu->if_s->enable_fetch << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << endl;
+
+
+
+
+
+
+
+ //ID_STAGE
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ID_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+
+ decode(top_level->instdataread,((unsigned int) ((sc_uint<32>)(top_level->instaddr))), out);
+
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx REGISTERS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+ out << endl;
+ for (int n=0; n < 8; n++)
+ {
+ out << "$"<< dec << n <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n]));
+
+ out << " $"<< dec << n+8 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+8]));
+
+ out << " $"<< dec << n+16 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+16]));
+
+ out << " $"<< dec << n+24 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+24]))<< endl;
+
+ }
+
+ out << " [HI] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_hi) << endl;
+
+ out << " [LO] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_lo) << endl;
+
+
+ out << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+
+ out << " dataaddr = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>)(top_level->dataaddr)) << endl;
+ out << " dataread = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->dataread_dec_cpu)) << " ("<< top_level->dataread_dec_cpu <<")"<< endl;
+ out << " datawrite = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->datawrite)) << " ("<< top_level->datawrite <<")"<< endl;
+ out << " datareq = " << top_level->datarw << endl;
+ out << " datarw = " << top_level->datareq << endl;
+ out << " databs = " << top_level->databs << endl;
+
+ out << endl;
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx INST_MEM xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+
+
+
+ out << " PC = 0x" << hex << setw(8) << setfill('0') << ((unsigned int)((sc_uint<32>)(top_level->instaddr))) << endl;
+ out << " InstDataRead = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->instdataread)) << " " << top_level->instdataread << endl;
+
+ out << " instreq = " << top_level->instreq << endl;
+
+ out << endl;
+ out << endl;
+
+
+ out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MEMORY xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl;
+
+ int temp, temp2, Start, Stop;
+ Start = Start_pos;
+ Stop = Finish_pos;
+ temp = (Start + (Stop - Start)/4);
+ temp2 = ((Stop - Start)/4);
+
+ for(int n= Start; n < temp; n=n+4)
+ {
+ out << "[0x"<< hex << n << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[(n >> 2)] << " ";
+
+ out << "[0x"<< hex << (n + temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+temp2) >> 2)] << " ";
+
+ out << "[0x"<< hex << (n + 2*temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+2*temp2) >> 2)] << " ";
+
+ out << "[0x"<< hex << (n + 3*temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+3*temp2) >> 2)] << " " << endl;
+
+ /*out << "cella [0x"<< hex << (n+8) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+8) >> 2)] << " ";
+
+ out << "cella [0x"<< hex << (n+12) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+12) >> 2)] << endl;*/
+
+ }
+
+
+
+ char buffer[256];
+ ifstream examplefile ("GIGINO.txt");
+ if (! examplefile.is_open())
+ { cout << "Error opening file"; exit (1); }
+
+ while (! examplefile.eof() )
+ {
+ examplefile.getline (buffer,100);
+ fprintf (fp ,"%s\n", buffer);
+ }
+}
Index: trunk/source/cpu/id_stage/reg_id.h
===================================================================
--- trunk/source/cpu/id_stage/reg_id.h (nonexistent)
+++ trunk/source/cpu/id_stage/reg_id.h (revision 4)
@@ -0,0 +1,88 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(reg_id)
+{
+ sc_in in_clk;
+ sc_in reset;
+ sc_in datahold;
+ sc_in insthold;
+
+ sc_out > id_ex_alu1;
+ sc_in > id_alu1;
+
+ sc_out > id_ex_alu2;
+ sc_in > id_alu2;
+
+ sc_out > id_ex_datastore;
+ sc_in > id_mux_fw2;
+
+ sc_out > id_ex_alu_ctrl;
+ sc_in > id_alu_ctrl;
+
+ sc_out > id_ex_alu_opcode;
+ sc_in > id_opcode;
+
+ sc_out > id_ex_alu_function;
+ sc_in > id_function;
+
+ sc_out > id_ex_alu_sa;
+ sc_in > id_alu_sa;
+
+ sc_out id_ex_equal;
+ sc_in id_equal;
+
+ sc_out id_ex_datareq;
+ sc_in id_datareq;
+
+ sc_out id_ex_datarw;
+ sc_in id_datarw;
+
+ sc_out id_ex_memtoreg;
+ sc_in id_memtoreg;
+
+ sc_out > id_ex_writeregister_out;
+ sc_in > id_writeregister;
+
+ sc_out > id_ex_writeregister;
+ //sc_in > id_writeregister;
+
+ sc_out id_ex_regwrite_out;
+ sc_in id_regwrite;
+
+ sc_out id_ex_regwrite;
+ //sc_in id_regwrite;
+
+ sc_out > id_ex_byteselect;
+ sc_in > id_byteselect;
+
+ sc_out id_ex_bssign;
+ sc_in id_bssign;
+
+ sc_in > if_id_inst;
+ sc_out > id_ex_inst;
+
+ // EXCEPTIONS SIGNALS
+ sc_in illegal_instruction;
+ sc_in syscall_exception;
+ sc_in if_id_IBUS;
+ sc_in if_id_inst_addrl;
+ sc_out id_ex_IBUS;
+ sc_out id_ex_inst_addrl;
+ sc_out id_ex_syscall_exception;
+ sc_out id_ex_illegal_instruction;
+
+ sc_in > if_id_instaddr;
+ sc_out > id_ex_instaddr;
+
+ sc_in enable_decode;
+
+ void do_reg_id();
+
+ SC_CTOR(reg_id)
+ {
+ SC_METHOD(do_reg_id);
+ //sensitive_pos << reset;
+ sensitive_pos << in_clk;
+ }
+};
Index: trunk/source/cpu/id_stage/mux_alu1.h
===================================================================
--- trunk/source/cpu/id_stage/mux_alu1.h (nonexistent)
+++ trunk/source/cpu/id_stage/mux_alu1.h (revision 4)
@@ -0,0 +1,23 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(mux_alu1)
+{
+ sc_in > if_id_inst;
+ sc_in id_shamt_ctrl;
+ sc_in id_pc_store;
+ sc_out > id_alu1;
+ sc_in > if_id_next_pc;
+ sc_in > cp0_reg_out;
+ sc_in > id_mux_fw1;
+ sc_in id_mfc0;
+
+ void do_mux_alu1();
+
+ SC_CTOR(mux_alu1)
+ {
+ SC_METHOD(do_mux_alu1);
+ sensitive << id_pc_store << id_shamt_ctrl << if_id_inst << id_mux_fw1;
+ sensitive << if_id_next_pc << cp0_reg_out << id_mfc0;
+ }
+};
Index: trunk/source/cpu/id_stage/mux_alu2.h
===================================================================
--- trunk/source/cpu/id_stage/mux_alu2.h (nonexistent)
+++ trunk/source/cpu/id_stage/mux_alu2.h (revision 4)
@@ -0,0 +1,19 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(mux_alu2)
+{
+ sc_in > id_sign_extend;
+ sc_in > id_sign_ctrl;
+ sc_out > id_alu2;
+ sc_out > cp0_reg_rs;
+ sc_in > id_mux_fw2;
+
+ void do_mux_alu2();
+
+ SC_CTOR(mux_alu2)
+ {
+ SC_METHOD(do_mux_alu2);
+ sensitive << id_mux_fw2 << id_sign_extend << id_sign_ctrl;
+ }
+};
Index: trunk/source/cpu/id_stage/mux_forward_select.h
===================================================================
--- trunk/source/cpu/id_stage/mux_forward_select.h (nonexistent)
+++ trunk/source/cpu/id_stage/mux_forward_select.h (revision 4)
@@ -0,0 +1,21 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(mux_forward_select)
+{
+ sc_in > id_reg;
+ sc_in > ex_id_forward;
+ sc_in > m_id_forward;
+ sc_in > wb_id_forward;
+ sc_in > id_fw_ctrl;
+
+ sc_out > id_mux_fw;
+
+ void do_mux_forward_select();
+
+ SC_CTOR(mux_forward_select)
+ {
+ SC_METHOD(do_mux_forward_select);
+ sensitive << id_reg << ex_id_forward << m_id_forward << wb_id_forward << id_fw_ctrl;
+ }
+};
Index: trunk/source/cpu/id_stage/forwarding_control.cpp
===================================================================
--- trunk/source/cpu/id_stage/forwarding_control.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/forwarding_control.cpp (revision 4)
@@ -0,0 +1,21 @@
+#include "forwarding_control.h"
+
+void forwarding_control::do_forwarding_control()
+{
+ if ((id_ex_writeregister.read() == rs.read()) && (id_ex_regwrite.read() == 1))
+ {
+ id_fw_ctrl.write("01");
+ }
+ else if ((id_ex_m_writeregister.read() == rs.read()) && (id_ex_m_regwrite.read() == 1))
+ {
+ id_fw_ctrl.write("10");
+ }
+ else if ((id_ex_m_wb_writeregister.read() == rs.read()) && (id_ex_m_wb_regwrite.read() == 1))
+ {
+ id_fw_ctrl.write("11");
+ }
+ else
+ {
+ id_fw_ctrl.write("00");
+ }
+}
Index: trunk/source/cpu/id_stage/mux_jump.cpp
===================================================================
--- trunk/source/cpu/id_stage/mux_jump.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/mux_jump.cpp (revision 4)
@@ -0,0 +1,16 @@
+#include "mux_jump.h"
+
+void mux_jump::do_mux_jump()
+{
+ sc_lv<32> iinp = if_id_next_pc.read();
+ sc_lv<32> iii = if_id_inst.read();
+
+ if(id_select_jump == SC_LOGIC_0)
+ {
+ id_jmp_tar.write((iinp.range(31,28),iii.range(25,0),"00"));
+ }
+ else
+ {
+ id_jmp_tar.write(id_mux_fw1.read());
+ }
+}
Index: trunk/source/cpu/id_stage/sign_extend.cpp
===================================================================
--- trunk/source/cpu/id_stage/sign_extend.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/sign_extend.cpp (revision 4)
@@ -0,0 +1,23 @@
+#include "sign_extend.h"
+
+void sign_extend::do_sign_extend()
+{
+ sc_lv<32> inst = if_id_inst.read();
+ sc_lv<2> iec = id_extend_ctrl.read();
+
+ if( iec == "00")
+ if(inst[15] == SC_LOGIC_1)
+ id_sign_extend = (HALFWORD_ONE,inst.range(15,0));
+ else
+ id_sign_extend = (HALFWORD_ZERO,inst.range(15,0));
+
+ else
+ if( iec == "01")
+ id_sign_extend = (HALFWORD_ZERO,inst.range(15,0));
+ else
+ if( iec == "10")
+ id_sign_extend = (inst.range(15,0),HALFWORD_ZERO);
+ else
+ id_sign_extend = WORD_ZERO;
+
+}
Index: trunk/source/cpu/id_stage/comparator.cpp
===================================================================
--- trunk/source/cpu/id_stage/comparator.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/comparator.cpp (revision 4)
@@ -0,0 +1,61 @@
+#include "comparator.h"
+
+void comparator::do_comparator()
+{
+ sc_logic result;
+
+ sc_lv<32> ss = id_mux_fw1.read();
+ sc_lv<32> tt = id_mux_fw2.read();
+
+
+ sc_int<32> sss = ss;
+ sc_int<32> ttt = tt;
+ sc_lv<3> ibs = id_branch_select.read();
+ result = SC_LOGIC_0;
+
+ if(ibs == "000")
+ result = SC_LOGIC_0;
+ else if(ibs == "001")
+ {
+ result = SC_LOGIC_0;
+ PRINT("***** ERROR COMPARATOR ****** ");
+ }
+ else if(ibs == "010") // beq
+ if( sss == ttt )
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else if(ibs == "011") // bne
+ if( sss != ttt)
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else if(ibs == "100") // bltz
+ if( sss < 0)
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else if(ibs == "101") // blez
+ if( sss <= 0)
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else if(ibs == "110") // bgtz
+ // Vil ikke godtage sss > 0 til verilog
+ // if( !(sss <= 0) )
+ if ( sss > 0 )
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else if(ibs == "111")
+ if( sss >= 0)
+ result = SC_LOGIC_1;
+ else
+ result = SC_LOGIC_0;
+ else
+ result = SC_LOGIC_0;
+
+ id_equal.write(result);
+ id_branch.write(result);
+}
+
Index: trunk/source/cpu/id_stage/decode_ctrl.cpp
===================================================================
--- trunk/source/cpu/id_stage/decode_ctrl.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/decode_ctrl.cpp (revision 4)
@@ -0,0 +1,13 @@
+#include "decode_ctrl.h"
+
+void decode_ctrl::do_decode_ctrl()
+{
+ if((if_id_IBUS.read() == SC_LOGIC_1) ||
+ (if_id_inst_addrl.read() == SC_LOGIC_1) ||
+ (syscall_exception.read() == SC_LOGIC_1) ||
+ (illegal_instruction.read() == SC_LOGIC_1))
+ id_exception.write(SC_LOGIC_1);
+ else
+ id_exception.write(SC_LOGIC_0);
+
+};
Index: trunk/source/cpu/id_stage/forwarding_control.h
===================================================================
--- trunk/source/cpu/id_stage/forwarding_control.h (nonexistent)
+++ trunk/source/cpu/id_stage/forwarding_control.h (revision 4)
@@ -0,0 +1,24 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(forwarding_control)
+{
+ sc_in > id_ex_writeregister;
+ sc_in > id_ex_m_writeregister;
+ sc_in > id_ex_m_wb_writeregister;
+ sc_in id_ex_regwrite;
+ sc_in id_ex_m_regwrite;
+ sc_in id_ex_m_wb_regwrite;
+ sc_in > rs;
+ sc_out > id_fw_ctrl;
+
+ void do_forwarding_control();
+
+ SC_CTOR(forwarding_control)
+ {
+ SC_METHOD(do_forwarding_control);
+ sensitive << id_ex_writeregister << id_ex_m_writeregister;
+ sensitive << id_ex_m_wb_writeregister << id_ex_regwrite;
+ sensitive << id_ex_m_regwrite << id_ex_m_wb_regwrite << rs;
+ }
+};
Index: trunk/source/cpu/id_stage/mux_jump.h
===================================================================
--- trunk/source/cpu/id_stage/mux_jump.h (nonexistent)
+++ trunk/source/cpu/id_stage/mux_jump.h (revision 4)
@@ -0,0 +1,20 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+#include "../../constants/config.h"
+
+SC_MODULE(mux_jump)
+{
+ sc_in > if_id_next_pc;
+ sc_in > if_id_inst;
+ sc_in id_select_jump;
+ sc_in > id_mux_fw1;
+ sc_out > id_jmp_tar;
+
+ void do_mux_jump();
+
+ SC_CTOR(mux_jump)
+ {
+ SC_METHOD(do_mux_jump);
+ sensitive << id_select_jump << if_id_inst << if_id_next_pc << id_mux_fw1;
+ }
+};
Index: trunk/source/cpu/id_stage/sign_extend.h
===================================================================
--- trunk/source/cpu/id_stage/sign_extend.h (nonexistent)
+++ trunk/source/cpu/id_stage/sign_extend.h (revision 4)
@@ -0,0 +1,18 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+#include "../../constants/config.h"
+
+SC_MODULE(sign_extend)
+{
+ sc_in > if_id_inst;
+ sc_in > id_extend_ctrl;
+ sc_out > id_sign_extend;
+
+ void do_sign_extend();
+
+ SC_CTOR(sign_extend)
+ {
+ SC_METHOD(do_sign_extend);
+ sensitive << if_id_inst << id_extend_ctrl;
+ }
+};
Index: trunk/source/cpu/id_stage/regfile_high.cpp
===================================================================
--- trunk/source/cpu/id_stage/regfile_high.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/regfile_high.cpp (revision 4)
@@ -0,0 +1,44 @@
+//!
+/*
+ No description
+*/
+#include "../../constants/config.h"
+
+// #ifdef _HIGH_LEVEL_SIM_
+#include "regfile_high.h"
+
+void regfile::storeregister()
+{
+ sc_lv<5> d = rd;
+ if(reset.read() == true)
+ {
+ for(int i = 0; i<32; i++)
+ r[i] = WORD_ZERO;
+ }
+ else
+ {
+ if(wr == SC_LOGIC_1)
+ r[(sc_uint<5>) d] = rd_in;
+ }
+}
+
+//! Load register outputs
+/*!
+ Sets the register file output signals according the inputs
+ */
+void regfile::loadregister()
+{
+ sc_lv<5> t = rt;
+ sc_lv<5> s = rs;
+
+ if(s == "00000")
+ rs_out = WORD_ZERO;
+ else
+ rs_out = r[(sc_uint<5>) s];
+
+ if(t == "00000")
+ rt_out = WORD_ZERO;
+ else
+ rt_out = r[(sc_uint<5>) t];
+}
+// #endif
Index: trunk/source/cpu/id_stage/comparator.h
===================================================================
--- trunk/source/cpu/id_stage/comparator.h (nonexistent)
+++ trunk/source/cpu/id_stage/comparator.h (revision 4)
@@ -0,0 +1,20 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(comparator)
+{
+ sc_in > id_mux_fw1;
+ sc_in > id_mux_fw2;
+ sc_in > id_branch_select;
+ sc_out id_equal;
+ sc_out id_branch;
+
+ void do_comparator();
+
+ SC_CTOR(comparator)
+ {
+ SC_METHOD(do_comparator);
+ sensitive << id_mux_fw1 << id_mux_fw2;
+ sensitive << id_branch_select;
+ }
+};
Index: trunk/source/cpu/id_stage/decode_ctrl.h
===================================================================
--- trunk/source/cpu/id_stage/decode_ctrl.h (nonexistent)
+++ trunk/source/cpu/id_stage/decode_ctrl.h (revision 4)
@@ -0,0 +1,20 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(decode_ctrl)
+{
+ sc_in if_id_IBUS;
+ sc_in if_id_inst_addrl;
+ sc_in illegal_instruction;
+ sc_in syscall_exception;
+ sc_out id_exception;
+
+ void do_decode_ctrl();
+
+ SC_CTOR(decode_ctrl)
+ {
+ SC_METHOD(do_decode_ctrl);
+ sensitive << if_id_IBUS << if_id_inst_addrl;
+ sensitive << syscall_exception << illegal_instruction;
+ }
+};
Index: trunk/source/cpu/id_stage/control.cpp
===================================================================
--- trunk/source/cpu/id_stage/control.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/control.cpp (revision 4)
@@ -0,0 +1,481 @@
+#include "control.h"
+
+
+
+void control::do_control()
+{
+
+ sc_logic n0 = SC_LOGIC_0;
+ sc_logic n1 = SC_LOGIC_1;
+
+ sc_lv<32> inst = if_id_inst;
+ sc_lv<6> func = inst.range(5,0);
+ sc_lv<6> op = inst.range(31,26);
+
+ id_opcode.write(op);
+ id_function.write(func);
+
+ sc_lv<5> lrs, lrt, lrd, lsa; // lv version of reg #
+ sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg #
+ sc_int<32> is, it, id; // integer version of register contents...
+
+ //! The immediate value in an instruction
+ sc_lv<16> imm;
+ sc_lv<32> imm_sign, imm_zero;
+ sc_int<32> iimm_sign, iimm_zero;
+ sc_uint<32> uiimm_sign, uiimm_zero;
+ sc_lv<28> instr_index;
+ sc_uint<28> uiinstr_index;
+
+ // register destinations and recipients
+ rs.write(inst.range(25,21));
+ rt.write(inst.range(20,16));
+ rd.write(inst.range(15,11));
+
+ uirs = lrs = inst.range(25,21);
+ uirt = lrt = inst.range(20,16);
+ uird = lrd = inst.range(15,11);
+ uisa = lsa = inst.range(10,6);
+
+ // signals for selection bytes and sign of lw/sw instructions
+ sc_lv<2> byteselect = "00";
+ sc_logic id_bssign = SC_LOGIC_0;
+
+#ifdef _HIGH_LEVEL_SIM_
+ is = 0; // localreg->r[uirs];
+ it = 0; // localreg->r[uirt];
+ id = 0; // localreg->r[uird];
+#endif
+
+
+ // Immediate values
+ imm = inst.range(15,0);
+ uiimm_zero = iimm_zero = imm_zero = (HALFWORD_ZERO,imm);
+ if( imm[15] == '1')
+ uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ONE,imm);
+ else
+ uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ZERO,imm);
+
+ uiinstr_index = instr_index = (inst.range(25,0), "00");
+
+ id_alu_ctrl.write(func);
+ id_alu_sa.write(inst.range(10,6));
+ id_ctrl.write(n0);
+ id_extend_ctrl.write("00");
+ id_sign_ctrl.write("00");
+ regdest.write("00");
+ id_select_jump.write(n0);
+ id_pc_store.write(n0);
+ id_branch_select.write("000");
+ id_regwrite.write(n0);
+ id_shamt_ctrl.write(n0);
+ id_datarw.write(n0);
+ id_datareq.write(n0);
+ id_memtoreg.write(n0);
+
+ // Signals to cp0
+ cp0_inst.write(CP0_NOTHING); // 4 bit...
+ // cp0_reg_rs will be set directly from forward-MUX
+ cp0_reg_no.write(uird);
+ cp0_reg_rw.write(SC_LOGIC_0); // default value...don't write!
+ id_mfc0.write(SC_LOGIC_0);
+ sc_logic cpo_co = inst[25];
+
+ illegal_instruction.write(SC_LOGIC_0);
+ syscall_exception.write(SC_LOGIC_0);
+
+#ifdef ONEHOT_DEBUG
+ inst_addiu.write(SC_LOGIC_0);
+ inst_jalr.write(SC_LOGIC_0);
+ inst_lw.write(SC_LOGIC_0);
+ inst_mfc0.write(SC_LOGIC_0);
+ inst_mtc0.write(SC_LOGIC_0);
+ inst_nop.write(SC_LOGIC_0);
+ inst_sw.write(SC_LOGIC_0);
+ inst_wait.write(SC_LOGIC_0);
+#endif
+
+ //switch stage
+ if(op == OP_RFORMAT)
+ {
+ if(func == FUNC_JR)
+ {
+ id_ctrl.write(n1);
+ id_select_jump.write(n1);
+ id_alu_ctrl.write("000000");
+ }
+ else if(func == FUNC_JALR)
+ {
+#ifdef ONEHOT_DEBUG
+ inst_jalr.write(SC_LOGIC_1);
+#endif
+ id_ctrl.write(n1);
+ id_select_jump.write(n1);
+ id_pc_store.write(n1);
+ id_regwrite.write(n1);
+ id_alu_ctrl.write(FUNC_ADDU);
+ id_sign_ctrl.write("10");
+ }
+
+ else
+ if(func == FUNC_MULT)
+ {
+ id_alu_ctrl.write(FUNC_MULT);
+ id_regwrite.write(n0);
+ }
+ else if(func == FUNC_MFLO)
+ {
+ id_alu_ctrl.write(FUNC_MFLO);
+ id_regwrite.write(n1);
+ }
+
+ else if(func == FUNC_MTHI)
+ {
+ id_alu_ctrl.write(FUNC_MTHI);
+ id_regwrite.write(n1);
+ }
+
+ else if(func == FUNC_MULTU)
+ {
+ id_alu_ctrl.write(FUNC_MULTU);
+ id_regwrite.write(n0);
+ }
+
+
+ else if(func == FUNC_DIV)
+ {
+ id_alu_ctrl.write(FUNC_DIV);
+ }
+
+ else if(func == FUNC_DIVU)
+ {
+ id_alu_ctrl.write(FUNC_DIVU);
+ }
+
+ else if(func == FUNC_SLL ||
+ func == FUNC_SRL ||
+ func == FUNC_SRA)
+ {
+ id_shamt_ctrl.write(n1);
+ id_regwrite.write(n1);
+#ifdef ONEHOT_DEBUG
+ inst_nop.write(SC_LOGIC_1);
+#endif
+ }
+ else if(func == FUNC_SLLV ||
+ func == FUNC_SRLV ||
+ func == FUNC_SRAV ||
+ func == FUNC_MFHI ||
+ func == FUNC_MFLO ||
+ func == FUNC_ADD ||
+ func == FUNC_ADDU ||
+ func == FUNC_SUB ||
+ func == FUNC_SUBU ||
+ func == FUNC_AND ||
+ func == FUNC_OR ||
+ func == FUNC_XOR ||
+ func == FUNC_NOR ||
+ func == FUNC_SLT ||
+ func == FUNC_SLTU)
+ {
+ id_regwrite.write(n1);
+ }
+#ifdef _INCLUDE_CP0_
+ else if (func == FUNC_BREAK)
+ {
+ cp0_inst.write(CP0_BREAK);
+ }
+ else if (func == FUNC_SYSCALL)
+ {
+ cp0_inst.write(CP0_SYSCALL);
+ syscall_exception.write(SC_LOGIC_1);
+ }
+#else
+ else if (func == FUNC_BREAK || func == FUNC_SYSCALL)
+ {
+
+ //sc_stop();
+ }
+#endif
+ else
+ {
+ illegal_instruction.write(SC_LOGIC_1);
+ cout << " illegal instruction " << endl;
+ //sc_stop();
+ }
+ }
+ else if(op == OP_BRANCH)
+ {
+ // PRINTLN("Branch format");
+ if(lrt.range(1,0) == BRANCH_BLTZ)
+ {
+ id_branch_select.write("100");
+ }
+ else if(lrt.range(1,0) == BRANCH_BGEZ)
+ {
+ id_branch_select.write("111");
+ }
+ else if(lrt.range(1,0) == BRANCH_BLTZAL)
+ {
+ id_branch_select.write("100");
+ id_pc_store.write(n1);
+ id_sign_ctrl.write("10");
+ regdest.write("10");
+ id_regwrite.write(n1);
+ id_alu_ctrl.write(FUNC_ADDU);
+ }
+ else if(lrt.range(1,0) == BRANCH_BGEZAL)
+ {
+ id_branch_select.write("111");
+ id_pc_store.write(n1);
+ id_sign_ctrl.write("10");
+ regdest.write("10");
+ id_regwrite.write(n1);
+ id_alu_ctrl.write(FUNC_ADDU);
+ }
+ else illegal_instruction.write(SC_LOGIC_1);
+ }
+ else if(op == OP_J)
+ {
+ id_ctrl.write(n1);
+ }
+ else if(op == OP_JAL)
+ {
+ id_ctrl.write(n1);
+ id_pc_store.write(n1);
+ // add 8 in total
+ id_alu_ctrl.write(FUNC_ADDU);
+ id_sign_ctrl.write("10");
+ regdest.write("10");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_BEQ)
+ {
+ id_branch_select.write("010");
+ }
+ else if(op == OP_BNE)
+ {
+ id_branch_select.write("011");
+ }
+ else if(op == OP_BLEZ)
+ {
+ id_branch_select.write("101");
+ }
+ else if(op == OP_BGTZ)
+ {
+ id_branch_select.write("110");
+ }
+ else if(op == OP_ADDI)
+ {
+ id_alu_ctrl.write(FUNC_ADD);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_ADDIU)
+ {
+ id_alu_ctrl.write(FUNC_ADDU);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_regwrite.write(n1);
+#ifdef ONEHOT_DEBUG
+ inst_addiu.write(SC_LOGIC_1);
+#endif
+ }
+ else if(op == OP_SLTI)
+ {
+ id_alu_ctrl.write(FUNC_SLT);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_SLTIU)
+ {
+ id_alu_ctrl.write(FUNC_SLTU);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_ANDI)
+ {
+ id_alu_ctrl.write(FUNC_AND);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_extend_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_ORI)
+ {
+ id_alu_ctrl.write(FUNC_OR);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_extend_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_XORI)
+ {
+ id_alu_ctrl.write(FUNC_XOR);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_extend_ctrl.write("01");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_LUI)
+ {
+ id_alu_ctrl.write(FUNC_ADDU);
+ regdest.write("01");
+ id_sign_ctrl.write("01");
+ id_extend_ctrl.write("10");
+ id_regwrite.write(n1);
+ }
+ else if(op == OP_LB ||
+ op == OP_LH ||
+ op == OP_LWL ||
+ op == OP_LW ||
+ op == OP_LBU ||
+ op == OP_LHU ||
+ op == OP_LWR)
+ {
+ id_alu_ctrl.write(FUNC_ADDU);
+ id_regwrite.write(n1);
+ regdest.write("01");
+ id_datareq.write(n1);
+ id_memtoreg.write(n1);
+ id_sign_ctrl.write("01");
+ // Select bytes to be read!
+ if (op == OP_LB || op == OP_LBU)
+ byteselect = "01";
+ else if (op == OP_LH || op == OP_LHU)
+ byteselect = "10";
+ else
+ byteselect = "00";
+ // select to sign_extend or not
+ if ((op == OP_LBU) || (op == OP_LHU))
+ id_bssign = SC_LOGIC_1;
+#ifdef ONEHOT_DEBUG
+ inst_lw = SC_LOGIC_1;
+#endif
+ }
+ else if(op == OP_SB ||
+ op == OP_SH ||
+ op == OP_SWL ||
+ op == OP_SW ||
+ op == OP_SWR)
+ {
+ id_alu_ctrl.write(FUNC_ADDU);
+ id_datarw.write(n1);
+ id_datareq.write(n1);
+ id_memtoreg.write(n1);
+ id_sign_ctrl.write("01");
+ // Select bytes to be written
+ if (op == OP_SB)
+ byteselect = "01";
+ else if (op == OP_SH)
+ byteselect = "10";
+ else
+ byteselect = "00";
+#ifdef ONEHOT_DEBUG
+ inst_sw = SC_LOGIC_1;
+#endif
+ }
+#ifdef _INCLUDE_CP0_
+ else if(op == OP_CACHE)
+ {
+ cp0_inst.write(CP0_CACHE);
+ }
+#endif
+ /*!
+ In order to include co-processor you need to enable it in the config file.
+ */
+ else
+ if(op == OP_COPROC0)
+ {
+ if(cpo_co == SC_LOGIC_1)
+ {
+ if(func == FUNC_TLBR)
+ {
+ cp0_inst.write(CP0_TLBR);
+ }
+ else
+ if(func == FUNC_TLBWI)
+ {
+ cp0_inst.write(CP0_TLBWI);
+ }
+ else
+ if(func == FUNC_TLBWR)
+ {
+ cp0_inst.write(CP0_TLBWR);
+ }
+ else
+ if(func == FUNC_TLBP)
+ {
+ cp0_inst.write(CP0_TLBP);
+ }
+ else
+ if(func == FUNC_ERET)
+ {
+ cp0_inst.write(CP0_ERET);
+
+ }
+ else
+ if(func == FUNC_DERET)
+ {
+ cp0_inst.write(CP0_DERET);
+ }
+ else
+ if(func == FUNC_WAIT)
+ {
+ cp0_inst.write(CP0_WAIT);
+ // Do same actions as jalr...except jump!
+ id_ctrl.write(n0);
+ id_select_jump.write(n0);
+ id_pc_store.write(n1);
+ id_regwrite.write(n1);
+ id_alu_ctrl.write(FUNC_ADDU);
+ id_sign_ctrl.write("10");
+ #ifdef ONEHOT_DEBUG
+ inst_wait.write(SC_LOGIC_1);
+ #endif
+ }
+ }
+ else
+ {
+ if(lrs == RS_MFC0)
+ {
+ cp0_inst.write(CP0_MFC0);
+ cp0_reg_rw.write(SC_LOGIC_0);
+ id_mfc0.write(SC_LOGIC_1);
+
+ id_alu_ctrl.write(FUNC_ADDU);
+ regdest.write("01");
+ id_sign_ctrl.write("00");
+ id_regwrite.write(n1);
+#ifdef ONEHOT_DEBUG
+ inst_mfc0.write(SC_LOGIC_1);
+#endif
+ }
+ else
+ if(lrs == RS_MTC0)
+ {
+ cp0_inst.write(CP0_MTC0);
+ cp0_reg_rw.write(SC_LOGIC_1);
+ id_alu_ctrl.write(FUNC_ADDU);
+ cp0_reg_no.write(uird);
+ id_mfc0.write(SC_LOGIC_0);
+#ifdef ONEHOT_DEBUG
+ inst_mtc0.write(SC_LOGIC_1);
+#endif
+ }
+ }
+ //cout << "illegal instruction " << endl;
+ //illegal_instruction.write(SC_LOGIC_1);
+ }
+
+ else
+ {
+ illegal_instruction.write(SC_LOGIC_1);
+ cout << " illegal instruction " << endl;
+ //sc_stop();
+ }
+ id_byteselect = byteselect;
+}
Index: trunk/source/cpu/id_stage/regfile_high.h
===================================================================
--- trunk/source/cpu/id_stage/regfile_high.h (nonexistent)
+++ trunk/source/cpu/id_stage/regfile_high.h (revision 4)
@@ -0,0 +1,44 @@
+//
+// $Id: regfile_high.h,v 1.1 2006-01-25 17:00:04 igorloi Exp $
+//
+
+#ifndef _REGFILE_H
+#define _REGFILE_H
+
+#include
+#include "../../constants/config.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(regfile)
+{
+ // default input
+ sc_in in_clk;
+ sc_in reset;
+ sc_in > rs;
+ sc_in > rt;
+ sc_in wr;
+ sc_in > rd_in;
+ sc_in > rd;
+ sc_out > rs_out;
+ sc_out > rt_out;
+
+ sc_signal > r[32];
+
+ void storeregister();
+ void loadregister();
+
+ SC_CTOR(regfile)
+ {
+ SC_METHOD(storeregister);
+ sensitive_neg << in_clk;
+
+ SC_METHOD(loadregister);
+ sensitive << rs << rt << in_clk;
+ }
+};
+
+#endif
+
+
+
+
Index: trunk/source/cpu/id_stage/add_new_pc.cpp
===================================================================
--- trunk/source/cpu/id_stage/add_new_pc.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/add_new_pc.cpp (revision 4)
@@ -0,0 +1,6 @@
+#include "add_new_pc.h"
+
+void add_new_pc::do_add_new_pc()
+{
+ id_new_pc.write(((sc_int<32>) (if_id_next_pc.read())) + (((sc_int<32>) (id_sign_extend.read()) << 2)));
+}
Index: trunk/source/cpu/id_stage/control.h
===================================================================
--- trunk/source/cpu/id_stage/control.h (nonexistent)
+++ trunk/source/cpu/id_stage/control.h (revision 4)
@@ -0,0 +1,58 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+#include "../../constants/config.h"
+
+SC_MODULE(control)
+{
+ sc_in > if_id_inst;
+ sc_out > rs;
+ sc_out > rt;
+ sc_out > rd;
+ sc_out > id_alu_ctrl;
+
+ //*************************************************//
+ //******** segnali per il moltiplicatore **********//
+ sc_out > id_opcode;
+ sc_out > id_function;
+ //*************************************************//
+ //*************************************************//
+
+ sc_out > id_alu_sa;
+ sc_out id_ctrl;
+ sc_out > id_extend_ctrl;
+ sc_out > id_sign_ctrl;
+ sc_out > regdest;
+ sc_out id_select_jump;
+ sc_out id_pc_store;
+ sc_out > id_branch_select;
+ sc_out id_regwrite;
+ sc_out id_shamt_ctrl;
+ sc_out id_datarw;
+ sc_out id_datareq;
+ sc_out id_memtoreg;
+ sc_out > id_byteselect;
+
+ sc_out > cp0_inst;
+ sc_out > cp0_reg_no;
+ sc_out cp0_reg_rw;
+ sc_out id_mfc0;
+ sc_out illegal_instruction;
+ sc_out syscall_exception;
+#ifdef ONEHOT_DEBUG
+ sc_out inst_addiu;
+ sc_out inst_jalr;
+ sc_out inst_lw;
+ sc_out inst_mfc0;
+ sc_out inst_mtc0;
+ sc_out inst_nop;
+ sc_out inst_sw;
+ sc_out inst_wait;
+#endif
+ void do_control();
+
+ SC_CTOR(control)
+ {
+ SC_METHOD(do_control);
+ sensitive << if_id_inst;
+ }
+};
Index: trunk/source/cpu/id_stage/add_new_pc.h
===================================================================
--- trunk/source/cpu/id_stage/add_new_pc.h (nonexistent)
+++ trunk/source/cpu/id_stage/add_new_pc.h (revision 4)
@@ -0,0 +1,18 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(add_new_pc)
+{
+ sc_in > if_id_next_pc;
+ sc_in > id_sign_extend;
+ sc_out > id_new_pc;
+
+ void do_add_new_pc();
+
+ SC_CTOR(add_new_pc)
+ {
+ SC_METHOD(do_add_new_pc);
+ sensitive << if_id_next_pc << id_sign_extend;
+ }
+
+};
Index: trunk/source/cpu/id_stage/mux_writeregister.cpp
===================================================================
--- trunk/source/cpu/id_stage/mux_writeregister.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/mux_writeregister.cpp (revision 4)
@@ -0,0 +1,19 @@
+//Multiplexer per scittura registri
+// Stabilisce il registro di destinazione, che puo' essere
+// il registro rt, rd o il registro 31!
+
+#include "mux_writeregister.h"
+
+void mux_writeregister::do_mux_writeregister()
+{
+ if(regdest.read() == "00")
+ id_writeregister.write(rd);
+ else
+ if(regdest.read() == "01")
+ id_writeregister.write(rt);
+ else
+ if(regdest.read() == "10")
+ id_writeregister.write("11111");
+ else
+ id_writeregister.write("00000");
+}
Index: trunk/source/cpu/id_stage/reg_id.cpp
===================================================================
--- trunk/source/cpu/id_stage/reg_id.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/reg_id.cpp (revision 4)
@@ -0,0 +1,106 @@
+#include "reg_id.h"
+
+void reg_id::do_reg_id()
+{
+ if(reset.read() == true)
+ {
+ id_ex_alu1.write(WORD_ZERO);
+ id_ex_alu2.write(WORD_ZERO);
+ id_ex_datastore.write(WORD_ZERO);
+ id_ex_alu_ctrl.write("000000");
+ id_ex_alu_sa.write("00000");
+ id_ex_equal.write(SC_LOGIC_0);
+ id_ex_datareq.write(SC_LOGIC_0);
+ id_ex_datarw.write(SC_LOGIC_0);
+ id_ex_memtoreg.write(SC_LOGIC_0);
+ id_ex_writeregister_out.write("00000");
+ id_ex_regwrite_out.write(SC_LOGIC_0);
+ id_ex_writeregister.write("00000");
+ id_ex_regwrite.write(SC_LOGIC_0);
+ id_ex_byteselect.write("00");
+ id_ex_bssign.write(SC_LOGIC_0);
+ id_ex_inst.write(WORD_ZERO);
+
+ // EXCEPTION SIGNALS
+ id_ex_IBUS.write(SC_LOGIC_0);
+ id_ex_inst_addrl.write(SC_LOGIC_0);
+ id_ex_syscall_exception.write(SC_LOGIC_0);
+ id_ex_illegal_instruction.write(SC_LOGIC_0);
+ id_ex_instaddr.write(0);
+ id_ex_alu_opcode.write("000000");
+ id_ex_alu_function.write("000000");
+ }
+ else
+ if((datahold.read() == false) && (insthold.read() == false) && (enable_decode.read() == SC_LOGIC_1))
+ {
+ id_ex_alu1.write(id_alu1.read());
+ id_ex_alu2.write(id_alu2.read());
+ id_ex_datastore.write(id_mux_fw2.read());
+ id_ex_alu_ctrl.write(id_alu_ctrl.read());
+ id_ex_alu_sa.write(id_alu_sa.read());
+ id_ex_equal.write(id_equal.read());
+ id_ex_datareq.write(id_datareq.read());
+ id_ex_datarw.write(id_datarw.read());
+ id_ex_memtoreg.write(id_memtoreg.read());
+ id_ex_writeregister_out.write(id_writeregister.read());
+ id_ex_writeregister.write(id_writeregister.read());
+ id_ex_regwrite_out.write(id_regwrite.read());
+ id_ex_regwrite.write(id_regwrite.read());
+ id_ex_byteselect.write(id_byteselect.read());
+ id_ex_bssign.write(id_bssign.read());
+ id_ex_inst.write(if_id_inst.read());
+ // EXCEPTION SIGNALS
+ id_ex_IBUS.write(if_id_IBUS.read());
+ id_ex_inst_addrl.write(if_id_inst_addrl.read());
+ id_ex_syscall_exception.write(syscall_exception.read());
+ id_ex_illegal_instruction.write(illegal_instruction.read());
+ id_ex_instaddr.write(if_id_instaddr);
+
+ id_ex_alu_opcode.write(id_opcode.read());
+ id_ex_alu_function.write(id_function.read());
+ }
+ else
+ if((datahold.read() == false) && (insthold.read() == false) && (enable_decode.read() == SC_LOGIC_0))
+ {
+ id_ex_alu1.write(WORD_ZERO);
+ id_ex_alu2.write(WORD_ZERO);
+ id_ex_datastore.write(WORD_ZERO);
+ id_ex_alu_ctrl.write("000000");
+ id_ex_alu_sa.write("00000");
+ id_ex_equal.write(SC_LOGIC_0);
+ id_ex_datareq.write(SC_LOGIC_0);
+ id_ex_datarw.write(SC_LOGIC_0);
+ id_ex_memtoreg.write(SC_LOGIC_0);
+ id_ex_writeregister_out.write("00000");
+ id_ex_regwrite_out.write(SC_LOGIC_0);
+ id_ex_writeregister.write("00000");
+ id_ex_regwrite.write(SC_LOGIC_0);
+ id_ex_byteselect.write("00");
+ id_ex_bssign.write(SC_LOGIC_0);
+
+ id_ex_alu_opcode.write("000000");
+ id_ex_alu_function.write("000000");
+ id_ex_IBUS.write(if_id_IBUS.read());
+ id_ex_inst_addrl.write(if_id_inst_addrl.read());
+ id_ex_inst.write(if_id_inst.read());
+ id_ex_syscall_exception.write(syscall_exception.read());
+ id_ex_illegal_instruction.write(illegal_instruction.read());
+ id_ex_instaddr.write(if_id_instaddr);
+ }
+ else;
+
+
+
+
+}
+
+
+
+
+
+
+
+
+
+
+
Index: trunk/source/cpu/id_stage/mux_alu1.cpp
===================================================================
--- trunk/source/cpu/id_stage/mux_alu1.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/mux_alu1.cpp (revision 4)
@@ -0,0 +1,28 @@
+#include "mux_alu1.h"
+
+void mux_alu1::do_mux_alu1()
+{
+ sc_logic isc = id_shamt_ctrl;
+ sc_logic ips = id_pc_store;
+
+ sc_lv<2> select;
+ select[1] = isc;
+ select[0] = ips;
+ sc_lv<32> iii = if_id_inst;
+ sc_lv<32> v_id_alu1;
+
+
+ if (id_mfc0.read() == SC_LOGIC_1)
+ v_id_alu1 = cp0_reg_out;
+ else
+ if(select == "00")
+ v_id_alu1 = id_mux_fw1;
+ else
+ if(select == "01")
+ v_id_alu1 = if_id_next_pc;
+ else
+ v_id_alu1 = ("00000000000000000000000000",iii.range(11,6));
+
+
+ id_alu1 = v_id_alu1;
+}
Index: trunk/source/cpu/id_stage/mux_forward_select.cpp
===================================================================
--- trunk/source/cpu/id_stage/mux_forward_select.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/mux_forward_select.cpp (revision 4)
@@ -0,0 +1,17 @@
+#include "mux_forward_select.h"
+
+void mux_forward_select::do_mux_forward_select()
+{
+ sc_lv<2> ifc = id_fw_ctrl.read();
+
+ if( ifc == "00")
+ id_mux_fw.write(id_reg.read());
+ else
+ if( ifc == "01")
+ id_mux_fw.write(ex_id_forward.read());
+ else
+ if( ifc == "10")
+ id_mux_fw.write(m_id_forward.read());
+ else
+ id_mux_fw.write(wb_id_forward.read());
+}
Index: trunk/source/cpu/id_stage/mux_alu2.cpp
===================================================================
--- trunk/source/cpu/id_stage/mux_alu2.cpp (nonexistent)
+++ trunk/source/cpu/id_stage/mux_alu2.cpp (revision 4)
@@ -0,0 +1,18 @@
+#include "mux_alu2.h"
+
+void mux_alu2::do_mux_alu2()
+{
+ sc_lv<2> isc = id_sign_ctrl;
+ sc_lv<32> v_id_alu2;
+ if(isc == "00")
+ v_id_alu2 = id_mux_fw2;
+ else
+ if(isc == "01")
+ v_id_alu2 = id_sign_extend;
+ else
+ v_id_alu2 = (sc_int<32>) 4;
+
+ id_alu2 = v_id_alu2;
+ cp0_reg_rs = v_id_alu2;
+
+}
Index: trunk/source/cpu/id_stage/mux_writeregister.h
===================================================================
--- trunk/source/cpu/id_stage/mux_writeregister.h (nonexistent)
+++ trunk/source/cpu/id_stage/mux_writeregister.h (revision 4)
@@ -0,0 +1,18 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(mux_writeregister)
+{
+ sc_in > regdest;
+ sc_in > rt;
+ sc_in > rd;
+ sc_out > id_writeregister;
+
+ void do_mux_writeregister();
+
+ SC_CTOR(mux_writeregister)
+ {
+ SC_METHOD(do_mux_writeregister);
+ sensitive << rt << rd << regdest;
+ }
+};
Index: trunk/source/cpu/writeback_ctrl.cpp
===================================================================
--- trunk/source/cpu/writeback_ctrl.cpp (nonexistent)
+++ trunk/source/cpu/writeback_ctrl.cpp (revision 4)
@@ -0,0 +1,25 @@
+#include "writeback_ctrl.h"
+
+void writeback_ctrl::do_writeback_ctrl()
+{
+ if((m_wb_IBUS.read() == SC_LOGIC_1) ||
+ (m_wb_inst_addrl.read() == SC_LOGIC_1) ||
+ (m_wb_syscall_exception.read() == SC_LOGIC_1) ||
+ (m_wb_illegal_instruction.read() == SC_LOGIC_1) ||
+ (m_wb_ovf_excep.read() == SC_LOGIC_1) ||
+ (m_wb_DBUS.read() == SC_LOGIC_1) ||
+ (m_wb_data_addrl.read() == SC_LOGIC_1) ||
+ (m_wb_data_addrs.read() == SC_LOGIC_1) ||
+ (m_wb_interrupt_signal.read() == SC_LOGIC_1))
+ wb_exception.write(SC_LOGIC_1);
+ else
+ wb_exception.write(SC_LOGIC_0);
+
+
+
+
+
+
+
+
+}
Index: trunk/source/cpu/ex_stage.cpp
===================================================================
--- trunk/source/cpu/ex_stage.cpp (nonexistent)
+++ trunk/source/cpu/ex_stage.cpp (revision 4)
@@ -0,0 +1,6 @@
+//! EX Stage module
+//
+// $Id: ex_stage.cpp,v 1.00 2004/12/23 22:253:00 DIEE Cagliari
+//
+#include "ex_stage.h"
+
\ No newline at end of file
Index: trunk/source/cpu/if_stage/select_next_pc.cpp
===================================================================
--- trunk/source/cpu/if_stage/select_next_pc.cpp (nonexistent)
+++ trunk/source/cpu/if_stage/select_next_pc.cpp (revision 4)
@@ -0,0 +1,29 @@
+#include "select_next_pc.h"
+
+void select_next_pc::do_select_next_pc()
+{
+ #ifdef _DOBRANCH_
+
+ //sc_lv<32> temp = new_pc;
+
+ if (load_epc.read() == SC_LOGIC_1)
+ {
+ pc_in.write(new_pc.read());
+ }
+ else
+ {
+ if ((id_ctrl.read() == 0) && (id_branch.read() == 0))
+ pc_in.write(if_pc_add.read());
+ else
+ if ((id_ctrl.read() == 0) && (id_branch.read() == 1))
+ pc_in.write(id_new_pc.read());
+ else
+ if ((id_ctrl.read() == 1) && (id_branch.read() == 0))
+ pc_in.write(id_jmp_tar.read());
+ else // 1 && 1 - should never happen!
+ pc_in.write(id_jmp_tar.read());
+ }
+ #else
+ pc_in.write(if_pc_add.read());
+ #endif
+}
Index: trunk/source/cpu/if_stage/reg_if.h
===================================================================
--- trunk/source/cpu/if_stage/reg_if.h (nonexistent)
+++ trunk/source/cpu/if_stage/reg_if.h (revision 4)
@@ -0,0 +1,33 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(reg_if)
+{
+ sc_in in_clk;
+ sc_in reset;
+ sc_in insthold;
+ sc_in datahold;
+
+ sc_in > instdataread;
+ sc_in > if_pc_add;
+
+ sc_out > if_id_inst;
+ sc_out > if_id_next_pc;
+
+ sc_in IBUS;
+ sc_in inst_addrl;
+ sc_out if_id_IBUS;
+ sc_out if_id_inst_addrl;
+
+ sc_in > pc_if_instaddr;
+ sc_out > if_id_instaddr;
+ sc_in enable_fetch;
+
+ void do_reg_if();
+
+ SC_CTOR(reg_if)
+ {
+ SC_METHOD(do_reg_if);
+ sensitive_pos << in_clk;
+ }
+};
Index: trunk/source/cpu/if_stage/if_ctrl.cpp
===================================================================
--- trunk/source/cpu/if_stage/if_ctrl.cpp (nonexistent)
+++ trunk/source/cpu/if_stage/if_ctrl.cpp (revision 4)
@@ -0,0 +1,10 @@
+#include "if_ctrl.h"
+
+void if_ctrl::do_if_ctrl()
+{
+ if((IBUS.read() == SC_LOGIC_1) || (inst_addrl.read() == SC_LOGIC_1))
+ if_exception.write(SC_LOGIC_1);
+ else
+ if_exception.write(SC_LOGIC_0);
+
+}
Index: trunk/source/cpu/if_stage/select_next_pc.h
===================================================================
--- trunk/source/cpu/if_stage/select_next_pc.h (nonexistent)
+++ trunk/source/cpu/if_stage/select_next_pc.h (revision 4)
@@ -0,0 +1,27 @@
+#include "systemc.h"
+#define _DOBRANCH_ 1
+#include "../../constants/constants.h"
+#include "../../constants/config.h"
+
+SC_MODULE(select_next_pc)
+{
+ sc_in > new_pc;
+ sc_in load_epc;
+ sc_in id_ctrl;
+ sc_in id_branch;
+ sc_in > if_pc_add;
+ sc_in > id_new_pc;
+ sc_in > id_jmp_tar;
+
+ sc_out > pc_in;
+
+
+ void do_select_next_pc();
+
+ SC_CTOR(select_next_pc)
+ {
+ SC_METHOD(do_select_next_pc);
+ sensitive << if_pc_add << id_jmp_tar << id_new_pc << id_branch << id_ctrl << new_pc << load_epc;
+
+ }
+};
Index: trunk/source/cpu/if_stage/if_ctrl.h
===================================================================
--- trunk/source/cpu/if_stage/if_ctrl.h (nonexistent)
+++ trunk/source/cpu/if_stage/if_ctrl.h (revision 4)
@@ -0,0 +1,17 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(if_ctrl)
+{
+ sc_in IBUS;
+ sc_in inst_addrl;
+ sc_out if_exception;
+
+ void do_if_ctrl();
+
+ SC_CTOR(if_ctrl)
+ {
+ SC_METHOD(do_if_ctrl);
+ sensitive << IBUS << inst_addrl;
+ }
+};
Index: trunk/source/cpu/if_stage/add.cpp
===================================================================
--- trunk/source/cpu/if_stage/add.cpp (nonexistent)
+++ trunk/source/cpu/if_stage/add.cpp (revision 4)
@@ -0,0 +1,6 @@
+#include "add.h"
+
+void add::do_add()
+{
+ if_pc_add.write(((sc_uint<32>) pc_out.read()) + 4);
+}
Index: trunk/source/cpu/if_stage/reg_if.cpp
===================================================================
--- trunk/source/cpu/if_stage/reg_if.cpp (nonexistent)
+++ trunk/source/cpu/if_stage/reg_if.cpp (revision 4)
@@ -0,0 +1,42 @@
+#include "reg_if.h"
+/*
+enable_fetch: segnale posto ad 1 per il normale funzionamento della pipeline.
+Se si verifica un eccezione il coprocessore setta questo segnale a zero inibendo
+la scrittura sui registri di pipeline di questo stadio.
+Segnale per la gestione delle eccezioni IBUS e inst_addrl
+*/
+
+
+void reg_if::do_reg_if()
+{
+ if(reset.read() == true)
+ {
+ if_id_next_pc.write(0);
+ if_id_inst.write(0);
+ if_id_IBUS.write(SC_LOGIC_0);
+ if_id_inst_addrl.write(SC_LOGIC_0);
+ if_id_instaddr.write(0);
+ }
+ else
+ {
+ if((insthold.read() == false) && (datahold.read() == false) && (enable_fetch.read() == SC_LOGIC_1))
+ {
+ if_id_next_pc.write(if_pc_add.read());
+ if_id_inst.write(instdataread.read());
+ if_id_IBUS.write(IBUS.read());
+ if_id_inst_addrl.write(inst_addrl.read());
+ if_id_instaddr.write(pc_if_instaddr.read());
+ }
+ else
+ if((insthold.read() == false) && (datahold.read() == false) && (enable_fetch.read() == SC_LOGIC_0))
+ {
+ // QUESTA PaRTE �DA RIVEDERE!!!!
+ if_id_next_pc.write(0);
+ if_id_inst.write(0);
+ if_id_IBUS.write(IBUS.read());
+ if_id_inst_addrl.write(inst_addrl.read());
+ if_id_instaddr.write(pc_if_instaddr.read());
+ }
+ else;
+ }
+}
Index: trunk/source/cpu/if_stage/add.h
===================================================================
--- trunk/source/cpu/if_stage/add.h (nonexistent)
+++ trunk/source/cpu/if_stage/add.h (revision 4)
@@ -0,0 +1,15 @@
+#include "systemc.h"
+
+SC_MODULE(add)
+{
+ sc_out > if_pc_add;
+ sc_in > pc_out;
+
+ void do_add();
+
+ SC_CTOR(add)
+ {
+ SC_METHOD(do_add);
+ sensitive << pc_out;
+ }
+};
Index: trunk/source/cpu/mux_instaddr.cpp
===================================================================
--- trunk/source/cpu/mux_instaddr.cpp (nonexistent)
+++ trunk/source/cpu/mux_instaddr.cpp (revision 4)
@@ -0,0 +1,45 @@
+#include "mux_instaddr.h"
+
+void mux_instaddr::do_mux_instaddr()
+{
+ if(m_wb_interrupt_signal.read() == true)
+ {
+ sc_lv<16> temp_1;
+ sc_lv<5> temp_2;
+ sc_lv<6> temp_3;
+
+ temp_1 = (ex_mem_inst.read()).range(31,16); // upper 16 bit
+ temp_2 = (ex_mem_inst.read()).range(10,6); //
+ temp_3 = (ex_mem_inst.read()).range(5,0); //opcode
+
+ cout << " interrupt" << endl;
+ cout << " temp1 = " << temp_1 << endl;
+ cout << " temp2 = " << temp_2 << endl;
+ cout << " temp3 = " << temp_3 << endl;
+ cout << " inst = " << ex_mem_inst.read() << endl;
+
+ //||
+
+
+ if(((ex_m_instaddr.read() - m_wb_instaddr.read()) == 4))
+ {
+ if(((temp_1 == HALFWORD_ZERO) && (temp_2 == "00000") && ((temp_3 == "010010") || (temp_3 == "010000") )))
+ {
+ m_wb_instaddr_s.write(m_wb_instaddr.read() - 4 );
+ cout << " Istruz MFLO o MFHI durante l'interrupt" << endl;
+ }
+ else
+ {
+ m_wb_instaddr_s.write(m_wb_instaddr.read());
+ cout << " Indirizzi consecutivi delle ultime 2 istruz durante l'interrupt" << endl;
+ }
+ }
+ else
+ {
+ m_wb_instaddr_s.write(ex_m_instaddr.read());
+ cout << " indirizzi delle ultime due istruz non consecutivi durante l'interrupt" << endl;
+ }
+ }
+ else
+ m_wb_instaddr_s.write(m_wb_instaddr.read());
+}
Index: trunk/source/cpu/cp0/exception.cpp
===================================================================
--- trunk/source/cpu/cp0/exception.cpp (nonexistent)
+++ trunk/source/cpu/cp0/exception.cpp (revision 4)
@@ -0,0 +1,101 @@
+#include "exception.h"
+
+void exception::compute_cause()
+{
+ sc_lv<5> cause_5;
+ sc_lv<32> cause_32;
+
+ if(m_wb_inst_addrl.read() == SC_LOGIC_1)
+ cause_5 = "00100" ;
+ else
+ if(m_wb_IBUS.read() == SC_LOGIC_1)
+ cause_5 = "00110" ;
+ else
+ if(m_wb_DBUS.read() == SC_LOGIC_1)
+ cause_5 = "00111" ;
+ else
+ if(m_wb_data_addrl.read() == SC_LOGIC_1)
+ cause_5 = "00100" ;
+ else
+ if(m_wb_data_addrs.read() == SC_LOGIC_1)
+ cause_5 = "00101" ;
+ else
+ if(m_wb_syscall_exception.read() == SC_LOGIC_1)
+ cause_5 = "01000" ;
+ else
+ if(m_wb_illegal_instruction.read() == SC_LOGIC_1) // RI
+ cause_5 = "01010";
+ else
+ if(m_wb_ovf_excep.read() == SC_LOGIC_1)
+ cause_5 = "01100";
+ else
+ if(m_wb_interrupt_signal.read() == SC_LOGIC_1)
+ cause_5 = "00000";
+ else
+ cause_5 = "00000";
+
+ cause_32 = WORD_ZERO;
+ cause_32.range(6,2) = cause_5;
+ cause.write(cause_32);
+}
+
+void exception::check_for_exception()
+{
+ if((m_wb_IBUS.read() == SC_LOGIC_1) ||
+ (m_wb_inst_addrl.read() == SC_LOGIC_1) ||
+ (m_wb_syscall_exception.read() == SC_LOGIC_1) ||
+ (m_wb_illegal_instruction.read() == SC_LOGIC_1) ||
+ (m_wb_ovf_excep.read() == SC_LOGIC_1) ||
+ (m_wb_DBUS.read() == SC_LOGIC_1) ||
+ (m_wb_data_addrl.read() == SC_LOGIC_1) ||
+ (m_wb_data_addrs.read() == SC_LOGIC_1) ||
+ (m_wb_interrupt_signal.read() == SC_LOGIC_1))
+ check_excep.write(true);
+ else
+ check_excep.write(false);
+}
+
+void exception::check_for_interrupt()
+{
+ /*if(interrupt_signal.read() == SC_LOGIC_1)
+ interrupt_exception.write(SC_LOGIC_1);
+ else
+ interrupt_exception.write(SC_LOGIC_0);*/
+}
+
+void exception::check_for_Page_fault()
+{
+ if((cause.read()).range(6,2) == "00110" )
+ to_BadVAddr.write(m_wb_instaddr.read());
+ else
+ if((cause.read()).range(6,2) == "00111" )
+ to_BadVAddr.write(m_wb_dataaddr.read());
+ else
+ to_BadVAddr.write(0);
+}
+
+void exception::save_EPC()
+{
+ if(check_excep.read() == SC_LOGIC_1)
+ to_EPC.write(m_wb_instaddr.read());
+ else
+ to_EPC.write(0);
+}
+
+//sensitive << m_wb_interrupt_signal;
+//sensitive << cp0_inst << reset;
+void exception::handling_status_register()
+{
+ if(reset.read() == true )
+ to_SR = SC_LOGIC_0;
+ else
+ {
+ if(m_wb_interrupt_signal.read() == SC_LOGIC_1)
+ to_SR = SC_LOGIC_1;
+ else
+ if(cp0_inst.read() == CP0_ERET)
+ to_SR = SC_LOGIC_0;
+ else;
+ }
+
+}
Index: trunk/source/cpu/cp0/set_stop_pc.cpp
===================================================================
--- trunk/source/cpu/cp0/set_stop_pc.cpp (nonexistent)
+++ trunk/source/cpu/cp0/set_stop_pc.cpp (revision 4)
@@ -0,0 +1,96 @@
+#include "set_stop_pc.h"
+
+void set_stop_pc::update_state()
+{
+ if (reset.read() == true)
+ {
+ currentstate.write(IdLe);
+ }
+ else
+ {
+ currentstate.write(nextstate.read());
+ }
+}
+
+void set_stop_pc::do_set_stop_pc()
+{
+
+ // FSM
+ switch(currentstate)
+ {
+ case IdLe:
+ {
+
+ if( check_excep.read() == SC_LOGIC_1 )
+ {
+ cout << " EXCEPTION " << endl;
+ nextstate.write(STATE1);
+ new_pc.write(WORD_ZERO);
+ load_epc.write(SC_LOGIC_0);
+ insthold.write(true);
+ }
+ else
+ if(cp0_inst.read() == CP0_ERET)
+ {
+ cout <<" CPO ERET" << endl;
+ nextstate.write(STATE3);
+ new_pc.write(WORD_ZERO);
+ load_epc.write(SC_LOGIC_0);
+ insthold.write(true);
+ }
+ else
+ {
+ nextstate.write(IdLe);
+ new_pc.write(WORD_ZERO);
+ load_epc.write(SC_LOGIC_0);
+ insthold.write(x_insthold.read());
+ }
+ }
+ break;
+
+ case STATE1:
+ {
+ insthold.write(x_insthold.read());
+ new_pc.write(0x00000008);
+ load_epc.write(SC_LOGIC_1);
+ nextstate.write(STATE2);
+ }
+ break;
+
+ case STATE2:
+ {
+ nextstate.write(IdLe);
+ insthold.write(x_insthold.read());
+ new_pc.write(0x00000008);
+ load_epc.write(SC_LOGIC_1);
+ }
+ break;
+
+ case STATE3:
+ {
+ insthold.write(x_insthold.read());
+ new_pc.write(EPC_FOR_RFE.read());
+ load_epc.write(SC_LOGIC_1);
+ nextstate.write(IdLe);
+ }
+ break;
+
+ case STATE4:
+ {
+ nextstate.write(IdLe);
+ insthold.write(x_insthold.read());
+ new_pc.write(EPC_FOR_RFE.read());
+ load_epc.write(SC_LOGIC_1);
+ }
+ break;
+
+ default:
+ {
+ nextstate.write(IdLe);
+ new_pc.write(WORD_ZERO);
+ load_epc.write(SC_LOGIC_0);
+ insthold.write(x_insthold.read());
+ }
+ break;
+ }
+}
Index: trunk/source/cpu/cp0/exception.h
===================================================================
--- trunk/source/cpu/cp0/exception.h (nonexistent)
+++ trunk/source/cpu/cp0/exception.h (revision 4)
@@ -0,0 +1,74 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(exception)
+{
+ sc_in in_clk;
+ sc_in reset;
+
+ sc_in m_wb_IBUS;
+ sc_in m_wb_inst_addrl;
+ sc_in m_wb_syscall_exception;
+ sc_in m_wb_illegal_instruction;
+ sc_in m_wb_ovf_excep;
+ sc_in m_wb_DBUS;
+ sc_in m_wb_data_addrl;
+ sc_in m_wb_data_addrs;
+ sc_in > m_wb_dataaddr;
+ sc_in > m_wb_instaddr;
+ sc_in > cp0_inst;
+
+ //**************INTERRUPT****************
+ sc_in m_wb_interrupt_signal;
+ //sc_out interrupt_exception;
+ //sc_in > ex_m_instaddr;
+ sc_signal to_SR;
+ //***************************************
+
+ sc_out > cause;
+ sc_out check_excep;
+ sc_out > to_EPC;
+ sc_out > to_BadVAddr;
+
+
+
+ void compute_cause();
+
+ void check_for_exception();
+
+ void check_for_interrupt();
+
+ void check_for_Page_fault();
+
+ void save_EPC();
+
+ void handling_status_register();
+
+ SC_CTOR(exception)
+ {
+ SC_METHOD(compute_cause);
+ sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception;
+ sensitive << m_wb_illegal_instruction << m_wb_ovf_excep;
+ sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs;
+ sensitive << m_wb_interrupt_signal;
+
+ SC_METHOD(check_for_exception);
+ sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception;
+ sensitive << m_wb_illegal_instruction << m_wb_ovf_excep;
+ sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs << m_wb_interrupt_signal;
+
+ SC_METHOD(check_for_interrupt);
+ //sensitive << interrupt_signal;
+
+ SC_METHOD(check_for_Page_fault);
+ sensitive << cause << m_wb_instaddr << m_wb_dataaddr;
+
+ SC_METHOD(save_EPC);
+ sensitive << check_excep;
+ sensitive << m_wb_instaddr;
+
+ SC_METHOD(handling_status_register);
+ sensitive << m_wb_interrupt_signal;
+ sensitive << cp0_inst << reset;
+ }
+};
Index: trunk/source/cpu/cp0/cp0_register.cpp
===================================================================
--- trunk/source/cpu/cp0/cp0_register.cpp (nonexistent)
+++ trunk/source/cpu/cp0/cp0_register.cpp (revision 4)
@@ -0,0 +1,110 @@
+#include "cp0_register.h"
+
+ //! Read registers
+/*!
+ sensitive << all registers, reg_wr and reg_no
+ */
+void cp0_register::cp0_register_read()
+{
+ EPC_FOR_RFE.write( (sc_uint<32>) cp0regs[14]);
+ reg_out = cp0regs[reg_no.read()];
+
+}
+
+//! Write registers
+/*!
+ sensitive_neg << in_clk
+ */
+void cp0_register::cp0_register_write()
+{
+ if (reset.read() == true)
+ {
+ cp0regs[0] = WORD_ZERO;
+ cp0regs[1] = WORD_ZERO;
+ cp0regs[2] = WORD_ZERO;
+ cp0regs[3] = WORD_ZERO;
+ cp0regs[4] = WORD_ZERO;
+ cp0regs[5] = WORD_ZERO;
+ cp0regs[6] = WORD_ZERO;
+ cp0regs[7] = WORD_ZERO;
+ cp0regs[8] = WORD_ZERO;
+ cp0regs[9] = WORD_ZERO;
+ cp0regs[0] = WORD_ZERO;
+ cp0regs[11] = WORD_ZERO;
+ cp0regs[12] = WORD_ZERO;
+ cp0regs[13] = WORD_ZERO;
+ cp0regs[14] = WORD_ZERO;
+ cp0regs[15] = WORD_ZERO;
+ cp0regs[16] = WORD_ZERO;
+ cp0regs[17] = WORD_ZERO;
+ cp0regs[18] = WORD_ZERO;
+ cp0regs[19] = WORD_ZERO;
+ cp0regs[20] = WORD_ZERO;
+ cp0regs[21] = WORD_ZERO;
+ cp0regs[22] = WORD_ZERO;
+ cp0regs[23] = WORD_ZERO;
+ cp0regs[24] = WORD_ZERO;
+ cp0regs[25] = WORD_ZERO;
+ cp0regs[26] = WORD_ZERO;
+ cp0regs[27] = WORD_ZERO;
+ cp0regs[28] = WORD_ZERO;
+ cp0regs[29] = WORD_ZERO;
+ cp0regs[30] = WORD_ZERO;
+ cp0regs[31] = WORD_ZERO;
+ }
+ else
+ if(check_excep.read() == SC_LOGIC_1)
+ {
+ cp0regs[13] = cause.read();
+ cp0regs[14] = (sc_lv<32>) to_EPC.read();
+ cp0regs[8] = (sc_lv<32>) to_BadVAddr.read();
+ cp0regs[12] = Temp_Status_Register.read();
+ }
+ else
+ if((cp0_inst.read() == CP0_ERET) && (insthold.read()==true))
+ cp0regs[12] = Temp_Status_Register.read();
+ else
+ if ((reg_rw.read() == SC_LOGIC_1))
+ {
+ cp0regs[reg_no.read()] = reg_rs.read();
+ }
+}
+
+void cp0_register::cp0_status_register()
+{
+
+ sc_lv<6> temp;
+ sc_lv<32> temp_32;
+
+ if((check_excep.read() == SC_LOGIC_1))
+ {
+ temp_32 = (cp0regs[12]).read();
+
+ temp.range(5,2) = temp_32.range(3,0);
+ temp.range(1,0) = "00";
+
+ temp_32.range(5,0) = temp;
+
+ Temp_Status_Register.write(temp_32);
+ }
+ else
+ {
+ temp_32 = (cp0regs[12]).read();
+
+ temp.range(3,0) = temp_32.range(5,2);
+ temp.range(5,4) = temp_32.range(5,4);
+
+ temp_32.range(5,0) = temp;
+
+ Temp_Status_Register.write(temp_32);
+ }
+}
+
+void cp0_register::enable_interrupt_and_OS()
+{
+ enable_interrupt.write(((cp0regs[12]).read())[0]);
+ enable_kernel_mode.write(((cp0regs[12]).read())[1]);
+
+
+}
+
Index: trunk/source/cpu/cp0/set_stop_pc.h
===================================================================
--- trunk/source/cpu/cp0/set_stop_pc.h (nonexistent)
+++ trunk/source/cpu/cp0/set_stop_pc.h (revision 4)
@@ -0,0 +1,39 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+enum State {IdLe, STATE1, STATE2, STATE3, STATE4};
+SC_MODULE(set_stop_pc)
+{
+ sc_in in_clk; // clock
+ sc_in reset; // reset
+
+ sc_in x_insthold; // freeze signal from InstMemory
+ sc_out insthold; // output freeze signal
+
+ sc_in > pc_in; // program counter from PC_STAGE
+ sc_in > cp0_inst; // coprocessor CP0 instruction
+ sc_out > new_pc; // next PC when exception occur!
+ sc_out load_epc; // signal that tell to PC STAGE to load Exception_PC
+ sc_in check_excep; // signal that tell if there is an exception
+ sc_in > EPC_FOR_RFE; // PC that must be loaded when exception routine finish!
+
+ sc_signal currentstate , nextstate; // State from Finite State Machine
+
+ void update_state();
+ void do_set_stop_pc();
+
+ SC_CTOR(set_stop_pc)
+ {
+ SC_METHOD(update_state);
+ sensitive_pos << in_clk;
+
+ SC_METHOD(do_set_stop_pc);
+ sensitive << reset;
+ sensitive << x_insthold;
+ sensitive << check_excep;
+ sensitive << currentstate;
+ sensitive << cp0_inst;
+ sensitive << EPC_FOR_RFE;
+
+ }
+};
Index: trunk/source/cpu/cp0/cp0_register.h
===================================================================
--- trunk/source/cpu/cp0/cp0_register.h (nonexistent)
+++ trunk/source/cpu/cp0/cp0_register.h (revision 4)
@@ -0,0 +1,61 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+
+SC_MODULE(cp0_register)
+{
+ sc_in in_clk;
+ sc_in reset;
+ sc_in insthold;
+
+ sc_signal > cp0regs[32];
+
+ sc_in > reg_no;
+ sc_in reg_rw;
+ sc_in > reg_rs;
+ sc_out > reg_out;
+
+ sc_in check_excep;
+ //sc_in interrupt_signal;
+ sc_in > cause;
+ sc_in > to_BadVAddr;
+ sc_in > to_EPC;
+
+ sc_in > cp0_inst;
+
+ sc_out > EPC_FOR_RFE;
+ sc_signal > Temp_Status_Register;
+
+ sc_out enable_interrupt;
+ sc_out enable_kernel_mode;
+
+ void cp0_register_read();
+ void cp0_register_write();
+ void cp0_status_register();
+ void enable_interrupt_and_OS();
+
+ SC_CTOR(cp0_register)
+ {
+ SC_METHOD(cp0_register_read);
+ sensitive << reg_no << cp0regs[0] << cp0regs[1] << cp0regs[2];
+ sensitive << cp0regs[3] << cp0regs[4] << cp0regs[5] << cp0regs[6] << cp0regs[7];
+ sensitive << cp0regs[8] << cp0regs[9] << cp0regs[10] << cp0regs[11] << cp0regs[12];
+ sensitive << cp0regs[13] << cp0regs[14] << cp0regs[15] << cp0regs[16] << cp0regs[17];
+ sensitive << cp0regs[18] << cp0regs[19] << cp0regs[20] << cp0regs[21] << cp0regs[22];
+ sensitive << cp0regs[23] << cp0regs[24] << cp0regs[25] << cp0regs[26] << cp0regs[27];
+ sensitive << cp0regs[28] << cp0regs[29] << cp0regs[30] << cp0regs[31];
+
+ SC_METHOD(cp0_register_write);
+ sensitive_neg << in_clk;
+ //sensitive << cause << to_EPC << to_BadVAddr;
+ //sensitive << check_excep;
+
+ SC_METHOD(cp0_status_register);
+ sensitive << check_excep << cp0_inst << cp0regs[12];
+
+ SC_METHOD(enable_interrupt_and_OS);
+ sensitive << cp0regs[12];
+ }
+
+
+
+};
Index: trunk/source/cpu/mem_stage.cpp
===================================================================
--- trunk/source/cpu/mem_stage.cpp (nonexistent)
+++ trunk/source/cpu/mem_stage.cpp (revision 4)
@@ -0,0 +1,5 @@
+//! MEM Stage module
+//
+// $Id: mem_stage.cpp,v 1.1 2006-01-25 17:00:01 igorloi Exp $
+//
+#include "mem_stage.h"
Index: trunk/source/cpu/writeback_ctrl.h
===================================================================
--- trunk/source/cpu/writeback_ctrl.h (nonexistent)
+++ trunk/source/cpu/writeback_ctrl.h (revision 4)
@@ -0,0 +1,28 @@
+#include "systemc.h"
+#include "../constants/constants.h"
+
+SC_MODULE(writeback_ctrl)
+{
+ sc_in m_wb_IBUS;
+ sc_in m_wb_inst_addrl;
+ sc_in m_wb_syscall_exception;
+ sc_in m_wb_illegal_instruction;
+ sc_in m_wb_ovf_excep;
+ sc_in m_wb_DBUS;
+ sc_in m_wb_data_addrl;
+ sc_in m_wb_data_addrs;
+ sc_in m_wb_interrupt_signal;
+
+
+ sc_out wb_exception;
+
+ void do_writeback_ctrl();
+
+ SC_CTOR(writeback_ctrl)
+ {
+ SC_METHOD(do_writeback_ctrl);
+ sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception;
+ sensitive << m_wb_illegal_instruction << m_wb_ovf_excep;
+ sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs << m_wb_interrupt_signal;
+ }
+};
Index: trunk/source/cpu/pc_stage/reg_pc.cpp
===================================================================
--- trunk/source/cpu/pc_stage/reg_pc.cpp (nonexistent)
+++ trunk/source/cpu/pc_stage/reg_pc.cpp (revision 4)
@@ -0,0 +1,37 @@
+#include "reg_pc.h"
+
+void reg_pc::do_reg_pc()
+{
+ sc_lv<32> pc;
+
+ instdatawrite = WORD_ZERO;
+
+ if(reset.read() == true)
+ {
+ instreq.write(SC_LOGIC_1);
+ instrw.write(SC_LOGIC_0);
+
+ instaddr = pc = PC_START;
+ pc_out = pc = PC_START;
+ }
+ else
+ {
+ if((datahold.read() == false) && (insthold.read() == false) && (enable_pc.read() == SC_LOGIC_1))
+ {
+ instreq.write(SC_LOGIC_1);
+ instrw.write(SC_LOGIC_0);
+ pc = pc_in.read();
+ instaddr.write(pc);
+ pc_out.write(pc_in.read());
+ }
+ else
+ if((datahold.read() == false) && (insthold.read() == false) && (enable_pc.read() == SC_LOGIC_0))
+ {
+ instreq.write(SC_LOGIC_0);
+ instrw.write(SC_LOGIC_0);
+
+ instaddr = pc = PC_START;
+ pc_out = pc = PC_START;
+ }
+ }
+}
Index: trunk/source/cpu/pc_stage/reg_pc.h
===================================================================
--- trunk/source/cpu/pc_stage/reg_pc.h (nonexistent)
+++ trunk/source/cpu/pc_stage/reg_pc.h (revision 4)
@@ -0,0 +1,32 @@
+#include "systemc.h"
+#include "../../constants/constants.h"
+#include "../../constants/config.h"
+
+SC_MODULE(reg_pc)
+{
+ sc_in in_clk;
+ sc_in reset;
+
+ sc_in insthold;
+ sc_in datahold;
+
+ sc_in enable_pc;
+
+ sc_in > pc_in;
+ sc_out > pc_out;
+
+ sc_out > instaddr;
+ sc_out