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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/sdhc-sc-core/trunk/.gitignore
2,4 → 2,4
*.aux
*.dvi
*.backup
*work*
sim/work/*
/sdhc-sc-core/trunk/src/crc-ea.vhdl
1,9 → 1,14
-------------------------------------------------
-- CRC7
-- author: Rainer Kastl
--
-- CRC implementation with the common polynomial
-- x^7 + x^3 + 1
-- CRC implementation with generic polynoms.
--
-- While the data is shifted in bit by bit iDataIn
-- has to be '1'. The CRC can be shifted out by
-- setting iDataIn to '0'.
-- If the CRC should be checked it has to be shifted
-- in directly after the data. If the remainder is 0,
-- the CRC is correct.
-------------------------------------------------
 
library ieee;
12,24 → 17,34
 
entity crc is
generic (
gPolynom : std_ulogic_vector := crc7 -- x^7 + x^3 + 1
gPolynom : std_ulogic_vector := crc7
);
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iEn : in std_ulogic;
iClear : in std_ulogic;
iData : in std_ulogic;
oCRC : out std_ulogic_vector(gPolynom'high - 1 downto gPolynom'low)
inResetAsync : in std_ulogic; -- Asynchronous low active reset
iClear : in std_ulogic; -- Synchronous reset for the registers
iDataIn : in std_ulogic; -- Signal that currently data is shifted in.
-- Otherwise the current remainder is shifted out.
iData : in std_ulogic; -- Data input
oSerial : out std_ulogic; -- Serial data output
oParallel : out std_ulogic_vector(gPolynom'high - 1 downto gPolynom'low)
-- parallel data output
);
begin
-- check the used polynom
assert gPolynom(gPolynom'high) = '1' report
"Invalid polynom: no '1' at the highest position." severity failure;
assert gPolynom(gPolynom'low) = '1' report
"Invalid polynom: no '1' at the lowest position." severity failure;
end crc;
 
architecture rtl of crc is
 
signal regs : std_ulogic_vector(oCRC'range);
signal regs : std_ulogic_vector(oParallel'range);
 
begin
 
-- shift registers
crc : process (iClk, inResetAsync) is
variable input : std_ulogic;
begin
36,8 → 51,11
if (inResetAsync = '0') then
regs <= (others => '0');
elsif (rising_edge(iClk)) then
if (iEn = '1') then
if (iClear = '0') then
if (iClear = '1') then
regs <= (others => '0');
elsif (iClear = '0') then
if (iDataIn = '1') then
-- calculate CRC
input := iData xor regs(regs'high);
 
regs(0) <= input;
50,12 → 68,17
end if;
end loop;
else
regs <= (others => '0');
-- shift data out
regs(0) <= '0';
for idx in 1 to regs'high loop
regs(idx) <= regs(idx-1);
end loop;
end if;
end if;
end if;
end process crc;
 
oCRC <= regs;
oParallel <= regs;
oSerial <= regs(regs'high);
 
end architecture rtl;
/sdhc-sc-core/trunk/src/tb-crc-ea.vhdl
17,70 → 17,66
signal CRC_7 : std_ulogic_vector(6 downto 0);
signal CRC_16 : std_ulogic_vector(15 downto 0);
signal DataToCrc_7, DataToCrc_16 : std_ulogic;
signal CRCEnable_7,CRCClear_7 : std_ulogic;
signal CRCEnable_16,CRCClear_16 : std_ulogic;
signal CRCDataIn_7,CRCClear_7 : std_ulogic;
signal CRCDataIn_16,CRCClear_16 : std_ulogic;
signal SerialCRC_7, SerialCRC_16 : std_ulogic;
 
signal EndOfSim : boolean := false;
 
procedure ApplyData (
-- setup data in front of clk -> use the negative clock edge
procedure Test (
Data : in std_ulogic_vector;
signal CRCEnable : out std_ulogic;
Valid : in std_ulogic_vector;
signal CRC : in std_ulogic_vector;
signal SerialCRC : in std_ulogic;
signal CRCDataIn : out std_ulogic;
signal DataToCrc : out std_ulogic;
signal CRCClear : out std_ulogic) is
 
variable counter : natural := 0;
 
begin
wait until Clk = '1';
wait until Clk = '0';
CRCClear <= '0';
CRCEnable <= '1';
CRCDataIn <= '1';
 
while (counter <= Data'high) loop
DataToCrc <= Data(counter);
counter := counter + 1;
wait until Clk = '1';
wait until Clk = '0';
end loop;
 
DataToCrc <= '0';
wait until Clk = '1';
CRCDataIn <= '0';
 
end procedure ApplyData;
assert (Valid = CRC) report "CRC error." severity error;
 
procedure ClearData (
signal CRCClear : out std_ulogic;
signal CRCEnable : out std_ulogic) is
begin
counter := 0;
while (counter <= CRC'high) loop
assert (Valid(counter) = SerialCRC) report "Serial CRC error"
severity error;
counter := counter + 1;
wait until clk = '0';
end loop;
 
CRCClear <= '1';
wait until Clk = '1';
wait until Clk = '0';
 
CRCEnable <= '0';
 
CRCClear <= '0';
end procedure;
 
procedure Test (
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector;
signal CRC : in std_ulogic_vector;
signal CRCEnable : out std_ulogic;
signal DataToCrc : out std_ulogic;
signal CRCClear : out std_ulogic) is
begin
ApplyData(Data, CRCEnable, DataToCrc, CRCClear);
assert (Valid = CRC) report "CRC error." severity
error;
ClearData(CRCClear, CRCEnable);
end procedure;
 
begin
 
Clk <= not Clk after 10 ns when EndOfSim = false else '0';
nResetAsync <= '1' after 100 ns;
 
generate_and_test : process is
generate_and_test7 : process is
procedure Test7(
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector) is
begin
Test(Data, Valid, CRC_7, CRCEnable_7, DataToCrc_7, CRCClear_7);
Test(Data, Valid, CRC_7, SerialCRC_7, CRCDataIn_7, DataToCrc_7,
CRCClear_7);
end procedure;
 
procedure Test16(
87,16 → 83,23
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector) is
begin
Test(Data, Valid, CRC_16, CRCEnable_16, DataToCrc_16, CRCClear_16);
Test(Data, Valid, CRC_16, SerialCRC_16, CRCDataIn_16, DataToCrc_16,
CRCClear_16);
end procedure;
 
variable data : std_ulogic_vector(0 to (512*8)-1) := (others => '1');
variable DataWithCRC : std_ulogic_vector(0 to (516*8)-1) := (
512*8 to 516*8-1 => std_ulogic_vector(X"7FA1"),
others => '1');
begin
wait until (nResetAsync = '1');
 
Test7("0100000000000000000000000000000000000000","1001010");
Test7("01000000000000000000000000000000000000001001010","0000000");
Test7("0101000100000000000000000000000000000000","0101010");
Test7("01010001000000000000000000000000000000000101010","0000000");
Test7("0001000100000000000000000000100100000000","0110011");
Test7("00010001000000000000000000001001000000000110011","0000000");
Test16(data, X"7FA1");
 
EndOfSim <= true;
106,18 → 109,20
duv7: entity work.crc
port map (iClk => Clk,
inResetAsync => nResetAsync,
iEn => CRCEnable_7,
iDataIn => CRCDataIn_7,
iClear => CRCClear_7,
iData => DataToCrc_7,
oCRC => CRC_7);
oParallel => CRC_7,
oSerial => SerialCRC_7);
 
duv16: entity work.crc
generic map (gPolynom => crc16)
port map (iClk => Clk,
inResetAsync => nResetAsync,
iEn => CRCEnable_16,
iDataIn => CRCDataIn_16,
iClear => CRCClear_16,
iData => DataToCrc_16,
oCRC => CRC_16);
oParallel => CRC_16,
oSerial => SerialCRC_16);
 
end architecture bhv;

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