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/trunk/VHDL/TG68_fast.vhd
21,12 → 21,16
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- Add MOVEP INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
236,6 → 240,11
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
283,7 → 292,7
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trap : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
307,8 → 316,7
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal check_movep : std_logic;
signal check_chk : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
383,54 → 391,57
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap,
memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
--PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap,
-- memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
-- trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
-- data_write_tmp, addsub_q, set_vectoraddr)
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
-- IF rising_edge(clk) THEN
-- IF clkena='1' THEN
-- trap_vector <= "000000000000000000000000011"&rIPL_nr&"00";
trap_vector <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
-- END IF;
ELSIF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
-- END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
ELSIF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
-- END IF;
ELSIF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
-- END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
ELSIF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
-- END IF;
ELSIF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
-- END IF;
ELSIF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
-- ELSIF trap_interrupt='1' THEN
ELSE
trap_vector(7 downto 2) <= "011"&rIPL_nr;
-- END IF;
-- END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
 
memaddr_a(3 downto 0) <= "0000";
613,6 → 624,8
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
645,7 → 658,7
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' THEN
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
679,6 → 692,8
directSR <= set_directSR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
691,41 → 706,38
END IF;
IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
-- IF stop='0' THEN
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
trap_interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
execOPC <= '1';
fetchOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
-- END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
735,6 → 747,7
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
752,6 → 765,8
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
815,9 → 830,12
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)&registerin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
ELSIF movem_busy='1' AND datatype="10" AND movem_presub='1' THEN
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trap AND decodeOPC)='1' OR movem_busy='1'THEN
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
829,11 → 847,11
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trap, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trap;
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
923,7 → 941,7
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" THEN
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
1105,7 → 1123,7
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trap='0' THEN
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
1141,7 → 1159,7
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trap, trapd, interrupt, trap_interrupt,
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec)
BEGIN
1224,7 → 1242,7
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trap <='0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
1240,9 → 1258,11
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
 
check_movep <= '0';
check_chk <= '0';
trap_chk <= '0';
 
------------------------------------------------------------------------------
--Sourcepass
1346,10 → 1366,32
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
--hier muss noch MOVEP rein
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
trap_illegal <= '1';
trap <= '1';
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
microstep <='1';
micronext <="01010110";
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
1394,7 → 1436,7
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trap='0' THEN
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
1401,7 → 1443,7
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
1557,12 → 1599,35
END IF;
ELSE
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
END IF;
ELSE --chk
trap_illegal <= '1';
trap <= '1';
check_chk <= '1';
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
1595,7 → 1660,7
WHEN "001"=>
IF opcode(7downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
1646,7 → 1711,7
END IF;
ELSE
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
1735,7 → 1800,7
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
1832,7 → 1897,7
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trap <= '1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
1879,7 → 1944,7
END IF;
ELSE
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
1892,13 → 1957,13
END IF;
ELSE
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
1906,7 → 1971,7
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
1929,7 → 1994,7
END IF;
ELSE
trap_priv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
1946,12 → 2011,12
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trap <= '1';
trapmake <= '1';
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
END CASE;
END IF;
END CASE;
2055,7 → 2120,7
END IF;
ELSE
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
2110,7 → 2175,7
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trap <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
2201,7 → 2266,7
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trap <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
2389,7 → 2454,7
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trap <= '1';
trapmake <= '1';
 
END CASE;
2401,7 → 2466,7
--PROCESS (microaddr)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
 
 
IF trapd='0' THEN
writePC <= '1';
microset <= '1';
2408,7 → 2473,7
END IF;
END IF;
IF trap='1' AND trapd='0' THEN
IF trapmake='1' AND trapd='0' THEN
microstep <= '1';
micronext <= "01010000";
presub <= '1';
2431,7 → 2496,7
prefix <= '1';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trap;
trapd <= trapmake;
prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC);
IF prefix='1' AND ea_build='0' AND microset='0' THEN
microaddr <= microaddr + micronext;
2620,9 → 2685,51
WHEN "01010010" => -- TRAP
datatype <= "10";
WHEN "01010110" => -- MOVEP d(An)
microstep <='1';
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
WHEN "01010111" =>
microstep <='1';
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
WHEN "01011000" =>
IF opcode(6)='1' THEN
microstep <='1';
set_movepw <= '1';
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN "01011001" =>
microstep <='1';
 
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
WHEN "01011010" =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
 
 
WHEN "01100000" => -- init SP
microstep <='1';
longreaddirect <= '1';
/trunk/VHDL/TG68.vhd
21,12 → 21,15
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- Add MOVEP INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
99,7 → 102,7
 
TG68_fast_inst: TG68_fast
PORT MAP (
clk => not clk, -- : in std_logic;
clk => not clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);

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