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/tiny_aes/trunk/testbench/test_final_round.v File deleted
/tiny_aes/trunk/testbench/test_one_round.v File deleted
/tiny_aes/trunk/testbench/test_one_round_128.v
0,0 → 1,77
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
 
`timescale 1ns / 1ps
 
module test_one_round;
 
// Inputs
reg clk;
reg [127:0] state_in;
reg [127:0] key_in;
reg [7:0] rcon;
 
// Outputs
wire [127:0] state_out;
wire [127:0] key_out;
wire [31:0] k0, k1, k2, k3, s0, s1, s2, s3;
 
// Instantiate the Unit Under Test (UUT)
one_round_128 uut (
.clk(clk),
.state_in(state_in),
.key_in(key_in),
.state_out(state_out),
.key_out(key_out),
.rcon(rcon)
);
 
assign {k0, k1, k2, k3} = key_out;
assign {s0, s1, s2, s3} = state_out;
 
initial begin
clk = 0;
state_in = 0;
key_in = 0;
rcon = 0;
 
#100;
@ (negedge clk);
state_in = {32'h19_3d_e3_be, 32'ha0_f4_e2_2b, 32'h9a_c6_8d_2a, 32'he9_f8_48_08};
key_in = {32'h2b_7e_15_16, 32'h28_ae_d2_a6, 32'hab_f7_15_88, 32'h09_cf_4f_3c};
rcon = 1;
#10;
state_in = 0;
key_in = 0;
rcon = 0;
#10;
if(k0 != 32'ha0_fa_fe_17) begin $display("E"); $finish; end
if(k1 != 32'h88_54_2c_b1) begin $display("E"); $finish; end
if(k2 != 32'h23_a3_39_39) begin $display("E"); $finish; end
if(k3 != 32'h2a_6c_76_05) begin $display("E"); $finish; end
if(s0 != 32'ha4_9c_7f_f2) begin $display("E"); $finish; end
if(s1 != 32'h68_9f_35_2b) begin $display("E"); $finish; end
if(s2 != 32'h6b_5b_ea_43) begin $display("E"); $finish; end
if(s3 != 32'h02_6a_50_49) begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
 
/tiny_aes/trunk/testbench/test_final_round_128.v
0,0 → 1,70
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
 
`timescale 1ns / 1ps
 
module test_final_round_128;
 
// Inputs
reg clk;
reg [127:0] state_in;
reg [127:0] key_in;
reg [7:0] rcon;
 
// Outputs
wire [127:0] state_out;
wire [31:0] s0, s1, s2, s3;
 
// Instantiate the Unit Under Test (UUT)
final_round_128 uut (
.clk(clk),
.state_in(state_in),
.key_in(key_in),
.state_out(state_out),
.rcon(rcon)
);
 
assign {s0, s1, s2, s3} = state_out;
 
initial begin
clk = 0;
state_in = 0;
key_in = 0;
rcon = 0;
 
#100;
@ (negedge clk);
state_in = {32'heb_40_f2_1e, 32'h59_2e_38_84, 32'h8b_a1_13_e7, 32'h1b_c3_42_d2};
key_in = {32'hac_77_66_f3, 32'h19_fa_dc_21, 32'h28_d1_29_41, 32'h57_5c_00_6e};
rcon = 8'h36;
#10;
state_in = 0;
key_in = 0;
rcon = 0;
#10;
 
if(s0 != 32'h39_25_84_1d) begin $display("E"); $finish; end
if(s1 != 32'h02_dc_09_fb) begin $display("E"); $finish; end
if(s2 != 32'hdc_11_85_97) begin $display("E"); $finish; end
if(s3 != 32'h19_6a_0b_32) begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
 
/tiny_aes/trunk/rtl/aes.v File deleted
/tiny_aes/trunk/rtl/aes_128.v
0,0 → 1,133
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
 
module aes_128(clk, state, key, out);
input clk;
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, k1, s2, k2, s3, k3, s4, k4, s5, k5,
s6, k6, s7, k7, s8, k8, s9, k9, s10;
 
always @ (posedge clk)
begin
s0 <= state ^ key;
k0 <= key;
end
assign out = s10;
one_round_128
r1 (clk, s0, k0, s1, k1, 8'h1),
r2 (clk, s1, k1, s2, k2, 8'h2),
r3 (clk, s2, k2, s3, k3, 8'h4),
r4 (clk, s3, k3, s4, k4, 8'h8),
r5 (clk, s4, k4, s5, k5, 8'h10),
r6 (clk, s5, k5, s6, k6, 8'h20),
r7 (clk, s6, k6, s7, k7, 8'h40),
r8 (clk, s7, k7, s8, k8, 8'h80),
r9 (clk, s8, k8, s9, k9, 8'h1b);
final_round_128
rf (clk, s9, k9, s10, 8'h36);
endmodule
 
module one_round_128(clk, state_in, key_in, state_out, key_out, rcon);
input clk;
input [127:0] state_in, key_in;
input [7:0] rcon;
output reg [127:0] state_out, key_out;
wire [31:0] s0, s1, s2, s3,
v0, v1, v2, v3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = key_in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
key_out <= {k0b, k1b, k2b, k3b};
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, s0, p00, p01, p02, p03),
t1 (clk, s1, p10, p11, p12, p13),
t2 (clk, s2, p20, p21, p22, p23),
t3 (clk, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0b;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1b;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2b;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3b;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
 
module final_round_128(clk, state_in, key_in, state_out, rcon);
input clk;
input [127:0] state_in, key_in;
input [7:0] rcon;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
v0, v1, v2, v3,
z0, z1, z2, z3,
k0, k1, k2, k3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, s0, {p00, p01, p02, p03}),
S4_2 (clk, s1, {p10, p11, p12, p13}),
S4_3 (clk, s2, {p20, p21, p22, p23}),
S4_4 (clk, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0b;
assign z1 = {p10, p21, p32, p03} ^ k1b;
assign z2 = {p20, p31, p02, p13} ^ k2b;
assign z3 = {p30, p01, p12, p23} ^ k3b;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule

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