OpenCores
URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v
0,0 → 1,26
module versatile_fifo_dual_port_ram_sc_sw
(
d_a,
adr_a,
we_a,
q_b,
adr_b,
clk
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input clk;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk)
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
0,0 → 1,27
module versatile_fifo_dual_port_ram_dc_sw
(
d_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
clk_b
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
0,0 → 1,46
module versatile_fifo_dual_port_ram_sc_dw
(
d_a,
q_a,
adr_a,
we_a,
q_b,
adr_b,
d_b,
we_b,
clk
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk)
begin
if (we_a)
begin
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[adr_a];
end
always @ (posedge clk)
begin
if (we_b)
begin
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[adr_b];
end
endmodule
/versatile_fifo/trunk/rtl/verilog/Makefile
1,5 → 1,8
dual_port_ram:
vppp --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_sw.v
vppp +define+TYPE+"sc_sw" --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_sw.v
vppp +define+TYPE+"sc_dw" +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_dw.v
vppp +define+TYPE+"dc_sw" +define+DC --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_sw.v
vppp +define+TYPE+"dc_dw" +define+DC +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
 
svn_export_versatile_counter:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/copyright.v
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
1,5 → 1,5
// true dual port RAM, sync
module versatile_fifo_dual_port_ram_dc_2w
module versatile_fifo_dual_port_ram_`TYPE
(
// A side
d_a,
12,7 → 12,7
clk_a,
`endif
// B side
q_b
q_b,
adr_b,
`ifdef DW
d_b,
28,13 → 28,13
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
input [(DATA_WIDTH-1):0] data_a;
input [(ADDR_WIDTH-1):0] addr_a;
input [(ADDR_WIDTH-1):0] addr_b;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output reg [(DATA_WIDTH-1):0] q_b;
output [(DATA_WIDTH-1):0] q_b;
`ifdef DW
input [(DATA_WIDTH-1):0] data_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
`endif
43,6 → 43,12
`else
input clk;
`endif
 
`ifndef DW
reg [(ADDR_WIDTH-1):0] adr_b_reg;
`else
reg [(DATA_WIDTH-1):0] q_b;
`endif
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
56,19 → 62,19
begin // Port A
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[addr_a];
q_a <= ram[adr_a];
end
`else
if (we_a)
ram[addr_a] <= data_a;
ram[adr_a] <= d_a;
`endif
`ifdef DC
always @ (posedge clk_a)
always @ (posedge clk_b)
`else
always @ (posedge clk)
`endif
76,14 → 82,16
begin // Port b
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[addr_b];
q_b <= ram[adr_b];
end
`else // !`ifdef DW
q_b <= ram[addr_b];
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
`endif // !`ifdef DW
endmodule // true_dual_port_ram_sync
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
0,0 → 1,47
module versatile_fifo_dual_port_ram_dc_dw
(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk_a, clk_b;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk_a)
begin
if (we_a)
begin
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[adr_a];
end
always @ (posedge clk_b)
begin
if (we_b)
begin
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[adr_b];
end
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.