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/trunk/apps/pci2dsp/rtl/verilog/top.v
45,15 → 45,12
// CVS History
//
// $Author: gvozden $
// $Date: 2003-01-16 18:06:03 $
// $Revision: 1.1.1.1 $
// $Date: 2003-02-28 14:10:52 $
// $Revision: 1.2 $
 
 
module TOP
(
CLK,
AD,
CBE,
RST,
INTA,
REQ,
67,7 → 64,43
PAR,
PERR,
SERR,
 
AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31,
CBE0,
CBE1,
CBE2,
CBE3,
WB_CLK,
 
DSP_HAD,
86,23 → 119,6
LED
);
 
input CLK;
inout [31:0] AD;
inout [ 3:0] CBE;
inout RST;
inout INTA;
output REQ;
input GNT;
inout FRAME;
inout IRDY;
input IDSEL;
inout DEVSEL;
inout TRDY;
inout STOP;
inout PAR;
inout PERR;
output SERR;
 
input WB_CLK;
 
inout [ 7:0] DSP_HAD;
122,233 → 138,339
 
wire INT_REQ;
 
input CLK ;
inout AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31 ;
 
inout CBE0,
CBE1,
CBE2,
CBE3 ;
 
inout RST ;
inout INTA ;
output REQ ;
input GNT ;
inout FRAME ;
inout IRDY ;
input IDSEL ;
inout DEVSEL ;
inout TRDY ;
inout STOP ;
inout PAR ;
inout PERR ;
output SERR ;
 
// WISHBONE system signals
wire RST_I = 1'b0;
wire RST_O;
wire INT_I = 1'b0;
wire INT_O;
wire RST_I = 1'b0 ;
wire RST_O ;
wire INT_I = 1'b0 ;
wire INT_O ;
 
wire [15:0] rgb_int ;
// WISHBONE slave interface
wire [31:0] ADR_I;
wire [31:0] SDAT_I;
wire [31:0] SDAT_O;
wire [ 3:0] SEL_I;
wire CYC_I;
wire STB_I;
wire WE_I;
wire CAB_I;
wire ACK_O;
wire RTY_O;
wire ERR_O;
wire [31:0] ADR_I ;
wire [31:0] SDAT_I ;
wire [31:0] SDAT_O ;
wire [3:0] SEL_I ;
wire CYC_I ;
wire STB_I ;
wire WE_I ;
wire CAB_I ;
wire ACK_O ;
wire RTY_O ;
wire ERR_O ;
 
// WISHBONE master interface
wire [31:0] ADR_O;
wire [31:0] MDAT_I;
wire [31:0] MDAT_O;
wire [3:0] SEL_O;
wire CYC_O;
wire STB_O;
wire WE_O;
wire CAB_O;
wire ACK_I;
wire RTY_I;
wire ERR_I;
wire [31:0] ADR_O ;
wire [31:0] MDAT_I ;
wire [31:0] MDAT_O ;
wire [3:0] SEL_O ;
wire CYC_O ;
wire STB_O ;
wire WE_O ;
wire CAB_O ;
wire ACK_I ;
wire RTY_I ;
wire ERR_I ;
 
wire [31:0] AD_out;
wire [31:0] AD_en;
wire [31:0] AD_in = AD;
wire [31:0] AD_out ;
wire [31:0] AD_en ;
 
wire [ 3:0] CBE_in = CBE;
wire [ 3:0] CBE_out;
wire [ 3:0] CBE_en;
 
wire RST_in = RST;
wire RST_out;
wire RST_en;
wire [31:0] AD_in =
{
AD31,
AD30,
AD29,
AD28,
AD27,
AD26,
AD25,
AD24,
AD23,
AD22,
AD21,
AD20,
AD19,
AD18,
AD17,
AD16,
AD15,
AD14,
AD13,
AD12,
AD11,
AD10,
AD9,
AD8,
AD7,
AD6,
AD5,
AD4,
AD3,
AD2,
AD1,
AD0
} ;
 
wire INTA_in = INTA;
wire INTA_en;
wire INTA_out;
wire [3:0] CBE_in =
{
CBE3,
CBE2,
CBE1,
CBE0
} ;
 
wire REQ_en;
wire REQ_out;
wire [3:0] CBE_out ;
wire [3:0] CBE_en ;
 
wire FRAME_in = FRAME;
wire FRAME_out;
wire FRAME_en;
 
wire IRDY_in = IRDY;
wire IRDY_out;
wire IRDY_en;
 
wire DEVSEL_in = DEVSEL;
wire DEVSEL_out;
wire DEVSEL_en;
wire RST_in = RST ;
wire RST_out ;
wire RST_en ;
 
wire TRDY_in = TRDY;
wire TRDY_out;
wire TRDY_en;
wire INTA_in = INTA ;
wire INTA_en ;
wire INTA_out ;
 
wire STOP_in = STOP;
wire STOP_out;
wire STOP_en;
wire REQ_en ;
wire REQ_out ;
 
wire PAR_in = PAR;
wire PAR_out;
wire PAR_en;
wire FRAME_in = FRAME ;
wire FRAME_out ;
wire FRAME_en ;
 
wire PERR_in = PERR;
wire PERR_out;
wire PERR_en;
wire IRDY_in = IRDY ;
wire IRDY_out ;
wire IRDY_en ;
 
wire SERR_out;
wire SERR_en;
wire DEVSEL_in = DEVSEL ;
wire DEVSEL_out ;
wire DEVSEL_en ;
 
wire TRDY_in = TRDY ;
wire TRDY_out ;
wire TRDY_en ;
 
wire STOP_in = STOP ;
wire STOP_out ;
wire STOP_en ;
 
wire PAR_in = PAR ;
wire PAR_out ;
wire PAR_en ;
 
wire PERR_in = PERR ;
wire PERR_out ;
wire PERR_en ;
 
wire SERR_out ;
wire SERR_en ;
 
wire [ 7:0] DSP_HAD_in = DSP_HAD;
wire [ 7:0] DSP_HAD_out;
wire DSP_HAD_en;
 
PCI_BRIDGE32 bridge
pci_bridge32 bridge
(
// WISHBONE system signals
// .CLK_I (WB_CLK),
.CLK_I (CLK),
.wb_clk_i(WB_CLK),
.wb_rst_i(RST_I),
.wb_rst_o(RST_O),
.wb_int_i(INT_I),
.wb_int_o(INT_O),
 
.RST_I (RST_I),
.RST_O (RST_O),
.INT_I (INT_REQ),
.INT_O (INT_O),
 
// WISHBONE slave interface
.ADR_I (ADR_I),
.SDAT_I (SDAT_I),
.SDAT_O (SDAT_O),
.SEL_I (SEL_I),
.CYC_I (CYC_I),
.STB_I (STB_I),
.WE_I (WE_I),
.CAB_I (CAB_I),
.ACK_O (ACK_O),
.RTY_O (RTY_O),
.ERR_O (ERR_O),
.wbs_adr_i(ADR_I),
.wbs_dat_i(SDAT_I),
.wbs_dat_o(SDAT_O),
.wbs_sel_i(SEL_I),
.wbs_cyc_i(CYC_I),
.wbs_stb_i(STB_I),
.wbs_we_i (WE_I),
.wbs_cab_i(CAB_I),
.wbs_ack_o(ACK_O),
.wbs_rty_o(RTY_O),
.wbs_err_o(ERR_O),
 
// WISHBONE master interface
.ADR_O (ADR_O),
.MDAT_I (MDAT_I),
.MDAT_O (MDAT_O),
.SEL_O (SEL_O),
.CYC_O (CYC_O),
.STB_O (STB_O),
.WE_O (WE_O),
.CAB_O (CAB_O),
.ACK_I (ACK_I),
.RTY_I (RTY_I),
.ERR_I (ERR_I),
.wbm_adr_o(ADR_O),
.wbm_dat_i(MDAT_I),
.wbm_dat_o(MDAT_O),
.wbm_sel_o(SEL_O),
.wbm_cyc_o(CYC_O),
.wbm_stb_o(STB_O),
.wbm_we_o (WE_O),
.wbm_cab_o(CAB_O),
.wbm_ack_i(ACK_I),
.wbm_rty_i(RTY_I),
.wbm_err_i(ERR_I),
 
// pci interface - system pins
.PCI_CLK_IN (CLK),
.PCI_RSTn_IN (RST_in),
.PCI_RSTn_OUT (RST_out),
.PCI_INTAn_IN (INTA_in),
.PCI_INTAn_OUT (INTA_out),
.PCI_RSTn_EN_OUT (RST_en),
.PCI_INTAn_EN_OUT (INTA_en),
.pci_clk_i ( CLK ),
.pci_rst_i ( RST_in ),
.pci_rst_o ( RST_out ),
.pci_inta_i ( INTA_in ),
.pci_inta_o ( INTA_out),
.pci_rst_oe_o ( RST_en),
.pci_inta_oe_o( INTA_en ),
 
// arbitration pins
.PCI_REQn_OUT (REQ_out),
.PCI_REQn_EN_OUT (REQ_en),
.PCI_GNTn_IN (GNT),
.pci_req_o ( REQ_out ),
.pci_req_oe_o( REQ_en ),
.pci_gnt_i ( GNT ),
 
// protocol pins
.PCI_FRAMEn_IN (FRAME_in),
.PCI_FRAMEn_OUT (FRAME_out),
.PCI_FRAMEn_EN_OUT (FRAME_en),
.PCI_IRDYn_EN_OUT (IRDY_en),
.PCI_DEVSELn_EN_OUT (DEVSEL_en),
.PCI_TRDYn_EN_OUT (TRDY_en),
.PCI_STOPn_EN_OUT (STOP_en),
.PCI_AD_EN_OUT (AD_en),
.PCI_CBEn_EN_OUT (CBE_en) ,
.PCI_IRDYn_IN (IRDY_in),
.PCI_IRDYn_OUT (IRDY_out),
.PCI_IDSEL_IN (IDSEL),
.PCI_DEVSELn_IN (DEVSEL_in),
.PCI_DEVSELn_OUT (DEVSEL_out),
.PCI_TRDYn_IN (TRDY_in),
.PCI_TRDYn_OUT (TRDY_out),
.PCI_STOPn_IN (STOP_in),
.PCI_STOPn_OUT (STOP_out),
.pci_frame_i ( FRAME_in),
.pci_frame_o ( FRAME_out ),
.pci_frame_oe_o ( FRAME_en ),
.pci_irdy_oe_o ( IRDY_en ),
.pci_devsel_oe_o ( DEVSEL_en ),
.pci_trdy_oe_o ( TRDY_en ),
.pci_stop_oe_o ( STOP_en ),
.pci_ad_oe_o ( AD_en ),
.pci_cbe_oe_o ( CBE_en) ,
.pci_irdy_i ( IRDY_in ),
.pci_irdy_o ( IRDY_out ),
.pci_idsel_i ( IDSEL ),
.pci_devsel_i ( DEVSEL_in ),
.pci_devsel_o ( DEVSEL_out ),
.pci_trdy_i ( TRDY_in ),
.pci_trdy_o ( TRDY_out ),
.pci_stop_i ( STOP_in ),
.pci_stop_o ( STOP_out ),
 
// data transfer pins
.PCI_AD_IN (AD_in),
.PCI_AD_OUT (AD_out),
.PCI_CBEn_IN (CBE_in),
.PCI_CBEn_OUT (CBE_out),
.pci_ad_i (AD_in),
.pci_ad_o (AD_out),
.pci_cbe_i( CBE_in ),
.pci_cbe_o( CBE_out ),
 
// parity generation and checking pins
.PCI_PAR_IN (PAR_in),
.PCI_PAR_OUT (PAR_out),
.PCI_PAR_EN_OUT (PAR_en),
.PCI_PERRn_IN (PERR_in),
.PCI_PERRn_OUT (PERR_out),
.PCI_PERRn_EN_OUT (PERR_en),
.pci_par_i ( PAR_in ),
.pci_par_o ( PAR_out ),
.pci_par_oe_o ( PAR_en ),
.pci_perr_i ( PERR_in ),
.pci_perr_o ( PERR_out ),
.pci_perr_oe_o( PERR_en ),
 
// system error pin
.PCI_SERRn_OUT (SERR_out),
.PCI_SERRn_EN_OUT (SERR_en)
.pci_serr_o ( SERR_out ),
.pci_serr_oe_o( SERR_en )
);
 
// PCI IO buffers instantiation
bufif0 AD_buf0 (AD[0], AD_out[0], AD_en[0]);
bufif0 AD_buf1 (AD[1], AD_out[1], AD_en[1]);
bufif0 AD_buf2 (AD[2], AD_out[2], AD_en[2]);
bufif0 AD_buf3 (AD[3], AD_out[3], AD_en[3]);
bufif0 AD_buf4 (AD[4], AD_out[4], AD_en[4]);
bufif0 AD_buf5 (AD[5], AD_out[5], AD_en[5]);
bufif0 AD_buf6 (AD[6], AD_out[6], AD_en[6]);
bufif0 AD_buf7 (AD[7], AD_out[7], AD_en[7]);
bufif0 AD_buf8 (AD[8], AD_out[8], AD_en[8]);
bufif0 AD_buf9 (AD[9], AD_out[9], AD_en[9]);
bufif0 AD_buf10 (AD[10], AD_out[10],AD_en[10]);
bufif0 AD_buf11 (AD[11], AD_out[11],AD_en[11]);
bufif0 AD_buf12 (AD[12], AD_out[12],AD_en[12]);
bufif0 AD_buf13 (AD[13], AD_out[13],AD_en[13]);
bufif0 AD_buf14 (AD[14], AD_out[14],AD_en[14]);
bufif0 AD_buf15 (AD[15], AD_out[15],AD_en[15]);
bufif0 AD_buf16 (AD[16], AD_out[16],AD_en[16]);
bufif0 AD_buf17 (AD[17], AD_out[17],AD_en[17]);
bufif0 AD_buf18 (AD[18], AD_out[18],AD_en[18]);
bufif0 AD_buf19 (AD[19], AD_out[19],AD_en[19]);
bufif0 AD_buf20 (AD[20], AD_out[20],AD_en[20]);
bufif0 AD_buf21 (AD[21], AD_out[21],AD_en[21]);
bufif0 AD_buf22 (AD[22], AD_out[22],AD_en[22]);
bufif0 AD_buf23 (AD[23], AD_out[23],AD_en[23]);
bufif0 AD_buf24 (AD[24], AD_out[24],AD_en[24]);
bufif0 AD_buf25 (AD[25], AD_out[25],AD_en[25]);
bufif0 AD_buf26 (AD[26], AD_out[26],AD_en[26]);
bufif0 AD_buf27 (AD[27], AD_out[27],AD_en[27]);
bufif0 AD_buf28 (AD[28], AD_out[28],AD_en[28]);
bufif0 AD_buf29 (AD[29], AD_out[29],AD_en[29]);
bufif0 AD_buf30 (AD[30], AD_out[30],AD_en[30]);
bufif0 AD_buf31 (AD[31], AD_out[31],AD_en[31]);
bufif0 AD_buf0 ( AD0, AD_out[0], AD_en[0]) ;
bufif0 AD_buf1 ( AD1, AD_out[1], AD_en[1]) ;
bufif0 AD_buf2 ( AD2, AD_out[2], AD_en[2]) ;
bufif0 AD_buf3 ( AD3, AD_out[3], AD_en[3]) ;
bufif0 AD_buf4 ( AD4, AD_out[4], AD_en[4]) ;
bufif0 AD_buf5 ( AD5, AD_out[5], AD_en[5]) ;
bufif0 AD_buf6 ( AD6, AD_out[6], AD_en[6]) ;
bufif0 AD_buf7 ( AD7, AD_out[7], AD_en[7]) ;
bufif0 AD_buf8 ( AD8, AD_out[8], AD_en[8]) ;
bufif0 AD_buf9 ( AD9, AD_out[9], AD_en[9]) ;
bufif0 AD_buf10 ( AD10, AD_out[10],AD_en[10] ) ;
bufif0 AD_buf11 ( AD11, AD_out[11],AD_en[11] ) ;
bufif0 AD_buf12 ( AD12, AD_out[12],AD_en[12] ) ;
bufif0 AD_buf13 ( AD13, AD_out[13],AD_en[13] ) ;
bufif0 AD_buf14 ( AD14, AD_out[14],AD_en[14] ) ;
bufif0 AD_buf15 ( AD15, AD_out[15],AD_en[15] ) ;
bufif0 AD_buf16 ( AD16, AD_out[16],AD_en[16] ) ;
bufif0 AD_buf17 ( AD17, AD_out[17],AD_en[17] ) ;
bufif0 AD_buf18 ( AD18, AD_out[18],AD_en[18] ) ;
bufif0 AD_buf19 ( AD19, AD_out[19],AD_en[19] ) ;
bufif0 AD_buf20 ( AD20, AD_out[20],AD_en[20] ) ;
bufif0 AD_buf21 ( AD21, AD_out[21],AD_en[21] ) ;
bufif0 AD_buf22 ( AD22, AD_out[22],AD_en[22] ) ;
bufif0 AD_buf23 ( AD23, AD_out[23],AD_en[23] ) ;
bufif0 AD_buf24 ( AD24, AD_out[24],AD_en[24] ) ;
bufif0 AD_buf25 ( AD25, AD_out[25],AD_en[25] ) ;
bufif0 AD_buf26 ( AD26, AD_out[26],AD_en[26] ) ;
bufif0 AD_buf27 ( AD27, AD_out[27],AD_en[27] ) ;
bufif0 AD_buf28 ( AD28, AD_out[28],AD_en[28] ) ;
bufif0 AD_buf29 ( AD29, AD_out[29],AD_en[29] ) ;
bufif0 AD_buf30 ( AD30, AD_out[30],AD_en[30] ) ;
bufif0 AD_buf31 ( AD31, AD_out[31],AD_en[31] ) ;
 
bufif0 CBE_buf0 (CBE[0], CBE_out[0], CBE_en[0]);
bufif0 CBE_buf1 (CBE[1], CBE_out[1], CBE_en[1]);
bufif0 CBE_buf2 (CBE[2], CBE_out[2], CBE_en[2]);
bufif0 CBE_buf3 (CBE[3], CBE_out[3], CBE_en[3]);
bufif0 CBE_buf0 ( CBE0, CBE_out[0], CBE_en[0] ) ;
bufif0 CBE_buf1 ( CBE1, CBE_out[1], CBE_en[1] ) ;
bufif0 CBE_buf2 ( CBE2, CBE_out[2], CBE_en[2] ) ;
bufif0 CBE_buf3 ( CBE3, CBE_out[3], CBE_en[3] ) ;
 
bufif0 FRAME_buf (FRAME, FRAME_out, FRAME_en);
bufif0 IRDY_buf (IRDY, IRDY_out, IRDY_en);
bufif0 DEVSEL_buf (DEVSEL, DEVSEL_out, DEVSEL_en);
bufif0 TRDY_buf (TRDY, TRDY_out, TRDY_en);
bufif0 STOP_buf (STOP, STOP_out, STOP_en);
bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ;
bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ;
bufif0 DEVSEL_buf ( DEVSEL, DEVSEL_out, DEVSEL_en ) ;
bufif0 TRDY_buf ( TRDY, TRDY_out, TRDY_en ) ;
bufif0 STOP_buf ( STOP, STOP_out, STOP_en ) ;
 
bufif0 RST_buf (RST, RST_out, RST_en);
bufif0 INTA_buf (INTA, INTA_out, INTA_en);
bufif0 REQ_buf (REQ, REQ_out, REQ_en);
bufif0 PAR_buf (PAR, PAR_out, PAR_en);
bufif0 PERR_buf (PERR, PERR_out, PERR_en);
bufif0 SERR_buf (SERR, SERR_out, SERR_en);
bufif0 RST_buf ( RST, RST_out, RST_en ) ;
bufif0 INTA_buf ( INTA, INTA_out, INTA_en) ;
bufif0 REQ_buf ( REQ, REQ_out, REQ_en ) ;
bufif0 PAR_buf ( PAR, PAR_out, PAR_en ) ;
bufif0 PERR_buf ( PERR, PERR_out, PERR_en ) ;
bufif0 SERR_buf ( SERR, SERR_out, SERR_en ) ;
 
bufif0 DSP_HAD_buf0 (DSP_HAD[0], DSP_HAD_out[0], DSP_HAD_en);
bufif0 DSP_HAD_buf1 (DSP_HAD[1], DSP_HAD_out[1], DSP_HAD_en);
/trunk/apps/pci2dsp/syn/xilinxISE/ucf/pci2dsp.ucf
1,7 → 1,7
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2003-01-16 18:06:03 $
# $Revision: 1.1.1.1 $
# $Date: 2003-02-28 14:10:54 $
# $Revision: 1.2 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
10,84 → 10,84
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %;
 
INST "AD[0].PAD" TNM = "PCI_AD";
INST "AD[1].PAD" TNM = "PCI_AD";
INST "AD[2].PAD" TNM = "PCI_AD";
INST "AD[3].PAD" TNM = "PCI_AD";
INST "AD[4].PAD" TNM = "PCI_AD";
INST "AD[5].PAD" TNM = "PCI_AD";
INST "AD[6].PAD" TNM = "PCI_AD";
INST "AD[7].PAD" TNM = "PCI_AD";
INST "AD[8].PAD" TNM = "PCI_AD";
INST "AD[9].PAD" TNM = "PCI_AD";
INST "AD[10].PAD" TNM = "PCI_AD";
INST "AD[11].PAD" TNM = "PCI_AD";
INST "AD[12].PAD" TNM = "PCI_AD";
INST "AD[13].PAD" TNM = "PCI_AD";
INST "AD[14].PAD" TNM = "PCI_AD";
INST "AD[15].PAD" TNM = "PCI_AD";
INST "AD[16].PAD" TNM = "PCI_AD";
INST "AD[17].PAD" TNM = "PCI_AD";
INST "AD[18].PAD" TNM = "PCI_AD";
INST "AD[19].PAD" TNM = "PCI_AD";
INST "AD[20].PAD" TNM = "PCI_AD";
INST "AD[21].PAD" TNM = "PCI_AD";
INST "AD[22].PAD" TNM = "PCI_AD";
INST "AD[23].PAD" TNM = "PCI_AD";
INST "AD[24].PAD" TNM = "PCI_AD";
INST "AD[25].PAD" TNM = "PCI_AD";
INST "AD[26].PAD" TNM = "PCI_AD";
INST "AD[27].PAD" TNM = "PCI_AD";
INST "AD[28].PAD" TNM = "PCI_AD";
INST "AD[29].PAD" TNM = "PCI_AD";
INST "AD[30].PAD" TNM = "PCI_AD";
INST "AD[31].PAD" TNM = "PCI_AD";
INST "AD0.PAD" TNM = "PCI_AD";
INST "AD1.PAD" TNM = "PCI_AD";
INST "AD2.PAD" TNM = "PCI_AD";
INST "AD3.PAD" TNM = "PCI_AD";
INST "AD4.PAD" TNM = "PCI_AD";
INST "AD5.PAD" TNM = "PCI_AD";
INST "AD6.PAD" TNM = "PCI_AD";
INST "AD7.PAD" TNM = "PCI_AD";
INST "AD8.PAD" TNM = "PCI_AD";
INST "AD9.PAD" TNM = "PCI_AD";
INST "AD10.PAD" TNM = "PCI_AD";
INST "AD11.PAD" TNM = "PCI_AD";
INST "AD12.PAD" TNM = "PCI_AD";
INST "AD13.PAD" TNM = "PCI_AD";
INST "AD14.PAD" TNM = "PCI_AD";
INST "AD15.PAD" TNM = "PCI_AD";
INST "AD16.PAD" TNM = "PCI_AD";
INST "AD17.PAD" TNM = "PCI_AD";
INST "AD18.PAD" TNM = "PCI_AD";
INST "AD19.PAD" TNM = "PCI_AD";
INST "AD20.PAD" TNM = "PCI_AD";
INST "AD21.PAD" TNM = "PCI_AD";
INST "AD22.PAD" TNM = "PCI_AD";
INST "AD23.PAD" TNM = "PCI_AD";
INST "AD24.PAD" TNM = "PCI_AD";
INST "AD25.PAD" TNM = "PCI_AD";
INST "AD26.PAD" TNM = "PCI_AD";
INST "AD27.PAD" TNM = "PCI_AD";
INST "AD28.PAD" TNM = "PCI_AD";
INST "AD29.PAD" TNM = "PCI_AD";
INST "AD30.PAD" TNM = "PCI_AD";
INST "AD31.PAD" TNM = "PCI_AD";
 
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "AD[0]" IOSTANDARD = PCI33_5;
NET "AD[1]" IOSTANDARD = PCI33_5;
NET "AD[2]" IOSTANDARD = PCI33_5;
NET "AD[3]" IOSTANDARD = PCI33_5;
NET "AD[4]" IOSTANDARD = PCI33_5;
NET "AD[5]" IOSTANDARD = PCI33_5;
NET "AD[6]" IOSTANDARD = PCI33_5;
NET "AD[7]" IOSTANDARD = PCI33_5;
NET "AD[8]" IOSTANDARD = PCI33_5;
NET "AD[9]" IOSTANDARD = PCI33_5;
NET "AD[10]" IOSTANDARD = PCI33_5;
NET "AD[11]" IOSTANDARD = PCI33_5;
NET "AD[12]" IOSTANDARD = PCI33_5;
NET "AD[13]" IOSTANDARD = PCI33_5;
NET "AD[14]" IOSTANDARD = PCI33_5;
NET "AD[15]" IOSTANDARD = PCI33_5;
NET "AD[16]" IOSTANDARD = PCI33_5;
NET "AD[17]" IOSTANDARD = PCI33_5;
NET "AD[18]" IOSTANDARD = PCI33_5;
NET "AD[19]" IOSTANDARD = PCI33_5;
NET "AD[20]" IOSTANDARD = PCI33_5;
NET "AD[21]" IOSTANDARD = PCI33_5;
NET "AD[22]" IOSTANDARD = PCI33_5;
NET "AD[23]" IOSTANDARD = PCI33_5;
NET "AD[24]" IOSTANDARD = PCI33_5;
NET "AD[25]" IOSTANDARD = PCI33_5;
NET "AD[26]" IOSTANDARD = PCI33_5;
NET "AD[27]" IOSTANDARD = PCI33_5;
NET "AD[28]" IOSTANDARD = PCI33_5;
NET "AD[29]" IOSTANDARD = PCI33_5;
NET "AD[30]" IOSTANDARD = PCI33_5;
NET "AD[31]" IOSTANDARD = PCI33_5;
NET "AD0" IOSTANDARD = PCI33_5;
NET "AD1" IOSTANDARD = PCI33_5;
NET "AD2" IOSTANDARD = PCI33_5;
NET "AD3" IOSTANDARD = PCI33_5;
NET "AD4" IOSTANDARD = PCI33_5;
NET "AD5" IOSTANDARD = PCI33_5;
NET "AD6" IOSTANDARD = PCI33_5;
NET "AD7" IOSTANDARD = PCI33_5;
NET "AD8" IOSTANDARD = PCI33_5;
NET "AD9" IOSTANDARD = PCI33_5;
NET "AD10" IOSTANDARD = PCI33_5;
NET "AD11" IOSTANDARD = PCI33_5;
NET "AD12" IOSTANDARD = PCI33_5;
NET "AD13" IOSTANDARD = PCI33_5;
NET "AD14" IOSTANDARD = PCI33_5;
NET "AD15" IOSTANDARD = PCI33_5;
NET "AD16" IOSTANDARD = PCI33_5;
NET "AD17" IOSTANDARD = PCI33_5;
NET "AD18" IOSTANDARD = PCI33_5;
NET "AD19" IOSTANDARD = PCI33_5;
NET "AD20" IOSTANDARD = PCI33_5;
NET "AD21" IOSTANDARD = PCI33_5;
NET "AD22" IOSTANDARD = PCI33_5;
NET "AD23" IOSTANDARD = PCI33_5;
NET "AD24" IOSTANDARD = PCI33_5;
NET "AD25" IOSTANDARD = PCI33_5;
NET "AD26" IOSTANDARD = PCI33_5;
NET "AD27" IOSTANDARD = PCI33_5;
NET "AD28" IOSTANDARD = PCI33_5;
NET "AD29" IOSTANDARD = PCI33_5;
NET "AD30" IOSTANDARD = PCI33_5;
NET "AD31" IOSTANDARD = PCI33_5;
 
INST "CBE[0].PAD" TNM = "PCI_CBE";
INST "CBE[1].PAD" TNM = "PCI_CBE";
INST "CBE[2].PAD" TNM = "PCI_CBE";
INST "CBE[3].PAD" TNM = "PCI_CBE";
INST "CBE0.PAD" TNM = "PCI_CBE";
INST "CBE1.PAD" TNM = "PCI_CBE";
INST "CBE2.PAD" TNM = "PCI_CBE";
INST "CBE3.PAD" TNM = "PCI_CBE";
 
NET "CBE[0]" IOSTANDARD = PCI33_5;
NET "CBE[1]" IOSTANDARD = PCI33_5;
NET "CBE[2]" IOSTANDARD = PCI33_5;
NET "CBE[3]" IOSTANDARD = PCI33_5;
NET "CBE0" IOSTANDARD = PCI33_5;
NET "CBE1" IOSTANDARD = PCI33_5;
NET "CBE2" IOSTANDARD = PCI33_5;
NET "CBE3" IOSTANDARD = PCI33_5;
 
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK";
144,43 → 144,43
NET "GNT" LOC = "P200";
NET "REQ" LOC = "P201";
 
NET "AD[0]" LOC = "P67";
NET "AD[1]" LOC = "P63";
NET "AD[2]" LOC = "P62";
NET "AD[3]" LOC = "P61";
NET "AD[4]" LOC = "P59";
NET "AD[5]" LOC = "P58";
NET "AD[6]" LOC = "P57";
NET "AD[7]" LOC = "P49";
NET "AD[8]" LOC = "P47";
NET "AD[9]" LOC = "P46";
NET "AD[10]" LOC = "P45";
NET "AD[11]" LOC = "P43";
NET "AD[12]" LOC = "P42";
NET "AD[13]" LOC = "P41";
NET "AD[14]" LOC = "P37";
NET "AD[15]" LOC = "P36";
NET "AD[16]" LOC = "P21";
NET "AD[17]" LOC = "P20";
NET "AD[18]" LOC = "P18";
NET "AD[19]" LOC = "P17";
NET "AD[20]" LOC = "P16";
NET "AD[21]" LOC = "P15";
NET "AD[22]" LOC = "P14";
NET "AD[23]" LOC = "P10";
NET "AD[24]" LOC = "P6";
NET "AD[25]" LOC = "P5";
NET "AD[26]" LOC = "P4";
NET "AD[27]" LOC = "P3";
NET "AD[28]" LOC = "P206";
NET "AD[29]" LOC = "P205";
NET "AD[30]" LOC = "P204";
NET "AD[31]" LOC = "P203";
NET "AD0" LOC = "P67";
NET "AD1" LOC = "P63";
NET "AD2" LOC = "P62";
NET "AD3" LOC = "P61";
NET "AD4" LOC = "P59";
NET "AD5" LOC = "P58";
NET "AD6" LOC = "P57";
NET "AD7" LOC = "P49";
NET "AD8" LOC = "P47";
NET "AD9" LOC = "P46";
NET "AD10" LOC = "P45";
NET "AD11" LOC = "P43";
NET "AD12" LOC = "P42";
NET "AD13" LOC = "P41";
NET "AD14" LOC = "P37";
NET "AD15" LOC = "P36";
NET "AD16" LOC = "P21";
NET "AD17" LOC = "P20";
NET "AD18" LOC = "P18";
NET "AD19" LOC = "P17";
NET "AD20" LOC = "P16";
NET "AD21" LOC = "P15";
NET "AD22" LOC = "P14";
NET "AD23" LOC = "P10";
NET "AD24" LOC = "P6";
NET "AD25" LOC = "P5";
NET "AD26" LOC = "P4";
NET "AD27" LOC = "P3";
NET "AD28" LOC = "P206";
NET "AD29" LOC = "P205";
NET "AD30" LOC = "P204";
NET "AD31" LOC = "P203";
 
NET "CBE[0]" LOC = "P48";
NET "CBE[1]" LOC = "P35";
NET "CBE[2]" LOC = "P22";
NET "CBE[3]" LOC = "P8";
NET "CBE0" LOC = "P48";
NET "CBE1" LOC = "P35";
NET "CBE2" LOC = "P22";
NET "CBE3" LOC = "P8";
 
NET "IDSEL" LOC = "P9";
NET "FRAME" LOC = "P23";
/trunk/apps/pci2dsp/syn/synplify/src/regPCI.sdc
1,40 → 1,41
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2003-01-16 18:06:03 $
# $Revision: 1.1.1.1 $
# $Date: 2003-02-28 14:10:53 $
# $Revision: 1.2 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
 
#
# Clocks
#
define_clock -name {CLK} -freq 35.000 -clockgroup clkkrp_pci
define_clock -name {WB_CLK} -freq 30.000 -clockgroup clkgrp_wb
define_clock -name {CLK} -freq 35.000 -clockgroup clkkrp_pci
define_clock -name {WB_CLK} -freq 30.000 -clockgroup clkgrp_wb
 
#
# Inputs/Outputs
#
define_input_delay {AD[31:0]} 7.00 -ref CLK:r
define_input_delay {CBE[3:0]} 7.00 -ref CLK:r
define_input_delay {FRAME} 7.00 -ref CLK:r
define_input_delay {IRDY} 7.00 -ref CLK:r
define_input_delay {IDSEL} 7.00 -ref CLK:r
define_input_delay {TRDY} 7.00 -route 3.00 -ref CLK:r
define_input_delay {STOP} 7.00 -route 1.00 -ref CLK:r
define_input_delay {PAR} 7.00 -ref CLK:r
define_input_delay {PERR} 7.00 -ref CLK:r
define_input_delay {GNT} 10.00 -route 2.00 -ref CLK:r
define_output_delay {AD[31:0]} 11.00 -route 4.00 -ref CLK:r
define_output_delay {CBE[3:0]} 11.00 -ref CLK:r
define_output_delay {FRAME} 11.00 -ref CLK:r
define_output_delay {IRDY} 11.00 -ref CLK:r
define_input_delay {DEVSEL} 11.00 -ref CLK:r
define_output_delay {TRDY} 11.00 -ref CLK:r
define_output_delay {STOP} 11.00 -ref CLK:r
define_output_delay {PAR} 11.00 -ref CLK:r
define_output_delay {PERR} 11.00 -ref CLK:r
define_output_delay {SERR} 11.00 -ref CLK:r
define_output_delay {REQ} 12.00 -ref CLK:r
define_input_delay {AD[31:0]} 7.00 -ref CLK:r
define_input_delay {CBE[3:0]} 7.00 -ref CLK:r
define_input_delay {FRAME} 7.00 -ref CLK:r
define_input_delay {IRDY} 7.00 -ref CLK:r
define_input_delay {IDSEL} 7.00 -ref CLK:r
define_input_delay {TRDY} 7.00 -route 3.00 -ref CLK:r
define_input_delay {STOP} 7.00 -route 1.00 -ref CLK:r
define_input_delay {PAR} 7.00 -ref CLK:r
define_input_delay {PERR} 7.00 -ref CLK:r
define_input_delay {GNT} 10.00 -route 2.00 -ref CLK:r
define_output_delay {AD[31:0]} 11.00 -route 4.00 -ref CLK:r
define_output_delay {CBE[3:0]} 11.00 -ref CLK:r
define_output_delay {FRAME} 11.00 -ref CLK:r
define_output_delay {IRDY} 11.00 -ref CLK:r
define_input_delay {DEVSEL} 11.00 -ref CLK:r
define_output_delay {TRDY} 11.00 -ref CLK:r
define_output_delay {STOP} 11.00 -ref CLK:r
define_output_delay {PAR} 11.00 -ref CLK:r
define_output_delay {PERR} 11.00 -ref CLK:r
define_output_delay {SERR} 11.00 -ref CLK:r
define_output_delay {REQ} 12.00 -ref CLK:r
 
#
# Registers
47,54 → 48,53
#
# False Path
#
define_false_path -from {i:bridge.configuration.*} -to {i:WB2HPI.WB_slave.WBS_DAT_O[31:0]}
define_false_path -from {i:bridge.configuration.*} -to {i:WB2HPI.WB_slave.WBS_DAT_O[31:0]}
 
#
# Attributes
#
define_global_attribute syn_netlist_hierarchy {0}
define_global_attribute syn_netlist_hierarchy {0}
define_global_attribute syn_forward_io_constraints {1}
define_attribute {v:work.pci_io_mux} syn_hier {hard}
define_attribute {v:work.pci_parity_check} syn_hier {hard}
define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
define_attribute {v:work.pci_par_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
define_attribute {v:work.pci_perr_crit} syn_hier {hard}
define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_crit} syn_hier {hard}
define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
define_attribute {v:work.pci_cur_out_reg} syn_hier {hard}
define_attribute {v:work.pci_out_reg} syn_hier {hard}
define_attribute {AD[31:0]} syn_useioff {1}
define_attribute {CBE[3:0]} syn_useioff {1}
define_attribute {DEVSEL} syn_useioff {1}
define_attribute {FRAME} syn_useioff {1}
define_attribute {GNT} syn_useioff {1}
define_attribute {IDSEL} syn_useioff {1}
define_attribute {INTA} syn_useioff {1}
define_attribute {IRDY} syn_useioff {1}
define_attribute {PAR} syn_useioff {1}
define_attribute {PERR} syn_useioff {1}
define_attribute {REQ} syn_useioff {1}
define_attribute {RST} syn_useioff {1}
define_attribute {SERR} syn_useioff {1}
define_attribute {STOP} syn_useioff {1}
define_attribute {TRDY} syn_useioff {1}
define_attribute {CLK} xc_padtype {BUFGP}
define_attribute {DSP_HINT} syn_noclockbuf {1}
 
define_attribute {v:work.PCI_IO_MUX} syn_hier {hard}
define_attribute {v:work.PCI_PARITY_CHECK} syn_hier {hard}
define_attribute {v:work.CBE_EN_CRIT} syn_hier {hard}
define_attribute {v:work.FRAME_CRIT} syn_hier {hard}
define_attribute {v:work.FRAME_EN_CRIT} syn_hier {hard}
define_attribute {v:work.FRAME_LOAD_CRIT} syn_hier {hard}
define_attribute {v:work.IRDY_OUT_CRIT} syn_hier {hard}
define_attribute {v:work.MAS_AD_EN_CRIT} syn_hier {hard}
define_attribute {v:work.MAS_AD_LOAD_CRIT} syn_hier {hard}
define_attribute {v:work.MAS_CH_STATE_CRIT} syn_hier {hard}
define_attribute {v:work.PAR_CRIT} syn_hier {hard}
define_attribute {v:work.PCI_IO_MUX_AD_EN_CRIT} syn_hier {hard}
define_attribute {v:work.PCI_IO_MUX_AD_LOAD_CRIT} syn_hier {hard}
define_attribute {v:work.PCI_TARGET32_DEVS_CRIT} syn_hier {hard}
define_attribute {v:work.PCI_TARGET32_STOP_CRIT} syn_hier {hard}
define_attribute {v:work.PCI_TARGET32_TRDY_CRIT} syn_hier {hard}
define_attribute {v:work.PERR_CRIT} syn_hier {hard}
define_attribute {v:work.PERR_EN_CRIT} syn_hier {hard}
define_attribute {v:work.SERR_CRIT} syn_hier {hard}
define_attribute {v:work.SERR_EN_CRIT} syn_hier {hard}
define_attribute {v:work.CUR_OUT_REG} syn_hier {hard}
define_attribute {v:work.OUT_REG} syn_hier {hard}
define_attribute {AD[31:0]} syn_useioff {1}
define_attribute {CBE[3:0]} syn_useioff {1}
define_attribute {DEVSEL} syn_useioff {1}
define_attribute {FRAME} syn_useioff {1}
define_attribute {GNT} syn_useioff {1}
define_attribute {IDSEL} syn_useioff {1}
define_attribute {INTA} syn_useioff {1}
define_attribute {IRDY} syn_useioff {1}
define_attribute {PAR} syn_useioff {1}
define_attribute {PERR} syn_useioff {1}
define_attribute {REQ} syn_useioff {1}
define_attribute {RST} syn_useioff {1}
define_attribute {SERR} syn_useioff {1}
define_attribute {STOP} syn_useioff {1}
define_attribute {TRDY} syn_useioff {1}
define_attribute {CLK} xc_padtype {BUFGP}
define_attribute {DSP_HINT} syn_noclockbuf {1}
 
#
# Other Constraints
#
/trunk/apps/pci2dsp/syn/synplify/src/regPCI.prj
1,104 → 1,104
#************************** CVS history ***************************#
# $Author: gvozden $
# $Date: 2003-01-16 18:06:03 $
# $Revision: 1.1.1.1 $
# $Date: 2003-02-28 14:10:53 $
# $Revision: 1.2 $
# $Name: not supported by cvs2svn $
#************************** CVS history ***************************#
 
#add_file options
add_file -verilog "../../../pci/virtex.v"
add_file -verilog "../../../pci/crtc_iob.v"
add_file -verilog "../../../pci/bus_commands.v"
add_file -verilog "../../../pci/cbe_en_crit.v"
add_file -verilog "../../../pci/conf_cyc_addr_dec.v"
add_file -verilog "../../../pci/conf_space.v"
add_file -verilog "../../../pci/cur_out_reg.v"
add_file -verilog "../../../pci/decoder.v"
add_file -verilog "../../../pci/delayed_sync.v"
add_file -verilog "../../../pci/delayed_write_reg.v"
add_file -verilog "../../../pci/fifo_control.v"
add_file -verilog "../../../pci/frame_crit.v"
add_file -verilog "../../../pci/frame_en_crit.v"
add_file -verilog "../../../pci/async_reset_flop.v"
add_file -verilog "../../../pci/frame_load_crit.v"
add_file -verilog "../../../pci/irdy_out_crit.v"
add_file -verilog "../../../pci/mas_ad_en_crit.v"
add_file -verilog "../../../pci/mas_ad_load_crit.v"
add_file -verilog "../../../pci/mas_ch_state_crit.v"
add_file -verilog "../../../pci/out_reg.v"
add_file -verilog "../../../pci/par_crit.v"
add_file -verilog "../../../pci/pci_bridge32.v"
add_file -verilog "../../../pci/pci_decoder.v"
add_file -verilog "../../../pci/pci_in_reg.v"
add_file -verilog "../../../pci/pci_io_mux.v"
add_file -verilog "../../../pci/pci_io_mux_ad_en_crit.v"
add_file -verilog "../../../pci/pci_io_mux_ad_load_crit.v"
add_file -verilog "../../../pci/pci_master32_sm.v"
add_file -verilog "../../../pci/pci_master32_sm_if.v"
add_file -verilog "../../../pci/pci_parity_check.v"
add_file -verilog "../../../pci/pci_rst_int.v"
add_file -verilog "../../../pci/pci_target32_clk_en.v"
add_file -verilog "../../../pci/pci_target32_devs_crit.v"
add_file -verilog "../../../pci/pci_target32_interface.v"
add_file -verilog "../../../pci/pci_target32_sm.v"
add_file -verilog "../../../pci/pci_target32_stop_crit.v"
add_file -verilog "../../../pci/pci_target32_trdy_crit.v"
add_file -verilog "../../../pci/pci_target_unit.v"
add_file -verilog "../../../pci/pci_tpram.v"
add_file -verilog "../../../pci/pciw_fifo_control.v"
add_file -verilog "../../../pci/pciw_pcir_fifos.v"
add_file -verilog "../../../pci/perr_crit.v"
add_file -verilog "../../../pci/perr_en_crit.v"
add_file -verilog "../../../pci/serr_crit.v"
add_file -verilog "../../../pci/serr_en_crit.v"
add_file -verilog "../../../pci/sync_module.v"
add_file -verilog "../../../pci/synchronizer_flop.v"
add_file -verilog "../../../pci/wb_addr_mux.v"
add_file -verilog "../../../pci/wb_master.v"
add_file -verilog "../../../pci/wb_slave.v"
add_file -verilog "../../../pci/wb_slave_unit.v"
add_file -verilog "../../../pci/wb_tpram.v"
add_file -verilog "../../../pci/wbr_fifo_control.v"
add_file -verilog "../../../pci/wbw_fifo_control.v"
add_file -verilog "../../../pci/wbw_wbr_fifos.v"
add_file -verilog "../../../rtl/verilog/top.v"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBmaster.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBslave.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_control.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_interface.vhd"
add_file -constraint "regPCI.sdc"
add_file -verilog "../../../pci/virtex.v"
add_file -verilog "../../../rtl/verilog/top.v"
add_file -verilog "../../../pci/meta_flop.v"
add_file -verilog "../../../pci/pci_async_reset_flop.v"
add_file -verilog "../../../pci/pci_bridge32.v"
add_file -verilog "../../../pci/pci_cbe_en_crit.v"
add_file -verilog "../../../pci/pci_conf_cyc_addr_dec.v"
add_file -verilog "../../../pci/pci_conf_space.v"
add_file -verilog "../../../pci/pci_constants.v"
add_file -verilog "../../../pci/pci_cur_out_reg.v"
add_file -verilog "../../../pci/pci_delayed_sync.v"
add_file -verilog "../../../pci/pci_delayed_write_reg.v"
add_file -verilog "../../../pci/pci_frame_crit.v"
add_file -verilog "../../../pci/pci_frame_en_crit.v"
add_file -verilog "../../../pci/pci_frame_load_crit.v"
add_file -verilog "../../../pci/pci_in_reg.v"
add_file -verilog "../../../pci/pci_io_mux.v"
add_file -verilog "../../../pci/pci_io_mux_ad_en_crit.v"
add_file -verilog "../../../pci/pci_io_mux_ad_load_crit.v"
add_file -verilog "../../../pci/pci_irdy_out_crit.v"
add_file -verilog "../../../pci/pci_mas_ad_en_crit.v"
add_file -verilog "../../../pci/pci_mas_ad_load_crit.v"
add_file -verilog "../../../pci/pci_mas_ch_state_crit.v"
add_file -verilog "../../../pci/pci_master32_sm.v"
add_file -verilog "../../../pci/pci_master32_sm_if.v"
add_file -verilog "../../../pci/pci_out_reg.v"
add_file -verilog "../../../pci/pci_par_crit.v"
add_file -verilog "../../../pci/pci_parity_check.v"
add_file -verilog "../../../pci/pci_pci_decoder.v"
add_file -verilog "../../../pci/pci_pci_tpram.v"
add_file -verilog "../../../pci/pci_pcir_fifo_control.v"
add_file -verilog "../../../pci/pci_pciw_fifo_control.v"
add_file -verilog "../../../pci/pci_pciw_pcir_fifos.v"
add_file -verilog "../../../pci/pci_perr_crit.v"
add_file -verilog "../../../pci/pci_perr_en_crit.v"
add_file -verilog "../../../pci/pci_ram_16x40d.v"
add_file -verilog "../../../pci/pci_rst_int.v"
add_file -verilog "../../../pci/pci_serr_crit.v"
add_file -verilog "../../../pci/pci_serr_en_crit.v"
add_file -verilog "../../../pci/pci_sync_module.v"
add_file -verilog "../../../pci/pci_target32_clk_en.v"
add_file -verilog "../../../pci/pci_target32_devs_crit.v"
add_file -verilog "../../../pci/pci_target32_interface.v"
add_file -verilog "../../../pci/pci_target32_sm.v"
add_file -verilog "../../../pci/pci_target32_stop_crit.v"
add_file -verilog "../../../pci/pci_target32_trdy_crit.v"
add_file -verilog "../../../pci/pci_target_unit.v"
add_file -verilog "../../../pci/pci_wb_addr_mux.v"
add_file -verilog "../../../pci/pci_wb_decoder.v"
add_file -verilog "../../../pci/pci_wb_master.v"
add_file -verilog "../../../pci/pci_wb_slave.v"
add_file -verilog "../../../pci/pci_wb_slave_unit.v"
add_file -verilog "../../../pci/pci_wb_tpram.v"
add_file -verilog "../../../pci/pci_wbr_fifo_control.v"
add_file -verilog "../../../pci/pci_wbw_fifo_control.v"
add_file -verilog "../../../pci/pci_wbw_wbr_fifos.v"
add_file -verilog "../../../pci/synchronizer_flop.v"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBmaster.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBslave.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_control.vhd"
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_interface.vhd"
add_file -constraint "regPCI.sdc"
 
#reporting options
 
 
#implementation: "syn"
impl -add syn
 
#device options
set_option -technology SPARTAN2
set_option -part XC2S200
set_option -package PQ208
set_option -part XC2S200
set_option -package PQ208
set_option -speed_grade -5
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 1
set_option -top_module "TOP"
set_option -resource_sharing 0
set_option -use_fsm_explorer 1
set_option -top_module "TOP"
 
#map options
set_option -frequency 30.000
set_option -fanout_limit 32
set_option -frequency 30.000
set_option -fanout_limit 32
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 1
set_option -modular 0
set_option -pipe 1
set_option -retiming 1
set_option -modular 0
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
107,4 → 107,4
project -result_format "edif"
project -log_file "../log/pci2dsp.log"
project -result_file "../out/pci2dsp.edn"
impl -active "syn"
impl -active "syn"
/trunk/apps/pci2dsp/pci/README.TXT
1,4 → 65,4
Put Opencores PCI core here!
Put Opencores PCI core here:
-------------------------------------------------
pci_user_constants.v
pci_target_unit.v
pci_target32_trdy_crit.v
pci_target32_stop_crit.v
pci_target32_sm.v
pci_target32_interface.v
pci_target32_devs_crit.v
pci_target32_clk_en.v
pci_rst_int.v
pci_parity_check.v
pci_master32_sm_if.v
pci_master32_sm.v
pci_io_mux_ad_load_crit.v
pci_io_mux_ad_en_crit.v
pci_io_mux.v
pci_in_reg.v
pci_bridge32.v
pci_serr_en_crit.v
pci_serr_crit.v
pci_perr_en_crit.v
pci_perr_crit.v
pci_par_crit.v
pci_wbw_wbr_fifos.v
pci_wb_master.v
pci_pciw_pcir_fifos.v
pci_wbw_fifo_control.v
pci_wbr_fifo_control.v
pci_wb_tpram.v
pci_wb_slave_unit.v
pci_wb_slave.v
pci_wb_decoder.v
pci_wb_addr_mux.v
pci_sync_module.v
pci_pciw_fifo_control.v
pci_pcir_fifo_control.v
pci_pci_tpram.v
pci_pci_decoder.v
pci_out_reg.v
pci_mas_ch_state_crit.v
pci_mas_ad_load_crit.v
pci_mas_ad_en_crit.v
pci_irdy_out_crit.v
pci_frame_load_crit.v
pci_frame_en_crit.v
pci_frame_crit.v
pci_delayed_write_reg.v
pci_delayed_sync.v
pci_cur_out_reg.v
pci_conf_space.v
pci_conf_cyc_addr_dec.v
pci_cbe_en_crit.v
pci_async_reset_flop.v
bus_commands.v
meta_flop.v
pci_ram_16x40d.v
timescale.v
synchronizer_flop.v
pci_constants.v
 
Put library files here:
-------------------------------------------------
virtex.v
 

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