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Rev 3 → Rev 4

/xucpu/trunk/Xilinx/startup_sim.wcfg
0,0 → 1,176
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/jurgen/Projects/lisp/FPGA/startup_sim_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="arrayio" />
<top_module name="components" />
<top_module name="controllers" />
<top_module name="mux_parts" />
<top_module name="numeric_std" />
<top_module name="ram_parts" />
<top_module name="startup_sim" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="35" />
<wvobject fp_name="/startup_sim/clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RST1/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CLOCK1/clk_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_out</obj_property>
<obj_property name="ObjectShortName">clk_out</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/pc_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pc_out[14:0]</obj_property>
<obj_property name="ObjectShortName">pc_out[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/PC/q" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q[14:0]</obj_property>
<obj_property name="ObjectShortName">q[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/MEM1/address_reg_2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">address_reg_2[9:0]</obj_property>
<obj_property name="ObjectShortName">address_reg_2[9:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/MEM1/q2" type="array" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">q2[15:0]</obj_property>
<obj_property name="ObjectShortName">q2[15:0]</obj_property>
<obj_property name="label">INSTRUCTION</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/IR/q" type="array" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">q[15:0]</obj_property>
<obj_property name="ObjectShortName">q[15:0]</obj_property>
<obj_property name="label">IR_Q</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/DR/q" type="array" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">q[15:0]</obj_property>
<obj_property name="ObjectShortName">q[15:0]</obj_property>
<obj_property name="label">DR_Q</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/curr_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">curr_state</obj_property>
<obj_property name="ObjectShortName">curr_state</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/pc_src" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pc_src[2:0]</obj_property>
<obj_property name="ObjectShortName">pc_src[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/ld_pc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_pc</obj_property>
<obj_property name="ObjectShortName">ld_pc</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/ld_ir" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_ir</obj_property>
<obj_property name="ObjectShortName">ld_ir</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/ld_dp" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_dp</obj_property>
<obj_property name="ObjectShortName">ld_dp</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/operation" type="array" db_ref_id="1">
<obj_property name="ElementShortName">operation[3:0]</obj_property>
<obj_property name="ObjectShortName">operation[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_addr_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_addr_a[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_addr_a[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_addr_b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_addr_b[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_addr_b[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/reg_src" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_src[2:0]</obj_property>
<obj_property name="ObjectShortName">reg_src[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/REG_MUX/y" type="array" db_ref_id="1">
<obj_property name="ElementShortName">y[15:0]</obj_property>
<obj_property name="ObjectShortName">y[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d[15:0]</obj_property>
<obj_property name="ObjectShortName">d[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/reg_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reg_wr</obj_property>
<obj_property name="ObjectShortName">reg_wr</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/reg[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">reg[0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/reg[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">reg[1]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/reg[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">reg[2]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/reg[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">reg[3]</obj_property>
</wvobject>
<wvobject fp_name="divider33" type="divider">
<obj_property name="label">Memory</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/data_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_address[14:0]</obj_property>
<obj_property name="ObjectShortName">data_address[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/databus_write" type="array" db_ref_id="1">
<obj_property name="ElementShortName">databus_write[15:0]</obj_property>
<obj_property name="ObjectShortName">databus_write[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/mem_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_wr</obj_property>
<obj_property name="ObjectShortName">mem_wr</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/DEC1/bus_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bus_sel[2:0]</obj_property>
<obj_property name="ObjectShortName">bus_sel[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/DEC1/gpio_1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">gpio_1</obj_property>
<obj_property name="ObjectShortName">gpio_1</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/OUT1/ena" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ena</obj_property>
<obj_property name="ObjectShortName">ena</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/OUT1/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/OUT1/port_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">port_out[7:0]</obj_property>
<obj_property name="ObjectShortName">port_out[7:0]</obj_property>
</wvobject>
</wave_config>
/xucpu/trunk/Xilinx/startup_sim_pr.wcfg
0,0 → 1,145
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/jurgen/Projects/lisp/FPGA/startup_sim_isim_par.wdb" id="1" type="auto">
<top_modules>
<top_module name="startup_sim" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_signed" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpackage" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="28" />
<wave_markers>
<marker time="534414000" label="" />
<marker time="554414000" label="" />
<marker time="494414000" label="" />
<marker time="499866000" label="" />
</wave_markers>
<wvobject fp_name="/startup_sim/clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CLOCK1/clk_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_out</obj_property>
<obj_property name="ObjectShortName">clk_out</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RST1/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/PC_MUX/y" type="array" db_ref_id="1">
<obj_property name="ElementShortName">y[14:0]</obj_property>
<obj_property name="ObjectShortName">y[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/ld_pc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_pc</obj_property>
<obj_property name="ObjectShortName">ld_pc</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/ld_ir" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_ir</obj_property>
<obj_property name="ObjectShortName">ld_ir</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/ld_dp" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ld_dp</obj_property>
<obj_property name="ObjectShortName">ld_dp</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/PC/q" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q[14:0]</obj_property>
<obj_property name="ObjectShortName">q[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/MEM1/a2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a2[9:0]</obj_property>
<obj_property name="ObjectShortName">a2[9:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/MEM1/q2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q2[15:0]</obj_property>
<obj_property name="ObjectShortName">q2[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/IR/q" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q[15:0]</obj_property>
<obj_property name="ObjectShortName">q[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/DR/q" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q[15:0]</obj_property>
<obj_property name="ObjectShortName">q[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/operation" type="array" db_ref_id="1">
<obj_property name="ElementShortName">operation[3:0]</obj_property>
<obj_property name="ObjectShortName">operation[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_addr_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_addr_a[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_addr_a[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_addr_b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_addr_b[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_addr_b[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reg_wr</obj_property>
<obj_property name="ObjectShortName">reg_wr</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/CTRL1/reg_src" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_src[2:0]</obj_property>
<obj_property name="ObjectShortName">reg_src[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d[15:0]</obj_property>
<obj_property name="ObjectShortName">d[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/q1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">q1[15:0]</obj_property>
<obj_property name="ObjectShortName">q1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/RF1/q2" type="array" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">q2[15:0]</obj_property>
<obj_property name="ObjectShortName">q2[15:0]</obj_property>
<obj_property name="label">q2[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/zero" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">zero</obj_property>
<obj_property name="ObjectShortName">zero</obj_property>
</wvobject>
<wvobject fp_name="divider28" type="divider">
<obj_property name="label">Memory</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/mem_wr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_wr</obj_property>
<obj_property name="ObjectShortName">mem_wr</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/data_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_address[14:0]</obj_property>
<obj_property name="ObjectShortName">data_address[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/databus_write" type="array" db_ref_id="1">
<obj_property name="ElementShortName">databus_write[15:0]</obj_property>
<obj_property name="ObjectShortName">databus_write[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/led_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">led_out[7:0]</obj_property>
<obj_property name="ObjectShortName">led_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/startup_sim/uut/DEC1/gpio_1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">gpio_1</obj_property>
<obj_property name="ObjectShortName">gpio_1</obj_property>
</wvobject>
</wave_config>
/xucpu/trunk/Xilinx/system.ucf
0,0 → 1,86
NET "CLOCK1/MC/CLK_IN1" LOC = L15;
NET "reset" LOC = T15;
 
NET "led_out[0]" LOC = U18;
NET "led_out[1]" LOC = M14;
NET "led_out[2]" LOC = N14;
NET "led_out[3]" LOC = L14;
NET "led_out[4]" LOC = M13;
NET "led_out[5]" LOC = D4;
NET "led_out[6]" LOC = P16;
NET "led_out[7]" LOC = N12;
NET "pushb_in[0]" LOC = N4;
NET "pushb_in[1]" LOC = F5;
NET "pushb_in[2]" LOC = F6;
NET "pushb_in[3]" LOC = P4;
NET "pushb_in[4]" LOC = P3;
NET "switch_in[0]" LOC = A10;
NET "switch_in[1]" LOC = D14;
NET "switch_in[2]" LOC = C14;
NET "switch_in[3]" LOC = P15;
NET "switch_in[4]" LOC = P12;
NET "switch_in[5]" LOC = R5;
NET "switch_in[6]" LOC = T5;
NET "switch_in[7]" LOC = E4;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
NET "clock" TNM_NET = "clock";
TIMESPEC TS_clock = PERIOD "clock" 10 ns HIGH 50 %;
INST "pushb_in[0]" TNM = "Simple_IO";
INST "pushb_in[1]" TNM = "Simple_IO";
INST "pushb_in[2]" TNM = "Simple_IO";
INST "pushb_in[3]" TNM = "Simple_IO";
INST "pushb_in[4]" TNM = "Simple_IO";
INST "switch_in[0]" TNM = "Simple_IO";
INST "switch_in[1]" TNM = "Simple_IO";
INST "switch_in[2]" TNM = "Simple_IO";
INST "switch_in[3]" TNM = "Simple_IO";
INST "switch_in[4]" TNM = "Simple_IO";
INST "switch_in[5]" TNM = "Simple_IO";
INST "switch_in[6]" TNM = "Simple_IO";
INST "switch_in[7]" TNM = "Simple_IO";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
TIMEGRP "Simple_IO" OFFSET = IN 100 ns VALID 100 ns BEFORE "clock" RISING;
INST "led_out[0]" TNM = "Simple_output";
INST "led_out[1]" TNM = "Simple_output";
INST "led_out[2]" TNM = "Simple_output";
INST "led_out[3]" TNM = "Simple_output";
INST "led_out[4]" TNM = "Simple_output";
INST "led_out[5]" TNM = "Simple_output";
INST "led_out[6]" TNM = "Simple_output";
INST "led_out[7]" TNM = "Simple_output";
TIMEGRP "Simple_output" OFFSET = OUT 100 ns AFTER "clock";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
INST "CTRL1/OPERATION_0" TNM = "TS_datapath";
INST "CTRL1/OPERATION_1" TNM = "TS_datapath";
INST "CTRL1/OPERATION_2" TNM = "TS_datapath";
INST "CTRL1/OPERATION_3" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_0" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_1" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_2" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_3" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_0" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_1" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_2" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_3" TNM = "TS_datapath";
INST "MEM1/Mram_mem1" TNM = "TS_ram";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
INST "RST1/count_0" TNM = "Time_RST";
INST "RST1/count_1" TNM = "Time_RST";
TIMESPEC TS_reset = FROM "Time_RST" TO "TS_ram" TIG ;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
INST "PC/Q_0" TNM = "Time_PC";
INST "PC/Q_1" TNM = "Time_PC";
INST "PC/Q_2" TNM = "Time_PC";
INST "PC/Q_3" TNM = "Time_PC";
INST "PC/Q_4" TNM = "Time_PC";
INST "PC/Q_5" TNM = "Time_PC";
INST "PC/Q_6" TNM = "Time_PC";
INST "PC/Q_7" TNM = "Time_PC";
INST "PC/Q_8" TNM = "Time_PC";
INST "PC/Q_9" TNM = "Time_PC";
INST "PC/Q_10" TNM = "Time_PC";
INST "PC/Q_11" TNM = "Time_PC";
INST "PC/Q_12" TNM = "Time_PC";
INST "PC/Q_13" TNM = "Time_PC";
INST "PC/Q_14" TNM = "Time_PC";
TIMESPEC TS_PC_TIG = FROM "Time_RST" TO "Time_PC" TIG ;
/xucpu/trunk/Xilinx/input_data.txt
0,0 → 1,1024
3000
0000
9000
0008
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/xucpu/trunk/Xilinx/functional.wcfg
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/jurgen/Projects/lisp/harddev/system_sim_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="components" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="system_sim" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="23" />
<wvobject fp_name="/system_sim/clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/sys_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sys_clk</obj_property>
<obj_property name="ObjectShortName">sys_clk</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/sys_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sys_rst</obj_property>
<obj_property name="ObjectShortName">sys_rst</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/int_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">int_rst</obj_property>
<obj_property name="ObjectShortName">int_rst</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/addr_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_out[14:0]</obj_property>
<obj_property name="ObjectShortName">addr_out[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">address[14:0]</obj_property>
<obj_property name="ObjectShortName">address[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM/clka" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM/addra" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addra[14:0]</obj_property>
<obj_property name="ObjectShortName">addra[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM/douta" type="array" db_ref_id="1">
<obj_property name="ElementShortName">douta[15:0]</obj_property>
<obj_property name="ObjectShortName">douta[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/databus_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">databus_in[15:0]</obj_property>
<obj_property name="ObjectShortName">databus_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[15:0]</obj_property>
<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/d_ir_load" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">d_ir_load</obj_property>
<obj_property name="ObjectShortName">d_ir_load</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/ir" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ir[15:0]</obj_property>
<obj_property name="ObjectShortName">ir[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[15:0]</obj_property>
<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/register_file" type="array" db_ref_id="1">
<obj_property name="ElementShortName">register_file[0:31]</obj_property>
<obj_property name="ObjectShortName">register_file[0:31]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/pc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pc[14:0]</obj_property>
<obj_property name="ObjectShortName">pc[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/addr_out_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_out_reg[14:0]</obj_property>
<obj_property name="ObjectShortName">addr_out_reg[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/data_out_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_out_reg[15:0]</obj_property>
<obj_property name="ObjectShortName">data_out_reg[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[15:0]</obj_property>
<obj_property name="ObjectShortName">a[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b[15:0]</obj_property>
<obj_property name="ObjectShortName">b[15:0]</obj_property>
</wvobject>
</wave_config>
/xucpu/trunk/Xilinx/post_route.wcfg
0,0 → 1,107
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/jurgen/Projects/lisp/harddev/system_sim_isim_par.wdb" id="1" type="auto">
<top_modules>
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_signed" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="system_sim" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpackage" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="21" />
<wvobject fp_name="/system_sim/clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/sys_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sys_clk</obj_property>
<obj_property name="ObjectShortName">sys_clk</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/sys_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sys_rst</obj_property>
<obj_property name="ObjectShortName">sys_rst</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/int_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">int_rst</obj_property>
<obj_property name="ObjectShortName">int_rst</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/addr_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_out[14:0]</obj_property>
<obj_property name="ObjectShortName">addr_out[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">address[14:0]</obj_property>
<obj_property name="ObjectShortName">address[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/addra" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addra[13:0]</obj_property>
<obj_property name="ObjectShortName">addra[13:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/databus_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">databus_in[15:0]</obj_property>
<obj_property name="ObjectShortName">databus_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[15:0]</obj_property>
<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[15:0]</obj_property>
<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/reg_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_a[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_a[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/reg_b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_b[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_b[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/op_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_sel[3:0]</obj_property>
<obj_property name="ObjectShortName">op_sel[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/y" type="array" db_ref_id="1">
<obj_property name="ElementShortName">y[15:0]</obj_property>
<obj_property name="ObjectShortName">y[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/pc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pc[14:0]</obj_property>
<obj_property name="ObjectShortName">pc[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/addr_out_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_out_reg[14:0]</obj_property>
<obj_property name="ObjectShortName">addr_out_reg[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/data_out_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_out_reg[15:0]</obj_property>
<obj_property name="ObjectShortName">data_out_reg[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[15:0]</obj_property>
<obj_property name="ObjectShortName">a[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b[15:0]</obj_property>
<obj_property name="ObjectShortName">b[15:0]</obj_property>
</wvobject>
</wave_config>
/xucpu/trunk/Xilinx/simulation.wcfg
0,0 → 1,121
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/jurgen/Projects/lisp/harddev/system_sim_isim_par.wdb" id="1" type="auto">
<top_modules>
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_signed" />
<top_module name="std_logic_textio" />
<top_module name="std_logic_unsigned" />
<top_module name="system_sim" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpackage" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="23" />
<wvobject fp_name="/system_sim/clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/clock" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
<obj_property name="label">uc_clock</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/clock" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">clock</obj_property>
<obj_property name="ObjectShortName">clock</obj_property>
<obj_property name="label">dp_clock</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_16_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_8_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_24_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">clka</obj_property>
<obj_property name="ObjectShortName">clka</obj_property>
<obj_property name="label">mem_clka</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/CLK1/clk_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_valid</obj_property>
<obj_property name="ObjectShortName">clk_valid</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/switch_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">switch_in[7:0]</obj_property>
<obj_property name="ObjectShortName">switch_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/pushb_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pushb_in[4:0]</obj_property>
<obj_property name="ObjectShortName">pushb_in[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/led_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">led_out[7:0]</obj_property>
<obj_property name="ObjectShortName">led_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/DP1/pc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">pc[14:0]</obj_property>
<obj_property name="ObjectShortName">pc[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/reg_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_a[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_a[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/reg_b" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_b[3:0]</obj_property>
<obj_property name="ObjectShortName">reg_b[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/op_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_sel[3:0]</obj_property>
<obj_property name="ObjectShortName">op_sel[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[15:0]</obj_property>
<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/memw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">memw</obj_property>
<obj_property name="ObjectShortName">memw</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/uCTRL/memr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">memr</obj_property>
<obj_property name="ObjectShortName">memr</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_12_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/addra[3]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">addra[3]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/doa" type="array" db_ref_id="1">
<obj_property name="ElementShortName">doa[31:0]</obj_property>
<obj_property name="ObjectShortName">doa[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/wea" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wea[3:0]</obj_property>
<obj_property name="ObjectShortName">wea[3:0]</obj_property>
</wvobject>
</wave_config>
/xucpu/trunk/Xilinx/xucpu.xise
0,0 → 1,458
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../src/system.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../src/multiplexer/MUX.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../src/zerof.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../src/regf.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../src/data_reg.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../src/incr.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../src/uctrl.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../src/decoder.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../src/gpio_in.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../src/gpio_out.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../src/blockram/RAM.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../src/sync_reset.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../src/clock.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="ipcore_dir/clock_core_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../src/controllers.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../src/components.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../src/file/arrayio.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../src/startup_sim.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="system.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../src/ALU/alu.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../src/ALU/logic.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../src/ALU/shift.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../src/ALU/summation.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
</files>
 
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="startup_sim.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Custom Waveform Configuration File Par" xil_pn:value="startup_sim_pr.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Custom Waveform Configuration File Translate" xil_pn:value="startup_sim.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="../src/system.vhdl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/startup_sim" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.4/ISE_DS/ISE/spartan6/data/spartan6_performance_without_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|startup_sim|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="xucpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|startup_sim|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|startup_sim|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-03-04T13:58:59" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B540B9C03BB1FEABEDCBEFA706D63592" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings>
<binding xil_pn:location="/system" xil_pn:name="system.ucf"/>
</bindings>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/xucpu/trunk/ghdl/startup_sim.gtkw
0,0 → 1,1138
[*]
[*] GTKWave Analyzer v3.3.48 (w)1999-2013 BSI
[*] Sun Dec 21 13:13:35 2014
[*]
[dumpfile] "/Users/jurgen/local/shared/BAZAAR/lisp/FPGA/startup_sim.ghw"
[dumpfile_mtime] "Sun Dec 21 13:12:56 2014"
[dumpfile_size] 73164
[savefile] "/Users/jurgen/local/shared/BAZAAR/lisp/FPGA/startup_sim.gtkw"
[timestart] 295000000
[size] 1276 756
[pos] -1 -1
*-25.649773 -1 345000000 385000000 425000000 465000000 505000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.startup_sim.
[treeopen] top.startup_sim.uut.
[treeopen] top.startup_sim.uut.mar.
[treeopen] top.startup_sim.uut.rf1.reg.
[sst_width] 213
[signals_width] 179
[sst_expanded] 1
[sst_vpaned_height] 281
@28
top.startup_sim.clock
top.startup_sim.reset
top.startup_sim.uut.clk
top.startup_sim.uut.rst
@22
+{PC_OUT} #{top.startup_sim.uut.pc_mux.y[14:0]} top.startup_sim.uut.pc_mux.y[14] top.startup_sim.uut.pc_mux.y[13] top.startup_sim.uut.pc_mux.y[12] top.startup_sim.uut.pc_mux.y[11] top.startup_sim.uut.pc_mux.y[10] top.startup_sim.uut.pc_mux.y[9] top.startup_sim.uut.pc_mux.y[8] top.startup_sim.uut.pc_mux.y[7] top.startup_sim.uut.pc_mux.y[6] top.startup_sim.uut.pc_mux.y[5] top.startup_sim.uut.pc_mux.y[4] top.startup_sim.uut.pc_mux.y[3] top.startup_sim.uut.pc_mux.y[2] top.startup_sim.uut.pc_mux.y[1] top.startup_sim.uut.pc_mux.y[0]
+{PC_Q} #{top.startup_sim.uut.pc.q[14:0]} top.startup_sim.uut.pc.q[14] top.startup_sim.uut.pc.q[13] top.startup_sim.uut.pc.q[12] top.startup_sim.uut.pc.q[11] top.startup_sim.uut.pc.q[10] top.startup_sim.uut.pc.q[9] top.startup_sim.uut.pc.q[8] top.startup_sim.uut.pc.q[7] top.startup_sim.uut.pc.q[6] top.startup_sim.uut.pc.q[5] top.startup_sim.uut.pc.q[4] top.startup_sim.uut.pc.q[3] top.startup_sim.uut.pc.q[2] top.startup_sim.uut.pc.q[1] top.startup_sim.uut.pc.q[0]
+{IAR_Q} #{top.startup_sim.uut.mem1.address_reg_2[9:0]} top.startup_sim.uut.mem1.address_reg_2[9] top.startup_sim.uut.mem1.address_reg_2[8] top.startup_sim.uut.mem1.address_reg_2[7] top.startup_sim.uut.mem1.address_reg_2[6] top.startup_sim.uut.mem1.address_reg_2[5] top.startup_sim.uut.mem1.address_reg_2[4] top.startup_sim.uut.mem1.address_reg_2[3] top.startup_sim.uut.mem1.address_reg_2[2] top.startup_sim.uut.mem1.address_reg_2[1] top.startup_sim.uut.mem1.address_reg_2[0]
+{INSTRUCTION} #{top.startup_sim.uut.mem1.q2[15:0]} top.startup_sim.uut.mem1.q2[15] top.startup_sim.uut.mem1.q2[14] top.startup_sim.uut.mem1.q2[13] top.startup_sim.uut.mem1.q2[12] top.startup_sim.uut.mem1.q2[11] top.startup_sim.uut.mem1.q2[10] top.startup_sim.uut.mem1.q2[9] top.startup_sim.uut.mem1.q2[8] top.startup_sim.uut.mem1.q2[7] top.startup_sim.uut.mem1.q2[6] top.startup_sim.uut.mem1.q2[5] top.startup_sim.uut.mem1.q2[4] top.startup_sim.uut.mem1.q2[3] top.startup_sim.uut.mem1.q2[2] top.startup_sim.uut.mem1.q2[1] top.startup_sim.uut.mem1.q2[0]
[color] 3
+{IR_Q} #{top.startup_sim.uut.ir.q[15:0]} top.startup_sim.uut.ir.q[15] top.startup_sim.uut.ir.q[14] top.startup_sim.uut.ir.q[13] top.startup_sim.uut.ir.q[12] top.startup_sim.uut.ir.q[11] top.startup_sim.uut.ir.q[10] top.startup_sim.uut.ir.q[9] top.startup_sim.uut.ir.q[8] top.startup_sim.uut.ir.q[7] top.startup_sim.uut.ir.q[6] top.startup_sim.uut.ir.q[5] top.startup_sim.uut.ir.q[4] top.startup_sim.uut.ir.q[3] top.startup_sim.uut.ir.q[2] top.startup_sim.uut.ir.q[1] top.startup_sim.uut.ir.q[0]
+{DR_Q} #{top.startup_sim.uut.dr.q[15:0]} top.startup_sim.uut.dr.q[15] top.startup_sim.uut.dr.q[14] top.startup_sim.uut.dr.q[13] top.startup_sim.uut.dr.q[12] top.startup_sim.uut.dr.q[11] top.startup_sim.uut.dr.q[10] top.startup_sim.uut.dr.q[9] top.startup_sim.uut.dr.q[8] top.startup_sim.uut.dr.q[7] top.startup_sim.uut.dr.q[6] top.startup_sim.uut.dr.q[5] top.startup_sim.uut.dr.q[4] top.startup_sim.uut.dr.q[3] top.startup_sim.uut.dr.q[2] top.startup_sim.uut.dr.q[1] top.startup_sim.uut.dr.q[0]
@28
top.startup_sim.uut.ctrl1.curr_state
top.startup_sim.uut.ctrl1.next_state
top.startup_sim.uut.ctrl1.decoding
#{top.startup_sim.uut.ctrl1.pc_src[2:0]} top.startup_sim.uut.ctrl1.pc_src[2] top.startup_sim.uut.ctrl1.pc_src[1] top.startup_sim.uut.ctrl1.pc_src[0]
top.startup_sim.uut.ctrl1.ld_pc
top.startup_sim.uut.ctrl1.ld_ir
top.startup_sim.uut.ctrl1.ld_dp
@22
#{top.startup_sim.uut.ctrl1.operation[3:0]} top.startup_sim.uut.ctrl1.operation[3] top.startup_sim.uut.ctrl1.operation[2] top.startup_sim.uut.ctrl1.operation[1] top.startup_sim.uut.ctrl1.operation[0]
#{top.startup_sim.uut.ctrl1.reg_addr_a[3:0]} top.startup_sim.uut.ctrl1.reg_addr_a[3] top.startup_sim.uut.ctrl1.reg_addr_a[2] top.startup_sim.uut.ctrl1.reg_addr_a[1] top.startup_sim.uut.ctrl1.reg_addr_a[0]
#{top.startup_sim.uut.ctrl1.reg_addr_b[3:0]} top.startup_sim.uut.ctrl1.reg_addr_b[3] top.startup_sim.uut.ctrl1.reg_addr_b[2] top.startup_sim.uut.ctrl1.reg_addr_b[1] top.startup_sim.uut.ctrl1.reg_addr_b[0]
@200
-REGISTER FILE
@28
+{REG_SEL} #{top.startup_sim.uut.reg_mux.sel[2:0]} top.startup_sim.uut.reg_mux.sel[2] top.startup_sim.uut.reg_mux.sel[1] top.startup_sim.uut.reg_mux.sel[0]
@22
+{REG_IN} #{top.startup_sim.uut.reg_mux.y[15:0]} top.startup_sim.uut.reg_mux.y[15] top.startup_sim.uut.reg_mux.y[14] top.startup_sim.uut.reg_mux.y[13] top.startup_sim.uut.reg_mux.y[12] top.startup_sim.uut.reg_mux.y[11] top.startup_sim.uut.reg_mux.y[10] top.startup_sim.uut.reg_mux.y[9] top.startup_sim.uut.reg_mux.y[8] top.startup_sim.uut.reg_mux.y[7] top.startup_sim.uut.reg_mux.y[6] top.startup_sim.uut.reg_mux.y[5] top.startup_sim.uut.reg_mux.y[4] top.startup_sim.uut.reg_mux.y[3] top.startup_sim.uut.reg_mux.y[2] top.startup_sim.uut.reg_mux.y[1] top.startup_sim.uut.reg_mux.y[0]
+{REG_D} #{top.startup_sim.uut.rf1.d[15:0]} top.startup_sim.uut.rf1.d[15] top.startup_sim.uut.rf1.d[14] top.startup_sim.uut.rf1.d[13] top.startup_sim.uut.rf1.d[12] top.startup_sim.uut.rf1.d[11] top.startup_sim.uut.rf1.d[10] top.startup_sim.uut.rf1.d[9] top.startup_sim.uut.rf1.d[8] top.startup_sim.uut.rf1.d[7] top.startup_sim.uut.rf1.d[6] top.startup_sim.uut.rf1.d[5] top.startup_sim.uut.rf1.d[4] top.startup_sim.uut.rf1.d[3] top.startup_sim.uut.rf1.d[2] top.startup_sim.uut.rf1.d[1] top.startup_sim.uut.rf1.d[0]
@28
top.startup_sim.uut.reg_wr
@22
#{top.startup_sim.uut.rf1.reg[0][15:0]} top.startup_sim.uut.rf1.reg[0][15] top.startup_sim.uut.rf1.reg[0][14] top.startup_sim.uut.rf1.reg[0][13] top.startup_sim.uut.rf1.reg[0][12] top.startup_sim.uut.rf1.reg[0][11] top.startup_sim.uut.rf1.reg[0][10] top.startup_sim.uut.rf1.reg[0][9] top.startup_sim.uut.rf1.reg[0][8] top.startup_sim.uut.rf1.reg[0][7] top.startup_sim.uut.rf1.reg[0][6] top.startup_sim.uut.rf1.reg[0][5] top.startup_sim.uut.rf1.reg[0][4] top.startup_sim.uut.rf1.reg[0][3] top.startup_sim.uut.rf1.reg[0][2] top.startup_sim.uut.rf1.reg[0][1] top.startup_sim.uut.rf1.reg[0][0]
#{top.startup_sim.uut.rf1.reg[1][15:0]} top.startup_sim.uut.rf1.reg[1][15] top.startup_sim.uut.rf1.reg[1][14] top.startup_sim.uut.rf1.reg[1][13] top.startup_sim.uut.rf1.reg[1][12] top.startup_sim.uut.rf1.reg[1][11] top.startup_sim.uut.rf1.reg[1][10] top.startup_sim.uut.rf1.reg[1][9] top.startup_sim.uut.rf1.reg[1][8] top.startup_sim.uut.rf1.reg[1][7] top.startup_sim.uut.rf1.reg[1][6] top.startup_sim.uut.rf1.reg[1][5] top.startup_sim.uut.rf1.reg[1][4] top.startup_sim.uut.rf1.reg[1][3] top.startup_sim.uut.rf1.reg[1][2] top.startup_sim.uut.rf1.reg[1][1] top.startup_sim.uut.rf1.reg[1][0]
#{top.startup_sim.uut.rf1.reg[2][15:0]} top.startup_sim.uut.rf1.reg[2][15] top.startup_sim.uut.rf1.reg[2][14] top.startup_sim.uut.rf1.reg[2][13] top.startup_sim.uut.rf1.reg[2][12] top.startup_sim.uut.rf1.reg[2][11] top.startup_sim.uut.rf1.reg[2][10] top.startup_sim.uut.rf1.reg[2][9] top.startup_sim.uut.rf1.reg[2][8] top.startup_sim.uut.rf1.reg[2][7] top.startup_sim.uut.rf1.reg[2][6] top.startup_sim.uut.rf1.reg[2][5] top.startup_sim.uut.rf1.reg[2][4] top.startup_sim.uut.rf1.reg[2][3] top.startup_sim.uut.rf1.reg[2][2] top.startup_sim.uut.rf1.reg[2][1] top.startup_sim.uut.rf1.reg[2][0]
#{top.startup_sim.uut.rf1.reg[3][15:0]} top.startup_sim.uut.rf1.reg[3][15] top.startup_sim.uut.rf1.reg[3][14] top.startup_sim.uut.rf1.reg[3][13] top.startup_sim.uut.rf1.reg[3][12] top.startup_sim.uut.rf1.reg[3][11] top.startup_sim.uut.rf1.reg[3][10] top.startup_sim.uut.rf1.reg[3][9] top.startup_sim.uut.rf1.reg[3][8] top.startup_sim.uut.rf1.reg[3][7] top.startup_sim.uut.rf1.reg[3][6] top.startup_sim.uut.rf1.reg[3][5] top.startup_sim.uut.rf1.reg[3][4] top.startup_sim.uut.rf1.reg[3][3] top.startup_sim.uut.rf1.reg[3][2] top.startup_sim.uut.rf1.reg[3][1] top.startup_sim.uut.rf1.reg[3][0]
#{top.startup_sim.uut.rf1.reg[4][15:0]} top.startup_sim.uut.rf1.reg[4][15] top.startup_sim.uut.rf1.reg[4][14] top.startup_sim.uut.rf1.reg[4][13] top.startup_sim.uut.rf1.reg[4][12] top.startup_sim.uut.rf1.reg[4][11] top.startup_sim.uut.rf1.reg[4][10] top.startup_sim.uut.rf1.reg[4][9] top.startup_sim.uut.rf1.reg[4][8] top.startup_sim.uut.rf1.reg[4][7] top.startup_sim.uut.rf1.reg[4][6] top.startup_sim.uut.rf1.reg[4][5] top.startup_sim.uut.rf1.reg[4][4] top.startup_sim.uut.rf1.reg[4][3] top.startup_sim.uut.rf1.reg[4][2] top.startup_sim.uut.rf1.reg[4][1] top.startup_sim.uut.rf1.reg[4][0]
#{top.startup_sim.uut.rf1.reg[5][15:0]} top.startup_sim.uut.rf1.reg[5][15] top.startup_sim.uut.rf1.reg[5][14] top.startup_sim.uut.rf1.reg[5][13] top.startup_sim.uut.rf1.reg[5][12] top.startup_sim.uut.rf1.reg[5][11] top.startup_sim.uut.rf1.reg[5][10] top.startup_sim.uut.rf1.reg[5][9] top.startup_sim.uut.rf1.reg[5][8] top.startup_sim.uut.rf1.reg[5][7] top.startup_sim.uut.rf1.reg[5][6] top.startup_sim.uut.rf1.reg[5][5] top.startup_sim.uut.rf1.reg[5][4] top.startup_sim.uut.rf1.reg[5][3] top.startup_sim.uut.rf1.reg[5][2] top.startup_sim.uut.rf1.reg[5][1] top.startup_sim.uut.rf1.reg[5][0]
#{top.startup_sim.uut.rf1.reg[6][15:0]} top.startup_sim.uut.rf1.reg[6][15] top.startup_sim.uut.rf1.reg[6][14] top.startup_sim.uut.rf1.reg[6][13] top.startup_sim.uut.rf1.reg[6][12] top.startup_sim.uut.rf1.reg[6][11] top.startup_sim.uut.rf1.reg[6][10] top.startup_sim.uut.rf1.reg[6][9] top.startup_sim.uut.rf1.reg[6][8] top.startup_sim.uut.rf1.reg[6][7] top.startup_sim.uut.rf1.reg[6][6] top.startup_sim.uut.rf1.reg[6][5] top.startup_sim.uut.rf1.reg[6][4] top.startup_sim.uut.rf1.reg[6][3] top.startup_sim.uut.rf1.reg[6][2] top.startup_sim.uut.rf1.reg[6][1] top.startup_sim.uut.rf1.reg[6][0]
#{top.startup_sim.uut.rf1.reg[7][15:0]} top.startup_sim.uut.rf1.reg[7][15] top.startup_sim.uut.rf1.reg[7][14] top.startup_sim.uut.rf1.reg[7][13] top.startup_sim.uut.rf1.reg[7][12] top.startup_sim.uut.rf1.reg[7][11] top.startup_sim.uut.rf1.reg[7][10] top.startup_sim.uut.rf1.reg[7][9] top.startup_sim.uut.rf1.reg[7][8] top.startup_sim.uut.rf1.reg[7][7] top.startup_sim.uut.rf1.reg[7][6] top.startup_sim.uut.rf1.reg[7][5] top.startup_sim.uut.rf1.reg[7][4] top.startup_sim.uut.rf1.reg[7][3] top.startup_sim.uut.rf1.reg[7][2] top.startup_sim.uut.rf1.reg[7][1] top.startup_sim.uut.rf1.reg[7][0]
#{top.startup_sim.uut.a_out[15:0]} top.startup_sim.uut.a_out[15] top.startup_sim.uut.a_out[14] top.startup_sim.uut.a_out[13] top.startup_sim.uut.a_out[12] top.startup_sim.uut.a_out[11] top.startup_sim.uut.a_out[10] top.startup_sim.uut.a_out[9] top.startup_sim.uut.a_out[8] top.startup_sim.uut.a_out[7] top.startup_sim.uut.a_out[6] top.startup_sim.uut.a_out[5] top.startup_sim.uut.a_out[4] top.startup_sim.uut.a_out[3] top.startup_sim.uut.a_out[2] top.startup_sim.uut.a_out[1] top.startup_sim.uut.a_out[0]
@29
top.startup_sim.uut.zero
@22
#{top.startup_sim.uut.b_out[15:0]} top.startup_sim.uut.b_out[15] top.startup_sim.uut.b_out[14] top.startup_sim.uut.b_out[13] top.startup_sim.uut.b_out[12] top.startup_sim.uut.b_out[11] top.startup_sim.uut.b_out[10] top.startup_sim.uut.b_out[9] top.startup_sim.uut.b_out[8] top.startup_sim.uut.b_out[7] top.startup_sim.uut.b_out[6] top.startup_sim.uut.b_out[5] top.startup_sim.uut.b_out[4] top.startup_sim.uut.b_out[3] top.startup_sim.uut.b_out[2] top.startup_sim.uut.b_out[1] top.startup_sim.uut.b_out[0]
@200
-ALU
@22
#{top.startup_sim.uut.rega.q[15:0]} top.startup_sim.uut.rega.q[15] top.startup_sim.uut.rega.q[14] top.startup_sim.uut.rega.q[13] top.startup_sim.uut.rega.q[12] top.startup_sim.uut.rega.q[11] top.startup_sim.uut.rega.q[10] top.startup_sim.uut.rega.q[9] top.startup_sim.uut.rega.q[8] top.startup_sim.uut.rega.q[7] top.startup_sim.uut.rega.q[6] top.startup_sim.uut.rega.q[5] top.startup_sim.uut.rega.q[4] top.startup_sim.uut.rega.q[3] top.startup_sim.uut.rega.q[2] top.startup_sim.uut.rega.q[1] top.startup_sim.uut.rega.q[0]
#{top.startup_sim.uut.alu1.a[15:0]} top.startup_sim.uut.alu1.a[15] top.startup_sim.uut.alu1.a[14] top.startup_sim.uut.alu1.a[13] top.startup_sim.uut.alu1.a[12] top.startup_sim.uut.alu1.a[11] top.startup_sim.uut.alu1.a[10] top.startup_sim.uut.alu1.a[9] top.startup_sim.uut.alu1.a[8] top.startup_sim.uut.alu1.a[7] top.startup_sim.uut.alu1.a[6] top.startup_sim.uut.alu1.a[5] top.startup_sim.uut.alu1.a[4] top.startup_sim.uut.alu1.a[3] top.startup_sim.uut.alu1.a[2] top.startup_sim.uut.alu1.a[1] top.startup_sim.uut.alu1.a[0]
#{top.startup_sim.uut.regb.q[15:0]} top.startup_sim.uut.regb.q[15] top.startup_sim.uut.regb.q[14] top.startup_sim.uut.regb.q[13] top.startup_sim.uut.regb.q[12] top.startup_sim.uut.regb.q[11] top.startup_sim.uut.regb.q[10] top.startup_sim.uut.regb.q[9] top.startup_sim.uut.regb.q[8] top.startup_sim.uut.regb.q[7] top.startup_sim.uut.regb.q[6] top.startup_sim.uut.regb.q[5] top.startup_sim.uut.regb.q[4] top.startup_sim.uut.regb.q[3] top.startup_sim.uut.regb.q[2] top.startup_sim.uut.regb.q[1] top.startup_sim.uut.regb.q[0]
#{top.startup_sim.uut.alu1.b[15:0]} top.startup_sim.uut.alu1.b[15] top.startup_sim.uut.alu1.b[14] top.startup_sim.uut.alu1.b[13] top.startup_sim.uut.alu1.b[12] top.startup_sim.uut.alu1.b[11] top.startup_sim.uut.alu1.b[10] top.startup_sim.uut.alu1.b[9] top.startup_sim.uut.alu1.b[8] top.startup_sim.uut.alu1.b[7] top.startup_sim.uut.alu1.b[6] top.startup_sim.uut.alu1.b[5] top.startup_sim.uut.alu1.b[4] top.startup_sim.uut.alu1.b[3] top.startup_sim.uut.alu1.b[2] top.startup_sim.uut.alu1.b[1] top.startup_sim.uut.alu1.b[0]
#{top.startup_sim.uut.alu1.op[3:0]} top.startup_sim.uut.alu1.op[3] top.startup_sim.uut.alu1.op[2] top.startup_sim.uut.alu1.op[1] top.startup_sim.uut.alu1.op[0]
#{top.startup_sim.uut.alu1.y[15:0]} top.startup_sim.uut.alu1.y[15] top.startup_sim.uut.alu1.y[14] top.startup_sim.uut.alu1.y[13] top.startup_sim.uut.alu1.y[12] top.startup_sim.uut.alu1.y[11] top.startup_sim.uut.alu1.y[10] top.startup_sim.uut.alu1.y[9] top.startup_sim.uut.alu1.y[8] top.startup_sim.uut.alu1.y[7] top.startup_sim.uut.alu1.y[6] top.startup_sim.uut.alu1.y[5] top.startup_sim.uut.alu1.y[4] top.startup_sim.uut.alu1.y[3] top.startup_sim.uut.alu1.y[2] top.startup_sim.uut.alu1.y[1] top.startup_sim.uut.alu1.y[0]
@200
-DATA MEM
@28
top.startup_sim.uut.mem1.we
@c00022
#{top.startup_sim.uut.mem1.mem[0:1023]} top.startup_sim.uut.mem1.mem[0] top.startup_sim.uut.mem1.mem[1] top.startup_sim.uut.mem1.mem[2] top.startup_sim.uut.mem1.mem[3] top.startup_sim.uut.mem1.mem[4] top.startup_sim.uut.mem1.mem[5] top.startup_sim.uut.mem1.mem[6] top.startup_sim.uut.mem1.mem[7] top.startup_sim.uut.mem1.mem[8] top.startup_sim.uut.mem1.mem[9] top.startup_sim.uut.mem1.mem[10] top.startup_sim.uut.mem1.mem[11] top.startup_sim.uut.mem1.mem[12] top.startup_sim.uut.mem1.mem[13] top.startup_sim.uut.mem1.mem[14] top.startup_sim.uut.mem1.mem[15] top.startup_sim.uut.mem1.mem[16] top.startup_sim.uut.mem1.mem[17] top.startup_sim.uut.mem1.mem[18] top.startup_sim.uut.mem1.mem[19] top.startup_sim.uut.mem1.mem[20] top.startup_sim.uut.mem1.mem[21] top.startup_sim.uut.mem1.mem[22] top.startup_sim.uut.mem1.mem[23] top.startup_sim.uut.mem1.mem[24] top.startup_sim.uut.mem1.mem[25] top.startup_sim.uut.mem1.mem[26] top.startup_sim.uut.mem1.mem[27] top.startup_sim.uut.mem1.mem[28] top.startup_sim.uut.mem1.mem[29] top.startup_sim.uut.mem1.mem[30] top.startup_sim.uut.mem1.mem[31] top.startup_sim.uut.mem1.mem[32] top.startup_sim.uut.mem1.mem[33] top.startup_sim.uut.mem1.mem[34] top.startup_sim.uut.mem1.mem[35] top.startup_sim.uut.mem1.mem[36] top.startup_sim.uut.mem1.mem[37] top.startup_sim.uut.mem1.mem[38] top.startup_sim.uut.mem1.mem[39] top.startup_sim.uut.mem1.mem[40] top.startup_sim.uut.mem1.mem[41] top.startup_sim.uut.mem1.mem[42] top.startup_sim.uut.mem1.mem[43] top.startup_sim.uut.mem1.mem[44] top.startup_sim.uut.mem1.mem[45] top.startup_sim.uut.mem1.mem[46] top.startup_sim.uut.mem1.mem[47] top.startup_sim.uut.mem1.mem[48] top.startup_sim.uut.mem1.mem[49] top.startup_sim.uut.mem1.mem[50] top.startup_sim.uut.mem1.mem[51] top.startup_sim.uut.mem1.mem[52] top.startup_sim.uut.mem1.mem[53] top.startup_sim.uut.mem1.mem[54] top.startup_sim.uut.mem1.mem[55] top.startup_sim.uut.mem1.mem[56] top.startup_sim.uut.mem1.mem[57] top.startup_sim.uut.mem1.mem[58] top.startup_sim.uut.mem1.mem[59] top.startup_sim.uut.mem1.mem[60] top.startup_sim.uut.mem1.mem[61] top.startup_sim.uut.mem1.mem[62] top.startup_sim.uut.mem1.mem[63] top.startup_sim.uut.mem1.mem[64] top.startup_sim.uut.mem1.mem[65] top.startup_sim.uut.mem1.mem[66] top.startup_sim.uut.mem1.mem[67] top.startup_sim.uut.mem1.mem[68] top.startup_sim.uut.mem1.mem[69] top.startup_sim.uut.mem1.mem[70] top.startup_sim.uut.mem1.mem[71] top.startup_sim.uut.mem1.mem[72] top.startup_sim.uut.mem1.mem[73] top.startup_sim.uut.mem1.mem[74] top.startup_sim.uut.mem1.mem[75] top.startup_sim.uut.mem1.mem[76] top.startup_sim.uut.mem1.mem[77] top.startup_sim.uut.mem1.mem[78] top.startup_sim.uut.mem1.mem[79] top.startup_sim.uut.mem1.mem[80] top.startup_sim.uut.mem1.mem[81] top.startup_sim.uut.mem1.mem[82] top.startup_sim.uut.mem1.mem[83] top.startup_sim.uut.mem1.mem[84] top.startup_sim.uut.mem1.mem[85] top.startup_sim.uut.mem1.mem[86] top.startup_sim.uut.mem1.mem[87] top.startup_sim.uut.mem1.mem[88] top.startup_sim.uut.mem1.mem[89] top.startup_sim.uut.mem1.mem[90] top.startup_sim.uut.mem1.mem[91] top.startup_sim.uut.mem1.mem[92] top.startup_sim.uut.mem1.mem[93] top.startup_sim.uut.mem1.mem[94] top.startup_sim.uut.mem1.mem[95] top.startup_sim.uut.mem1.mem[96] top.startup_sim.uut.mem1.mem[97] top.startup_sim.uut.mem1.mem[98] top.startup_sim.uut.mem1.mem[99] top.startup_sim.uut.mem1.mem[100] top.startup_sim.uut.mem1.mem[101] top.startup_sim.uut.mem1.mem[102] top.startup_sim.uut.mem1.mem[103] top.startup_sim.uut.mem1.mem[104] top.startup_sim.uut.mem1.mem[105] top.startup_sim.uut.mem1.mem[106] top.startup_sim.uut.mem1.mem[107] top.startup_sim.uut.mem1.mem[108] top.startup_sim.uut.mem1.mem[109] top.startup_sim.uut.mem1.mem[110] top.startup_sim.uut.mem1.mem[111] top.startup_sim.uut.mem1.mem[112] top.startup_sim.uut.mem1.mem[113] top.startup_sim.uut.mem1.mem[114] top.startup_sim.uut.mem1.mem[115] top.startup_sim.uut.mem1.mem[116] top.startup_sim.uut.mem1.mem[117] top.startup_sim.uut.mem1.mem[118] top.startup_sim.uut.mem1.mem[119] top.startup_sim.uut.mem1.mem[120] top.startup_sim.uut.mem1.mem[121] top.startup_sim.uut.mem1.mem[122] top.startup_sim.uut.mem1.mem[123] top.startup_sim.uut.mem1.mem[124] top.startup_sim.uut.mem1.mem[125] top.startup_sim.uut.mem1.mem[126] top.startup_sim.uut.mem1.mem[127] top.startup_sim.uut.mem1.mem[128] top.startup_sim.uut.mem1.mem[129] top.startup_sim.uut.mem1.mem[130] top.startup_sim.uut.mem1.mem[131] top.startup_sim.uut.mem1.mem[132] top.startup_sim.uut.mem1.mem[133] top.startup_sim.uut.mem1.mem[134] top.startup_sim.uut.mem1.mem[135] top.startup_sim.uut.mem1.mem[136] top.startup_sim.uut.mem1.mem[137] top.startup_sim.uut.mem1.mem[138] top.startup_sim.uut.mem1.mem[139] top.startup_sim.uut.mem1.mem[140] top.startup_sim.uut.mem1.mem[141] top.startup_sim.uut.mem1.mem[142] top.startup_sim.uut.mem1.mem[143] top.startup_sim.uut.mem1.mem[144] top.startup_sim.uut.mem1.mem[145] top.startup_sim.uut.mem1.mem[146] top.startup_sim.uut.mem1.mem[147] top.startup_sim.uut.mem1.mem[148] top.startup_sim.uut.mem1.mem[149] top.startup_sim.uut.mem1.mem[150] top.startup_sim.uut.mem1.mem[151] top.startup_sim.uut.mem1.mem[152] top.startup_sim.uut.mem1.mem[153] top.startup_sim.uut.mem1.mem[154] top.startup_sim.uut.mem1.mem[155] top.startup_sim.uut.mem1.mem[156] top.startup_sim.uut.mem1.mem[157] top.startup_sim.uut.mem1.mem[158] top.startup_sim.uut.mem1.mem[159] top.startup_sim.uut.mem1.mem[160] top.startup_sim.uut.mem1.mem[161] top.startup_sim.uut.mem1.mem[162] top.startup_sim.uut.mem1.mem[163] top.startup_sim.uut.mem1.mem[164] top.startup_sim.uut.mem1.mem[165] top.startup_sim.uut.mem1.mem[166] top.startup_sim.uut.mem1.mem[167] top.startup_sim.uut.mem1.mem[168] top.startup_sim.uut.mem1.mem[169] top.startup_sim.uut.mem1.mem[170] top.startup_sim.uut.mem1.mem[171] top.startup_sim.uut.mem1.mem[172] top.startup_sim.uut.mem1.mem[173] top.startup_sim.uut.mem1.mem[174] top.startup_sim.uut.mem1.mem[175] top.startup_sim.uut.mem1.mem[176] top.startup_sim.uut.mem1.mem[177] top.startup_sim.uut.mem1.mem[178] top.startup_sim.uut.mem1.mem[179] top.startup_sim.uut.mem1.mem[180] top.startup_sim.uut.mem1.mem[181] top.startup_sim.uut.mem1.mem[182] top.startup_sim.uut.mem1.mem[183] top.startup_sim.uut.mem1.mem[184] top.startup_sim.uut.mem1.mem[185] top.startup_sim.uut.mem1.mem[186] top.startup_sim.uut.mem1.mem[187] top.startup_sim.uut.mem1.mem[188] top.startup_sim.uut.mem1.mem[189] top.startup_sim.uut.mem1.mem[190] top.startup_sim.uut.mem1.mem[191] top.startup_sim.uut.mem1.mem[192] top.startup_sim.uut.mem1.mem[193] top.startup_sim.uut.mem1.mem[194] top.startup_sim.uut.mem1.mem[195] top.startup_sim.uut.mem1.mem[196] top.startup_sim.uut.mem1.mem[197] top.startup_sim.uut.mem1.mem[198] top.startup_sim.uut.mem1.mem[199] top.startup_sim.uut.mem1.mem[200] top.startup_sim.uut.mem1.mem[201] top.startup_sim.uut.mem1.mem[202] top.startup_sim.uut.mem1.mem[203] top.startup_sim.uut.mem1.mem[204] top.startup_sim.uut.mem1.mem[205] top.startup_sim.uut.mem1.mem[206] top.startup_sim.uut.mem1.mem[207] top.startup_sim.uut.mem1.mem[208] top.startup_sim.uut.mem1.mem[209] top.startup_sim.uut.mem1.mem[210] top.startup_sim.uut.mem1.mem[211] top.startup_sim.uut.mem1.mem[212] top.startup_sim.uut.mem1.mem[213] top.startup_sim.uut.mem1.mem[214] top.startup_sim.uut.mem1.mem[215] top.startup_sim.uut.mem1.mem[216] top.startup_sim.uut.mem1.mem[217] top.startup_sim.uut.mem1.mem[218] top.startup_sim.uut.mem1.mem[219] top.startup_sim.uut.mem1.mem[220] top.startup_sim.uut.mem1.mem[221] top.startup_sim.uut.mem1.mem[222] top.startup_sim.uut.mem1.mem[223] top.startup_sim.uut.mem1.mem[224] top.startup_sim.uut.mem1.mem[225] top.startup_sim.uut.mem1.mem[226] top.startup_sim.uut.mem1.mem[227] top.startup_sim.uut.mem1.mem[228] top.startup_sim.uut.mem1.mem[229] top.startup_sim.uut.mem1.mem[230] top.startup_sim.uut.mem1.mem[231] top.startup_sim.uut.mem1.mem[232] top.startup_sim.uut.mem1.mem[233] top.startup_sim.uut.mem1.mem[234] top.startup_sim.uut.mem1.mem[235] top.startup_sim.uut.mem1.mem[236] top.startup_sim.uut.mem1.mem[237] top.startup_sim.uut.mem1.mem[238] top.startup_sim.uut.mem1.mem[239] top.startup_sim.uut.mem1.mem[240] top.startup_sim.uut.mem1.mem[241] top.startup_sim.uut.mem1.mem[242] top.startup_sim.uut.mem1.mem[243] top.startup_sim.uut.mem1.mem[244] top.startup_sim.uut.mem1.mem[245] top.startup_sim.uut.mem1.mem[246] top.startup_sim.uut.mem1.mem[247] top.startup_sim.uut.mem1.mem[248] top.startup_sim.uut.mem1.mem[249] top.startup_sim.uut.mem1.mem[250] top.startup_sim.uut.mem1.mem[251] top.startup_sim.uut.mem1.mem[252] top.startup_sim.uut.mem1.mem[253] top.startup_sim.uut.mem1.mem[254] top.startup_sim.uut.mem1.mem[255] top.startup_sim.uut.mem1.mem[256] top.startup_sim.uut.mem1.mem[257] top.startup_sim.uut.mem1.mem[258] top.startup_sim.uut.mem1.mem[259] top.startup_sim.uut.mem1.mem[260] top.startup_sim.uut.mem1.mem[261] top.startup_sim.uut.mem1.mem[262] top.startup_sim.uut.mem1.mem[263] top.startup_sim.uut.mem1.mem[264] top.startup_sim.uut.mem1.mem[265] top.startup_sim.uut.mem1.mem[266] top.startup_sim.uut.mem1.mem[267] top.startup_sim.uut.mem1.mem[268] top.startup_sim.uut.mem1.mem[269] top.startup_sim.uut.mem1.mem[270] top.startup_sim.uut.mem1.mem[271] top.startup_sim.uut.mem1.mem[272] top.startup_sim.uut.mem1.mem[273] top.startup_sim.uut.mem1.mem[274] top.startup_sim.uut.mem1.mem[275] top.startup_sim.uut.mem1.mem[276] top.startup_sim.uut.mem1.mem[277] top.startup_sim.uut.mem1.mem[278] top.startup_sim.uut.mem1.mem[279] top.startup_sim.uut.mem1.mem[280] top.startup_sim.uut.mem1.mem[281] top.startup_sim.uut.mem1.mem[282] top.startup_sim.uut.mem1.mem[283] top.startup_sim.uut.mem1.mem[284] top.startup_sim.uut.mem1.mem[285] top.startup_sim.uut.mem1.mem[286] top.startup_sim.uut.mem1.mem[287] top.startup_sim.uut.mem1.mem[288] top.startup_sim.uut.mem1.mem[289] top.startup_sim.uut.mem1.mem[290] top.startup_sim.uut.mem1.mem[291] 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top.startup_sim.uut.mem1.mem[843] top.startup_sim.uut.mem1.mem[844] top.startup_sim.uut.mem1.mem[845] top.startup_sim.uut.mem1.mem[846] top.startup_sim.uut.mem1.mem[847] top.startup_sim.uut.mem1.mem[848] top.startup_sim.uut.mem1.mem[849] top.startup_sim.uut.mem1.mem[850] top.startup_sim.uut.mem1.mem[851] top.startup_sim.uut.mem1.mem[852] top.startup_sim.uut.mem1.mem[853] top.startup_sim.uut.mem1.mem[854] top.startup_sim.uut.mem1.mem[855] top.startup_sim.uut.mem1.mem[856] top.startup_sim.uut.mem1.mem[857] top.startup_sim.uut.mem1.mem[858] top.startup_sim.uut.mem1.mem[859] top.startup_sim.uut.mem1.mem[860] top.startup_sim.uut.mem1.mem[861] top.startup_sim.uut.mem1.mem[862] top.startup_sim.uut.mem1.mem[863] top.startup_sim.uut.mem1.mem[864] top.startup_sim.uut.mem1.mem[865] top.startup_sim.uut.mem1.mem[866] top.startup_sim.uut.mem1.mem[867] top.startup_sim.uut.mem1.mem[868] top.startup_sim.uut.mem1.mem[869] top.startup_sim.uut.mem1.mem[870] top.startup_sim.uut.mem1.mem[871] top.startup_sim.uut.mem1.mem[872] top.startup_sim.uut.mem1.mem[873] top.startup_sim.uut.mem1.mem[874] top.startup_sim.uut.mem1.mem[875] top.startup_sim.uut.mem1.mem[876] top.startup_sim.uut.mem1.mem[877] top.startup_sim.uut.mem1.mem[878] top.startup_sim.uut.mem1.mem[879] top.startup_sim.uut.mem1.mem[880] top.startup_sim.uut.mem1.mem[881] top.startup_sim.uut.mem1.mem[882] top.startup_sim.uut.mem1.mem[883] top.startup_sim.uut.mem1.mem[884] top.startup_sim.uut.mem1.mem[885] top.startup_sim.uut.mem1.mem[886] top.startup_sim.uut.mem1.mem[887] top.startup_sim.uut.mem1.mem[888] top.startup_sim.uut.mem1.mem[889] top.startup_sim.uut.mem1.mem[890] top.startup_sim.uut.mem1.mem[891] top.startup_sim.uut.mem1.mem[892] top.startup_sim.uut.mem1.mem[893] top.startup_sim.uut.mem1.mem[894] top.startup_sim.uut.mem1.mem[895] top.startup_sim.uut.mem1.mem[896] top.startup_sim.uut.mem1.mem[897] top.startup_sim.uut.mem1.mem[898] top.startup_sim.uut.mem1.mem[899] top.startup_sim.uut.mem1.mem[900] top.startup_sim.uut.mem1.mem[901] top.startup_sim.uut.mem1.mem[902] top.startup_sim.uut.mem1.mem[903] top.startup_sim.uut.mem1.mem[904] top.startup_sim.uut.mem1.mem[905] top.startup_sim.uut.mem1.mem[906] top.startup_sim.uut.mem1.mem[907] top.startup_sim.uut.mem1.mem[908] top.startup_sim.uut.mem1.mem[909] top.startup_sim.uut.mem1.mem[910] top.startup_sim.uut.mem1.mem[911] top.startup_sim.uut.mem1.mem[912] top.startup_sim.uut.mem1.mem[913] top.startup_sim.uut.mem1.mem[914] top.startup_sim.uut.mem1.mem[915] top.startup_sim.uut.mem1.mem[916] top.startup_sim.uut.mem1.mem[917] top.startup_sim.uut.mem1.mem[918] top.startup_sim.uut.mem1.mem[919] top.startup_sim.uut.mem1.mem[920] top.startup_sim.uut.mem1.mem[921] top.startup_sim.uut.mem1.mem[922] top.startup_sim.uut.mem1.mem[923] top.startup_sim.uut.mem1.mem[924] top.startup_sim.uut.mem1.mem[925] top.startup_sim.uut.mem1.mem[926] top.startup_sim.uut.mem1.mem[927] top.startup_sim.uut.mem1.mem[928] top.startup_sim.uut.mem1.mem[929] top.startup_sim.uut.mem1.mem[930] top.startup_sim.uut.mem1.mem[931] top.startup_sim.uut.mem1.mem[932] top.startup_sim.uut.mem1.mem[933] top.startup_sim.uut.mem1.mem[934] top.startup_sim.uut.mem1.mem[935] top.startup_sim.uut.mem1.mem[936] top.startup_sim.uut.mem1.mem[937] top.startup_sim.uut.mem1.mem[938] top.startup_sim.uut.mem1.mem[939] top.startup_sim.uut.mem1.mem[940] top.startup_sim.uut.mem1.mem[941] top.startup_sim.uut.mem1.mem[942] top.startup_sim.uut.mem1.mem[943] top.startup_sim.uut.mem1.mem[944] top.startup_sim.uut.mem1.mem[945] top.startup_sim.uut.mem1.mem[946] top.startup_sim.uut.mem1.mem[947] top.startup_sim.uut.mem1.mem[948] top.startup_sim.uut.mem1.mem[949] top.startup_sim.uut.mem1.mem[950] top.startup_sim.uut.mem1.mem[951] top.startup_sim.uut.mem1.mem[952] top.startup_sim.uut.mem1.mem[953] top.startup_sim.uut.mem1.mem[954] top.startup_sim.uut.mem1.mem[955] top.startup_sim.uut.mem1.mem[956] top.startup_sim.uut.mem1.mem[957] top.startup_sim.uut.mem1.mem[958] top.startup_sim.uut.mem1.mem[959] top.startup_sim.uut.mem1.mem[960] top.startup_sim.uut.mem1.mem[961] top.startup_sim.uut.mem1.mem[962] top.startup_sim.uut.mem1.mem[963] top.startup_sim.uut.mem1.mem[964] top.startup_sim.uut.mem1.mem[965] top.startup_sim.uut.mem1.mem[966] top.startup_sim.uut.mem1.mem[967] top.startup_sim.uut.mem1.mem[968] top.startup_sim.uut.mem1.mem[969] top.startup_sim.uut.mem1.mem[970] top.startup_sim.uut.mem1.mem[971] top.startup_sim.uut.mem1.mem[972] top.startup_sim.uut.mem1.mem[973] top.startup_sim.uut.mem1.mem[974] top.startup_sim.uut.mem1.mem[975] top.startup_sim.uut.mem1.mem[976] top.startup_sim.uut.mem1.mem[977] top.startup_sim.uut.mem1.mem[978] top.startup_sim.uut.mem1.mem[979] top.startup_sim.uut.mem1.mem[980] top.startup_sim.uut.mem1.mem[981] top.startup_sim.uut.mem1.mem[982] top.startup_sim.uut.mem1.mem[983] top.startup_sim.uut.mem1.mem[984] top.startup_sim.uut.mem1.mem[985] top.startup_sim.uut.mem1.mem[986] top.startup_sim.uut.mem1.mem[987] top.startup_sim.uut.mem1.mem[988] top.startup_sim.uut.mem1.mem[989] top.startup_sim.uut.mem1.mem[990] top.startup_sim.uut.mem1.mem[991] top.startup_sim.uut.mem1.mem[992] top.startup_sim.uut.mem1.mem[993] top.startup_sim.uut.mem1.mem[994] top.startup_sim.uut.mem1.mem[995] top.startup_sim.uut.mem1.mem[996] top.startup_sim.uut.mem1.mem[997] top.startup_sim.uut.mem1.mem[998] top.startup_sim.uut.mem1.mem[999] top.startup_sim.uut.mem1.mem[1000] top.startup_sim.uut.mem1.mem[1001] top.startup_sim.uut.mem1.mem[1002] top.startup_sim.uut.mem1.mem[1003] top.startup_sim.uut.mem1.mem[1004] top.startup_sim.uut.mem1.mem[1005] top.startup_sim.uut.mem1.mem[1006] top.startup_sim.uut.mem1.mem[1007] top.startup_sim.uut.mem1.mem[1008] top.startup_sim.uut.mem1.mem[1009] top.startup_sim.uut.mem1.mem[1010] top.startup_sim.uut.mem1.mem[1011] top.startup_sim.uut.mem1.mem[1012] top.startup_sim.uut.mem1.mem[1013] top.startup_sim.uut.mem1.mem[1014] top.startup_sim.uut.mem1.mem[1015] top.startup_sim.uut.mem1.mem[1016] top.startup_sim.uut.mem1.mem[1017] top.startup_sim.uut.mem1.mem[1018] top.startup_sim.uut.mem1.mem[1019] top.startup_sim.uut.mem1.mem[1020] top.startup_sim.uut.mem1.mem[1021] top.startup_sim.uut.mem1.mem[1022] top.startup_sim.uut.mem1.mem[1023]
@28
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top.startup_sim.uut.mem1.mem[1005]
top.startup_sim.uut.mem1.mem[1006]
top.startup_sim.uut.mem1.mem[1007]
top.startup_sim.uut.mem1.mem[1008]
top.startup_sim.uut.mem1.mem[1009]
top.startup_sim.uut.mem1.mem[1010]
top.startup_sim.uut.mem1.mem[1011]
top.startup_sim.uut.mem1.mem[1012]
top.startup_sim.uut.mem1.mem[1013]
top.startup_sim.uut.mem1.mem[1014]
top.startup_sim.uut.mem1.mem[1015]
top.startup_sim.uut.mem1.mem[1016]
top.startup_sim.uut.mem1.mem[1017]
top.startup_sim.uut.mem1.mem[1018]
top.startup_sim.uut.mem1.mem[1019]
top.startup_sim.uut.mem1.mem[1020]
top.startup_sim.uut.mem1.mem[1021]
top.startup_sim.uut.mem1.mem[1022]
top.startup_sim.uut.mem1.mem[1023]
@1401200
-group_end
@200
-OUT1
@28
top.startup_sim.uut.ld_mar
@22
#{top.startup_sim.uut.mar.d[14:0]} top.startup_sim.uut.mar.d[14] top.startup_sim.uut.mar.d[13] top.startup_sim.uut.mar.d[12] top.startup_sim.uut.mar.d[11] top.startup_sim.uut.mar.d[10] top.startup_sim.uut.mar.d[9] top.startup_sim.uut.mar.d[8] top.startup_sim.uut.mar.d[7] top.startup_sim.uut.mar.d[6] top.startup_sim.uut.mar.d[5] top.startup_sim.uut.mar.d[4] top.startup_sim.uut.mar.d[3] top.startup_sim.uut.mar.d[2] top.startup_sim.uut.mar.d[1] top.startup_sim.uut.mar.d[0]
#{top.startup_sim.uut.mar.q[14:0]} top.startup_sim.uut.mar.q[14] top.startup_sim.uut.mar.q[13] top.startup_sim.uut.mar.q[12] top.startup_sim.uut.mar.q[11] top.startup_sim.uut.mar.q[10] top.startup_sim.uut.mar.q[9] top.startup_sim.uut.mar.q[8] top.startup_sim.uut.mar.q[7] top.startup_sim.uut.mar.q[6] top.startup_sim.uut.mar.q[5] top.startup_sim.uut.mar.q[4] top.startup_sim.uut.mar.q[3] top.startup_sim.uut.mar.q[2] top.startup_sim.uut.mar.q[1] top.startup_sim.uut.mar.q[0]
#{top.startup_sim.uut.data_address[14:0]} top.startup_sim.uut.data_address[14] top.startup_sim.uut.data_address[13] top.startup_sim.uut.data_address[12] top.startup_sim.uut.data_address[11] top.startup_sim.uut.data_address[10] top.startup_sim.uut.data_address[9] top.startup_sim.uut.data_address[8] top.startup_sim.uut.data_address[7] top.startup_sim.uut.data_address[6] top.startup_sim.uut.data_address[5] top.startup_sim.uut.data_address[4] top.startup_sim.uut.data_address[3] top.startup_sim.uut.data_address[2] top.startup_sim.uut.data_address[1] top.startup_sim.uut.data_address[0]
#{top.startup_sim.uut.memo4[15:0]} top.startup_sim.uut.memo4[15] top.startup_sim.uut.memo4[14] top.startup_sim.uut.memo4[13] top.startup_sim.uut.memo4[12] top.startup_sim.uut.memo4[11] top.startup_sim.uut.memo4[10] top.startup_sim.uut.memo4[9] top.startup_sim.uut.memo4[8] top.startup_sim.uut.memo4[7] top.startup_sim.uut.memo4[6] top.startup_sim.uut.memo4[5] top.startup_sim.uut.memo4[4] top.startup_sim.uut.memo4[3] top.startup_sim.uut.memo4[2] top.startup_sim.uut.memo4[1] top.startup_sim.uut.memo4[0]
@28
#{top.startup_sim.uut.dosel[2:0]} top.startup_sim.uut.dosel[2] top.startup_sim.uut.dosel[1] top.startup_sim.uut.dosel[0]
@22
#{top.startup_sim.uut.databus_read[15:0]} top.startup_sim.uut.databus_read[15] top.startup_sim.uut.databus_read[14] top.startup_sim.uut.databus_read[13] top.startup_sim.uut.databus_read[12] top.startup_sim.uut.databus_read[11] top.startup_sim.uut.databus_read[10] top.startup_sim.uut.databus_read[9] top.startup_sim.uut.databus_read[8] top.startup_sim.uut.databus_read[7] top.startup_sim.uut.databus_read[6] top.startup_sim.uut.databus_read[5] top.startup_sim.uut.databus_read[4] top.startup_sim.uut.databus_read[3] top.startup_sim.uut.databus_read[2] top.startup_sim.uut.databus_read[1] top.startup_sim.uut.databus_read[0]
@28
#{top.startup_sim.uut.dec1.bus_sel[2:0]} top.startup_sim.uut.dec1.bus_sel[2] top.startup_sim.uut.dec1.bus_sel[1] top.startup_sim.uut.dec1.bus_sel[0]
top.startup_sim.uut.dec1.gpio_1
top.startup_sim.uut.dec1.gpio_2
top.startup_sim.uut.dec1.gpio_3
+{OUT1 WRITE} top.startup_sim.uut.out1.we
+{OUT1 ENABLE} top.startup_sim.uut.out1.ena
@22
#{top.startup_sim.uut.out1.output[15:0]} top.startup_sim.uut.out1.output[15] top.startup_sim.uut.out1.output[14] top.startup_sim.uut.out1.output[13] top.startup_sim.uut.out1.output[12] top.startup_sim.uut.out1.output[11] top.startup_sim.uut.out1.output[10] top.startup_sim.uut.out1.output[9] top.startup_sim.uut.out1.output[8] top.startup_sim.uut.out1.output[7] top.startup_sim.uut.out1.output[6] top.startup_sim.uut.out1.output[5] top.startup_sim.uut.out1.output[4] top.startup_sim.uut.out1.output[3] top.startup_sim.uut.out1.output[2] top.startup_sim.uut.out1.output[1] top.startup_sim.uut.out1.output[0]
#{top.startup_sim.uut.out1.port_out[7:0]} top.startup_sim.uut.out1.port_out[7] top.startup_sim.uut.out1.port_out[6] top.startup_sim.uut.out1.port_out[5] top.startup_sim.uut.out1.port_out[4] top.startup_sim.uut.out1.port_out[3] top.startup_sim.uut.out1.port_out[2] top.startup_sim.uut.out1.port_out[1] top.startup_sim.uut.out1.port_out[0]
#{top.startup_sim.uut.out1.d[15:0]} top.startup_sim.uut.out1.d[15] top.startup_sim.uut.out1.d[14] top.startup_sim.uut.out1.d[13] top.startup_sim.uut.out1.d[12] top.startup_sim.uut.out1.d[11] top.startup_sim.uut.out1.d[10] top.startup_sim.uut.out1.d[9] top.startup_sim.uut.out1.d[8] top.startup_sim.uut.out1.d[7] top.startup_sim.uut.out1.d[6] top.startup_sim.uut.out1.d[5] top.startup_sim.uut.out1.d[4] top.startup_sim.uut.out1.d[3] top.startup_sim.uut.out1.d[2] top.startup_sim.uut.out1.d[1] top.startup_sim.uut.out1.d[0]
#{top.startup_sim.uut.out1.q[15:0]} top.startup_sim.uut.out1.q[15] top.startup_sim.uut.out1.q[14] top.startup_sim.uut.out1.q[13] top.startup_sim.uut.out1.q[12] top.startup_sim.uut.out1.q[11] top.startup_sim.uut.out1.q[10] top.startup_sim.uut.out1.q[9] top.startup_sim.uut.out1.q[8] top.startup_sim.uut.out1.q[7] top.startup_sim.uut.out1.q[6] top.startup_sim.uut.out1.q[5] top.startup_sim.uut.out1.q[4] top.startup_sim.uut.out1.q[3] top.startup_sim.uut.out1.q[2] top.startup_sim.uut.out1.q[1] top.startup_sim.uut.out1.q[0]
[pattern_trace] 1
[pattern_trace] 0
/xucpu/trunk/ghdl/input_data.txt
0,0 → 1,1024
3000
0000
9000
0008
3000
FEED
0000
0000
3000
BEAF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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0000
0000
0000
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0000
0000
0000
0000
0000
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0000
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/xucpu/trunk/ghdl/win.make
0,0 → 1,80
 
#
# This file is part of the Experimental Unstable CPU System.
#
# The Experimental Unstable CPU System Is free software: you can redistribute
# it and/or modify it under the terms of the GNU Lesser General Public License
# as published by the Free Software Foundation, either version 3 of the
# License, or (at your option) any later version.
#
# The Experimental Unstable CPU System is distributed in the hope that it will
# be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
# General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Experimental Unstable CPU System. If not, see
# http://www.gnu.org/licenses/lgpl.txt.
 
FIND=find
XARGS=xargs
UNISIM=D:/cygwin64/usr/local/share
SOURCE= ../src/file/arrayio.vhdl \
../src/multiplexer/MUX.vhdl \
../src/blockram/RAM.vhdl \
../src/components.vhdl \
../src/ALU/alu.vhdl \
../src/ALU/logic.vhdl \
../src/ALU/shift.vhdl \
../src/ALU/summation.vhdl \
../src/controllers.vhdl \
../src/uctrl.vhdl \
../src/system.vhdl \
../src/gpio_in.vhdl \
../src/gpio_out.vhdl \
../src/incr.vhdl \
../src/regf.vhdl \
../src/sync_reset.vhdl \
../src/zerof.vhdl \
../src/decoder.vhdl \
../src/system_sim.vhdl \
../src/startup_sim.vhdl \
../src/clock.vhdl \
../Xilinx/ipcore_dir/clock_core_gen.vhd \
../src/data_reg.vhdl
 
unisim: unisim-obj93.cf
ghdl -a --ieee=synopsys --work=unisim --workdir=tmp $(UNISIM)/unisims/*.vhd
$(FIND) $(UNISIM)/unisims/primitive/*.vhd -print0 | $(XARGS) -0 -n 1 -t ghdl -a --ieee=synopsys --work=unisim --workdir=tmp -fexplicit
 
unisim-obj93.cf:
 
analyse:
ghdl -a -P./. -P./tmp --ieee=synopsys --workdir=tmp $(SOURCE)
 
build: unisim-obj93.cf analyse
ghdl -e -g -P./. -P./tmp --warn-unused --ieee=synopsys --workdir=tmp startup_sim
 
run: build
ghdl -r -P. startup_sim --wave=startup_sim.ghw --stop-time=2us
 
clean:
-rm *.o
-rm unisim*
 
init: cp_init
 
cp_init:
cp uctrl-init.vhdl uctrl.vhdl
 
main: cp_main
 
cp_main:
cp uctrl-main.vhdl uctrl.vhdl
 
test: cp_test
 
cp_test:
cp test/$(INST).txt input_data.txt
 
# vim:set noet tw=0 ts=8:
/xucpu/trunk/ghdl/Makefile
0,0 → 1,80
 
#
# This file is part of the Experimental Unstable CPU System.
#
# The Experimental Unstable CPU System Is free software: you can redistribute
# it and/or modify it under the terms of the GNU Lesser General Public License
# as published by the Free Software Foundation, either version 3 of the
# License, or (at your option) any later version.
#
# The Experimental Unstable CPU System is distributed in the hope that it will
# be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
# General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Experimental Unstable CPU System. If not, see
# http://www.gnu.org/licenses/lgpl.txt.
 
FIND=gfind
XARGS=gxargs
UNISIM=/usr/local/share
SOURCE= ../src/file/arrayio.vhdl \
../src/multiplexer/MUX.vhdl \
../src/blockram/RAM.vhdl \
../src/components.vhdl \
../src/ALU/alu.vhdl \
../src/ALU/logic.vhdl \
../src/ALU/shift.vhdl \
../src/ALU/summation.vhdl \
../src/controllers.vhdl \
../src/uctrl.vhdl \
../src/system.vhdl \
../src/gpio_in.vhdl \
../src/gpio_out.vhdl \
../src/incr.vhdl \
../src/regf.vhdl \
../src/sync_reset.vhdl \
../src/zerof.vhdl \
../src/decoder.vhdl \
../src/system_sim.vhdl \
../src/startup_sim.vhdl \
../src/clock.vhdl \
../Xilinx/ipcore_dir/clock_core_gen.vhd \
../src/data_reg.vhdl
 
unisim: unisim-obj93.cf
ghdl -a --ieee=synopsys --work=unisim --workdir=tmp $(UNISIM)/unisims/*.vhd
$(FIND) $(UNISIM)/unisims/primitive/*.vhd -print0 | $(XARGS) -0 -n 1 -t ghdl -a --ieee=synopsys --work=unisim --workdir=tmp -fexplicit
 
unisim-obj93.cf:
 
analyse:
ghdl -a -P./. -P./tmp --ieee=synopsys --workdir=tmp $(SOURCE)
 
build: unisim-obj93.cf analyse
ghdl -e -g -P./. -P./tmp --warn-unused --ieee=synopsys --workdir=tmp startup_sim
 
run: build
ghdl -r -P. -P./tmp --ieee=synopsys --workdir=tmp startup_sim --wave=startup_sim.ghw --stop-time=300ns
 
clean:
-rm *.o
-rm unisim*
 
init: cp_init
 
cp_init:
cp uctrl-init.vhdl uctrl.vhdl
 
main: cp_main
 
cp_main:
cp uctrl-main.vhdl uctrl.vhdl
 
test: cp_test
 
cp_test:
cp test/$(INST).txt input_data.txt
 
# vim:set noet tw=0 ts=8:

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